lynxpoint: Fix GPIO and PM base reservations

The kernel ACPI was not happy with the Add inside a
ResourceTemplate (or perhaps within the IO declaration)

Instead make a buffer of IO reservations and turn _CRS
into a method that updates the buffer depending on the
chipset type.

This adds an \ISLP() method that checks the chipset LPC
device ID to see if it is -LP or -H.

It also increases the PM base reservation to 256 bytes
and moves both GPIO and PM base to above 0x1000 on -LP
chipsets.

Change-Id: I747b658588a4d8ed15a0134009a7c0d74b3916ba
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2815
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

src/southbridge/intel/lynxpoint/acpi/lpc.asl

@@ -28,6 +28,8 @@ Device (LPCB)
 	OperationRegion(LPC0, PCI_Config, 0x00, 0x100)
 	Field (LPC0, AnyAcc, NoLock, Preserve)
 	{
+		Offset (0x3),
+		DIDH,	8,	// Device ID High Byte
 		Offset (0x40),
 		PMBS,	16,	// PMBASE
 		Offset (0x60),	// Interrupt Routing Registers
@@ -181,36 +183,80 @@ Device (LPCB)
 	{
 		Name (_HID, EISAID("PNP0C02"))
 		Name (_UID, 2)
-		Name (_CRS, ResourceTemplate()
-		{
-			IO (Decode16, 0x2e, 0x2e, 0x1, 0x02)		// First SuperIO
-			IO (Decode16, 0x4e, 0x4e, 0x1, 0x02)		// Second SuperIO
-			IO (Decode16, 0x61, 0x61, 0x1, 0x01)		// NMI Status
-			IO (Decode16, 0x63, 0x63, 0x1, 0x01)		// CPU Reserved
-			IO (Decode16, 0x65, 0x65, 0x1, 0x01)		// CPU Reserved
-			IO (Decode16, 0x67, 0x67, 0x1, 0x01)		// CPU Reserved
-			IO (Decode16, 0x80, 0x80, 0x1, 0x01)		// Port 80 Post
-			IO (Decode16, 0x92, 0x92, 0x1, 0x01)		// CPU Reserved
-			IO (Decode16, 0xb2, 0xb2, 0x1, 0x02)		// SWSMI
-			//IO (Decode16, 0x800, 0x800, 0x1, 0x10)		// ACPI I/O trap
-			IO (Decode16, DEFAULT_PMBASE, DEFAULT_PMBASE, 0x1, 0x80)	// ICH7-M ACPI
 
-#if CONFIG_INTEL_LYNXPOINT_LP
+		Name (RBUF, ResourceTemplate()
-			// LynxPoint LP GPIO is 1KB
+		{
-			IO (Decode16, DEFAULT_GPIOBASE,
+			IO (Decode16, 0x2e, 0x2e, 0x1, 0x02) // First SuperIO
-			    DEFAULT_GPIOBASE, 0x1, 0xff)
+			IO (Decode16, 0x4e, 0x4e, 0x1, 0x02) // Second SuperIO
-			IO (Decode16, Add(DEFAULT_GPIOBASE, 0x100),
+			IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status
-			     Add(DEFAULT_GPIOBASE, 0x100), 0x1, 0xff)
+			IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved
-			IO (Decode16, Add(DEFAULT_GPIOBASE, 0x200),
+			IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved
-			    Add(DEFAULT_GPIOBASE, 0x200), 0x1, 0xff)
+			IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved
-			IO (Decode16, Add(DEFAULT_GPIOBASE, 0x300),
+			IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post
-			    Add(DEFAULT_GPIOBASE, 0x300), 0x1, 0xff)
+			IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved
-#else
+			IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI
-			// LynxPoint GPIO is 128 bytes
+			IO (Decode16, DEFAULT_PMBASE, DEFAULT_PMBASE,
-			IO (Decode16, DEFAULT_GPIOBASE,
+			    0x1, 0xff)
-			    DEFAULT_GPIOBASE, 0x1, DEFAULT_GPIOSIZE)
+
-#endif
+			// GPIO region may be 128 bytes or 4096 bytes
+			IO (Decode16, DEFAULT_GPIOBASE, DEFAULT_GPIOBASE,
+			    0x1, 0x00, GPR1)
+			IO (Decode16, 0x0000, 0x0000, 0x1, 0x00, GPR2)
+			IO (Decode16, 0x0000, 0x0000, 0x1, 0x00, GPR3)
+			IO (Decode16, 0x0000, 0x0000, 0x1, 0x00, GPR4)
 		})
+
+		Method (_CRS, 0, NotSerialized)
+		{
+			CreateByteField (^RBUF, ^GPR1._LEN, R1LN)
+			CreateByteField (^RBUF, ^GPR2._LEN, R2LN)
+			CreateByteField (^RBUF, ^GPR3._LEN, R3LN)
+			CreateByteField (^RBUF, ^GPR4._LEN, R4LN)
+
+			CreateWordField (^RBUF, ^GPR1._MIN, R1MN)
+			CreateWordField (^RBUF, ^GPR2._MIN, R2MN)
+			CreateWordField (^RBUF, ^GPR3._MIN, R3MN)
+			CreateWordField (^RBUF, ^GPR4._MIN, R4MN)
+
+			CreateWordField (^RBUF, ^GPR1._MAX, R1MX)
+			CreateWordField (^RBUF, ^GPR2._MAX, R2MX)
+			CreateWordField (^RBUF, ^GPR3._MAX, R3MX)
+			CreateWordField (^RBUF, ^GPR4._MAX, R4MX)
+
+			// Update GPIO region for LynxPoint-LP
+			If (\ISLP ()) {
+				// LynxPoint-LP
+				Store (R1MN, Local0)
+
+				// Update GPIO bank 1
+				Store (Local0, R1MN)
+				Store (Local0, R1MX)
+				Store (0xff, R1LN)
+
+				// Update GPIO bank 2
+				Add (Local0, 0x100, Local0)
+				Store (Local0, R2MN)
+				Store (Local0, R2MX)
+				Store (0xff, R2LN)
+
+				// Update GPIO bank 3
+				Add (Local0, 0x100, Local0)
+				Store (Local0, R3MN)
+				Store (Local0, R3MN)
+				Store (0xff, R3LN)
+
+				// Update GPIO bank 4
+				Add (Local0, 0x100, Local0)
+				Store (Local0, R4MN)
+				Store (Local0, R4MN)
+				Store (0xff, R4LN)
+			} Else {
+				// LynxPoint-H
+				// Update GPIO region length
+				Store (DEFAULT_GPIOSIZE, R1LN)
+			}
+			Return (RBUF)
+		}
 	}
 
 	Device (RTC)	// Real Time Clock

src/southbridge/intel/lynxpoint/acpi/pch.asl

@@ -23,6 +23,16 @@
 
 Scope(\)
 {
+	// Return TRUE if chipset is LynxPoint-LP
+	Method (ISLP, 0, NotSerialized)
+	{
+		If (LEqual (\_SB.PCI0.LPCB.DIDH, 0x9c)) {
+			Return (1)
+		} else {
+			Return (0)
+		}
+	}
+
 	// IO-Trap at 0x800. This is the ACPI->SMI communication interface.
 
 	OperationRegion(IO_T, SystemIO, 0x800, 0x10)
@@ -33,7 +43,7 @@ Scope(\)
 	}
 
 	// PCH Power Management Registers, located at PMBASE (0x1f.0 0x40.l)
-	OperationRegion(PMIO, SystemIO, DEFAULT_PMBASE, 0x80)
+	OperationRegion(PMIO, SystemIO, DEFAULT_PMBASE, 0xff)
 	Field(PMIO, ByteAcc, NoLock, Preserve)
 	{
 		Offset(0x20),	// GPE0_STS

src/southbridge/intel/lynxpoint/lpc.c

@@ -630,11 +630,11 @@ static void pch_lpc_add_io_resources(device_t dev)
 	res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
 	/* GPIOBASE */
-	pch_lpc_add_io_resource(dev, DEFAULT_GPIOBASE, DEFAULT_GPIOSIZE,
+	pch_lpc_add_io_resource(dev, get_gpiobase(), DEFAULT_GPIOSIZE,
 	                        GPIO_BASE);
 
 	/* PMBASE */
-	pch_lpc_add_io_resource(dev, DEFAULT_PMBASE, 128, PMBASE);
+	pch_lpc_add_io_resource(dev, get_pmbase(), 256, PMBASE);
 
 	/* LPC Generic IO Decode range. */
 	pch_lpc_add_gen_io_resources(dev, config->gen1_dec, LPC_GEN1_DEC);

src/southbridge/intel/lynxpoint/pch.h

@@ -65,12 +65,13 @@
  */
 #define SMBUS_IO_BASE		0x0400
 #define SMBUS_SLAVE_ADDR	0x24
-#define DEFAULT_PMBASE		0x0500
 
 #if CONFIG_INTEL_LYNXPOINT_LP
-#define DEFAULT_GPIOBASE	0x1000
+#define DEFAULT_PMBASE		0x1000
+#define DEFAULT_GPIOBASE	0x1400
 #define DEFAULT_GPIOSIZE	0x400
 #else
+#define DEFAULT_PMBASE		0x500
 #define DEFAULT_GPIOBASE	0x480
 #define DEFAULT_GPIOSIZE	0x80
 #endif