WIP: Reorganize devicetree
Change-Id: Ia17916de8794077e57ce7fd04464e99d3751479d
This commit is contained in:
Jeremy Soller
@@ -34,51 +34,18 @@ chip soc/intel/tigerlake
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.tdp_pl2_override = 60,
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}"
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# eSPI (soc/intel/tigerlake/espi.c)
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# LPC configuration from lspci -s 1f.0 -xxx
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# Address 0x84: Decode 0x80 - 0x8F (Port 80)
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register "gen1_dec" = "0x000c0081"
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# Address 0x88: Decode 0x68 - 0x6F (PMC)
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register "gen2_dec" = "0x00040069"
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# Address 0x8C: Decode 0xE00 - 0xEFF (AP/EC command)
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register "gen3_dec" = "0x00fc0E01"
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# Address 0x90: Decode 0xF00 - 0xFFF (AP/EC debug)
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register "gen4_dec" = "0x00fc0F01"
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# Finalize (soc/intel/tigerlake/finalize.c)
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# PM Timer Disabled, saves power
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register "PmTimerDisabled" = "1"
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# FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c)
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# DDIA is eDP
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register "DdiPortAConfig" = "1"
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register "DdiPortAHpd" = "1"
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register "DdiPortADdc" = "0"
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# DDIB is HDMI
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register "DdiPortBConfig" = "0"
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register "DdiPortBHpd" = "1"
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register "DdiPortBDdc" = "1"
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# Enable C6 DRAM
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register "enable_c6dram" = "1"
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# High Definition Audio
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register "PchHdaAudioLinkHdaEnable" = "1"
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# System Agent dynamic frequency support
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register "SaGv" = "SaGv_Enabled"
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# Enable SMBus
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register "SmbusEnable" = "1"
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# TCSS USB3
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register "TcssXhciEn" = "1"
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# FSP Silicon (soc/intel/tigerlake/fsp_params.c)
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# Enable DPTF device
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register "Device4Enable" = "1"
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# FIVR configuration
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# Read EXT_RAIL_CONFIG to determine bitmaps
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# sudo devmem2 0xfe0011b8
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@@ -125,108 +92,10 @@ chip soc/intel/tigerlake
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LPM_S0i3_4
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"
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# I2C channels
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register "SerialIoI2cMode" = "{
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[PchSerialIoIndexI2C0] = PchSerialIoPci, // Touchpad I2C bus
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[PchSerialIoIndexI2C1] = PchSerialIoPci, // TODO: USB-PD?
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[PchSerialIoIndexI2C2] = PchSerialIoPci, // TODO: Pantone ROM
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[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
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}"
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# SPI channels
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register "SerialIoGSpiMode" = "{
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[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
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[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
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[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
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[PchSerialIoIndexGSPI3] = PchSerialIoDisabled,
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}"
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#TODO: GSpiCsMode and GSpiCsState ?
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# UART channels
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register "SerialIoUartMode" = "{
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[PchSerialIoIndexUART0] = PchSerialIoDisabled,
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[PchSerialIoIndexUART1] = PchSerialIoDisabled,
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[PchSerialIoIndexUART2] = PchSerialIoPci, // Debug console
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}"
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# USB2
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register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB Type-A Port 1 TODO
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register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB Type-C Port 2 TODO
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register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB Type-A Port 3 TODO
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register "usb2_ports[3]" = "USB2_PORT_EMPTY"
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register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
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register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB Type-C Port 4 TODO
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register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Camera
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register "usb2_ports[7]" = "USB2_PORT_EMPTY"
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register "usb2_ports[8]" = "USB2_PORT_EMPTY"
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register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
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# USB3
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB Type-A Port 1 TODO
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB Type-C Port 2 TODO
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB Type-A Port 3 TODO
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB Type-C Port 4 TODO
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# PCIe root ports:
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# PCIe 4 x4 - SSD1
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# 5 x4 - DGPU
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# 9 x1 - CARD
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# 10 x1 - GLAN
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# 11 x1 - WLAN
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# PCIe clocks:
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# 0 - SSD1
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# 1 - WLAN
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# 2 - DGPU
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# 3 - CARD
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# 4 - GLAN
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# PCIe PEG0 x4, Clock 0 (SSD1)
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register "PcieClkSrcUsage[0]" = "0x40"
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register "PcieClkSrcClkReq[0]" = "0"
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# PCIe root port #5 x4, Clock 2 (NVIDIA GPU)
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register "PcieRpEnable[4]" = "1"
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register "PcieRpLtrEnable[4]" = "1"
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register "PcieClkSrcUsage[2]" = "4"
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register "PcieClkSrcClkReq[2]" = "2"
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# PCIe root port #9 x1, Clock 3 (Card Reader)
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register "PcieRpEnable[8]" = "1"
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register "PcieRpLtrEnable[8]" = "1"
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register "PcieClkSrcUsage[3]" = "8"
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register "PcieClkSrcClkReq[3]" = "3"
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# PCIe root port #10 x1, Clock 4 (GLAN)
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register "PcieRpEnable[9]" = "1"
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register "PcieRpLtrEnable[9]" = "1"
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register "PcieClkSrcUsage[4]" = "9"
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register "PcieClkSrcClkReq[4]" = "4"
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# PCIe root port #11 x1, Clock 1 (WLAN)
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register "PcieRpEnable[10]" = "1"
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register "PcieRpLtrEnable[10]" = "1"
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register "PcieClkSrcUsage[1]" = "10"
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register "PcieClkSrcClkReq[1]" = "1"
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# Thermal
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# rdmsr --bitfield 31:24 --decimal 0x1A2
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register "tcc_offset" = "13"
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# Graphics (soc/intel/tigerlake/graphics.c)
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register "gfx" = "GMA_STATIC_DISPLAYS(0)"
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# PMC (soc/intel/tigerlake/pmc.c)
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# Disable deep Sx states
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register "deep_s3_enable_ac" = "0"
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register "deep_s3_enable_dc" = "0"
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register "deep_s5_enable_ac" = "0"
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register "deep_s5_enable_dc" = "0"
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register "deep_sx_config" = "0"
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# PM Util (soc/intel/tigerlake/pmutil.c)
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# GPE configuration
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# sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
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@@ -235,67 +104,89 @@ chip soc/intel/tigerlake
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register "pmc_gpe0_dw1" = "PMC_GPP_R"
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register "pmc_gpe0_dw2" = "PMC_GPD"
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# SMI Handler (soc/intel/tigerlake/smihandler.c)
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#TODO Disable HECI
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register "HeciEnabled" = "1"
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# Actual device tree
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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#TODO: Adjustments
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device domain 0 on
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#From EDS(575683)
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device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y
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device pci 02.0 on end # Graphics
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device pci 04.0 on end # DPTF 0x9A03
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device pci 05.0 off end # IPU 0x9A19
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device pci 06.0 on
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chip soc/intel/common/block/pcie/rtd3
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD1_PWR_DN#
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" # GPP_H0_RTD3
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#TODO: Support disable/enable CPU RP clock
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register "srcclk_pin" = "-1" # SSD1_CLKREQ#
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device generic 0 on end
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end
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end # PEG60 0x9A09
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device pci 07.0 on end # TBT_PCIe0 0x9A23
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device pci 07.1 off end # TBT_PCIe1 0x9A25
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device pci 07.2 off end # TBT_PCIe2 0x9A27
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device pci 07.3 off end # TBT_PCIe3 0x9A29
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device pci 08.0 on end # GNA 0x9A11
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device pci 09.0 off end # NPK 0x9A33
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device pci 0a.0 on end # Crash-log SRAM 0x9A0D
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device pci 0d.0 on end # USB xHCI 0x9A13
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device pci 0d.1 off end # USB xDCI (OTG) 0x9A15
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device pci 0d.2 on
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#From CPU EDS(575683)
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device ref system_agent on end
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device ref igpu on
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# DDIA is eDP
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register "DdiPortAConfig" = "1"
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register "DdiPortAHpd" = "1"
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register "DdiPortADdc" = "0"
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# DDIB is HDMI
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register "DdiPortBConfig" = "0"
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register "DdiPortBHpd" = "1"
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register "DdiPortBDdc" = "1"
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register "gfx" = "GMA_STATIC_DISPLAYS(0)"
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end
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device ref dptf on
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# Enable DPTF device
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register "Device4Enable" = "1"
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end
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device ref peg on
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# PCIe PEG0 x4, Clock 0 (SSD1)
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register "PcieClkSrcUsage[0]" = "0x40"
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register "PcieClkSrcClkReq[0]" = "0"
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#TODO: causes failure on resume
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# chip soc/intel/common/block/pcie/rtd3
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# register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD1_PWR_DN#
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# register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" # GPP_H0_RTD3
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# #TODO: Support disable/enable CPU RP clock
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# register "srcclk_pin" = "-1" # SSD1_CLKREQ#
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# device generic 0 on end
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# end
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end
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device ref tbt_pcie_rp0 on end # J_TYPEC2
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device ref gna on end
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device ref chrashlog on end # TODO: purpose?
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device ref north_xhci on # J_TYPEC2
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register "TcssXhciEn" = "1"
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# TODO: usb/acpi
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end
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device ref tbt_dma0 on
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chip drivers/intel/usb4/retimer
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register "power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A23)"
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device generic 0 on end
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end
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end # TBT DMA0 0x9A1B
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device pci 0d.3 off end # TBT DMA1 0x9A1D
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device pci 0e.0 off end # VMD 0x9A0B
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end
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# From PCH EDS(576591)
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device pci 10.2 on end # CNVi: BT 0xA0F5 - A0F7
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device pci 10.6 off end # THC0 0xA0D0
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device pci 10.7 off end # THC1 0xA0D1
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device pci 12.0 off end # SensorHUB 0xA0FC
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device pci 12.6 off end # GSPI2 0x34FB
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device pci 13.0 off end # GSPI3 0xA0FD
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device pci 14.0 on end # USB3.1 xHCI 0xA0ED
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device pci 14.1 off end # USB3.1 xDCI 0xA0EE
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device pci 14.2 on end # Shared RAM 0xA0EF
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device pci 14.3 on
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device ref cnvi_bt on end
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device ref south_xhci on
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# USB2
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register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # J_USB3_2
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register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC1
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register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # J_USB3_1
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register "usb2_ports[3]" = "USB2_PORT_EMPTY"
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register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
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register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC2
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register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Camera
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register "usb2_ports[7]" = "USB2_PORT_EMPTY"
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register "usb2_ports[8]" = "USB2_PORT_EMPTY"
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register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
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# USB3
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_USB3_2
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1 Channel 0
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_USB3_1
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1 Channel 0
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# TODO: usb/acpi
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end
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device ref shared_ram on end
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device ref cnvi_wifi on
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chip drivers/wifi/generic
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register "wake" = "GPE0_PME_B0"
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device generic 0 on end
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end
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end # CNVi: WiFi 0xA0F0 - A0F3
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device pci 15.0 on # I2C0 0xA0E8
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end
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device ref i2c0 on
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# Touchpad I2C bus
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register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
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chip drivers/i2c/hid
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register "generic.hid" = ""PNP0C50""
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register "generic.desc" = ""TODO Touchpad""
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@@ -304,37 +195,49 @@ chip soc/intel/tigerlake
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register "hid_desc_reg_offset" = "0x01"
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device i2c 38 on end
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end
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end # I2C0
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device pci 15.1 on end # I2C1 0xA0E9
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device pci 15.2 on end # I2C2 0xA0EA
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device pci 15.3 off end # I2C3 0xA0EB
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device pci 16.0 on end # HECI1 0xA0E0
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device pci 16.1 off end # HECI2 0xA0E1
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device pci 16.2 off end # CSME 0xA0E2
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device pci 16.3 off end # CSME 0xA0E3
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device pci 16.4 off end # HECI3 0xA0E4
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device pci 16.5 off end # HECI4 0xA0E5
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device pci 17.0 off end # SATA 0xA0D3
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device pci 19.0 off end # I2C4 0xA0C5
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device pci 19.1 off end # I2C5 0xA0C6
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device pci 19.2 on end # UART2 0xA0C7
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device pci 1c.0 off end # RP1 0xA0B8
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device pci 1c.1 off end # RP2 0xA0B9
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device pci 1c.2 off end # RP3 0xA0BA
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device pci 1c.3 off end # RP4 0xA0BB
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device pci 1c.4 on
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end
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device ref i2c1 on
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#TODO: USB-PD?
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register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
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end
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device ref i2c2 on
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#TODO: Pantone ROM?
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register "SerialIoI2cMode[PchSerialIoIndexI2C2]" = "PchSerialIoPci"
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end
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device rev heci1 on
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#TODO Disable ME and HECI
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register "HeciEnabled" = "1"
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end
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device ref uart2 on
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# Debug console
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register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoPci"
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end
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device ref pcie_rp5 on
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# PCIe root port #5 x4, Clock 2 (NVIDIA GPU)
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register "PcieRpEnable[4]" = "1"
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register "PcieRpLtrEnable[4]" = "1"
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register "PcieClkSrcUsage[2]" = "4"
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register "PcieClkSrcClkReq[2]" = "2"
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chip soc/intel/common/block/pcie/rtd3
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_U5)" # DGPU_PWR_EN
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_U4)" # DGPU_RST#_PCH
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register "srcclk_pin" = "2" # PEG_CLKREQ#
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device generic 0 on end
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end
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end # RP5 0xA0BC
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device pci 1c.5 off end # RP6 0xA0BD
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device pci 1c.6 off end # RP7 0xA0BE
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device pci 1c.7 off end # RP8 0xA0BF
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device pci 1d.0 on end # RP9 0xA0B0
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device pci 1d.1 on
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end
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device ref pcie_rp9 on
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# PCIe root port #9 x1, Clock 3 (Card Reader)
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register "PcieRpEnable[8]" = "1"
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register "PcieRpLtrEnable[8]" = "1"
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register "PcieClkSrcUsage[3]" = "8"
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register "PcieClkSrcClkReq[3]" = "3"
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end
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device ref pcie_rp10 on
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# PCIe root port #10 x1, Clock 4 (GLAN)
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register "PcieRpEnable[9]" = "1"
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register "PcieRpLtrEnable[9]" = "1"
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register "PcieClkSrcUsage[4]" = "9"
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register "PcieClkSrcClkReq[4]" = "4"
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chip soc/intel/common/block/pcie/rtd3
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F9)" # GPIO_LAN_EN
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#TODO: should this be GPIO_LANRTD3 or LAN_PLT_RST# ?
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@@ -342,46 +245,36 @@ chip soc/intel/tigerlake
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register "srcclk_pin" = "4" # LAN_CLKREQ#
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device generic 0 on end
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end
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end # RP10 0xA0B1
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device pci 1d.2 on end # RP11 0xA0B2
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device pci 1d.3 off end # RP12 0xA0B3
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||||
device pci 1e.0 off end # UART0 0xA0A8
|
||||
device pci 1e.1 off end # UART1 0xA0A9
|
||||
device pci 1e.2 off end # GSPI0 0xA0AA
|
||||
device pci 1e.3 off end # GSPI1 0xA0AB
|
||||
device pci 1f.0 on # eSPI 0xA080 - A09F
|
||||
end
|
||||
device ref pcie_rp11 on
|
||||
# PCIe root port #11 x1, Clock 1 (WLAN)
|
||||
register "PcieRpEnable[10]" = "1"
|
||||
register "PcieRpLtrEnable[10]" = "1"
|
||||
register "PcieClkSrcUsage[1]" = "10"
|
||||
register "PcieClkSrcClkReq[1]" = "1"
|
||||
end
|
||||
device ref pch_espi on
|
||||
# LPC configuration from lspci -s 1f.0 -xxx
|
||||
# Address 0x84: Decode 0x80 - 0x8F (Port 80)
|
||||
register "gen1_dec" = "0x000c0081"
|
||||
# Address 0x88: Decode 0x68 - 0x6F (PMC)
|
||||
register "gen2_dec" = "0x00040069"
|
||||
# Address 0x8C: Decode 0xE00 - 0xEFF (AP/EC command)
|
||||
register "gen3_dec" = "0x00fc0E01"
|
||||
# Address 0x90: Decode 0xF00 - 0xFFF (AP/EC debug)
|
||||
register "gen4_dec" = "0x00fc0F01"
|
||||
# LPC TPM
|
||||
chip drivers/pc80/tpm
|
||||
device pnp 0c31.0 on end
|
||||
end
|
||||
end
|
||||
device pci 1f.1 on end # P2SB 0xA0A0
|
||||
device pci 1f.2 hidden # PMC 0xA0A1
|
||||
# TODO: verify
|
||||
# The pmc_mux chip driver is a placeholder for the
|
||||
# PMC.MUX device in the ACPI hierarchy.
|
||||
# chip drivers/intel/pmc_mux
|
||||
# device generic 0 on
|
||||
# chip drivers/intel/pmc_mux/conn
|
||||
# register "usb2_port_number" = "2"
|
||||
# register "usb3_port_number" = "2"
|
||||
# # SBU is fixed, HSL follows CC
|
||||
# register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
|
||||
# device generic 0 on end
|
||||
# end
|
||||
# chip drivers/intel/pmc_mux/conn
|
||||
# register "usb2_port_number" = "6"
|
||||
# register "usb3_port_number" = "4"
|
||||
# # SBU is fixed, HSL follows CC
|
||||
# register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
|
||||
# device generic 1 on end
|
||||
# end
|
||||
# end
|
||||
# end
|
||||
end # PMC
|
||||
device pci 1f.3 on end # Intel HD audio 0xA0C8-A0CF
|
||||
device pci 1f.4 on end # SMBus 0xA0A3
|
||||
device pci 1f.5 on end # SPI 0xA0A4
|
||||
device pci 1f.6 off end # GbE 0x15E1/0x15E2
|
||||
device pci 1f.7 off end # TH 0xA0A6
|
||||
device ref p2sb on end
|
||||
device ref hda on
|
||||
register "PchHdaAudioLinkHdaEnable" = "1"
|
||||
end
|
||||
device ref smbus on
|
||||
register "SmbusEnable" = "1"
|
||||
end
|
||||
device ref fast_spi end
|
||||
end
|
||||
end
|
||||
|
||||
Reference in New Issue
Block a user