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WIP: Reorganize devicetree

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Change-Id: Ia17916de8794077e57ce7fd04464e99d3751479d
This commit is contained in:
Jeremy Soller
2020-11-19 12:09:40 -07:00
parent cf36cd8f13
commit 7d302de633
1 changed files with 131 additions and 238 deletions
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367
src/mainboard/system76/galp5/devicetree.cb
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@@ -34,51 +34,18 @@ chip soc/intel/tigerlake
.tdp_pl2_override = 60, .tdp_pl2_override = 60,
}" }"
# eSPI (soc/intel/tigerlake/espi.c)
# LPC configuration from lspci -s 1f.0 -xxx
# Address 0x84: Decode 0x80 - 0x8F (Port 80)
register "gen1_dec" = "0x000c0081"
# Address 0x88: Decode 0x68 - 0x6F (PMC)
register "gen2_dec" = "0x00040069"
# Address 0x8C: Decode 0xE00 - 0xEFF (AP/EC command)
register "gen3_dec" = "0x00fc0E01"
# Address 0x90: Decode 0xF00 - 0xFFF (AP/EC debug)
register "gen4_dec" = "0x00fc0F01"
# Finalize (soc/intel/tigerlake/finalize.c) # Finalize (soc/intel/tigerlake/finalize.c)
# PM Timer Disabled, saves power # PM Timer Disabled, saves power
register "PmTimerDisabled" = "1" register "PmTimerDisabled" = "1"
# FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c) # FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c)
# DDIA is eDP
register "DdiPortAConfig" = "1"
register "DdiPortAHpd" = "1"
register "DdiPortADdc" = "0"
# DDIB is HDMI
register "DdiPortBConfig" = "0"
register "DdiPortBHpd" = "1"
register "DdiPortBDdc" = "1"
# Enable C6 DRAM # Enable C6 DRAM
register "enable_c6dram" = "1" register "enable_c6dram" = "1"
# High Definition Audio
register "PchHdaAudioLinkHdaEnable" = "1"
# System Agent dynamic frequency support # System Agent dynamic frequency support
register "SaGv" = "SaGv_Enabled" register "SaGv" = "SaGv_Enabled"
# Enable SMBus
register "SmbusEnable" = "1"
# TCSS USB3
register "TcssXhciEn" = "1"
# FSP Silicon (soc/intel/tigerlake/fsp_params.c) # FSP Silicon (soc/intel/tigerlake/fsp_params.c)
# Enable DPTF device
register "Device4Enable" = "1"
# FIVR configuration # FIVR configuration
# Read EXT_RAIL_CONFIG to determine bitmaps # Read EXT_RAIL_CONFIG to determine bitmaps
# sudo devmem2 0xfe0011b8 # sudo devmem2 0xfe0011b8
@@ -125,108 +92,10 @@ chip soc/intel/tigerlake
LPM_S0i3_4 LPM_S0i3_4
" "
# I2C channels
register "SerialIoI2cMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci, // Touchpad I2C bus
[PchSerialIoIndexI2C1] = PchSerialIoPci, // TODO: USB-PD?
[PchSerialIoIndexI2C2] = PchSerialIoPci, // TODO: Pantone ROM
[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
}"
# SPI channels
register "SerialIoGSpiMode" = "{
[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
[PchSerialIoIndexGSPI3] = PchSerialIoDisabled,
}"
#TODO: GSpiCsMode and GSpiCsState ?
# UART channels
register "SerialIoUartMode" = "{
[PchSerialIoIndexUART0] = PchSerialIoDisabled,
[PchSerialIoIndexUART1] = PchSerialIoDisabled,
[PchSerialIoIndexUART2] = PchSerialIoPci, // Debug console
}"
# USB2
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB Type-A Port 1 TODO
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB Type-C Port 2 TODO
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB Type-A Port 3 TODO
register "usb2_ports[3]" = "USB2_PORT_EMPTY"
register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB Type-C Port 4 TODO
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Camera
register "usb2_ports[7]" = "USB2_PORT_EMPTY"
register "usb2_ports[8]" = "USB2_PORT_EMPTY"
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
# USB3
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB Type-A Port 1 TODO
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB Type-C Port 2 TODO
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB Type-A Port 3 TODO
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB Type-C Port 4 TODO
# PCIe root ports:
# PCIe 4 x4 - SSD1
# 5 x4 - DGPU
# 9 x1 - CARD
# 10 x1 - GLAN
# 11 x1 - WLAN
# PCIe clocks:
# 0 - SSD1
# 1 - WLAN
# 2 - DGPU
# 3 - CARD
# 4 - GLAN
# PCIe PEG0 x4, Clock 0 (SSD1)
register "PcieClkSrcUsage[0]" = "0x40"
register "PcieClkSrcClkReq[0]" = "0"
# PCIe root port #5 x4, Clock 2 (NVIDIA GPU)
register "PcieRpEnable[4]" = "1"
register "PcieRpLtrEnable[4]" = "1"
register "PcieClkSrcUsage[2]" = "4"
register "PcieClkSrcClkReq[2]" = "2"
# PCIe root port #9 x1, Clock 3 (Card Reader)
register "PcieRpEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "PcieClkSrcUsage[3]" = "8"
register "PcieClkSrcClkReq[3]" = "3"
# PCIe root port #10 x1, Clock 4 (GLAN)
register "PcieRpEnable[9]" = "1"
register "PcieRpLtrEnable[9]" = "1"
register "PcieClkSrcUsage[4]" = "9"
register "PcieClkSrcClkReq[4]" = "4"
# PCIe root port #11 x1, Clock 1 (WLAN)
register "PcieRpEnable[10]" = "1"
register "PcieRpLtrEnable[10]" = "1"
register "PcieClkSrcUsage[1]" = "10"
register "PcieClkSrcClkReq[1]" = "1"
# Thermal # Thermal
# rdmsr --bitfield 31:24 --decimal 0x1A2 # rdmsr --bitfield 31:24 --decimal 0x1A2
register "tcc_offset" = "13" register "tcc_offset" = "13"
# Graphics (soc/intel/tigerlake/graphics.c)
register "gfx" = "GMA_STATIC_DISPLAYS(0)"
# PMC (soc/intel/tigerlake/pmc.c)
# Disable deep Sx states
register "deep_s3_enable_ac" = "0"
register "deep_s3_enable_dc" = "0"
register "deep_s5_enable_ac" = "0"
register "deep_s5_enable_dc" = "0"
register "deep_sx_config" = "0"
# PM Util (soc/intel/tigerlake/pmutil.c) # PM Util (soc/intel/tigerlake/pmutil.c)
# GPE configuration # GPE configuration
# sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG) # sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
@@ -235,67 +104,89 @@ chip soc/intel/tigerlake
register "pmc_gpe0_dw1" = "PMC_GPP_R" register "pmc_gpe0_dw1" = "PMC_GPP_R"
register "pmc_gpe0_dw2" = "PMC_GPD" register "pmc_gpe0_dw2" = "PMC_GPD"
# SMI Handler (soc/intel/tigerlake/smihandler.c)
#TODO Disable HECI
register "HeciEnabled" = "1"
# Actual device tree # Actual device tree
device cpu_cluster 0 on device cpu_cluster 0 on
device lapic 0 on end device lapic 0 on end
end end
#TODO: Adjustments
device domain 0 on device domain 0 on
#From EDS(575683) #From CPU EDS(575683)
device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y device ref system_agent on end
device pci 02.0 on end # Graphics device ref igpu on
device pci 04.0 on end # DPTF 0x9A03 # DDIA is eDP
device pci 05.0 off end # IPU 0x9A19 register "DdiPortAConfig" = "1"
device pci 06.0 on register "DdiPortAHpd" = "1"
chip soc/intel/common/block/pcie/rtd3 register "DdiPortADdc" = "0"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD1_PWR_DN#
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" # GPP_H0_RTD3 # DDIB is HDMI
#TODO: Support disable/enable CPU RP clock register "DdiPortBConfig" = "0"
register "srcclk_pin" = "-1" # SSD1_CLKREQ# register "DdiPortBHpd" = "1"
device generic 0 on end register "DdiPortBDdc" = "1"
register "gfx" = "GMA_STATIC_DISPLAYS(0)"
end end
end # PEG60 0x9A09 device ref dptf on
device pci 07.0 on end # TBT_PCIe0 0x9A23 # Enable DPTF device
device pci 07.1 off end # TBT_PCIe1 0x9A25 register "Device4Enable" = "1"
device pci 07.2 off end # TBT_PCIe2 0x9A27 end
device pci 07.3 off end # TBT_PCIe3 0x9A29 device ref peg on
device pci 08.0 on end # GNA 0x9A11 # PCIe PEG0 x4, Clock 0 (SSD1)
device pci 09.0 off end # NPK 0x9A33 register "PcieClkSrcUsage[0]" = "0x40"
device pci 0a.0 on end # Crash-log SRAM 0x9A0D register "PcieClkSrcClkReq[0]" = "0"
device pci 0d.0 on end # USB xHCI 0x9A13 #TODO: causes failure on resume
device pci 0d.1 off end # USB xDCI (OTG) 0x9A15 # chip soc/intel/common/block/pcie/rtd3
device pci 0d.2 on # register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD1_PWR_DN#
# register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" # GPP_H0_RTD3
# #TODO: Support disable/enable CPU RP clock
# register "srcclk_pin" = "-1" # SSD1_CLKREQ#
# device generic 0 on end
# end
end
device ref tbt_pcie_rp0 on end # J_TYPEC2
device ref gna on end
device ref chrashlog on end # TODO: purpose?
device ref north_xhci on # J_TYPEC2
register "TcssXhciEn" = "1"
# TODO: usb/acpi
end
device ref tbt_dma0 on
chip drivers/intel/usb4/retimer chip drivers/intel/usb4/retimer
register "power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A23)" register "power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A23)"
device generic 0 on end device generic 0 on end
end end
end # TBT DMA0 0x9A1B end
device pci 0d.3 off end # TBT DMA1 0x9A1D
device pci 0e.0 off end # VMD 0x9A0B
# From PCH EDS(576591) # From PCH EDS(576591)
device pci 10.2 on end # CNVi: BT 0xA0F5 - A0F7 device ref cnvi_bt on end
device pci 10.6 off end # THC0 0xA0D0 device ref south_xhci on
device pci 10.7 off end # THC1 0xA0D1 # USB2
device pci 12.0 off end # SensorHUB 0xA0FC register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # J_USB3_2
device pci 12.6 off end # GSPI2 0x34FB register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC1
device pci 13.0 off end # GSPI3 0xA0FD register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # J_USB3_1
device pci 14.0 on end # USB3.1 xHCI 0xA0ED register "usb2_ports[3]" = "USB2_PORT_EMPTY"
device pci 14.1 off end # USB3.1 xDCI 0xA0EE register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
device pci 14.2 on end # Shared RAM 0xA0EF register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC2
device pci 14.3 on register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Camera
register "usb2_ports[7]" = "USB2_PORT_EMPTY"
register "usb2_ports[8]" = "USB2_PORT_EMPTY"
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
# USB3
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_USB3_2
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1 Channel 0
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_USB3_1
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1 Channel 0
# TODO: usb/acpi
end
device ref shared_ram on end
device ref cnvi_wifi on
chip drivers/wifi/generic chip drivers/wifi/generic
register "wake" = "GPE0_PME_B0" register "wake" = "GPE0_PME_B0"
device generic 0 on end device generic 0 on end
end end
end # CNVi: WiFi 0xA0F0 - A0F3 end
device ref i2c0 on
device pci 15.0 on # I2C0 0xA0E8 # Touchpad I2C bus
register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
chip drivers/i2c/hid chip drivers/i2c/hid
register "generic.hid" = ""PNP0C50"" register "generic.hid" = ""PNP0C50""
register "generic.desc" = ""TODO Touchpad"" register "generic.desc" = ""TODO Touchpad""
@@ -304,37 +195,49 @@ chip soc/intel/tigerlake
register "hid_desc_reg_offset" = "0x01" register "hid_desc_reg_offset" = "0x01"
device i2c 38 on end device i2c 38 on end
end end
end # I2C0 end
device pci 15.1 on end # I2C1 0xA0E9 device ref i2c1 on
device pci 15.2 on end # I2C2 0xA0EA #TODO: USB-PD?
device pci 15.3 off end # I2C3 0xA0EB register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
device pci 16.0 on end # HECI1 0xA0E0 end
device pci 16.1 off end # HECI2 0xA0E1 device ref i2c2 on
device pci 16.2 off end # CSME 0xA0E2 #TODO: Pantone ROM?
device pci 16.3 off end # CSME 0xA0E3 register "SerialIoI2cMode[PchSerialIoIndexI2C2]" = "PchSerialIoPci"
device pci 16.4 off end # HECI3 0xA0E4 end
device pci 16.5 off end # HECI4 0xA0E5 device rev heci1 on
device pci 17.0 off end # SATA 0xA0D3 #TODO Disable ME and HECI
device pci 19.0 off end # I2C4 0xA0C5 register "HeciEnabled" = "1"
device pci 19.1 off end # I2C5 0xA0C6 end
device pci 19.2 on end # UART2 0xA0C7 device ref uart2 on
device pci 1c.0 off end # RP1 0xA0B8 # Debug console
device pci 1c.1 off end # RP2 0xA0B9 register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoPci"
device pci 1c.2 off end # RP3 0xA0BA end
device pci 1c.3 off end # RP4 0xA0BB device ref pcie_rp5 on
device pci 1c.4 on # PCIe root port #5 x4, Clock 2 (NVIDIA GPU)
register "PcieRpEnable[4]" = "1"
register "PcieRpLtrEnable[4]" = "1"
register "PcieClkSrcUsage[2]" = "4"
register "PcieClkSrcClkReq[2]" = "2"
chip soc/intel/common/block/pcie/rtd3 chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_U5)" # DGPU_PWR_EN register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_U5)" # DGPU_PWR_EN
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_U4)" # DGPU_RST#_PCH register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_U4)" # DGPU_RST#_PCH
register "srcclk_pin" = "2" # PEG_CLKREQ# register "srcclk_pin" = "2" # PEG_CLKREQ#
device generic 0 on end device generic 0 on end
end end
end # RP5 0xA0BC end
device pci 1c.5 off end # RP6 0xA0BD device ref pcie_rp9 on
device pci 1c.6 off end # RP7 0xA0BE # PCIe root port #9 x1, Clock 3 (Card Reader)
device pci 1c.7 off end # RP8 0xA0BF register "PcieRpEnable[8]" = "1"
device pci 1d.0 on end # RP9 0xA0B0 register "PcieRpLtrEnable[8]" = "1"
device pci 1d.1 on register "PcieClkSrcUsage[3]" = "8"
register "PcieClkSrcClkReq[3]" = "3"
end
device ref pcie_rp10 on
# PCIe root port #10 x1, Clock 4 (GLAN)
register "PcieRpEnable[9]" = "1"
register "PcieRpLtrEnable[9]" = "1"
register "PcieClkSrcUsage[4]" = "9"
register "PcieClkSrcClkReq[4]" = "4"
chip soc/intel/common/block/pcie/rtd3 chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F9)" # GPIO_LAN_EN register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F9)" # GPIO_LAN_EN
#TODO: should this be GPIO_LANRTD3 or LAN_PLT_RST# ? #TODO: should this be GPIO_LANRTD3 or LAN_PLT_RST# ?
@@ -342,46 +245,36 @@ chip soc/intel/tigerlake
register "srcclk_pin" = "4" # LAN_CLKREQ# register "srcclk_pin" = "4" # LAN_CLKREQ#
device generic 0 on end device generic 0 on end
end end
end # RP10 0xA0B1 end
device pci 1d.2 on end # RP11 0xA0B2 device ref pcie_rp11 on
device pci 1d.3 off end # RP12 0xA0B3 # PCIe root port #11 x1, Clock 1 (WLAN)
device pci 1e.0 off end # UART0 0xA0A8 register "PcieRpEnable[10]" = "1"
device pci 1e.1 off end # UART1 0xA0A9 register "PcieRpLtrEnable[10]" = "1"
device pci 1e.2 off end # GSPI0 0xA0AA register "PcieClkSrcUsage[1]" = "10"
device pci 1e.3 off end # GSPI1 0xA0AB register "PcieClkSrcClkReq[1]" = "1"
device pci 1f.0 on # eSPI 0xA080 - A09F end
device ref pch_espi on
# LPC configuration from lspci -s 1f.0 -xxx
# Address 0x84: Decode 0x80 - 0x8F (Port 80)
register "gen1_dec" = "0x000c0081"
# Address 0x88: Decode 0x68 - 0x6F (PMC)
register "gen2_dec" = "0x00040069"
# Address 0x8C: Decode 0xE00 - 0xEFF (AP/EC command)
register "gen3_dec" = "0x00fc0E01"
# Address 0x90: Decode 0xF00 - 0xFFF (AP/EC debug)
register "gen4_dec" = "0x00fc0F01"
# LPC TPM
chip drivers/pc80/tpm chip drivers/pc80/tpm
device pnp 0c31.0 on end device pnp 0c31.0 on end
end end
end end
device pci 1f.1 on end # P2SB 0xA0A0 device ref p2sb on end
device pci 1f.2 hidden # PMC 0xA0A1 device ref hda on
# TODO: verify register "PchHdaAudioLinkHdaEnable" = "1"
# The pmc_mux chip driver is a placeholder for the end
# PMC.MUX device in the ACPI hierarchy. device ref smbus on
# chip drivers/intel/pmc_mux register "SmbusEnable" = "1"
# device generic 0 on end
# chip drivers/intel/pmc_mux/conn device ref fast_spi end
# register "usb2_port_number" = "2"
# register "usb3_port_number" = "2"
# # SBU is fixed, HSL follows CC
# register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
# device generic 0 on end
# end
# chip drivers/intel/pmc_mux/conn
# register "usb2_port_number" = "6"
# register "usb3_port_number" = "4"
# # SBU is fixed, HSL follows CC
# register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
# device generic 1 on end
# end
# end
# end
end # PMC
device pci 1f.3 on end # Intel HD audio 0xA0C8-A0CF
device pci 1f.4 on end # SMBus 0xA0A3
device pci 1f.5 on end # SPI 0xA0A4
device pci 1f.6 off end # GbE 0x15E1/0x15E2
device pci 1f.7 off end # TH 0xA0A6
end end
end end