AGESA F15tn: AMD family15 AGESA code for Trinity
AMD AGESA code for trinity. Change-Id: I847a54b15e8ce03ad5dbc17b95ee6771a9da0592 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1155 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
zbao
Patrick Georgi
parent
78efc4c36c
commit
7d94cf93ee
@ -2,3 +2,4 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY10) += f10
|
||||
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += f12
|
||||
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += f14
|
||||
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15) += f15
|
||||
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) += f15tn
|
||||
|
||||
3718
src/vendorcode/amd/agesa/f15tn/AGESA.h
Normal file
3718
src/vendorcode/amd/agesa/f15tn/AGESA.h
Normal file
File diff suppressed because it is too large
Load Diff
506
src/vendorcode/amd/agesa/f15tn/AMD.h
Normal file
506
src/vendorcode/amd/agesa/f15tn/AMD.h
Normal file
@ -0,0 +1,506 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* Agesa structures and definitions
|
||||
*
|
||||
* Contains AMD AGESA core interface
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: Include
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
|
||||
#ifndef _AMD_H_
|
||||
#define _AMD_H_
|
||||
|
||||
#define AGESA_REVISION "Arch2008"
|
||||
#define AGESA_ID "AGESA"
|
||||
|
||||
#define Int16FromChar(a,b) ((a) << 0 | (b) << 8)
|
||||
#define Int32FromChar(a,b,c,d) ((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24)
|
||||
//
|
||||
//
|
||||
// AGESA Types and Definitions
|
||||
//
|
||||
//
|
||||
#define LAST_ENTRY 0xFFFFFFFF
|
||||
#define IMAGE_SIGNATURE Int32FromChar ('$', 'A', 'M', 'D')
|
||||
#define IOCF8 0xCF8
|
||||
#define IOCFC 0xCFC
|
||||
|
||||
/// The return status for all AGESA public services.
|
||||
///
|
||||
/// Services return the most severe status of any logged event. Status other than SUCCESS, UNSUPPORTED, and BOUNDS_CHK
|
||||
/// will have log entries with more detail.
|
||||
///
|
||||
typedef enum {
|
||||
AGESA_SUCCESS = 0, ///< The service completed normally. Info may be logged.
|
||||
AGESA_UNSUPPORTED, ///< The dispatcher or create struct had an unimplemented function requested.
|
||||
///< Not logged.
|
||||
AGESA_BOUNDS_CHK, ///< A dynamic parameter was out of range and the service was not provided.
|
||||
///< Example, memory address not installed, heap buffer handle not found.
|
||||
///< Not Logged.
|
||||
// AGESA_STATUS of greater severity (the ones below this line), always have a log entry available.
|
||||
AGESA_ALERT, ///< An observed condition, but no loss of function.
|
||||
///< See log. Example, HT CRC.
|
||||
AGESA_WARNING, ///< Possible or minor loss of function. See Log.
|
||||
AGESA_ERROR, ///< Significant loss of function, boot may be possible. See Log.
|
||||
AGESA_CRITICAL, ///< Continue boot only to notify user. See Log.
|
||||
AGESA_FATAL, ///< Halt booting. See Log, however Fatal errors pertaining to heap problems
|
||||
///< may not be able to reliably produce log events.
|
||||
AgesaStatusMax ///< Not a status, for limit checking.
|
||||
} AGESA_STATUS;
|
||||
|
||||
/// For checking whether a status is at or above the mandatory log level.
|
||||
#define AGESA_STATUS_LOG_LEVEL AGESA_ALERT
|
||||
|
||||
/**
|
||||
* Callout method to the host environment.
|
||||
*
|
||||
* Callout using a dispatch with appropriate thunk layer, which is determined by the host environment.
|
||||
*
|
||||
* @param[in] Function The specific callout function being invoked.
|
||||
* @param[in] FcnData Function specific data item.
|
||||
* @param[in,out] ConfigPtr Reference to Callout params.
|
||||
*/
|
||||
typedef AGESA_STATUS (*CALLOUT_ENTRY) (
|
||||
IN UINT32 Function,
|
||||
IN UINTN FcnData,
|
||||
IN OUT VOID *ConfigPtr
|
||||
);
|
||||
|
||||
typedef AGESA_STATUS (*IMAGE_ENTRY) (VOID *ConfigPtr);
|
||||
typedef AGESA_STATUS (*MODULE_ENTRY) (VOID *ConfigPtr);
|
||||
|
||||
///This allocation type is used by the AmdCreateStruct entry point
|
||||
typedef enum {
|
||||
PreMemHeap = 0, ///< Create heap in cache.
|
||||
PostMemDram, ///< Create heap in memory.
|
||||
ByHost ///< Create heap by Host.
|
||||
} ALLOCATION_METHOD;
|
||||
|
||||
/// These width descriptors are used by the library function, and others, to specify the data size
|
||||
typedef enum ACCESS_WIDTH {
|
||||
AccessWidth8 = 1, ///< Access width is 8 bits.
|
||||
AccessWidth16, ///< Access width is 16 bits.
|
||||
AccessWidth32, ///< Access width is 32 bits.
|
||||
AccessWidth64, ///< Access width is 64 bits.
|
||||
|
||||
AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data.
|
||||
AccessS3SaveWidth16, ///< Save 16 bits data.
|
||||
AccessS3SaveWidth32, ///< Save 32 bits data.
|
||||
AccessS3SaveWidth64, ///< Save 64 bits data.
|
||||
} ACCESS_WIDTH;
|
||||
|
||||
/// AGESA struct name
|
||||
typedef enum {
|
||||
// AGESA BASIC FUNCTIONS
|
||||
AMD_INIT_RECOVERY = 0x00020000, ///< AmdInitRecovery entry point handle
|
||||
AMD_CREATE_STRUCT, ///< AmdCreateStruct handle
|
||||
AMD_INIT_EARLY, ///< AmdInitEarly entry point handle
|
||||
AMD_INIT_ENV, ///< AmdInitEnv entry point handle
|
||||
AMD_INIT_LATE, ///< AmdInitLate entry point handle
|
||||
AMD_INIT_MID, ///< AmdInitMid entry point handle
|
||||
AMD_INIT_POST, ///< AmdInitPost entry point handle
|
||||
AMD_INIT_RESET, ///< AmdInitReset entry point handle
|
||||
AMD_INIT_RESUME, ///< AmdInitResume entry point handle
|
||||
AMD_RELEASE_STRUCT, ///< AmdReleaseStruct handle
|
||||
AMD_S3LATE_RESTORE, ///< AmdS3LateRestore entry point handle
|
||||
AMD_S3_SAVE, ///< AmdS3Save entry point handle
|
||||
AMD_GET_APIC_ID, ///< AmdGetApicId entry point handle
|
||||
AMD_GET_PCI_ADDRESS, ///< AmdGetPciAddress entry point handle
|
||||
AMD_IDENTIFY_CORE, ///< AmdIdentifyCore general service handle
|
||||
AMD_READ_EVENT_LOG, ///< AmdReadEventLog general service handle
|
||||
AMD_GET_EXECACHE_SIZE, ///< AmdGetAvailableExeCacheSize general service handle
|
||||
AMD_LATE_RUN_AP_TASK, ///< AmdLateRunApTask entry point handle
|
||||
AMD_IDENTIFY_DIMMS ///< AmdIdentifyDimm general service handle
|
||||
} AGESA_STRUCT_NAME;
|
||||
|
||||
/* ResetType constant values */
|
||||
#define WARM_RESET_WHENEVER 1
|
||||
#define COLD_RESET_WHENEVER 2
|
||||
#define WARM_RESET_IMMEDIATELY 3
|
||||
#define COLD_RESET_IMMEDIATELY 4
|
||||
|
||||
|
||||
// AGESA Structures
|
||||
|
||||
/// The standard header for all AGESA services.
|
||||
/// For internal AGESA naming conventions, see @ref amdconfigparamname .
|
||||
typedef struct {
|
||||
IN UINT32 ImageBasePtr; ///< The AGESA Image base address.
|
||||
IN UINT32 Func; ///< The service desired
|
||||
IN UINT32 AltImageBasePtr; ///< Alternate Image location
|
||||
IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA
|
||||
IN UINT8 HeapStatus; ///< For heap status from boot time slide.
|
||||
IN UINT64 HeapBasePtr; ///< Location of the heap
|
||||
IN OUT UINT8 Reserved[7]; ///< This space is reserved for future use.
|
||||
} AMD_CONFIG_PARAMS;
|
||||
|
||||
|
||||
/// Create Struct Interface.
|
||||
typedef struct {
|
||||
IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
|
||||
IN AGESA_STRUCT_NAME AgesaFunctionName; ///< The service to init
|
||||
IN ALLOCATION_METHOD AllocationMethod; ///< How to handle buffer allocation
|
||||
IN OUT UINT32 NewStructSize; ///< The size of the allocated data, in for ByHost, else out only.
|
||||
IN OUT VOID *NewStructPtr; ///< The struct for the service.
|
||||
///< The struct to init for ByHost allocation,
|
||||
///< the initialized struct on return.
|
||||
} AMD_INTERFACE_PARAMS;
|
||||
|
||||
#define FUNC_0 0 // bit-placed for PCI address creation
|
||||
#define FUNC_1 1
|
||||
#define FUNC_2 2
|
||||
#define FUNC_3 3
|
||||
#define FUNC_4 4
|
||||
#define FUNC_5 5
|
||||
#define FUNC_6 6
|
||||
#define FUNC_7 7
|
||||
|
||||
/// AGESA Binary module header structure
|
||||
typedef struct {
|
||||
IN UINT32 Signature; ///< Binary Signature
|
||||
IN CHAR8 CreatorID[8]; ///< 8 characters ID
|
||||
IN CHAR8 Version[12]; ///< 12 characters version
|
||||
IN UINT32 ModuleInfoOffset; ///< Offset of module
|
||||
IN UINT32 EntryPointAddress; ///< Entry address
|
||||
IN UINT32 ImageBase; ///< Image base
|
||||
IN UINT32 RelocTableOffset; ///< Relocate Table offset
|
||||
IN UINT32 ImageSize; ///< Size
|
||||
IN UINT16 Checksum; ///< Checksum
|
||||
IN UINT8 ImageType; ///< Type
|
||||
IN UINT8 V_Reserved; ///< Reserved
|
||||
} AMD_IMAGE_HEADER;
|
||||
/// AGESA Binary module header structure
|
||||
typedef struct _AMD_MODULE_HEADER {
|
||||
IN UINT32 ModuleHeaderSignature; ///< Module signature
|
||||
IN CHAR8 ModuleIdentifier[8]; ///< 8 characters ID
|
||||
IN CHAR8 ModuleVersion[12]; ///< 12 characters version
|
||||
IN VOID *ModuleDispatcher; ///< A pointer point to dispatcher
|
||||
IN struct _AMD_MODULE_HEADER *NextBlock; ///< Next module header link
|
||||
} AMD_MODULE_HEADER;
|
||||
|
||||
// AMD_CODE_HEADER Signatures.
|
||||
#define AGESA_CODE_SIGNATURE {'!', '!', 'A', 'G', 'E', 'S', 'A', ' '}
|
||||
#define CIMXNB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'N', 'B'}
|
||||
#define CIMXSB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'S', 'B'}
|
||||
|
||||
/// AGESA_CODE_SIGNATURE
|
||||
typedef struct {
|
||||
IN CHAR8 Signature[8]; ///< code header Signature
|
||||
IN CHAR8 ComponentName[8]; ///< 8 character name of the code module
|
||||
IN CHAR8 Version[12]; ///< 12 character version string
|
||||
IN CHAR8 TerminatorNull; ///< null terminated string
|
||||
IN CHAR8 VerReserved[7]; ///< reserved space
|
||||
} AMD_CODE_HEADER;
|
||||
|
||||
/// Extended PCI address format
|
||||
typedef struct {
|
||||
IN OUT UINT32 Register:12; ///< Register offset
|
||||
IN OUT UINT32 Function:3; ///< Function number
|
||||
IN OUT UINT32 Device:5; ///< Device number
|
||||
IN OUT UINT32 Bus:8; ///< Bus number
|
||||
IN OUT UINT32 Segment:4; ///< Segment
|
||||
} EXT_PCI_ADDR;
|
||||
|
||||
/// Union type for PCI address
|
||||
typedef union _PCI_ADDR {
|
||||
IN UINT32 AddressValue; ///< Formal address
|
||||
IN EXT_PCI_ADDR Address; ///< Extended address
|
||||
} PCI_ADDR;
|
||||
|
||||
// SBDFO - Segment Bus Device Function Offset
|
||||
// 31:28 Segment (4-bits)
|
||||
// 27:20 Bus (8-bits)
|
||||
// 19:15 Device (5-bits)
|
||||
// 14:12 Function(3-bits)
|
||||
// 11:00 Offset (12-bits)
|
||||
|
||||
#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((UINT32) (Seg)) << 28) | (((UINT32) (Bus)) << 20) | \
|
||||
(((UINT32)(Dev)) << 15) | (((UINT32)(Fun)) << 12) | ((UINT32)(Off)))
|
||||
#define ILLEGAL_SBDFO 0xFFFFFFFF
|
||||
|
||||
/// CPUID data received registers format
|
||||
typedef struct {
|
||||
OUT UINT32 EAX_Reg; ///< CPUID instruction result in EAX
|
||||
OUT UINT32 EBX_Reg; ///< CPUID instruction result in EBX
|
||||
OUT UINT32 ECX_Reg; ///< CPUID instruction result in ECX
|
||||
OUT UINT32 EDX_Reg; ///< CPUID instruction result in EDX
|
||||
} CPUID_DATA;
|
||||
|
||||
/// HT frequency for external callbacks
|
||||
typedef enum {
|
||||
HT_FREQUENCY_200M = 0, ///< HT speed 200 for external callbacks
|
||||
HT_FREQUENCY_400M = 2, ///< HT speed 400 for external callbacks
|
||||
HT_FREQUENCY_600M = 4, ///< HT speed 600 for external callbacks
|
||||
HT_FREQUENCY_800M = 5, ///< HT speed 800 for external callbacks
|
||||
HT_FREQUENCY_1000M = 6, ///< HT speed 1000 for external callbacks
|
||||
HT_FREQUENCY_1200M = 7, ///< HT speed 1200 for external callbacks
|
||||
HT_FREQUENCY_1400M = 8, ///< HT speed 1400 for external callbacks
|
||||
HT_FREQUENCY_1600M = 9, ///< HT speed 1600 for external callbacks
|
||||
HT_FREQUENCY_1800M = 10, ///< HT speed 1800 for external callbacks
|
||||
HT_FREQUENCY_2000M = 11, ///< HT speed 2000 for external callbacks
|
||||
HT_FREQUENCY_2200M = 12, ///< HT speed 2200 for external callbacks
|
||||
HT_FREQUENCY_2400M = 13, ///< HT speed 2400 for external callbacks
|
||||
HT_FREQUENCY_2600M = 14, ///< HT speed 2600 for external callbacks
|
||||
HT_FREQUENCY_2800M = 17, ///< HT speed 2800 for external callbacks
|
||||
HT_FREQUENCY_3000M = 18, ///< HT speed 3000 for external callbacks
|
||||
HT_FREQUENCY_3200M = 19, ///< HT speed 3200 for external callbacks
|
||||
HT_FREQUENCY_MAX ///< Limit check.
|
||||
} HT_FREQUENCIES;
|
||||
// The minimum HT3 frequency
|
||||
#define HT3_FREQUENCY_MIN HT_FREQUENCY_1200M
|
||||
|
||||
#ifndef BIT0
|
||||
#define BIT0 0x0000000000000001ull
|
||||
#endif
|
||||
#ifndef BIT1
|
||||
#define BIT1 0x0000000000000002ull
|
||||
#endif
|
||||
#ifndef BIT2
|
||||
#define BIT2 0x0000000000000004ull
|
||||
#endif
|
||||
#ifndef BIT3
|
||||
#define BIT3 0x0000000000000008ull
|
||||
#endif
|
||||
#ifndef BIT4
|
||||
#define BIT4 0x0000000000000010ull
|
||||
#endif
|
||||
#ifndef BIT5
|
||||
#define BIT5 0x0000000000000020ull
|
||||
#endif
|
||||
#ifndef BIT6
|
||||
#define BIT6 0x0000000000000040ull
|
||||
#endif
|
||||
#ifndef BIT7
|
||||
#define BIT7 0x0000000000000080ull
|
||||
#endif
|
||||
#ifndef BIT8
|
||||
#define BIT8 0x0000000000000100ull
|
||||
#endif
|
||||
#ifndef BIT9
|
||||
#define BIT9 0x0000000000000200ull
|
||||
#endif
|
||||
#ifndef BIT10
|
||||
#define BIT10 0x0000000000000400ull
|
||||
#endif
|
||||
#ifndef BIT11
|
||||
#define BIT11 0x0000000000000800ull
|
||||
#endif
|
||||
#ifndef BIT12
|
||||
#define BIT12 0x0000000000001000ull
|
||||
#endif
|
||||
#ifndef BIT13
|
||||
#define BIT13 0x0000000000002000ull
|
||||
#endif
|
||||
#ifndef BIT14
|
||||
#define BIT14 0x0000000000004000ull
|
||||
#endif
|
||||
#ifndef BIT15
|
||||
#define BIT15 0x0000000000008000ull
|
||||
#endif
|
||||
#ifndef BIT16
|
||||
#define BIT16 0x0000000000010000ull
|
||||
#endif
|
||||
#ifndef BIT17
|
||||
#define BIT17 0x0000000000020000ull
|
||||
#endif
|
||||
#ifndef BIT18
|
||||
#define BIT18 0x0000000000040000ull
|
||||
#endif
|
||||
#ifndef BIT19
|
||||
#define BIT19 0x0000000000080000ull
|
||||
#endif
|
||||
#ifndef BIT20
|
||||
#define BIT20 0x0000000000100000ull
|
||||
#endif
|
||||
#ifndef BIT21
|
||||
#define BIT21 0x0000000000200000ull
|
||||
#endif
|
||||
#ifndef BIT22
|
||||
#define BIT22 0x0000000000400000ull
|
||||
#endif
|
||||
#ifndef BIT23
|
||||
#define BIT23 0x0000000000800000ull
|
||||
#endif
|
||||
#ifndef BIT24
|
||||
#define BIT24 0x0000000001000000ull
|
||||
#endif
|
||||
#ifndef BIT25
|
||||
#define BIT25 0x0000000002000000ull
|
||||
#endif
|
||||
#ifndef BIT26
|
||||
#define BIT26 0x0000000004000000ull
|
||||
#endif
|
||||
#ifndef BIT27
|
||||
#define BIT27 0x0000000008000000ull
|
||||
#endif
|
||||
#ifndef BIT28
|
||||
#define BIT28 0x0000000010000000ull
|
||||
#endif
|
||||
#ifndef BIT29
|
||||
#define BIT29 0x0000000020000000ull
|
||||
#endif
|
||||
#ifndef BIT30
|
||||
#define BIT30 0x0000000040000000ull
|
||||
#endif
|
||||
#ifndef BIT31
|
||||
#define BIT31 0x0000000080000000ull
|
||||
#endif
|
||||
#ifndef BIT32
|
||||
#define BIT32 0x0000000100000000ull
|
||||
#endif
|
||||
#ifndef BIT33
|
||||
#define BIT33 0x0000000200000000ull
|
||||
#endif
|
||||
#ifndef BIT34
|
||||
#define BIT34 0x0000000400000000ull
|
||||
#endif
|
||||
#ifndef BIT35
|
||||
#define BIT35 0x0000000800000000ull
|
||||
#endif
|
||||
#ifndef BIT36
|
||||
#define BIT36 0x0000001000000000ull
|
||||
#endif
|
||||
#ifndef BIT37
|
||||
#define BIT37 0x0000002000000000ull
|
||||
#endif
|
||||
#ifndef BIT38
|
||||
#define BIT38 0x0000004000000000ull
|
||||
#endif
|
||||
#ifndef BIT39
|
||||
#define BIT39 0x0000008000000000ull
|
||||
#endif
|
||||
#ifndef BIT40
|
||||
#define BIT40 0x0000010000000000ull
|
||||
#endif
|
||||
#ifndef BIT41
|
||||
#define BIT41 0x0000020000000000ull
|
||||
#endif
|
||||
#ifndef BIT42
|
||||
#define BIT42 0x0000040000000000ull
|
||||
#endif
|
||||
#ifndef BIT43
|
||||
#define BIT43 0x0000080000000000ull
|
||||
#endif
|
||||
#ifndef BIT44
|
||||
#define BIT44 0x0000100000000000ull
|
||||
#endif
|
||||
#ifndef BIT45
|
||||
#define BIT45 0x0000200000000000ull
|
||||
#endif
|
||||
#ifndef BIT46
|
||||
#define BIT46 0x0000400000000000ull
|
||||
#endif
|
||||
#ifndef BIT47
|
||||
#define BIT47 0x0000800000000000ull
|
||||
#endif
|
||||
#ifndef BIT48
|
||||
#define BIT48 0x0001000000000000ull
|
||||
#endif
|
||||
#ifndef BIT49
|
||||
#define BIT49 0x0002000000000000ull
|
||||
#endif
|
||||
#ifndef BIT50
|
||||
#define BIT50 0x0004000000000000ull
|
||||
#endif
|
||||
#ifndef BIT51
|
||||
#define BIT51 0x0008000000000000ull
|
||||
#endif
|
||||
#ifndef BIT52
|
||||
#define BIT52 0x0010000000000000ull
|
||||
#endif
|
||||
#ifndef BIT53
|
||||
#define BIT53 0x0020000000000000ull
|
||||
#endif
|
||||
#ifndef BIT54
|
||||
#define BIT54 0x0040000000000000ull
|
||||
#endif
|
||||
#ifndef BIT55
|
||||
#define BIT55 0x0080000000000000ull
|
||||
#endif
|
||||
#ifndef BIT56
|
||||
#define BIT56 0x0100000000000000ull
|
||||
#endif
|
||||
#ifndef BIT57
|
||||
#define BIT57 0x0200000000000000ull
|
||||
#endif
|
||||
#ifndef BIT58
|
||||
#define BIT58 0x0400000000000000ull
|
||||
#endif
|
||||
#ifndef BIT59
|
||||
#define BIT59 0x0800000000000000ull
|
||||
#endif
|
||||
#ifndef BIT60
|
||||
#define BIT60 0x1000000000000000ull
|
||||
#endif
|
||||
#ifndef BIT61
|
||||
#define BIT61 0x2000000000000000ull
|
||||
#endif
|
||||
#ifndef BIT62
|
||||
#define BIT62 0x4000000000000000ull
|
||||
#endif
|
||||
#ifndef BIT63
|
||||
#define BIT63 0x8000000000000000ull
|
||||
#endif
|
||||
|
||||
#endif // _AMD_H_
|
||||
78
src/vendorcode/amd/agesa/f15tn/Dispatcher.h
Normal file
78
src/vendorcode/amd/agesa/f15tn/Dispatcher.h
Normal file
@ -0,0 +1,78 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* AMD Pushhigh Interface
|
||||
*
|
||||
* Contains interface to Pushhigh entry
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: Legacy
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
* ***************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef _DISPATCHER_H_
|
||||
#define _DISPATCHER_H_
|
||||
|
||||
// AGESA function prototypes
|
||||
AGESA_STATUS CALLCONV AmdAgesaDispatcher ( IN OUT VOID *ConfigPtr );
|
||||
AGESA_STATUS CALLCONV AmdAgesaCallout ( IN UINT32 Func, IN UINT32 Data, IN OUT VOID *ConfigPtr );
|
||||
|
||||
#endif // _DISPATCHER_H_
|
||||
193
src/vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h
Normal file
193
src/vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h
Normal file
@ -0,0 +1,193 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* Advanced API Interface for HT, Memory and CPU
|
||||
*
|
||||
* Contains additional declarations need to use HT, Memory and CPU Advanced interface, such as
|
||||
* would be required by the basic interface implementations.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: Include
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
|
||||
#ifndef _ADVANCED_API_H_
|
||||
#define _ADVANCED_API_H_
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* HT FUNCTIONS PROTOTYPE
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/**
|
||||
* A constructor for the HyperTransport input structure.
|
||||
*
|
||||
* Sets inputs to valid, basic level, defaults.
|
||||
*
|
||||
* @param[in] StdHeader Opaque handle to standard config header
|
||||
* @param[in] AmdHtInterface HT Interface structure to initialize.
|
||||
*
|
||||
* @retval AGESA_SUCCESS Constructors are not allowed to fail
|
||||
*/
|
||||
AGESA_STATUS
|
||||
AmdHtInterfaceConstructor (
|
||||
IN AMD_CONFIG_PARAMS *StdHeader,
|
||||
IN AMD_HT_INTERFACE *AmdHtInterface
|
||||
);
|
||||
|
||||
/**
|
||||
* The top level external interface for Hypertransport Initialization.
|
||||
*
|
||||
* Create our initial internal state, initialize the coherent fabric,
|
||||
* initialize the non-coherent chains, and perform any required fabric tuning or
|
||||
* optimization.
|
||||
*
|
||||
* @param[in] StdHeader Opaque handle to standard config header
|
||||
* @param[in] PlatformConfiguration The platform configuration options.
|
||||
* @param[in] AmdHtInterface HT Interface structure.
|
||||
*
|
||||
* @retval AGESA_SUCCESS Only information events logged.
|
||||
* @retval AGESA_ALERT Sync Flood or CRC error logged.
|
||||
* @retval AGESA_WARNING Example: expected capability not found
|
||||
* @retval AGESA_ERROR logged events indicating some devices may not be available
|
||||
* @retval AGESA_FATAL Mixed Family or MP capability mismatch
|
||||
*
|
||||
*/
|
||||
AGESA_STATUS
|
||||
AmdHtInitialize (
|
||||
IN AMD_CONFIG_PARAMS *StdHeader,
|
||||
IN PLATFORM_CONFIGURATION *PlatformConfiguration,
|
||||
IN AMD_HT_INTERFACE *AmdHtInterface
|
||||
);
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* HT Recovery FUNCTIONS PROTOTYPE
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/**
|
||||
* A constructor for the HyperTransport input structure.
|
||||
*
|
||||
*/
|
||||
AGESA_STATUS
|
||||
AmdHtResetConstructor (
|
||||
IN AMD_CONFIG_PARAMS *StdHeader,
|
||||
IN AMD_HT_RESET_INTERFACE *AmdHtResetInterface
|
||||
);
|
||||
|
||||
/**
|
||||
* Initialize HT at Reset for both Normal and Recovery.
|
||||
*
|
||||
*/
|
||||
AGESA_STATUS
|
||||
AmdHtInitReset (
|
||||
IN AMD_CONFIG_PARAMS *StdHeader,
|
||||
IN AMD_HT_RESET_INTERFACE *AmdHtResetInterface
|
||||
);
|
||||
|
||||
/**
|
||||
* Initialize the Node and Socket maps for an AP Core.
|
||||
*
|
||||
*/
|
||||
AGESA_STATUS
|
||||
AmdHtInitRecovery (
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
///----------------------------------------------------------------------------
|
||||
/// MEMORY FUNCTIONS PROTOTYPE
|
||||
///
|
||||
///----------------------------------------------------------------------------
|
||||
|
||||
AGESA_STATUS
|
||||
AmdMemRecovery (
|
||||
IN OUT MEM_DATA_STRUCT *MemPtr
|
||||
);
|
||||
|
||||
AGESA_STATUS
|
||||
AmdMemAuto (
|
||||
IN OUT MEM_DATA_STRUCT *MemPtr
|
||||
);
|
||||
|
||||
VOID
|
||||
AmdMemInitDataStructDef (
|
||||
IN OUT MEM_DATA_STRUCT *MemPtr,
|
||||
IN OUT PLATFORM_CONFIGURATION *PlatFormConfig
|
||||
);
|
||||
|
||||
VOID
|
||||
memDefRet ( VOID );
|
||||
|
||||
BOOLEAN
|
||||
memDefTrue ( VOID );
|
||||
|
||||
BOOLEAN
|
||||
memDefFalse ( VOID );
|
||||
|
||||
VOID
|
||||
MemRecDefRet ( VOID );
|
||||
|
||||
BOOLEAN
|
||||
MemRecDefTrue ( VOID );
|
||||
|
||||
#endif // _ADVANCED_API_H_
|
||||
186
src/vendorcode/amd/agesa/f15tn/Include/ComalInstall.h
Normal file
186
src/vendorcode/amd/agesa/f15tn/Include/ComalInstall.h
Normal file
@ -0,0 +1,186 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* Install of build options for a Comal platform solution
|
||||
*
|
||||
* This file generates the defaults tables for the "Comal" platform solution
|
||||
* set of processors. The documented build options are imported from a user
|
||||
* controlled file for processing.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: Core
|
||||
* @e \$Revision: 65876 $ @e \$Date: 2012-02-26 21:30:10 -0600 (Sun, 26 Feb 2012) $
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
#include "cpuRegisters.h"
|
||||
#include "cpuFamRegisters.h"
|
||||
#include "cpuFamilyTranslation.h"
|
||||
#include "AdvancedApi.h"
|
||||
#include "heapManager.h"
|
||||
#include "CreateStruct.h"
|
||||
#include "cpuFeatures.h"
|
||||
#include "Table.h"
|
||||
#include "CommonReturns.h"
|
||||
#include "cpuEarlyInit.h"
|
||||
#include "cpuLateInit.h"
|
||||
#include "GnbInterface.h"
|
||||
|
||||
/*****************************************************************************
|
||||
* Define the RELEASE VERSION string
|
||||
*
|
||||
* The Release Version string should identify the next planned release.
|
||||
* When a branch is made in preparation for a release, the release manager
|
||||
* should change/confirm that the branch version of this file contains the
|
||||
* string matching the desired version for the release. The trunk version of
|
||||
* the file should always contain a trailing 'X'. This will make sure that a
|
||||
* development build from trunk will not be confused for a released version.
|
||||
* The release manager will need to remove the trailing 'X' and update the
|
||||
* version string as appropriate for the release. The trunk copy of this file
|
||||
* should also be updated/incremented for the next expected version, + trailing 'X'
|
||||
****************************************************************************/
|
||||
// This is the delivery package title, "TrinyPI "
|
||||
// This string MUST be exactly 8 characters long
|
||||
#define AGESA_PACKAGE_STRING {'T', 'r', 'i', 'n', 'y', 'P', 'I', ' '}
|
||||
|
||||
// This is the release version number of the AGESA component
|
||||
// This string MUST be exactly 12 characters long
|
||||
#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '2', ' ', ' ', ' ', ' '}
|
||||
|
||||
|
||||
// The Comal solution is defined to be family 0x15 models 0x10 - 0x1F in the FS1 and FP2 sockets.
|
||||
#define INSTALL_FS1_SOCKET_SUPPORT TRUE
|
||||
#define INSTALL_FP2_SOCKET_SUPPORT TRUE
|
||||
#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
|
||||
|
||||
#ifdef BLDOPT_REMOVE_FS1_SOCKET_SUPPORT
|
||||
#if BLDOPT_REMOVE_FS1_SOCKET_SUPPORT == TRUE
|
||||
#undef INSTALL_FS1_SOCKET_SUPPORT
|
||||
#define INSTALL_FS1_SOCKET_SUPPORT FALSE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef BLDOPT_REMOVE_FP2_SOCKET_SUPPORT
|
||||
#if BLDOPT_REMOVE_FP2_SOCKET_SUPPORT == TRUE
|
||||
#undef INSTALL_FP2_SOCKET_SUPPORT
|
||||
#define INSTALL_FP2_SOCKET_SUPPORT FALSE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
// The following definitions specify the default values for various parameters in which there are
|
||||
// no clearly defined defaults to be used in the common file. The values below are based on product
|
||||
// and BKDG content, please consult the AGESA Memory team for consultation.
|
||||
#define DFLT_SCRUB_DRAM_RATE (0)
|
||||
#define DFLT_SCRUB_L2_RATE (0)
|
||||
#define DFLT_SCRUB_L3_RATE (0)
|
||||
#define DFLT_SCRUB_IC_RATE (0)
|
||||
#define DFLT_SCRUB_DC_RATE (0)
|
||||
#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
|
||||
#define DFLT_VRM_SLEW_RATE (5000)
|
||||
|
||||
|
||||
#define DFLT_SMBUS0_BASE_ADDRESS 0xB00
|
||||
#define DFLT_SMBUS1_BASE_ADDRESS 0xB20
|
||||
#define DFLT_SIO_PME_BASE_ADDRESS 0xE00
|
||||
#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400
|
||||
#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404
|
||||
#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x408
|
||||
#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410
|
||||
#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x420
|
||||
#define DFLT_SPI_BASE_ADDRESS 0xFEC10000ul
|
||||
#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0ul
|
||||
#define DFLT_HPET_BASE_ADDRESS 0xFED00000ul
|
||||
#define DFLT_SMI_CMD_PORT 0xB0
|
||||
#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00
|
||||
#define DFLT_GEC_BASE_ADDRESS 0xFED61000ul
|
||||
#define DFLT_SMBUS_SSID 0x780B1022ul
|
||||
#define DFLT_IDE_SSID 0x780C1022ul
|
||||
#define DFLT_SATA_AHCI_SSID 0x78011022ul
|
||||
#define DFLT_SATA_IDE_SSID 0x78001022ul
|
||||
#define DFLT_SATA_RAID5_SSID 0x78031022ul
|
||||
#define DFLT_SATA_RAID_SSID 0x78021022ul
|
||||
#define DFLT_EHCI_SSID 0x78081022ul
|
||||
#define DFLT_OHCI_SSID 0x78071022ul
|
||||
#define DFLT_LPC_SSID 0x780E1022ul
|
||||
#define DFLT_SD_SSID 0x78061022ul
|
||||
#define DFLT_XHCI_SSID 0x78121022ul
|
||||
#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE
|
||||
#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
|
||||
#define DFLT_FCH_GPP_LINK_CONFIG PortA4
|
||||
#define DFLT_FCH_GPP_PORT0_PRESENT FALSE
|
||||
#define DFLT_FCH_GPP_PORT1_PRESENT FALSE
|
||||
#define DFLT_FCH_GPP_PORT2_PRESENT FALSE
|
||||
#define DFLT_FCH_GPP_PORT3_PRESENT FALSE
|
||||
#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE
|
||||
#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
|
||||
#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
|
||||
#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
|
||||
|
||||
#ifdef BLDCFG_VRM_INRUSH_CURRENT_LIMIT
|
||||
#error BLDCFG: BLDCFG_VRM_INRUSH_CURRENT_LIMIT is deprecated. Use BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT instead.
|
||||
#endif
|
||||
|
||||
#ifdef BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT
|
||||
#error BLDCFG: BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT is deprecated. Use BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT instead.
|
||||
#endif
|
||||
|
||||
// Instantiate all solution relevant data.
|
||||
#include "PlatformInstall.h"
|
||||
|
||||
151
src/vendorcode/amd/agesa/f15tn/Include/CommonReturns.h
Normal file
151
src/vendorcode/amd/agesa/f15tn/Include/CommonReturns.h
Normal file
@ -0,0 +1,151 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* Common Return routines.
|
||||
*
|
||||
* Routines which do nothing, returning a result (preferably some version of zero) which
|
||||
* is consistent with "do nothing" or "default". Useful for function pointer tables.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: Common
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*
|
||||
*/
|
||||
/*
|
||||
*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
* ***************************************************************************
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _COMMON_RETURNS_H_
|
||||
#define _COMMON_RETURNS_H_
|
||||
|
||||
|
||||
/**
|
||||
* Return True
|
||||
*
|
||||
* @retval True Default case, no special action
|
||||
*/
|
||||
BOOLEAN
|
||||
CommonReturnTrue ( VOID );
|
||||
|
||||
/**
|
||||
* Return False.
|
||||
*
|
||||
* @retval FALSE Default case, no special action
|
||||
*/
|
||||
BOOLEAN
|
||||
CommonReturnFalse ( VOID );
|
||||
|
||||
/**
|
||||
* Return (UINT8)zero.
|
||||
*
|
||||
*
|
||||
* @retval zero None, or only case zero.
|
||||
*/
|
||||
UINT8
|
||||
CommonReturnZero8 ( VOID );
|
||||
|
||||
/**
|
||||
* Return (UINT32)zero.
|
||||
*
|
||||
*
|
||||
* @retval zero None, or only case zero.
|
||||
*/
|
||||
UINT32
|
||||
CommonReturnZero32 ( VOID );
|
||||
|
||||
/**
|
||||
* Return (UINT64)zero.
|
||||
*
|
||||
*
|
||||
* @retval zero None, or only case zero.
|
||||
*/
|
||||
UINT64
|
||||
CommonReturnZero64 ( VOID );
|
||||
|
||||
/**
|
||||
* Return NULL
|
||||
*
|
||||
* @retval NULL pointer to nothing
|
||||
*/
|
||||
VOID *
|
||||
CommonReturnNULL ( VOID );
|
||||
|
||||
/**
|
||||
* Return AGESA_SUCCESS.
|
||||
*
|
||||
* @retval AGESA_SUCCESS Success.
|
||||
*/
|
||||
AGESA_STATUS
|
||||
CommonReturnAgesaSuccess ( VOID );
|
||||
|
||||
/**
|
||||
* Do Nothing.
|
||||
*
|
||||
*/
|
||||
VOID
|
||||
CommonVoid ( VOID );
|
||||
|
||||
/**
|
||||
* ASSERT if this routine is called.
|
||||
*
|
||||
*/
|
||||
VOID
|
||||
CommonAssert ( VOID );
|
||||
|
||||
#endif // _COMMON_RETURNS_H_
|
||||
1113
src/vendorcode/amd/agesa/f15tn/Include/Filecode.h
Normal file
1113
src/vendorcode/amd/agesa/f15tn/Include/Filecode.h
Normal file
File diff suppressed because it is too large
Load Diff
228
src/vendorcode/amd/agesa/f15tn/Include/GeneralServices.h
Normal file
228
src/vendorcode/amd/agesa/f15tn/Include/GeneralServices.h
Normal file
@ -0,0 +1,228 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* General Services
|
||||
*
|
||||
* Provides Services similar to the external General Services API, except
|
||||
* suited to use within AGESA components. Socket, Core and PCI identification.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: Common
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*
|
||||
*/
|
||||
/*
|
||||
******************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef _GENERAL_SERVICES_H_
|
||||
#define _GENERAL_SERVICES_H_
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* D E F I N I T I O N S A N D M A C R O S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
#define NUMBER_OF_EVENT_DATA_PARAMS 4
|
||||
|
||||
/**
|
||||
* AMD Device id for MMIO check.
|
||||
*/
|
||||
#define AMD_DEV_VEN_ID 0x1022
|
||||
#define AMD_DEV_VEN_ID_ADDRESS 0
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* T Y P E D E F S, S T R U C T U R E S, E N U M S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/**
|
||||
* An AGESA Event Log entry.
|
||||
*/
|
||||
typedef struct {
|
||||
AGESA_STATUS EventClass; ///< The severity of the event, its associated AGESA_STATUS.
|
||||
UINT32 EventInfo; ///< Uniquely identifies the event.
|
||||
UINT32 DataParam1; ///< Event specific additional data
|
||||
UINT32 DataParam2; ///< Event specific additional data
|
||||
UINT32 DataParam3; ///< Event specific additional data
|
||||
UINT32 DataParam4; ///< Event specific additional data
|
||||
} AGESA_EVENT;
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* F U N C T I O N P R O T O T Y P E
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/**
|
||||
* Get a specified Core's APIC ID.
|
||||
*
|
||||
* @param[in] StdHeader Header for library and services.
|
||||
* @param[in] Socket The Core's Socket.
|
||||
* @param[in] Core The Core id.
|
||||
* @param[out] ApicAddress The Core's APIC ID.
|
||||
* @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds.
|
||||
*
|
||||
* @retval TRUE The core is present, APIC Id valid
|
||||
* @retval FALSE The core is not present, APIC Id not valid.
|
||||
*/
|
||||
BOOLEAN
|
||||
GetApicId (
|
||||
IN AMD_CONFIG_PARAMS *StdHeader,
|
||||
IN UINT32 Socket,
|
||||
IN UINT32 Core,
|
||||
OUT UINT8 *ApicAddress,
|
||||
OUT AGESA_STATUS *AgesaStatus
|
||||
);
|
||||
|
||||
/**
|
||||
* Get Processor Module's PCI Config Space address.
|
||||
*
|
||||
* @param[in] StdHeader Header for library and services.
|
||||
* @param[in] Socket The Core's Socket.
|
||||
* @param[in] Module The Module in that Processor
|
||||
* @param[out] PciAddress The Processor's PCI Config Space address (Function 0, Register 0)
|
||||
* @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds.
|
||||
*
|
||||
* @retval TRUE The core is present, PCI Address valid
|
||||
* @retval FALSE The core is not present, PCI Address not valid.
|
||||
*/
|
||||
BOOLEAN
|
||||
GetPciAddress (
|
||||
IN AMD_CONFIG_PARAMS *StdHeader,
|
||||
IN UINT32 Socket,
|
||||
IN UINT32 Module,
|
||||
OUT PCI_ADDR *PciAddress,
|
||||
OUT AGESA_STATUS *AgesaStatus
|
||||
);
|
||||
|
||||
/**
|
||||
* "Who am I" for the current running core.
|
||||
*
|
||||
* @param[in] StdHeader Header for library and services.
|
||||
* @param[out] Socket The current Core's Socket
|
||||
* @param[out] Module The current Core's Processor Module
|
||||
* @param[out] Core The current Core's core id.
|
||||
* @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds.
|
||||
*
|
||||
*/
|
||||
VOID
|
||||
IdentifyCore (
|
||||
IN AMD_CONFIG_PARAMS *StdHeader,
|
||||
OUT UINT32 *Socket,
|
||||
OUT UINT32 *Module,
|
||||
OUT UINT32 *Core,
|
||||
OUT AGESA_STATUS *AgesaStatus
|
||||
);
|
||||
|
||||
/**
|
||||
* A boolean function determine executed CPU is BSP core.
|
||||
*/
|
||||
BOOLEAN
|
||||
IsBsp (
|
||||
IN OUT AMD_CONFIG_PARAMS *StdHeader,
|
||||
OUT AGESA_STATUS *AgesaStatus
|
||||
);
|
||||
|
||||
/**
|
||||
* This function logs AGESA events into the event log.
|
||||
*/
|
||||
VOID
|
||||
PutEventLog (
|
||||
IN AGESA_STATUS EventClass,
|
||||
IN UINT32 EventInfo,
|
||||
IN UINT32 DataParam1,
|
||||
IN UINT32 DataParam2,
|
||||
IN UINT32 DataParam3,
|
||||
IN UINT32 DataParam4,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
/**
|
||||
* This function gets event logs from the circular buffer.
|
||||
*/
|
||||
AGESA_STATUS
|
||||
GetEventLog (
|
||||
OUT AGESA_EVENT *EventRecord,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
/**
|
||||
* This function gets event logs from the circular buffer without flushing the entry.
|
||||
*/
|
||||
BOOLEAN
|
||||
PeekEventLog (
|
||||
OUT AGESA_EVENT *EventRecord,
|
||||
IN UINT16 Index,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* This routine programs the registers necessary to get the PCI MMIO mechanism
|
||||
* up and functioning.
|
||||
*/
|
||||
VOID
|
||||
InitializePciMmio (
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
#endif // _GENERAL_SERVICES_H_
|
||||
138
src/vendorcode/amd/agesa/f15tn/Include/GnbInterface.h
Normal file
138
src/vendorcode/amd/agesa/f15tn/Include/GnbInterface.h
Normal file
@ -0,0 +1,138 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* GNB API definition.
|
||||
*
|
||||
*
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: GNB
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*
|
||||
*/
|
||||
/*
|
||||
*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
* ***************************************************************************
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _GNBINTERFACE_H_
|
||||
#define _GNBINTERFACE_H_
|
||||
|
||||
AGESA_STATUS
|
||||
GnbInitAtReset (
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
AGESA_STATUS
|
||||
GnbInitAtEarly (
|
||||
IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr
|
||||
);
|
||||
|
||||
VOID
|
||||
GnbInitDataStructAtPostDef (
|
||||
IN OUT GNB_POST_CONFIGURATION *GnbPostConfigPtr,
|
||||
IN AMD_POST_PARAMS *PostParamsPtr
|
||||
);
|
||||
|
||||
AGESA_STATUS
|
||||
GnbInitAtPost (
|
||||
IN OUT AMD_POST_PARAMS *PostParamsPtr
|
||||
);
|
||||
|
||||
VOID
|
||||
GnbInitDataStructAtEnvDef (
|
||||
IN OUT GNB_ENV_CONFIGURATION *GnbEnvConfigPtr,
|
||||
IN AMD_ENV_PARAMS *EnvParamsPtr
|
||||
);
|
||||
|
||||
AGESA_STATUS
|
||||
GnbInitAtEnv (
|
||||
IN AMD_ENV_PARAMS *EnvParamsPtr
|
||||
);
|
||||
|
||||
AGESA_STATUS
|
||||
GnbInitAtMid (
|
||||
IN OUT AMD_MID_PARAMS *MidParamsPtr
|
||||
);
|
||||
|
||||
AGESA_STATUS
|
||||
GnbInitAtLate (
|
||||
IN OUT AMD_LATE_PARAMS *LateParamsPtr
|
||||
);
|
||||
|
||||
AGESA_STATUS
|
||||
GnbInitAtPostAfterDram (
|
||||
IN OUT AMD_POST_PARAMS *PostParamsPtr
|
||||
);
|
||||
|
||||
AGESA_STATUS
|
||||
AmdGnbRecovery (
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
AGESA_STATUS
|
||||
GnbInitAtEarlier (
|
||||
IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr
|
||||
);
|
||||
|
||||
AGESA_STATUS
|
||||
GnbInitAtS3Save (
|
||||
IN OUT AMD_S3SAVE_PARAMS *AmdS3SaveParams
|
||||
);
|
||||
|
||||
#endif
|
||||
2020
src/vendorcode/amd/agesa/f15tn/Include/GnbPage.h
Normal file
2020
src/vendorcode/amd/agesa/f15tn/Include/GnbPage.h
Normal file
File diff suppressed because it is too large
Load Diff
1365
src/vendorcode/amd/agesa/f15tn/Include/Ids.h
Normal file
1365
src/vendorcode/amd/agesa/f15tn/Include/Ids.h
Normal file
File diff suppressed because it is too large
Load Diff
150
src/vendorcode/amd/agesa/f15tn/Include/IdsHt.h
Normal file
150
src/vendorcode/amd/agesa/f15tn/Include/IdsHt.h
Normal file
@ -0,0 +1,150 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* AMD IDS HyperTransport Definitions
|
||||
*
|
||||
* Contains AMD AGESA Integrated Debug HT related items.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: IDS
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef _IDS_HT_H_
|
||||
#define _IDS_HT_H_
|
||||
|
||||
// Frequency equates for call backs which take an actual frequency setting
|
||||
#define HT_FREQUENCY_200M 0
|
||||
#define HT_FREQUENCY_400M 2
|
||||
#define HT_FREQUENCY_600M 4
|
||||
#define HT_FREQUENCY_800M 5
|
||||
#define HT_FREQUENCY_1000M 6
|
||||
#define HT_FREQUENCY_1200M 7
|
||||
#define HT_FREQUENCY_1400M 8
|
||||
#define HT_FREQUENCY_1600M 9
|
||||
#define HT_FREQUENCY_1800M 10
|
||||
#define HT_FREQUENCY_2000M 11
|
||||
#define HT_FREQUENCY_2200M 12
|
||||
#define HT_FREQUENCY_2400M 13
|
||||
#define HT_FREQUENCY_2600M 14
|
||||
#define HT_FREQUENCY_2800M 17
|
||||
#define HT_FREQUENCY_3000M 18
|
||||
#define HT_FREQUENCY_3200M 19
|
||||
#define HT_FREQUENCY_3600M 20
|
||||
|
||||
/**
|
||||
* HT IDS: HT Link Port Override params.
|
||||
*
|
||||
* Provide an absolute override of HT Link Port settings. No checking is done that
|
||||
* the settings obey limits or capabilities, this responsibility rests with the user.
|
||||
*
|
||||
* Rules for values of structure items:
|
||||
* - Socket
|
||||
* - HT_LIST_TERMINAL == end of port override list, rest of item is not accessed
|
||||
* - HT_LIST_MATCH_ANY == Match Any Socket
|
||||
* - 0 .. 7 == The matching socket
|
||||
* - Link
|
||||
* - HT_LIST_MATCH_ANY == Match Any package link (that is not the internal links)
|
||||
* - HT_LIST_MATCH_INTERNAL_LINK == Match the internal links
|
||||
* - 0 .. 7 == The matching package link. 0 .. 3 are the ganged links or sublink 0's, 4 .. 7 are the sublink1's.
|
||||
* - Frequency
|
||||
* - HT_LIST_TERMINAL == Do not override the frequency, AUTO setting
|
||||
* - HT_FREQUENCY_200M .. HT_FREQUENCY_3600M = The frequency value to use
|
||||
* - Widthin
|
||||
* - HT_LIST_TERMINAL == Do not override the width, AUTO setting
|
||||
* - 2, 4, 8, 16, 32 == The width value to use
|
||||
* - Widthout
|
||||
* - HT_LIST_TERMINAL == Do not override the width, AUTO setting
|
||||
* - 2, 4, 8, 16, 32 == The width value to use
|
||||
*/
|
||||
typedef struct {
|
||||
// Match Fields
|
||||
UINT8 Socket; ///< The Socket which this port is on.
|
||||
UINT8 Link; ///< The port for this package link on that socket.
|
||||
// Override fields
|
||||
UINT8 Frequency; ///< Absolutely override the port's frequency.
|
||||
UINT8 WidthIn; ///< Absolutely override the port's width.
|
||||
UINT8 WidthOut; ///< Absolutely override the port's width.
|
||||
} HTIDS_PORT_OVERRIDE;
|
||||
|
||||
/**
|
||||
* A list of port overrides to search.
|
||||
*/
|
||||
typedef HTIDS_PORT_OVERRIDE *HTIDS_PORT_OVERRIDE_LIST;
|
||||
VOID
|
||||
HtIdsGetPortOverride (
|
||||
IN BOOLEAN IsSourcePort,
|
||||
IN OUT PORT_DESCRIPTOR *Port0,
|
||||
IN OUT PORT_DESCRIPTOR *Port1,
|
||||
IN OUT HTIDS_PORT_OVERRIDE_LIST *PortOverrideList,
|
||||
IN STATE_DATA *State
|
||||
);
|
||||
|
||||
typedef
|
||||
VOID
|
||||
F_HtIdsGetPortOverride (
|
||||
IN BOOLEAN IsSourcePort,
|
||||
IN OUT PORT_DESCRIPTOR *Port0,
|
||||
IN OUT PORT_DESCRIPTOR *Port1,
|
||||
IN OUT HTIDS_PORT_OVERRIDE_LIST *PortOverrideList,
|
||||
IN STATE_DATA *State
|
||||
);
|
||||
typedef F_HtIdsGetPortOverride* PF_HtIdsGetPortOverride;
|
||||
#endif // _IDS_HT_H
|
||||
113
src/vendorcode/amd/agesa/f15tn/Include/OptionApmInstall.h
Normal file
113
src/vendorcode/amd/agesa/f15tn/Include/OptionApmInstall.h
Normal file
@ -0,0 +1,113 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* Install of build option: Application Power Management (APM).
|
||||
*
|
||||
* Contains AMD AGESA install macros and test conditions. Output is the
|
||||
* defaults tables reflecting the User's build options selection.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: Options
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef _OPTION_APM_INSTALL_H_
|
||||
#define _OPTION_APM_INSTALL_H_
|
||||
|
||||
#include "cpuApm.h"
|
||||
|
||||
/* This option is designed to be included into the platform solution install
|
||||
* file. The platform solution install file will define the options status.
|
||||
* Check to validate the definition
|
||||
*/
|
||||
#define OPTION_CPU_APM_FEAT
|
||||
#define F15_APM_SUPPORT
|
||||
|
||||
#if OPTION_CPU_APM == TRUE
|
||||
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
|
||||
// Family 15h
|
||||
#ifdef OPTION_FAMILY15H
|
||||
#if OPTION_FAMILY15H == TRUE
|
||||
#if (OPTION_FAMILY15H_OR == TRUE)
|
||||
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureApm;
|
||||
#undef OPTION_CPU_APM_FEAT
|
||||
#define OPTION_CPU_APM_FEAT &CpuFeatureApm,
|
||||
extern CONST APM_FAMILY_SERVICES ROMDATA F15ApmSupport;
|
||||
#undef F15_APM_SUPPORT
|
||||
#define F15_APM_SUPPORT {AMD_FAMILY_15_OR, &F15ApmSupport},
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA ApmFamilyServiceArray[] =
|
||||
{
|
||||
F15_APM_SUPPORT
|
||||
{0, NULL}
|
||||
};
|
||||
|
||||
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA ApmFamilyServiceTable =
|
||||
{
|
||||
(sizeof (ApmFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
|
||||
&ApmFamilyServiceArray[0]
|
||||
};
|
||||
|
||||
#endif // _OPTION_APM_INSTALL_H_
|
||||
205
src/vendorcode/amd/agesa/f15tn/Include/OptionC6Install.h
Normal file
205
src/vendorcode/amd/agesa/f15tn/Include/OptionC6Install.h
Normal file
@ -0,0 +1,205 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* Install of build option: C6 C-state
|
||||
*
|
||||
* Contains AMD AGESA install macros and test conditions. Output is the
|
||||
* defaults tables reflecting the User's build options selection.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: Options
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef _OPTION_C6_STATE_INSTALL_H_
|
||||
#define _OPTION_C6_STATE_INSTALL_H_
|
||||
|
||||
#include "cpuC6State.h"
|
||||
|
||||
/* This option is designed to be included into the platform solution install
|
||||
* file. The platform solution install file will define the options status.
|
||||
* Check to validate the definition
|
||||
*/
|
||||
#define OPTION_C6_STATE_FEAT
|
||||
#define F12_C6_STATE_SUPPORT
|
||||
#define F14_ON_C6_STATE_SUPPORT
|
||||
#define F15_OR_C6_STATE_SUPPORT
|
||||
#define F15_TN_C6_STATE_SUPPORT
|
||||
|
||||
#if OPTION_C6_STATE == TRUE
|
||||
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
|
||||
#ifdef OPTION_FAMILY12H
|
||||
#if OPTION_FAMILY12H == TRUE
|
||||
#if OPTION_FAMILY12H_LN == TRUE
|
||||
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State;
|
||||
#undef OPTION_C6_STATE_FEAT
|
||||
#define OPTION_C6_STATE_FEAT &CpuFeatureC6State,
|
||||
extern CONST C6_FAMILY_SERVICES ROMDATA F12C6Support;
|
||||
#undef F12_C6_STATE_SUPPORT
|
||||
#define F12_C6_STATE_SUPPORT {AMD_FAMILY_12_LN, &F12C6Support},
|
||||
|
||||
#if OPTION_EARLY_SAMPLES == TRUE
|
||||
extern F_F12_ES_C6_INIT F12C6A0Workaround;
|
||||
|
||||
CONST F12_ES_C6_SUPPORT ROMDATA F12EarlySampleC6Support =
|
||||
{
|
||||
F12C6A0Workaround
|
||||
};
|
||||
#else
|
||||
CONST F12_ES_C6_SUPPORT ROMDATA F12EarlySampleC6Support =
|
||||
{
|
||||
(PF_F12_ES_C6_INIT) CommonVoid
|
||||
};
|
||||
#endif
|
||||
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef OPTION_FAMILY14H
|
||||
#if OPTION_FAMILY14H == TRUE
|
||||
#if (OPTION_FAMILY14H_ON == TRUE)
|
||||
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State;
|
||||
#undef OPTION_C6_STATE_FEAT
|
||||
#define OPTION_C6_STATE_FEAT &CpuFeatureC6State,
|
||||
extern CONST C6_FAMILY_SERVICES ROMDATA F14OnC6Support;
|
||||
#undef F14_ON_C6_STATE_SUPPORT
|
||||
#define F14_ON_C6_STATE_SUPPORT {AMD_FAMILY_14_ON, &F14OnC6Support},
|
||||
|
||||
#if (OPTION_EARLY_SAMPLES == TRUE)
|
||||
extern F_F14_ON_ES_IS_C6_SUPPORTED F14IsC6DisabledEarlySample;
|
||||
extern F_F14_ON_ES_C6_INIT F14C6A0Workaround;
|
||||
|
||||
CONST F14_ON_ES_C6_SUPPORT ROMDATA F14OnEarlySampleC6Support =
|
||||
{
|
||||
F14IsC6DisabledEarlySample,
|
||||
F14C6A0Workaround
|
||||
};
|
||||
#else
|
||||
CONST F14_ON_ES_C6_SUPPORT ROMDATA F14OnEarlySampleC6Support =
|
||||
{
|
||||
(PF_F14_ON_ES_IS_C6_SUPPORTED) CommonVoid,
|
||||
(PF_F14_ON_ES_C6_INIT) CommonVoid
|
||||
};
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef OPTION_FAMILY15H
|
||||
#if OPTION_FAMILY15H == TRUE
|
||||
#if (OPTION_FAMILY15H_OR == TRUE)
|
||||
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State;
|
||||
#undef OPTION_C6_STATE_FEAT
|
||||
#define OPTION_C6_STATE_FEAT &CpuFeatureC6State,
|
||||
extern CONST C6_FAMILY_SERVICES ROMDATA F15OrC6Support;
|
||||
#undef F15_OR_C6_STATE_SUPPORT
|
||||
#define F15_OR_C6_STATE_SUPPORT {AMD_FAMILY_15_OR, &F15OrC6Support},
|
||||
|
||||
#if (OPTION_EARLY_SAMPLES == TRUE)
|
||||
extern F_F15_OR_ES_IS_C6_SUPPORTED F15OrIsC6DisabledEarlySample;
|
||||
|
||||
CONST F15_OR_ES_C6_SUPPORT ROMDATA F15OrEarlySampleC6Support =
|
||||
{
|
||||
F15OrIsC6DisabledEarlySample
|
||||
};
|
||||
#else
|
||||
CONST F15_OR_ES_C6_SUPPORT ROMDATA F15OrEarlySampleC6Support =
|
||||
{
|
||||
(PF_F15_OR_ES_IS_C6_SUPPORTED) CommonVoid
|
||||
};
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (OPTION_FAMILY15H_TN == TRUE)
|
||||
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State;
|
||||
#undef OPTION_C6_STATE_FEAT
|
||||
#define OPTION_C6_STATE_FEAT &CpuFeatureC6State,
|
||||
extern CONST C6_FAMILY_SERVICES ROMDATA F15TnC6Support;
|
||||
#undef F15_TN_C6_STATE_SUPPORT
|
||||
#define F15_TN_C6_STATE_SUPPORT {AMD_FAMILY_15_TN, &F15TnC6Support},
|
||||
#endif
|
||||
|
||||
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA C6FamilyServiceArray[] =
|
||||
{
|
||||
F12_C6_STATE_SUPPORT
|
||||
F14_ON_C6_STATE_SUPPORT
|
||||
{0, NULL},
|
||||
F15_OR_C6_STATE_SUPPORT
|
||||
F15_TN_C6_STATE_SUPPORT
|
||||
{0, NULL},
|
||||
{0, NULL}
|
||||
};
|
||||
|
||||
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA C6FamilyServiceTable =
|
||||
{
|
||||
(sizeof (C6FamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
|
||||
&C6FamilyServiceArray[0]
|
||||
};
|
||||
|
||||
#endif // _OPTION_C6_STATE_INSTALL_H_
|
||||
211
src/vendorcode/amd/agesa/f15tn/Include/OptionCpbInstall.h
Normal file
211
src/vendorcode/amd/agesa/f15tn/Include/OptionCpbInstall.h
Normal file
@ -0,0 +1,211 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* Install of build option: Core Performance Boost
|
||||
*
|
||||
* Contains AMD AGESA install macros and test conditions. Output is the
|
||||
* defaults tables reflecting the User's build options selection.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: Options
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef _OPTION_CPB_INSTALL_H_
|
||||
#define _OPTION_CPB_INSTALL_H_
|
||||
|
||||
#include "cpuCpb.h"
|
||||
|
||||
/* This option is designed to be included into the platform solution install
|
||||
* file. The platform solution install file will define the options status.
|
||||
* Check to validate the definition
|
||||
*/
|
||||
#define OPTION_CPB_FEAT
|
||||
#define F10_CPB_SUPPORT
|
||||
#define F12_CPB_SUPPORT
|
||||
#define F14_ON_CPB_SUPPORT
|
||||
#define F15_OR_CPB_SUPPORT
|
||||
#define F15_TN_CPB_SUPPORT
|
||||
|
||||
#if OPTION_CPB == TRUE
|
||||
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)
|
||||
// Family 10h
|
||||
#ifdef OPTION_FAMILY10H
|
||||
#if OPTION_FAMILY10H == TRUE
|
||||
#if OPTION_FAMILY10H_PH == TRUE
|
||||
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb;
|
||||
#undef OPTION_CPB_FEAT
|
||||
#define OPTION_CPB_FEAT &CpuFeatureCpb,
|
||||
extern CONST CPB_FAMILY_SERVICES ROMDATA F10CpbSupport;
|
||||
#undef F10_CPB_SUPPORT
|
||||
#define F10_CPB_SUPPORT {AMD_FAMILY_10_PH, &F10CpbSupport},
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
// Family 12h
|
||||
#ifdef OPTION_FAMILY12H
|
||||
#if OPTION_FAMILY12H == TRUE
|
||||
#if OPTION_FAMILY12H_LN == TRUE
|
||||
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb;
|
||||
#undef OPTION_CPB_FEAT
|
||||
#define OPTION_CPB_FEAT &CpuFeatureCpb,
|
||||
extern CONST CPB_FAMILY_SERVICES ROMDATA F12CpbSupport;
|
||||
#undef F12_CPB_SUPPORT
|
||||
#define F12_CPB_SUPPORT {AMD_FAMILY_12_LN, &F12CpbSupport},
|
||||
#if OPTION_EARLY_SAMPLES == TRUE
|
||||
#if (AGESA_ENTRY_INIT_EARLY == TRUE)
|
||||
extern F_F12_ES_CPB_INIT F12LnA1CpbHook;
|
||||
|
||||
CONST F12_ES_CPB_SUPPORT ROMDATA F12EarlySampleCpbSupport =
|
||||
{
|
||||
F12LnA1CpbHook
|
||||
};
|
||||
#else
|
||||
CONST F12_ES_CPB_SUPPORT ROMDATA F12EarlySampleCpbSupport =
|
||||
{
|
||||
(PF_F12_ES_CPB_INIT) CommonVoid
|
||||
};
|
||||
#endif
|
||||
#else
|
||||
CONST F12_ES_CPB_SUPPORT ROMDATA F12EarlySampleCpbSupport =
|
||||
{
|
||||
(PF_F12_ES_CPB_INIT) CommonVoid
|
||||
};
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
// Family 14h
|
||||
#ifdef OPTION_FAMILY14H
|
||||
#if OPTION_FAMILY14H == TRUE
|
||||
#if OPTION_FAMILY14H_ON == TRUE
|
||||
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb;
|
||||
#undef OPTION_CPB_FEAT
|
||||
#define OPTION_CPB_FEAT &CpuFeatureCpb,
|
||||
extern CONST CPB_FAMILY_SERVICES ROMDATA F14OnCpbSupport;
|
||||
#undef F14_ON_CPB_SUPPORT
|
||||
#define F14_ON_CPB_SUPPORT {AMD_FAMILY_14_ON, &F14OnCpbSupport},
|
||||
#endif
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
// Family 15h
|
||||
#ifdef OPTION_FAMILY15H
|
||||
#if OPTION_FAMILY15H == TRUE
|
||||
#if (OPTION_FAMILY15H_OR == TRUE)
|
||||
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb;
|
||||
#undef OPTION_CPB_FEAT
|
||||
#define OPTION_CPB_FEAT &CpuFeatureCpb,
|
||||
extern CONST CPB_FAMILY_SERVICES ROMDATA F15OrCpbSupport;
|
||||
#undef F15_OR_CPB_SUPPORT
|
||||
#define F15_OR_CPB_SUPPORT {AMD_FAMILY_15_OR, &F15OrCpbSupport},
|
||||
|
||||
#if OPTION_EARLY_SAMPLES == TRUE
|
||||
extern F_F15_OR_ES_IS_CPB_SUPPORTED F15OrIsCpbDisabledEarlySample;
|
||||
|
||||
CONST F15_OR_ES_CPB_SUPPORT ROMDATA F15OrEarlySampleCpbSupport =
|
||||
{
|
||||
F15OrIsCpbDisabledEarlySample
|
||||
};
|
||||
#else
|
||||
CONST F15_OR_ES_CPB_SUPPORT ROMDATA F15OrEarlySampleCpbSupport =
|
||||
{
|
||||
(PF_F15_OR_ES_IS_CPB_SUPPORTED) CommonVoid
|
||||
};
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (OPTION_FAMILY15H_TN == TRUE)
|
||||
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb;
|
||||
#undef OPTION_CPB_FEAT
|
||||
#define OPTION_CPB_FEAT &CpuFeatureCpb,
|
||||
extern CONST CPB_FAMILY_SERVICES ROMDATA F15TnCpbSupport;
|
||||
#undef F15_TN_CPB_SUPPORT
|
||||
#define F15_TN_CPB_SUPPORT {AMD_FAMILY_15_TN, &F15TnCpbSupport},
|
||||
#endif
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CpbFamilyServiceArray[] =
|
||||
{
|
||||
F10_CPB_SUPPORT
|
||||
F12_CPB_SUPPORT
|
||||
F14_ON_CPB_SUPPORT
|
||||
{0, NULL},
|
||||
F15_OR_CPB_SUPPORT
|
||||
F15_TN_CPB_SUPPORT
|
||||
{0, NULL},
|
||||
{0, NULL}
|
||||
};
|
||||
|
||||
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CpbFamilyServiceTable =
|
||||
{
|
||||
(sizeof (CpbFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
|
||||
&CpbFamilyServiceArray[0]
|
||||
};
|
||||
|
||||
#endif // _OPTION_CPB_INSTALL_H_
|
||||
@ -0,0 +1,154 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* Install of build option: CPU Cache Flush On Halt
|
||||
*
|
||||
* Contains AMD AGESA install macros and test conditions. Output is the
|
||||
* defaults tables reflecting the User's build options selection.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: Options
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_
|
||||
#define _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_
|
||||
|
||||
#include "cpuPostInit.h"
|
||||
|
||||
/* This option is designed to be included into the platform solution install
|
||||
* file. The platform solution install file will define the options status.
|
||||
* Check to validate the definition
|
||||
*/
|
||||
#define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
|
||||
#define F10_BL_CPU_CFOH_SUPPORT
|
||||
#define F10_DA_CPU_CFOH_SUPPORT
|
||||
#define F10_CPU_CFOH_SUPPORT
|
||||
#define F15_OR_CPU_CFOH_SUPPORT
|
||||
#define F15_TN_CPU_CFOH_SUPPORT
|
||||
|
||||
#if OPTION_CPU_CFOH == TRUE
|
||||
#if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE)
|
||||
#ifdef OPTION_FAMILY10H
|
||||
#if OPTION_FAMILY10H == TRUE
|
||||
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCacheFlushOnHalt;
|
||||
#undef OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
|
||||
#define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT &CpuFeatureCacheFlushOnHalt,
|
||||
|
||||
#if OPTION_FAMILY10H_BL == TRUE
|
||||
extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10BlCacheFlushOnHalt;
|
||||
#undef F10_BL_CPU_CFOH_SUPPORT
|
||||
#define F10_BL_CPU_CFOH_SUPPORT {AMD_FAMILY_10_BL, &F10BlCacheFlushOnHalt},
|
||||
#endif
|
||||
|
||||
#if OPTION_FAMILY10H_DA == TRUE
|
||||
extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10DaCacheFlushOnHalt;
|
||||
#undef F10_DA_CPU_CFOH_SUPPORT
|
||||
#define F10_DA_CPU_CFOH_SUPPORT {AMD_FAMILY_10_DA, &F10DaCacheFlushOnHalt},
|
||||
#endif
|
||||
|
||||
#if (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_HY == TRUE) || (OPTION_FAMILY10H_PH == TRUE)
|
||||
extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10CacheFlushOnHalt;
|
||||
#undef F10_CPU_CFOH_SUPPORT
|
||||
#define F10_CPU_CFOH_SUPPORT {AMD_FAMILY_10_RB | AMD_FAMILY_10_HY | AMD_FAMILY_10_PH, &F10CacheFlushOnHalt},
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef OPTION_FAMILY15H
|
||||
#if OPTION_FAMILY15H == TRUE
|
||||
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCacheFlushOnHalt;
|
||||
#undef OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
|
||||
#define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT &CpuFeatureCacheFlushOnHalt,
|
||||
|
||||
#if OPTION_FAMILY15H_OR == TRUE
|
||||
extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F15OrCacheFlushOnHalt;
|
||||
#undef F15_OR_CPU_CFOH_SUPPORT
|
||||
#define F15_OR_CPU_CFOH_SUPPORT {AMD_FAMILY_15_OR, &F15OrCacheFlushOnHalt},
|
||||
#endif
|
||||
|
||||
#if OPTION_FAMILY15H_TN == TRUE
|
||||
extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F15TnCacheFlushOnHalt;
|
||||
#undef F15_TN_CPU_CFOH_SUPPORT
|
||||
#define F15_TN_CPU_CFOH_SUPPORT {AMD_FAMILY_15_TN, &F15TnCacheFlushOnHalt},
|
||||
#endif
|
||||
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CacheFlushOnHaltFamilyServiceArray[] =
|
||||
{
|
||||
F10_BL_CPU_CFOH_SUPPORT
|
||||
F10_DA_CPU_CFOH_SUPPORT
|
||||
F10_CPU_CFOH_SUPPORT
|
||||
F15_OR_CPU_CFOH_SUPPORT
|
||||
F15_TN_CPU_CFOH_SUPPORT
|
||||
{0, NULL},
|
||||
{0, NULL}
|
||||
};
|
||||
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CacheFlushOnHaltFamilyServiceTable =
|
||||
{
|
||||
(sizeof (CacheFlushOnHaltFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
|
||||
&CacheFlushOnHaltFamilyServiceArray[0]
|
||||
};
|
||||
|
||||
#endif // _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_
|
||||
@ -0,0 +1,149 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* Install of build option: CPU Core Leveling
|
||||
*
|
||||
* Contains AMD AGESA install macros and test conditions. Output is the
|
||||
* defaults tables reflecting the User's build options selection.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: Options
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef _OPTION_CPU_CORELEVELING_INSTALL_H_
|
||||
#define _OPTION_CPU_CORELEVELING_INSTALL_H_
|
||||
|
||||
|
||||
/* This option is designed to be included into the platform solution install
|
||||
* file. The platform solution install file will define the options status.
|
||||
* Check to validate the definition
|
||||
*/
|
||||
#define OPTION_CPU_CORE_LEVELING_FEAT
|
||||
#define F10_REVE_CPU_CORELEVELING_SUPPORT
|
||||
#define F10_REVD_CPU_CORELEVELING_SUPPORT
|
||||
#define F10_REVC_CPU_CORELEVELING_SUPPORT
|
||||
#define F15_OR_CPU_CORELEVELING_SUPPORT
|
||||
#define F15_TN_CPU_CORELEVELING_SUPPORT
|
||||
|
||||
#if OPTION_CPU_CORELEVLING == TRUE
|
||||
#if (AGESA_ENTRY_INIT_EARLY == TRUE)
|
||||
// Family 10h
|
||||
#if OPTION_FAMILY10H == TRUE
|
||||
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCoreLeveling;
|
||||
#undef OPTION_CPU_CORE_LEVELING_FEAT
|
||||
#define OPTION_CPU_CORE_LEVELING_FEAT &CpuFeatureCoreLeveling,
|
||||
#if OPTION_FAMILY10H_HY == TRUE
|
||||
extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevDCoreLeveling;
|
||||
#undef F10_REVD_CPU_CORELEVELING_SUPPORT
|
||||
#define F10_REVD_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_10_HY, &F10RevDCoreLeveling},
|
||||
#endif
|
||||
|
||||
#if (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_BL == TRUE) || (OPTION_FAMILY10H_DA == TRUE)
|
||||
extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevCCoreLeveling;
|
||||
#undef F10_REVC_CPU_CORELEVELING_SUPPORT
|
||||
#define F10_REVC_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_10_RB | AMD_FAMILY_10_BL | AMD_FAMILY_10_DA, &F10RevCCoreLeveling},
|
||||
#endif
|
||||
|
||||
#if (OPTION_FAMILY10H_PH == TRUE)
|
||||
extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevECoreLeveling;
|
||||
#undef F10_REVE_CPU_CORELEVELING_SUPPORT
|
||||
#define F10_REVE_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_10_PH, &F10RevECoreLeveling},
|
||||
#endif
|
||||
#endif
|
||||
// Family 15h
|
||||
#if OPTION_FAMILY15H == TRUE
|
||||
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCoreLeveling;
|
||||
#undef OPTION_CPU_CORE_LEVELING_FEAT
|
||||
#define OPTION_CPU_CORE_LEVELING_FEAT &CpuFeatureCoreLeveling,
|
||||
|
||||
#if (OPTION_FAMILY15H_OR == TRUE)
|
||||
extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F15OrCoreLeveling;
|
||||
#undef F15_OR_CPU_CORELEVELING_SUPPORT
|
||||
#define F15_OR_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_15_OR, &F15OrCoreLeveling},
|
||||
#endif
|
||||
|
||||
#if (OPTION_FAMILY15H_TN == TRUE)
|
||||
extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F15TnCoreLeveling;
|
||||
#undef F15_TN_CPU_CORELEVELING_SUPPORT
|
||||
#define F15_TN_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_15_TN, &F15TnCoreLeveling},
|
||||
#endif
|
||||
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CoreLevelingFamilyServiceArray[] =
|
||||
{
|
||||
{0, NULL},
|
||||
F15_TN_CPU_CORELEVELING_SUPPORT
|
||||
F15_OR_CPU_CORELEVELING_SUPPORT
|
||||
F10_REVE_CPU_CORELEVELING_SUPPORT
|
||||
F10_REVD_CPU_CORELEVELING_SUPPORT
|
||||
F10_REVC_CPU_CORELEVELING_SUPPORT
|
||||
{0, NULL}
|
||||
};
|
||||
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CoreLevelingFamilyServiceTable =
|
||||
{
|
||||
(sizeof (CoreLevelingFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
|
||||
&CoreLevelingFamilyServiceArray[0]
|
||||
};
|
||||
|
||||
#endif // _OPTION_CPU_CORELEVELING_INSTALL_H_
|
||||
@ -0,0 +1,434 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* Install of all appropriate CPU family specific support.
|
||||
*
|
||||
* This file generates the defaults tables for all family specific
|
||||
* combinations.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: Core
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
/* Default all CPU Specific Service members to off. They
|
||||
will be enabled as needed by cross referencing families
|
||||
with entry points in the family / model install files. */
|
||||
#define GET_PSTATE_POWER FALSE
|
||||
#define GET_PSTATE_FREQ FALSE
|
||||
#define DISABLE_PSTATE FALSE
|
||||
#define TRANSITION_PSTATE FALSE
|
||||
#define PROC_IDD_MAX FALSE
|
||||
#define GET_TSC_RATE FALSE
|
||||
#define PSTATE_TRANSITION_LATENCY FALSE
|
||||
#define GET_PSTATE_REGISTER_INFO FALSE
|
||||
#define GET_PSTATE_MAX_STATE FALSE
|
||||
#define SET_PSTATE_LEVELING_REG FALSE
|
||||
#define GET_NB_FREQ FALSE
|
||||
#define GET_NB_IDD_MAX FALSE
|
||||
#define IS_NBCOF_INIT_NEEDED FALSE
|
||||
#define AP_INITIAL_LAUNCH FALSE
|
||||
#define GET_AP_MAILBOX_FROM_HW FALSE
|
||||
#define SET_AP_CORE_NUMBER FALSE
|
||||
#define GET_AP_CORE_NUMBER FALSE
|
||||
#define TRANSFER_AP_CORE_NUMBER FALSE
|
||||
#define ID_POSITION_INITIAL_APICID FALSE
|
||||
#define SAVE_FEATURES FALSE
|
||||
#define WRITE_FEATURES FALSE
|
||||
#define SET_DOWN_CORE_REG FALSE
|
||||
#define SET_WARM_RESET_FLAG FALSE
|
||||
#define GET_WARM_RESET_FLAG FALSE
|
||||
#define USES_REGISTER_TABLES FALSE
|
||||
#define BASE_FAMILY_PCI FALSE
|
||||
#define MODEL_SPECIFIC_PCI FALSE
|
||||
#define BASE_FAMILY_MSR FALSE
|
||||
#define MODEL_SPECIFIC_MSR FALSE
|
||||
#define BRAND_STRING1 FALSE
|
||||
#define BRAND_STRING2 FALSE
|
||||
#define BASE_FAMILY_HT_PCI FALSE
|
||||
#define MODEL_SPECIFIC_HT_PCI FALSE
|
||||
#define BASE_FAMILY_WORKAROUNDS FALSE
|
||||
#define GET_PATCHES FALSE
|
||||
#define GET_PATCHES_EQUIVALENCE_TABLE FALSE
|
||||
#define GET_CACHE_INFO FALSE
|
||||
#define GET_SYSTEM_PM_TABLE FALSE
|
||||
#define GET_WHEA_INIT FALSE
|
||||
#define GET_CFOH_REG FALSE
|
||||
#define GET_PLATFORM_TYPE_SPECIFIC_INFO FALSE
|
||||
#define IS_NB_PSTATE_ENABLED FALSE
|
||||
|
||||
/*
|
||||
* Pull in family specific services based on entry point
|
||||
*/
|
||||
#if AGESA_ENTRY_INIT_RESET == TRUE
|
||||
#undef ID_POSITION_INITIAL_APICID
|
||||
#define ID_POSITION_INITIAL_APICID TRUE
|
||||
#undef GET_AP_MAILBOX_FROM_HW
|
||||
#define GET_AP_MAILBOX_FROM_HW TRUE
|
||||
#undef SET_WARM_RESET_FLAG
|
||||
#define SET_WARM_RESET_FLAG TRUE
|
||||
#undef GET_WARM_RESET_FLAG
|
||||
#define GET_WARM_RESET_FLAG TRUE
|
||||
#undef GET_CACHE_INFO
|
||||
#define GET_CACHE_INFO TRUE
|
||||
#undef GET_AP_CORE_NUMBER
|
||||
#define GET_AP_CORE_NUMBER TRUE
|
||||
#undef TRANSFER_AP_CORE_NUMBER
|
||||
#define TRANSFER_AP_CORE_NUMBER TRUE
|
||||
#endif
|
||||
|
||||
#if AGESA_ENTRY_INIT_RECOVERY == TRUE
|
||||
#undef ID_POSITION_INITIAL_APICID
|
||||
#define ID_POSITION_INITIAL_APICID TRUE
|
||||
#undef USES_REGISTER_TABLES
|
||||
#define USES_REGISTER_TABLES TRUE
|
||||
#undef BASE_FAMILY_PCI
|
||||
#define BASE_FAMILY_PCI TRUE
|
||||
#undef MODEL_SPECIFIC_PCI
|
||||
#define MODEL_SPECIFIC_PCI TRUE
|
||||
#undef BASE_FAMILY_MSR
|
||||
#define BASE_FAMILY_MSR TRUE
|
||||
#undef MODEL_SPECIFIC_MSR
|
||||
#define MODEL_SPECIFIC_MSR TRUE
|
||||
#undef GET_CACHE_INFO
|
||||
#define GET_CACHE_INFO TRUE
|
||||
#undef GET_PLATFORM_TYPE_SPECIFIC_INFO
|
||||
#define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE
|
||||
#undef IS_NB_PSTATE_ENABLED
|
||||
#define IS_NB_PSTATE_ENABLED TRUE
|
||||
#undef GET_PATCHES
|
||||
#define GET_PATCHES TRUE
|
||||
#undef GET_PATCHES_EQUIVALENCE_TABLE
|
||||
#define GET_PATCHES_EQUIVALENCE_TABLE TRUE
|
||||
#endif
|
||||
|
||||
#if AGESA_ENTRY_INIT_EARLY == TRUE
|
||||
#undef TRANSITION_PSTATE
|
||||
#define TRANSITION_PSTATE TRUE
|
||||
#undef DISABLE_PSTATE
|
||||
#define DISABLE_PSTATE TRUE
|
||||
#undef PROC_IDD_MAX
|
||||
#define PROC_IDD_MAX TRUE
|
||||
#undef GET_TSC_RATE
|
||||
#define GET_TSC_RATE TRUE
|
||||
#undef GET_NB_FREQ
|
||||
#define GET_NB_FREQ TRUE
|
||||
#undef GET_NB_IDD_MAX
|
||||
#define GET_NB_IDD_MAX TRUE
|
||||
#undef IS_NBCOF_INIT_NEEDED
|
||||
#define IS_NBCOF_INIT_NEEDED TRUE
|
||||
#undef AP_INITIAL_LAUNCH
|
||||
#define AP_INITIAL_LAUNCH TRUE
|
||||
#undef GET_AP_MAILBOX_FROM_HW
|
||||
#define GET_AP_MAILBOX_FROM_HW TRUE
|
||||
#undef SET_AP_CORE_NUMBER
|
||||
#define SET_AP_CORE_NUMBER TRUE
|
||||
#undef GET_AP_CORE_NUMBER
|
||||
#define GET_AP_CORE_NUMBER TRUE
|
||||
#undef TRANSFER_AP_CORE_NUMBER
|
||||
#define TRANSFER_AP_CORE_NUMBER TRUE
|
||||
#undef ID_POSITION_INITIAL_APICID
|
||||
#define ID_POSITION_INITIAL_APICID TRUE
|
||||
#undef SET_DOWN_CORE_REG
|
||||
#define SET_DOWN_CORE_REG TRUE
|
||||
#undef SET_WARM_RESET_FLAG
|
||||
#define SET_WARM_RESET_FLAG TRUE
|
||||
#undef GET_WARM_RESET_FLAG
|
||||
#define GET_WARM_RESET_FLAG TRUE
|
||||
#undef USES_REGISTER_TABLES
|
||||
#define USES_REGISTER_TABLES TRUE
|
||||
#undef BASE_FAMILY_PCI
|
||||
#define BASE_FAMILY_PCI TRUE
|
||||
#undef MODEL_SPECIFIC_PCI
|
||||
#define MODEL_SPECIFIC_PCI TRUE
|
||||
#undef BASE_FAMILY_MSR
|
||||
#define BASE_FAMILY_MSR TRUE
|
||||
#undef MODEL_SPECIFIC_MSR
|
||||
#define MODEL_SPECIFIC_MSR TRUE
|
||||
#undef BRAND_STRING1
|
||||
#define BRAND_STRING1 TRUE
|
||||
#undef BRAND_STRING2
|
||||
#define BRAND_STRING2 TRUE
|
||||
#undef BASE_FAMILY_HT_PCI
|
||||
#define BASE_FAMILY_HT_PCI TRUE
|
||||
#undef MODEL_SPECIFIC_HT_PCI
|
||||
#define MODEL_SPECIFIC_HT_PCI TRUE
|
||||
#undef BASE_FAMILY_WORKAROUNDS
|
||||
#define BASE_FAMILY_WORKAROUNDS TRUE
|
||||
#undef GET_PATCHES
|
||||
#define GET_PATCHES TRUE
|
||||
#undef GET_PATCHES_EQUIVALENCE_TABLE
|
||||
#define GET_PATCHES_EQUIVALENCE_TABLE TRUE
|
||||
#undef GET_SYSTEM_PM_TABLE
|
||||
#define GET_SYSTEM_PM_TABLE TRUE
|
||||
#undef GET_CACHE_INFO
|
||||
#define GET_CACHE_INFO TRUE
|
||||
#undef GET_PLATFORM_TYPE_SPECIFIC_INFO
|
||||
#define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE
|
||||
#undef IS_NB_PSTATE_ENABLED
|
||||
#define IS_NB_PSTATE_ENABLED TRUE
|
||||
#endif
|
||||
|
||||
#if AGESA_ENTRY_INIT_POST == TRUE
|
||||
#undef ID_POSITION_INITIAL_APICID
|
||||
#define ID_POSITION_INITIAL_APICID TRUE
|
||||
#undef GET_PSTATE_POWER
|
||||
#define GET_PSTATE_POWER TRUE
|
||||
#undef GET_PSTATE_FREQ
|
||||
#define GET_PSTATE_FREQ TRUE
|
||||
#undef TRANSITION_PSTATE
|
||||
#define TRANSITION_PSTATE TRUE
|
||||
#undef PROC_IDD_MAX
|
||||
#define PROC_IDD_MAX TRUE
|
||||
#undef GET_AP_CORE_NUMBER
|
||||
#define GET_AP_CORE_NUMBER TRUE
|
||||
#undef GET_PSTATE_REGISTER_INFO
|
||||
#define GET_PSTATE_REGISTER_INFO TRUE
|
||||
#undef GET_PSTATE_MAX_STATE
|
||||
#define GET_PSTATE_MAX_STATE TRUE
|
||||
#undef SET_PSTATE_LEVELING_REG
|
||||
#define SET_PSTATE_LEVELING_REG TRUE
|
||||
#undef SET_WARM_RESET_FLAG
|
||||
#define SET_WARM_RESET_FLAG TRUE
|
||||
#undef GET_WARM_RESET_FLAG
|
||||
#define GET_WARM_RESET_FLAG TRUE
|
||||
#undef SAVE_FEATURES
|
||||
#define SAVE_FEATURES TRUE
|
||||
#undef WRITE_FEATURES
|
||||
#define WRITE_FEATURES TRUE
|
||||
#undef GET_CFOH_REG
|
||||
#define GET_CFOH_REG TRUE
|
||||
#undef IS_NB_PSTATE_ENABLED
|
||||
#define IS_NB_PSTATE_ENABLED TRUE
|
||||
#endif
|
||||
|
||||
#if AGESA_ENTRY_INIT_ENV == TRUE
|
||||
#endif
|
||||
|
||||
#if AGESA_ENTRY_INIT_MID == TRUE
|
||||
#endif
|
||||
|
||||
#if AGESA_ENTRY_INIT_LATE == TRUE
|
||||
#undef GET_AP_CORE_NUMBER
|
||||
#define GET_AP_CORE_NUMBER TRUE
|
||||
#undef GET_PSTATE_FREQ
|
||||
#define GET_PSTATE_FREQ TRUE
|
||||
#undef TRANSITION_PSTATE
|
||||
#define TRANSITION_PSTATE TRUE
|
||||
#undef PSTATE_TRANSITION_LATENCY
|
||||
#define PSTATE_TRANSITION_LATENCY TRUE
|
||||
#undef GET_WHEA_INIT
|
||||
#define GET_WHEA_INIT TRUE
|
||||
#undef GET_PLATFORM_TYPE_SPECIFIC_INFO
|
||||
#define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE
|
||||
#undef GET_TSC_RATE
|
||||
#define GET_TSC_RATE TRUE
|
||||
#undef BRAND_STRING1
|
||||
#define BRAND_STRING1 TRUE
|
||||
#undef BRAND_STRING2
|
||||
#define BRAND_STRING2 TRUE
|
||||
#endif
|
||||
|
||||
#if AGESA_ENTRY_INIT_S3SAVE == TRUE
|
||||
#endif
|
||||
|
||||
#if AGESA_ENTRY_INIT_RESUME == TRUE
|
||||
#undef GET_CFOH_REG
|
||||
#define GET_CFOH_REG TRUE
|
||||
#endif
|
||||
|
||||
#if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
|
||||
#endif
|
||||
|
||||
#if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE
|
||||
#undef ID_POSITION_INITIAL_APICID
|
||||
#define ID_POSITION_INITIAL_APICID TRUE
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Initialize PCI MMIO mask to 0
|
||||
*/
|
||||
#define FAMILY_MMIO_BASE_MASK (0ull)
|
||||
|
||||
|
||||
/*
|
||||
* Initialize all families to disabled
|
||||
*/
|
||||
#define OPT_F10_TABLE
|
||||
#define OPT_F12_TABLE
|
||||
#define OPT_F14_TABLE
|
||||
#define OPT_F15_TABLE
|
||||
|
||||
#define OPT_F10_ID_TABLE
|
||||
#define OPT_F12_ID_TABLE
|
||||
#define OPT_F14_ID_TABLE
|
||||
#define OPT_F15_ID_TABLE
|
||||
|
||||
|
||||
/*
|
||||
* Install family specific support
|
||||
*/
|
||||
#if (OPTION_FAMILY10H == TRUE)
|
||||
#include "OptionFamily10hInstall.h"
|
||||
#endif
|
||||
|
||||
#if (OPTION_FAMILY12H == TRUE)
|
||||
#include "OptionFamily12hInstall.h"
|
||||
#endif
|
||||
|
||||
#if (OPTION_FAMILY14H == TRUE)
|
||||
#include "OptionFamily14hInstall.h"
|
||||
#endif
|
||||
|
||||
#if (OPTION_FAMILY15H_OR == TRUE) || (OPTION_FAMILY15H_TN == TRUE)
|
||||
#include "OptionFamily15hInstall.h"
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Process PCI MMIO mask
|
||||
*/
|
||||
|
||||
// If size is 0, but base is not, break the build.
|
||||
#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE == 0)
|
||||
#error BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256
|
||||
#endif
|
||||
|
||||
// If base is 0, but size is not, break the build.
|
||||
#if (CFG_PCI_MMIO_BASE == 0) && (CFG_PCI_MMIO_SIZE != 0)
|
||||
#error BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater
|
||||
#endif
|
||||
|
||||
#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE != 0)
|
||||
// Both are non-zero, begin further processing.
|
||||
|
||||
// Heap runs from 4MB to 8MB. Disallow any addresses below 8MB.
|
||||
#if (CFG_PCI_MMIO_BASE < 0x800000)
|
||||
#error BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater
|
||||
#endif
|
||||
|
||||
// Break the build if the address is too high for the enabled families.
|
||||
#if ((CFG_PCI_MMIO_BASE & FAMILY_MMIO_BASE_MASK) != 0)
|
||||
#error BLDCFG: Invalid PCI MMIO base address for the installed CPU families
|
||||
#endif
|
||||
|
||||
// If the size parameter is not valid, break the build.
|
||||
#if (CFG_PCI_MMIO_SIZE != 1) && (CFG_PCI_MMIO_SIZE != 2) && (CFG_PCI_MMIO_SIZE != 4) && (CFG_PCI_MMIO_SIZE != 8) && (CFG_PCI_MMIO_SIZE != 16)
|
||||
#if (CFG_PCI_MMIO_SIZE != 32) && (CFG_PCI_MMIO_SIZE != 64) && (CFG_PCI_MMIO_SIZE != 128) && (CFG_PCI_MMIO_SIZE != 256)
|
||||
#error BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define PCI_MMIO_ALIGNMENT ((0x100000ul * CFG_PCI_MMIO_SIZE) - 1)
|
||||
// If the base is not aligned according to size, break the build.
|
||||
#if ((CFG_PCI_MMIO_BASE & PCI_MMIO_ALIGNMENT) != 0)
|
||||
#error BLDCFG: Invalid PCI MMIO base -- must be properly aligned according to MMIO size
|
||||
#endif
|
||||
#undef PCI_MMIO_ALIGNMENT
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Process sockets / modules
|
||||
*/
|
||||
#ifndef ADVCFG_PLATFORM_SOCKETS
|
||||
#error BLDOPT Set Family supported sockets.
|
||||
#endif
|
||||
#ifndef ADVCFG_PLATFORM_MODULES
|
||||
#error BLDOPT Set Family supported modules.
|
||||
#endif
|
||||
|
||||
CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration =
|
||||
{
|
||||
ADVCFG_PLATFORM_SOCKETS,
|
||||
ADVCFG_PLATFORM_MODULES
|
||||
};
|
||||
|
||||
/*
|
||||
* Instantiate global data needed for processor identification
|
||||
*/
|
||||
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CpuSupportedFamiliesArray[] =
|
||||
{
|
||||
OPT_F10_TABLE
|
||||
OPT_F12_TABLE
|
||||
OPT_F14_TABLE
|
||||
OPT_F15_TABLE
|
||||
{0, NULL}
|
||||
};
|
||||
|
||||
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CpuSupportedFamiliesTable =
|
||||
{
|
||||
(sizeof (CpuSupportedFamiliesArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
|
||||
&CpuSupportedFamiliesArray[0]
|
||||
};
|
||||
|
||||
|
||||
CONST CPU_LOGICAL_ID_FAMILY_XLAT ROMDATA CpuSupportedFamilyIdArray[] =
|
||||
{
|
||||
OPT_F10_ID_TABLE
|
||||
OPT_F12_ID_TABLE
|
||||
OPT_F14_ID_TABLE
|
||||
OPT_F15_ID_TABLE
|
||||
|
||||
};
|
||||
|
||||
CONST CPU_FAMILY_ID_XLAT_TABLE ROMDATA CpuSupportedFamilyIdTable =
|
||||
{
|
||||
(sizeof (CpuSupportedFamilyIdArray) / sizeof (CPU_LOGICAL_ID_FAMILY_XLAT)),
|
||||
CpuSupportedFamilyIdArray
|
||||
};
|
||||
@ -0,0 +1,108 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* Install of multiple CPU features.
|
||||
*
|
||||
* Aggregates enabled CPU features into a list for the dispatcher to process.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: Options
|
||||
* @e \$Revision: 63692 $ @e \$Date: 2012-01-03 22:13:28 -0600 (Tue, 03 Jan 2012) $
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef _OPTION_CPU_FEATURES_INSTALL_H_
|
||||
#define _OPTION_CPU_FEATURES_INSTALL_H_
|
||||
|
||||
#include "OptionHwC1eInstall.h"
|
||||
#include "OptionMsgBasedC1eInstall.h"
|
||||
#include "OptionSwC1eInstall.h"
|
||||
#include "OptionL3FeaturesInstall.h"
|
||||
#include "OptionCpuCoreLevelingInstall.h"
|
||||
#include "OptionIoCstateInstall.h"
|
||||
#include "OptionC6Install.h"
|
||||
#include "OptionCpbInstall.h"
|
||||
#include "OptionCpuCacheFlushOnHaltInstall.h"
|
||||
#include "OptionPstateHpcModeInstall.h"
|
||||
#include "OptionApmInstall.h"
|
||||
#include "OptionPsiInstall.h"
|
||||
#include "OptionHtcInstall.h"
|
||||
#include "OptionPreserveMailboxInstall.h"
|
||||
|
||||
CONST CPU_FEATURE_DESCRIPTOR* ROMDATA SupportedCpuFeatureList[] =
|
||||
{
|
||||
OPTION_HW_C1E_FEAT
|
||||
OPTION_MSG_BASED_C1E_FEAT
|
||||
OPTION_SW_C1E_FEAT
|
||||
OPTION_L3_FEAT
|
||||
OPTION_CPU_CORE_LEVELING_FEAT
|
||||
OPTION_IO_CSTATE_FEAT
|
||||
OPTION_C6_STATE_FEAT
|
||||
OPTION_CPB_FEAT
|
||||
OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
|
||||
OPTION_CPU_PSTATE_HPC_MODE_FEAT // this function should be run before low power pstate for prochot
|
||||
OPTION_CPU_APM_FEAT
|
||||
OPTION_CPU_PSI_FEAT
|
||||
OPTION_CPU_HTC_FEAT
|
||||
OPTION_PRESERVE_MAILBOX_FEAT
|
||||
NULL
|
||||
};
|
||||
|
||||
|
||||
#endif // _OPTION_CPU_FEATURES_INSTALL_H_
|
||||
116
src/vendorcode/amd/agesa/f15tn/Include/OptionDmi.h
Normal file
116
src/vendorcode/amd/agesa/f15tn/Include/OptionDmi.h
Normal file
@ -0,0 +1,116 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* AMD DMI option API.
|
||||
*
|
||||
* Contains structures and values used to control the DMI option code.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: OPTION
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef _OPTION_DMI_H_
|
||||
#define _OPTION_DMI_H_
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* D E F I N I T I O N S A N D M A C R O S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* T Y P E D E F S, S T R U C T U R E S, E N U M S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
typedef AGESA_STATUS OPTION_DMI_FEATURE (
|
||||
IN OUT AMD_CONFIG_PARAMS *StdHeader,
|
||||
IN OUT DMI_INFO **DmiPtr
|
||||
);
|
||||
|
||||
typedef AGESA_STATUS OPTION_DMI_RELEASE_BUFFER (
|
||||
IN OUT AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
#define DMI_STRUCT_VERSION 0x01
|
||||
|
||||
/// DMI option configuration. Determine the item of structure when compiling.
|
||||
typedef struct {
|
||||
UINT16 OptDmiVersion; ///< Dmi version.
|
||||
OPTION_DMI_FEATURE *DmiFeature; ///< Feature main routine, otherwise dummy.
|
||||
OPTION_DMI_RELEASE_BUFFER *DmiReleaseBuffer; ///< Release buffer
|
||||
UINT16 NumEntries; ///< Number of entry.
|
||||
VOID *((*FamilyList)[]); ///< Family service.
|
||||
} OPTION_DMI_CONFIGURATION;
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* F U N C T I O N P R O T O T Y P E
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
|
||||
#endif // _OPTION_DMI_H_
|
||||
242
src/vendorcode/amd/agesa/f15tn/Include/OptionDmiInstall.h
Normal file
242
src/vendorcode/amd/agesa/f15tn/Include/OptionDmiInstall.h
Normal file
@ -0,0 +1,242 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* Install of build option: DMI
|
||||
*
|
||||
* Contains AMD AGESA install macros and test conditions. Output is the
|
||||
* defaults tables reflecting the User's build options selection.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: Options
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef _OPTION_DMI_INSTALL_H_
|
||||
#define _OPTION_DMI_INSTALL_H_
|
||||
|
||||
#include "cpuLateInit.h"
|
||||
|
||||
/* This option is designed to be included into the platform solution install
|
||||
* file. The platform solution install file will define the options status.
|
||||
* Check to validate the definition
|
||||
*/
|
||||
#if AGESA_ENTRY_INIT_LATE == TRUE
|
||||
#ifndef OPTION_DMI
|
||||
#error BLDOPT: Option not defined: "OPTION_DMI"
|
||||
#endif
|
||||
#if OPTION_DMI == TRUE
|
||||
OPTION_DMI_FEATURE GetDmiInfoMain;
|
||||
OPTION_DMI_RELEASE_BUFFER ReleaseDmiBuffer;
|
||||
#define USER_DMI_OPTION &GetDmiInfoMain
|
||||
#define USER_DMI_RELEASE_BUFFER &ReleaseDmiBuffer
|
||||
|
||||
// This additional check keeps AP launch routines from being unnecessarily included
|
||||
// in single socket systems.
|
||||
#if OPTION_MULTISOCKET == TRUE
|
||||
#undef AGESA_ENTRY_LATE_RUN_AP_TASK
|
||||
#define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE
|
||||
#define CPU_DMI_AP_GET_TYPE4_TYPE7 {AP_LATE_TASK_GET_TYPE4_TYPE7, (IMAGE_ENTRY) GetType4Type7Info},
|
||||
#else
|
||||
#define CPU_DMI_AP_GET_TYPE4_TYPE7
|
||||
#endif
|
||||
|
||||
// Family 10
|
||||
#ifdef OPTION_FAMILY10H
|
||||
#if OPTION_FAMILY10H == TRUE
|
||||
extern PROC_FAMILY_TABLE ProcFamily10DmiTable;
|
||||
#define FAM10_DMI_SUPPORT FAM10_ENABLED,
|
||||
#define FAM10_DMI_TABLE &ProcFamily10DmiTable,
|
||||
#else
|
||||
#define FAM10_DMI_SUPPORT
|
||||
#define FAM10_DMI_TABLE
|
||||
#endif
|
||||
#else
|
||||
#define FAM10_DMI_SUPPORT
|
||||
#define FAM10_DMI_TABLE
|
||||
#endif
|
||||
|
||||
// Family 12
|
||||
#ifdef OPTION_FAMILY12H
|
||||
#if OPTION_FAMILY12H == TRUE
|
||||
extern PROC_FAMILY_TABLE ProcFamily12DmiTable;
|
||||
#define FAM12_DMI_SUPPORT FAM12_ENABLED,
|
||||
#define FAM12_DMI_TABLE &ProcFamily12DmiTable,
|
||||
#else
|
||||
#define FAM12_DMI_SUPPORT
|
||||
#define FAM12_DMI_TABLE
|
||||
#endif
|
||||
#else
|
||||
#define FAM12_DMI_SUPPORT
|
||||
#define FAM12_DMI_TABLE
|
||||
#endif
|
||||
|
||||
// Family 14
|
||||
#ifdef OPTION_FAMILY14H
|
||||
#if OPTION_FAMILY14H == TRUE
|
||||
extern PROC_FAMILY_TABLE ProcFamily14DmiTable;
|
||||
#define FAM14_DMI_SUPPORT FAM14_ENABLED,
|
||||
#define FAM14_DMI_TABLE &ProcFamily14DmiTable,
|
||||
#else
|
||||
#define FAM14_DMI_SUPPORT
|
||||
#define FAM14_DMI_TABLE
|
||||
#endif
|
||||
#else
|
||||
#define FAM14_DMI_SUPPORT
|
||||
#define FAM14_DMI_TABLE
|
||||
#endif
|
||||
|
||||
// Family 15
|
||||
#ifdef OPTION_FAMILY15H
|
||||
#if OPTION_FAMILY15H == TRUE
|
||||
#if OPTION_FAMILY15H_OR == TRUE
|
||||
extern PROC_FAMILY_TABLE ProcFamily15OrDmiTable;
|
||||
#define FAM15_OR_DMI_SUPPORT FAM15_OR_ENABLED,
|
||||
#define FAM15_OR_DMI_TABLE &ProcFamily15OrDmiTable,
|
||||
#else
|
||||
#define FAM15_OR_DMI_SUPPORT
|
||||
#define FAM15_OR_DMI_TABLE
|
||||
#endif
|
||||
#if OPTION_FAMILY15H_TN == TRUE
|
||||
extern PROC_FAMILY_TABLE ProcFamily15TnDmiTable;
|
||||
#define FAM15_TN_DMI_SUPPORT FAM15_TN_ENABLED,
|
||||
#define FAM15_TN_DMI_TABLE &ProcFamily15TnDmiTable,
|
||||
#else
|
||||
#define FAM15_TN_DMI_SUPPORT
|
||||
#define FAM15_TN_DMI_TABLE
|
||||
#endif
|
||||
#else
|
||||
#define FAM15_OR_DMI_SUPPORT
|
||||
#define FAM15_OR_DMI_TABLE
|
||||
#define FAM15_TN_DMI_SUPPORT
|
||||
#define FAM15_TN_DMI_TABLE
|
||||
#endif
|
||||
#else
|
||||
#define FAM15_OR_DMI_SUPPORT
|
||||
#define FAM15_OR_DMI_TABLE
|
||||
#define FAM15_TN_DMI_SUPPORT
|
||||
#define FAM15_TN_DMI_TABLE
|
||||
#endif
|
||||
|
||||
#else
|
||||
OPTION_DMI_FEATURE GetDmiInfoStub;
|
||||
OPTION_DMI_RELEASE_BUFFER ReleaseDmiBufferStub;
|
||||
#define USER_DMI_OPTION GetDmiInfoStub
|
||||
#define USER_DMI_RELEASE_BUFFER ReleaseDmiBufferStub
|
||||
#define FAM10_DMI_SUPPORT
|
||||
#define FAM10_DMI_TABLE
|
||||
#define FAM12_DMI_SUPPORT
|
||||
#define FAM12_DMI_TABLE
|
||||
#define FAM14_DMI_SUPPORT
|
||||
#define FAM14_DMI_TABLE
|
||||
#define FAM15_OR_DMI_SUPPORT
|
||||
#define FAM15_OR_DMI_TABLE
|
||||
#define FAM15_TN_DMI_SUPPORT
|
||||
#define FAM15_TN_DMI_TABLE
|
||||
#define CPU_DMI_AP_GET_TYPE4_TYPE7
|
||||
#endif
|
||||
#else
|
||||
OPTION_DMI_FEATURE GetDmiInfoStub;
|
||||
OPTION_DMI_RELEASE_BUFFER ReleaseDmiBufferStub;
|
||||
#define USER_DMI_OPTION GetDmiInfoStub
|
||||
#define USER_DMI_RELEASE_BUFFER ReleaseDmiBufferStub
|
||||
#define FAM10_DMI_SUPPORT
|
||||
#define FAM10_DMI_TABLE
|
||||
#define FAM12_DMI_SUPPORT
|
||||
#define FAM12_DMI_TABLE
|
||||
#define FAM14_DMI_SUPPORT
|
||||
#define FAM14_DMI_TABLE
|
||||
#define FAM15_OR_DMI_SUPPORT
|
||||
#define FAM15_OR_DMI_TABLE
|
||||
#define FAM15_TN_DMI_SUPPORT
|
||||
#define FAM15_TN_DMI_TABLE
|
||||
#define CPU_DMI_AP_GET_TYPE4_TYPE7
|
||||
#endif
|
||||
|
||||
/// DMI supported families enum
|
||||
typedef enum {
|
||||
FAM10_DMI_SUPPORT ///< Conditionally define F10 support
|
||||
FAM12_DMI_SUPPORT ///< Conditionally define F12 support
|
||||
FAM14_DMI_SUPPORT ///< Conditionally define F14 support
|
||||
FAM15_OR_DMI_SUPPORT ///< Conditionally define F15 OR support
|
||||
FAM15_TN_DMI_SUPPORT ///< Conditionally define F15 TN support
|
||||
NUM_DMI_FAMILIES ///< Number of installed families
|
||||
} AGESA_DMI_SUPPORTED_FAM;
|
||||
|
||||
/* Declare the Family List. An array of pointers to tables that each describe a family */
|
||||
CONST PROC_FAMILY_TABLE ROMDATA *ProcTables[] = {
|
||||
FAM10_DMI_TABLE
|
||||
FAM12_DMI_TABLE
|
||||
FAM14_DMI_TABLE
|
||||
FAM15_OR_DMI_TABLE
|
||||
FAM15_TN_DMI_TABLE
|
||||
NULL,
|
||||
NULL
|
||||
};
|
||||
|
||||
/* Declare the instance of the DMI option configuration structure */
|
||||
CONST OPTION_DMI_CONFIGURATION ROMDATA OptionDmiConfiguration = {
|
||||
DMI_STRUCT_VERSION,
|
||||
USER_DMI_OPTION,
|
||||
USER_DMI_RELEASE_BUFFER,
|
||||
NUM_DMI_FAMILIES,
|
||||
(VOID *((*)[])) &ProcTables // Compiler says array size must match struct decl
|
||||
};
|
||||
|
||||
#endif // _OPTION_DMI_INSTALL_H_
|
||||
1206
src/vendorcode/amd/agesa/f15tn/Include/OptionFamily15hInstall.h
Normal file
1206
src/vendorcode/amd/agesa/f15tn/Include/OptionFamily15hInstall.h
Normal file
File diff suppressed because it is too large
Load Diff
1024
src/vendorcode/amd/agesa/f15tn/Include/OptionFchInstall.h
Normal file
1024
src/vendorcode/amd/agesa/f15tn/Include/OptionFchInstall.h
Normal file
File diff suppressed because it is too large
Load Diff
108
src/vendorcode/amd/agesa/f15tn/Include/OptionGfxRecovery.h
Normal file
108
src/vendorcode/amd/agesa/f15tn/Include/OptionGfxRecovery.h
Normal file
@ -0,0 +1,108 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* AMD GFX Recovery option API.
|
||||
*
|
||||
* Contains structures and values used to control the GfxRecovery option code.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: OPTION
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef _OPTION_GFX_RECOVERY_H_
|
||||
#define _OPTION_GFX_RECOVERY_H_
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* D E F I N I T I O N S A N D M A C R O S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* T Y P E D E F S, S T R U C T U R E S, E N U M S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
typedef AGESA_STATUS OPTION_GFX_RECOVERY_FEATURE (
|
||||
IN OUT AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
#define GFX_RECOVERY_STRUCT_VERSION 0x01
|
||||
|
||||
/// The Option Configuration of GFX Recovery
|
||||
typedef struct {
|
||||
UINT16 OptGfxRecoveryVersion; ///< The version number of GFX Recovery
|
||||
OPTION_GFX_RECOVERY_FEATURE *GfxRecoveryFeature; ///< The Option Feature of GFX Recovery
|
||||
} OPTION_GFX_RECOVERY_CONFIGURATION;
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* F U N C T I O N P R O T O T Y P E
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
|
||||
#endif // _OPTION_GFX_RECOVERY_H_
|
||||
@ -0,0 +1,80 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* Install of build option: GfxRecovery
|
||||
*
|
||||
* Contains AMD AGESA install macros and test conditions. Output is the
|
||||
* defaults tables reflecting the User's build options selection.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: Options
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef _OPTION_GFX_RECOVERY_INSTALL_H_
|
||||
#define _OPTION_GFX_RECOVERY_INSTALL_H_
|
||||
|
||||
/* This option is designed to be included into the platform solution install
|
||||
* file. The platform solution install file will define the options status.
|
||||
* Check to validate the definition
|
||||
*/
|
||||
|
||||
|
||||
#endif // _OPTION_GFX_RECOVERY_INSTALL_H_
|
||||
149
src/vendorcode/amd/agesa/f15tn/Include/OptionGnb.h
Normal file
149
src/vendorcode/amd/agesa/f15tn/Include/OptionGnb.h
Normal file
@ -0,0 +1,149 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* AMD ALIB option API.
|
||||
*
|
||||
* Contains structures and values used to control the ALIB option code.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: OPTION
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef _OPTION_GNB_H_
|
||||
#define _OPTION_GNB_H_
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* D E F I N I T I O N S A N D M A C R O S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* T Y P E D E F S, S T R U C T U R E S, E N U M S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
|
||||
typedef AGESA_STATUS OPTION_GNB_FEATURE (
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
typedef AGESA_STATUS F_ALIB_UPDATE (
|
||||
IN OUT VOID *AlibSsdtBuffer,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
typedef VOID* F_ALIB_GET (
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
/// The Option Configuration
|
||||
typedef struct {
|
||||
UINT64 Type; ///< Type
|
||||
OPTION_GNB_FEATURE *GnbFeature; ///< The GNB Feature
|
||||
} OPTION_GNB_CONFIGURATION;
|
||||
|
||||
/// The Build time options configuration
|
||||
typedef struct {
|
||||
BOOLEAN IgfxModeAsPcieEp; ///< Itegrated Gfx mode Pcie EP or Legacy
|
||||
BOOLEAN LclkDeepSleepEn; ///< Default for LCLK deep sleep
|
||||
BOOLEAN LclkDpmEn; ///< Default for LCLK DPM
|
||||
UINT8 GmcPowerGating; ///< Control GMC power gating
|
||||
BOOLEAN SmuSclkClockGatingEnable; ///< Control SMU SCLK gating
|
||||
BOOLEAN PcieAspmBlackListEnable; ///< Control Pcie Aspm Black List
|
||||
BOOLEAN IvrsRelativeAddrNamesSupport; ///< Support for relative address names
|
||||
BOOLEAN GnbLoadRealFuseTable; ///< Support for fuse table loading
|
||||
UINT32 CfgGnbLinkReceiverDetectionPooling; ///< Receiver pooling detection time in us.
|
||||
UINT32 CfgGnbLinkL0Pooling; ///< Pooling for link to get to L0 in us
|
||||
UINT32 CfgGnbLinkGpioResetAssertionTime; ///< Gpio reset assertion time in us
|
||||
UINT32 CfgGnbLinkResetToTrainingTime; ///< Time duration between deassert GPIO reset and release training in us
|
||||
UINT8 CfgGnbTrainingAlgorithm; ///< distribution of training across interface calls
|
||||
BOOLEAN CfgForceCableSafeOff; ///< Force cable safe off
|
||||
BOOLEAN CfgOrbClockGatingEnable; ///< Control ORB clock gating
|
||||
UINT8 CfgPciePowerGatingFlags; ///< Pcie Power gating flags
|
||||
BOOLEAN CfgIocLclkClockGatingEnable; ///< Control IOC LCLK clock gating
|
||||
BOOLEAN CfgIocSclkClockGatingEnable; ///< Control IOC SCLK clock gating
|
||||
BOOLEAN CfgIommuL1ClockGatingEnable; ///< Control IOMMU L1 clock gating
|
||||
BOOLEAN CfgIommuL2ClockGatingEnable; ///< Control IOMMU L2 clock gating
|
||||
BOOLEAN CfgAltVddNb; ///< AltVDDNB support
|
||||
BOOLEAN CfgBapmSupport; ///< BAPM support
|
||||
BOOLEAN CfgUnusedSimdPowerGatingEnable; ///< Control unused SIMD power gate
|
||||
BOOLEAN CfgUnusedRbPowerGatingEnable; ///< Control unused SIMD power gate
|
||||
BOOLEAN CfgNbdpmEnable; ///< NBDPM refers to dynamically reprogramming High and Low NB Pstates under different system usage scenarios
|
||||
BOOLEAN CfgGmcClockGating; ///< Control GMC clock power gate
|
||||
BOOLEAN CfgMaxPayloadEnable; ///< Enables configuration of Max_Payload_Size in PCIe device links
|
||||
BOOLEAN CfgOrbDynWakeEnable; ///< Enables ORB Dynamic wake up
|
||||
BOOLEAN CfgLoadlineEnable; ///< Enable Loadline Optimization
|
||||
} GNB_BUILD_OPTIONS;
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* F U N C T I O N P R O T O T Y P E
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#endif // _OPTION_GNB_H_
|
||||
942
src/vendorcode/amd/agesa/f15tn/Include/OptionGnbInstall.h
Normal file
942
src/vendorcode/amd/agesa/f15tn/Include/OptionGnbInstall.h
Normal file
@ -0,0 +1,942 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* Install of build option: GNB
|
||||
*
|
||||
* Contains AMD AGESA install macros and test conditions. Output is the
|
||||
* defaults tables reflecting the User's build options selection.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: Options
|
||||
* @e \$Revision: 64464 $ @e \$Date: 2012-01-21 11:28:59 -0600 (Sat, 21 Jan 2012) $
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef _OPTION_GNB_INSTALL_H_
|
||||
#define _OPTION_GNB_INSTALL_H_
|
||||
|
||||
#include "S3SaveState.h"
|
||||
/* This option is designed to be included into the platform solution install
|
||||
* file. The platform solution install file will define the options status.
|
||||
* Check to validate the definition
|
||||
*/
|
||||
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
// Family installation
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
#define GNB_TYPE_TN FALSE
|
||||
#define GNB_TYPE_LN FALSE
|
||||
#define GNB_TYPE_ON FALSE
|
||||
|
||||
#if (OPTION_FAMILY14H_ON == TRUE)
|
||||
#undef GNB_TYPE_ON
|
||||
#define GNB_TYPE_ON TRUE
|
||||
#endif
|
||||
|
||||
#if (OPTION_FAMILY12H_LN == TRUE)
|
||||
#undef GNB_TYPE_LN
|
||||
#define GNB_TYPE_LN TRUE
|
||||
#endif
|
||||
|
||||
#if (OPTION_FAMILY15H_TN == TRUE)
|
||||
#undef GNB_TYPE_TN
|
||||
#define GNB_TYPE_TN TRUE
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#if (GNB_TYPE_TN == TRUE || GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
// Service installation
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
|
||||
#include "Gnb.h"
|
||||
#include "GnbPcie.h"
|
||||
#include "GnbGfx.h"
|
||||
|
||||
#define SERVICES_POINTER NULL
|
||||
#if (GNB_TYPE_TN == TRUE)
|
||||
#include "GnbInitTNInstall.h"
|
||||
#endif
|
||||
GNB_SERVICE *ServiceTable = SERVICES_POINTER;
|
||||
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
// BUILD options
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
|
||||
#ifndef CFG_IGFX_AS_PCIE_EP
|
||||
#define CFG_IGFX_AS_PCIE_EP TRUE
|
||||
#endif
|
||||
|
||||
#ifndef CFG_LCLK_DEEP_SLEEP_EN
|
||||
#if (GNB_TYPE_TN == TRUE)
|
||||
#define CFG_LCLK_DEEP_SLEEP_EN FALSE
|
||||
#else
|
||||
#define CFG_LCLK_DEEP_SLEEP_EN TRUE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef CFG_LCLK_DPM_EN
|
||||
#define CFG_LCLK_DPM_EN TRUE
|
||||
#endif
|
||||
|
||||
#ifndef CFG_GMC_POWER_GATING
|
||||
#if (GNB_TYPE_TN == TRUE)
|
||||
#define CFG_GMC_POWER_GATING GmcPowerGatingWidthStutter
|
||||
#else
|
||||
#define CFG_GMC_POWER_GATING GmcPowerGatingWidthStutter
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef CFG_SMU_SCLK_CLOCK_GATING_ENABLE
|
||||
#if (GNB_TYPE_ON == TRUE || GNB_TYPE_TN == TRUE)
|
||||
#define CFG_SMU_SCLK_CLOCK_GATING_ENABLE TRUE
|
||||
#else
|
||||
#define CFG_SMU_SCLK_CLOCK_GATING_ENABLE FALSE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef CFG_PCIE_ASPM_BLACK_LIST_ENABLE
|
||||
#define CFG_PCIE_ASPM_BLACK_LIST_ENABLE TRUE
|
||||
#endif
|
||||
|
||||
#ifndef CFG_GNB_IVRS_RELATIVE_ADDR_NAMES_SUPPORT
|
||||
#define CFG_GNB_IVRS_RELATIVE_ADDR_NAMES_SUPPORT FALSE
|
||||
#endif
|
||||
|
||||
#ifndef CFG_GNB_LOAD_REAL_FUSE
|
||||
#define CFG_GNB_LOAD_REAL_FUSE TRUE
|
||||
#endif
|
||||
|
||||
#ifndef CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING
|
||||
#define CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING (60 * 1000)
|
||||
#endif
|
||||
|
||||
#ifndef CFG_GNB_PCIE_LINK_L0_POOLING
|
||||
#define CFG_GNB_PCIE_LINK_L0_POOLING (60 * 1000)
|
||||
#endif
|
||||
|
||||
#ifndef CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME
|
||||
#define CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME (2 * 1000)
|
||||
#endif
|
||||
|
||||
#ifndef CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME
|
||||
#define CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME (2 * 1000)
|
||||
#endif
|
||||
|
||||
#ifdef BLDCFG_PCIE_TRAINING_ALGORITHM
|
||||
#define CFG_GNB_PCIE_TRAINING_ALGORITHM BLDCFG_PCIE_TRAINING_ALGORITHM
|
||||
#else
|
||||
#define CFG_GNB_PCIE_TRAINING_ALGORITHM PcieTrainingStandard
|
||||
#endif
|
||||
|
||||
#ifndef CFG_GNB_FORCE_CABLESAFE_OFF
|
||||
#define CFG_GNB_FORCE_CABLESAFE_OFF FALSE
|
||||
#endif
|
||||
|
||||
#ifndef CFG_ORB_CLOCK_GATING_ENABLE
|
||||
#define CFG_ORB_CLOCK_GATING_ENABLE TRUE
|
||||
#endif
|
||||
|
||||
#ifndef CFG_GNB_PCIE_POWERGATING_FLAGS
|
||||
#define CFG_GNB_PCIE_POWERGATING_FLAGS 0x0
|
||||
#endif
|
||||
|
||||
#ifndef CFG_IOC_LCLK_CLOCK_GATING_ENABLE
|
||||
#if (GNB_TYPE_TN == TRUE)
|
||||
#define CFG_IOC_LCLK_CLOCK_GATING_ENABLE TRUE
|
||||
#else
|
||||
#define CFG_IOC_LCLK_CLOCK_GATING_ENABLE FALSE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef CFG_IOC_SCLK_CLOCK_GATING_ENABLE
|
||||
#if (GNB_TYPE_TN == TRUE)
|
||||
#define CFG_IOC_SCLK_CLOCK_GATING_ENABLE TRUE
|
||||
#else
|
||||
#define CFG_IOC_SCLK_CLOCK_GATING_ENABLE FALSE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef CFG_IOMMU_L1_CLOCK_GATING_ENABLE
|
||||
#if (GNB_TYPE_TN == TRUE)
|
||||
#define CFG_IOMMU_L1_CLOCK_GATING_ENABLE TRUE
|
||||
#else
|
||||
#define CFG_IOMMU_L1_CLOCK_GATING_ENABLE FALSE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef CFG_IOMMU_L2_CLOCK_GATING_ENABLE
|
||||
#if (GNB_TYPE_TN == TRUE)
|
||||
#define CFG_IOMMU_L2_CLOCK_GATING_ENABLE TRUE
|
||||
#else
|
||||
#define CFG_IOMMU_L2_CLOCK_GATING_ENABLE FALSE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef CFG_GNB_ALTVDDNB_SUPPORT
|
||||
#define CFG_GNB_ALTVDDNB_SUPPORT TRUE
|
||||
#endif
|
||||
|
||||
#ifndef CFG_GNB_BAPM_SUPPORT
|
||||
#if (GNB_TYPE_TN == TRUE)
|
||||
#define CFG_GNB_BAPM_SUPPORT TRUE
|
||||
#else
|
||||
#define CFG_GNB_BAPM_SUPPORT FALSE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef CFG_UNUSED_SIMD_POWERGATING_ENABLE
|
||||
#define CFG_UNUSED_SIMD_POWERGATING_ENABLE TRUE
|
||||
#endif
|
||||
|
||||
#ifndef CFG_UNUSED_RB_POWERGATING_ENABLE
|
||||
#define CFG_UNUSED_RB_POWERGATING_ENABLE FALSE
|
||||
#endif
|
||||
|
||||
#ifndef CFG_NBDPM_ENABLE
|
||||
#define CFG_NBDPM_ENABLE TRUE
|
||||
#endif
|
||||
|
||||
#ifndef CFG_MAX_PAYLOAD_ENABLE
|
||||
#define CFG_MAX_PAYLOAD_ENABLE TRUE
|
||||
#endif
|
||||
|
||||
#ifndef CFG_GMC_CLOCK_GATING
|
||||
#if (GNB_TYPE_TN == TRUE)
|
||||
#define CFG_GMC_CLOCK_GATING TRUE
|
||||
#else
|
||||
#define CFG_GMC_CLOCK_GATING TRUE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef CFG_ORB_DYN_WAKE_ENABLE
|
||||
#if (GNB_TYPE_TN == TRUE)
|
||||
#define CFG_ORB_DYN_WAKE_ENABLE TRUE
|
||||
#else
|
||||
#define CFG_ORB_DYN_WAKE_ENABLE TRUE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef CFG_LOADLINE_ENABLE
|
||||
#define CFG_LOADLINE_ENABLE TRUE
|
||||
#endif
|
||||
|
||||
GNB_BUILD_OPTIONS ROMDATA GnbBuildOptions = {
|
||||
CFG_IGFX_AS_PCIE_EP,
|
||||
CFG_LCLK_DEEP_SLEEP_EN,
|
||||
CFG_LCLK_DPM_EN,
|
||||
CFG_GMC_POWER_GATING,
|
||||
CFG_SMU_SCLK_CLOCK_GATING_ENABLE,
|
||||
CFG_PCIE_ASPM_BLACK_LIST_ENABLE,
|
||||
CFG_GNB_IVRS_RELATIVE_ADDR_NAMES_SUPPORT,
|
||||
CFG_GNB_LOAD_REAL_FUSE,
|
||||
CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING,
|
||||
CFG_GNB_PCIE_LINK_L0_POOLING,
|
||||
CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME,
|
||||
CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME,
|
||||
CFG_GNB_PCIE_TRAINING_ALGORITHM,
|
||||
CFG_GNB_FORCE_CABLESAFE_OFF,
|
||||
CFG_ORB_CLOCK_GATING_ENABLE,
|
||||
CFG_GNB_PCIE_POWERGATING_FLAGS,
|
||||
CFG_IOC_LCLK_CLOCK_GATING_ENABLE,
|
||||
CFG_IOC_SCLK_CLOCK_GATING_ENABLE,
|
||||
CFG_IOMMU_L1_CLOCK_GATING_ENABLE,
|
||||
CFG_IOMMU_L2_CLOCK_GATING_ENABLE,
|
||||
CFG_GNB_ALTVDDNB_SUPPORT,
|
||||
CFG_GNB_BAPM_SUPPORT,
|
||||
CFG_UNUSED_SIMD_POWERGATING_ENABLE,
|
||||
CFG_UNUSED_RB_POWERGATING_ENABLE,
|
||||
CFG_NBDPM_ENABLE,
|
||||
CFG_GMC_CLOCK_GATING,
|
||||
CFG_MAX_PAYLOAD_ENABLE,
|
||||
CFG_ORB_DYN_WAKE_ENABLE,
|
||||
CFG_LOADLINE_ENABLE
|
||||
};
|
||||
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
// Module entries
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
|
||||
#if (AGESA_ENTRY_INIT_EARLY == TRUE)
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
#ifndef OPTION_NB_EARLY_INIT
|
||||
#define OPTION_NB_EARLY_INIT TRUE
|
||||
#endif
|
||||
#if (OPTION_NB_EARLY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
|
||||
OPTION_GNB_FEATURE NbInitAtEarly;
|
||||
#define OPTION_NBINITATEARLY_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , NbInitAtEarly},
|
||||
#else
|
||||
#define OPTION_NBINITATEARLY_ENTRY
|
||||
#endif
|
||||
#if (OPTION_NB_EARLY_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
|
||||
OPTION_GNB_FEATURE GnbEarlyInterfaceTN;
|
||||
#define OPTION_GNBEARLYINTERFACETN_ENTRY {AMD_FAMILY_TN, GnbEarlyInterfaceTN},
|
||||
#else
|
||||
#define OPTION_GNBEARLYINTERFACETN_ENTRY
|
||||
#endif
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
// SMU init
|
||||
#ifndef OPTION_SMU
|
||||
#define OPTION_SMU TRUE
|
||||
#endif
|
||||
#if (OPTION_SMU == TRUE) && (GNB_TYPE_LN == TRUE)
|
||||
OPTION_GNB_FEATURE F12NbSmuInitFeature;
|
||||
#define OPTION_F12NBSMUINITFEATURE_ENTRY {AMD_FAMILY_LN, F12NbSmuInitFeature},
|
||||
#else
|
||||
#define OPTION_F12NBSMUINITFEATURE_ENTRY
|
||||
#endif
|
||||
#if (OPTION_SMU == TRUE) && (GNB_TYPE_ON == TRUE)
|
||||
OPTION_GNB_FEATURE F14NbSmuInitFeature;
|
||||
#define OPTION_F14NBSMUINITFEATURE_ENTRY {AMD_FAMILY_ON, F14NbSmuInitFeature},
|
||||
#else
|
||||
#define OPTION_F14NBSMUINITFEATURE_ENTRY
|
||||
#endif
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
#ifndef OPTION_PCIE_CONFIG_MAP
|
||||
#define OPTION_PCIE_CONFIG_MAP TRUE
|
||||
#endif
|
||||
#if (OPTION_PCIE_CONFIG_MAP == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE || GNB_TYPE_TN == TRUE )
|
||||
OPTION_GNB_FEATURE PcieConfigurationMap;
|
||||
#define OPTION_PCIECONFIGURATIONMAP_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON | AMD_FAMILY_TN , PcieConfigurationMap},
|
||||
#else
|
||||
#define OPTION_PCIECONFIGURATIONMAP_ENTRY
|
||||
#endif
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
#ifndef OPTION_PCIE_EARLY_INIT
|
||||
#define OPTION_PCIE_EARLY_INIT TRUE
|
||||
#endif
|
||||
#if (OPTION_PCIE_EARLY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
|
||||
OPTION_GNB_FEATURE PcieInitAtEarly;
|
||||
#define OPTION_PCIEINITATEARLY_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , PcieInitAtEarly},
|
||||
#else
|
||||
#define OPTION_PCIEINITATEARLY_ENTRY
|
||||
#endif
|
||||
#if (OPTION_PCIE_EARLY_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
|
||||
OPTION_GNB_FEATURE PcieEarlyInterfaceTN;
|
||||
#define OPTION_PCIEEARLYINTERFACETN_ENTRY {AMD_FAMILY_TN, PcieEarlyInterfaceTN},
|
||||
#else
|
||||
#define OPTION_PCIEEARLYINTERFACETN_ENTRY
|
||||
#endif
|
||||
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
OPTION_GNB_CONFIGURATION GnbEarlyFeatureTable[] = {
|
||||
OPTION_NBINITATEARLY_ENTRY
|
||||
OPTION_GNBEARLYINTERFACETN_ENTRY
|
||||
OPTION_F12NBSMUINITFEATURE_ENTRY
|
||||
OPTION_F14NBSMUINITFEATURE_ENTRY
|
||||
OPTION_PCIECONFIGURATIONMAP_ENTRY
|
||||
OPTION_PCIEINITATEARLY_ENTRY
|
||||
OPTION_PCIEEARLYINTERFACETN_ENTRY
|
||||
{0, NULL}
|
||||
};
|
||||
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
#ifndef OPTION_PCIE_CONFIG_INIT
|
||||
#define OPTION_PCIE_CONFIG_INIT TRUE
|
||||
#endif
|
||||
#if (OPTION_PCIE_CONFIG_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE || GNB_TYPE_TN == TRUE )
|
||||
OPTION_GNB_FEATURE PcieConfigurationInit;
|
||||
#define OPTION_PCIECONFIGURATIONINIT_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON | AMD_FAMILY_TN , PcieConfigurationInit},
|
||||
#else
|
||||
#define OPTION_PCIECONFIGURATIONINIT_ENTRY
|
||||
#endif
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
#ifndef OPTION_NB_EARLIER_INIT
|
||||
#define OPTION_NB_EARLIER_INIT TRUE
|
||||
#endif
|
||||
#if (OPTION_NB_EARLIER_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
|
||||
OPTION_GNB_FEATURE GnbEarlierInterfaceTN;
|
||||
#define OPTION_GNBEARLIERINTERFACETN_ENTRY {AMD_FAMILY_TN, GnbEarlierInterfaceTN},
|
||||
#else
|
||||
#define OPTION_GNBEARLIERINTERFACETN_ENTRY
|
||||
#endif
|
||||
|
||||
OPTION_GNB_CONFIGURATION GnbEarlierFeatureTable[] = {
|
||||
OPTION_PCIECONFIGURATIONINIT_ENTRY
|
||||
OPTION_GNBEARLIERINTERFACETN_ENTRY
|
||||
{0, NULL}
|
||||
};
|
||||
#endif
|
||||
|
||||
#if (AGESA_ENTRY_INIT_POST == TRUE)
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
#ifndef OPTION_GFX_CONFIG_POST_INIT
|
||||
#define OPTION_GFX_CONFIG_POST_INIT TRUE
|
||||
#endif
|
||||
#if (OPTION_GFX_CONFIG_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE || GNB_TYPE_TN == TRUE )
|
||||
OPTION_GNB_FEATURE GfxConfigPostInterface;
|
||||
#define OPTION_GFXCONFIGPOSTINTERFACE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON | AMD_FAMILY_TN , GfxConfigPostInterface},
|
||||
#else
|
||||
#define OPTION_GFXCONFIGPOSTINTERFACE_ENTRY
|
||||
#endif
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
#ifndef OPTION_GFX_POST_INIT
|
||||
#define OPTION_GFX_POST_INIT TRUE
|
||||
#endif
|
||||
#if (OPTION_GFX_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
|
||||
OPTION_GNB_FEATURE GfxInitAtPost;
|
||||
#define OPTION_GFXINITATPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , GfxInitAtPost},
|
||||
#else
|
||||
#define OPTION_GFXINITATPOST_ENTRY
|
||||
#endif
|
||||
#if (OPTION_GFX_POST_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
|
||||
OPTION_GNB_FEATURE GfxPostInterfaceTN;
|
||||
#define OPTION_GFXPOSTINTERFACETN_ENTRY {AMD_FAMILY_TN, GfxPostInterfaceTN},
|
||||
#else
|
||||
#define OPTION_GFXPOSTINTERFACETN_ENTRY
|
||||
#endif
|
||||
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
#ifndef OPTION_NB_POST_INIT
|
||||
#define OPTION_NB_POST_INIT TRUE
|
||||
#endif
|
||||
#if (OPTION_NB_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
|
||||
OPTION_GNB_FEATURE NbInitAtPost;
|
||||
#define OPTION_NBINITATPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , NbInitAtPost},
|
||||
#else
|
||||
#define OPTION_NBINITATPOST_ENTRY
|
||||
#endif
|
||||
#if (OPTION_NB_POST_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
|
||||
OPTION_GNB_FEATURE GnbPostInterfaceTN;
|
||||
#define OPTION_GNBPOSTINTERFACETN_ENTRY {AMD_FAMILY_TN, GnbPostInterfaceTN},
|
||||
#else
|
||||
#define OPTION_GNBPOSTINTERFACETN_ENTRY
|
||||
#endif
|
||||
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
#ifndef OPTION_PCIE_POST_EALRY_INIT
|
||||
#define OPTION_PCIE_POST_EALRY_INIT TRUE
|
||||
#endif
|
||||
#if (OPTION_PCIE_POST_EALRY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
|
||||
OPTION_GNB_FEATURE PcieInitAtPostEarly;
|
||||
#define OPTION_PCIEINITATPOSTEARLY_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , PcieInitAtPostEarly},
|
||||
#else
|
||||
#define OPTION_PCIEINITATPOSTEARLY_ENTRY
|
||||
#endif
|
||||
#if (OPTION_PCIE_POST_EALRY_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
|
||||
OPTION_GNB_FEATURE PciePostEarlyInterfaceTN;
|
||||
#define OPTION_PCIEPOSTEARLYINTERFACETN_ENTRY {AMD_FAMILY_TN, PciePostEarlyInterfaceTN},
|
||||
#else
|
||||
#define OPTION_PCIEPOSTEARLYINTERFACETN_ENTRY
|
||||
#endif
|
||||
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
#ifndef OPTION_PCIE_POST_INIT
|
||||
#define OPTION_PCIE_POST_INIT TRUE
|
||||
#endif
|
||||
#if (OPTION_PCIE_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
|
||||
OPTION_GNB_FEATURE PcieInitAtPost;
|
||||
#define OPTION_PCIEINITATPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , PcieInitAtPost},
|
||||
#else
|
||||
#define OPTION_PCIEINITATPOST_ENTRY
|
||||
#endif
|
||||
#if (OPTION_PCIE_POST_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
|
||||
OPTION_GNB_FEATURE PciePostInterfaceTN;
|
||||
#define OPTION_PCIEPOSTINTERFACETN_ENTRY {AMD_FAMILY_TN, PciePostInterfaceTN},
|
||||
#else
|
||||
#define OPTION_PCIEPOSTINTERFACETN_ENTRY
|
||||
#endif
|
||||
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
OPTION_GNB_CONFIGURATION GnbPostFeatureTable[] = {
|
||||
OPTION_PCIEINITATPOSTEARLY_ENTRY
|
||||
OPTION_PCIEPOSTEARLYINTERFACETN_ENTRY
|
||||
OPTION_GFXCONFIGPOSTINTERFACE_ENTRY
|
||||
OPTION_GFXINITATPOST_ENTRY
|
||||
OPTION_GFXPOSTINTERFACETN_ENTRY
|
||||
{0, NULL}
|
||||
};
|
||||
|
||||
OPTION_GNB_CONFIGURATION GnbPostAfterDramFeatureTable[] = {
|
||||
OPTION_NBINITATPOST_ENTRY
|
||||
OPTION_GNBPOSTINTERFACETN_ENTRY
|
||||
OPTION_PCIEINITATPOST_ENTRY
|
||||
OPTION_PCIEPOSTINTERFACETN_ENTRY
|
||||
{0, NULL}
|
||||
};
|
||||
#endif
|
||||
|
||||
#if (AGESA_ENTRY_INIT_ENV == TRUE)
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
#ifndef OPTION_FUSE_TABLE_INIT
|
||||
#define OPTION_FUSE_TABLE_INIT TRUE
|
||||
#endif
|
||||
#if (OPTION_FUSE_TABLE_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
|
||||
OPTION_GNB_FEATURE NbFuseTableFeature;
|
||||
#define OPTION_NBFUSETABLEFEATURE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , NbFuseTableFeature},
|
||||
#else
|
||||
#define OPTION_NBFUSETABLEFEATURE_ENTRY
|
||||
#endif
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
#ifndef OPTION_NB_ENV_INIT
|
||||
#define OPTION_NB_ENV_INIT TRUE
|
||||
#endif
|
||||
#if (OPTION_NB_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
|
||||
OPTION_GNB_FEATURE NbInitAtEnv;
|
||||
#define OPTION_NBINITATENVT_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , NbInitAtEnv},
|
||||
#else
|
||||
#define OPTION_NBINITATENVT_ENTRY
|
||||
#endif
|
||||
#if (OPTION_NB_ENV_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
|
||||
OPTION_GNB_FEATURE GnbEnvInterfaceTN;
|
||||
#define OPTION_GNBENVINTERFACETN_ENTRY {AMD_FAMILY_TN, GnbEnvInterfaceTN},
|
||||
#else
|
||||
#define OPTION_GNBENVINTERFACETN_ENTRY
|
||||
#endif
|
||||
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
#ifndef OPTION_GFX_CONFIG_ENV_INIT
|
||||
#define OPTION_GFX_CONFIG_ENV_INIT TRUE
|
||||
#endif
|
||||
#if (OPTION_GFX_CONFIG_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE || GNB_TYPE_TN == TRUE )
|
||||
OPTION_GNB_FEATURE GfxConfigEnvInterface;
|
||||
#define OPTION_GFXCONFIGENVINTERFACE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON | AMD_FAMILY_TN, GfxConfigEnvInterface},
|
||||
#else
|
||||
#define OPTION_GFXCONFIGENVINTERFACE_ENTRY
|
||||
#endif
|
||||
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
#ifndef OPTION_GFX_ENV_INIT
|
||||
#define OPTION_GFX_ENV_INIT TRUE
|
||||
#endif
|
||||
#if (OPTION_GFX_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
|
||||
OPTION_GNB_FEATURE GfxInitAtEnvPost;
|
||||
#define OPTION_GFXINITATENVPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , GfxInitAtEnvPost},
|
||||
#else
|
||||
#define OPTION_GFXINITATENVPOST_ENTRY
|
||||
#endif
|
||||
#if (OPTION_GFX_ENV_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
|
||||
OPTION_GNB_FEATURE GfxEnvInterfaceTN;
|
||||
#define OPTION_GFXENVINTERFACETN_ENTRY {AMD_FAMILY_TN, GfxEnvInterfaceTN},
|
||||
#else
|
||||
#define OPTION_GFXENVINTERFACETN_ENTRY
|
||||
#endif
|
||||
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
#ifndef OPTION_POWER_GATE
|
||||
#define OPTION_POWER_GATE TRUE
|
||||
#endif
|
||||
#if (OPTION_POWER_GATE == TRUE) && (GNB_TYPE_LN == TRUE)
|
||||
OPTION_GNB_FEATURE F12NbPowerGateFeature;
|
||||
#define OPTION_F12NBPOWERGATEFEATURE_ENTRY {AMD_FAMILY_LN, F12NbPowerGateFeature},
|
||||
#else
|
||||
#define OPTION_F12NBPOWERGATEFEATURE_ENTRY
|
||||
#endif
|
||||
#if (OPTION_POWER_GATE == TRUE) && (GNB_TYPE_ON == TRUE)
|
||||
OPTION_GNB_FEATURE F14NbPowerGateFeature;
|
||||
#define OPTION_F14NBPOWERGATEFEATURE_ENTRY {AMD_FAMILY_ON, F14NbPowerGateFeature},
|
||||
#else
|
||||
#define OPTION_F14NBPOWERGATEFEATURE_ENTRY
|
||||
#endif
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
#ifndef OPTION_PCIE_ENV_INIT
|
||||
#define OPTION_PCIE_ENV_INIT TRUE
|
||||
#endif
|
||||
#if (OPTION_PCIE_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
|
||||
OPTION_GNB_FEATURE PcieInitAtEnv;
|
||||
#define OPTION_PCIEINITATENV_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , PcieInitAtEnv},
|
||||
#else
|
||||
#define OPTION_PCIEINITATENV_ENTRY
|
||||
#endif
|
||||
#if (OPTION_PCIE_ENV_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
|
||||
OPTION_GNB_FEATURE PcieEnvInterfaceTN;
|
||||
#define OPTION_PCIEENVINTERFACETN_ENTRY {AMD_FAMILY_TN, PcieEnvInterfaceTN},
|
||||
#else
|
||||
#define OPTION_PCIEENVINTERFACETN_ENTRY
|
||||
#endif
|
||||
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
|
||||
OPTION_GNB_CONFIGURATION GnbEnvFeatureTable[] = {
|
||||
OPTION_NBFUSETABLEFEATURE_ENTRY
|
||||
OPTION_NBINITATENVT_ENTRY
|
||||
OPTION_GNBENVINTERFACETN_ENTRY
|
||||
OPTION_PCIEINITATENV_ENTRY
|
||||
OPTION_PCIEENVINTERFACETN_ENTRY
|
||||
OPTION_GFXCONFIGENVINTERFACE_ENTRY
|
||||
OPTION_GFXINITATENVPOST_ENTRY
|
||||
OPTION_GFXENVINTERFACETN_ENTRY
|
||||
OPTION_F12NBPOWERGATEFEATURE_ENTRY
|
||||
OPTION_F14NBPOWERGATEFEATURE_ENTRY
|
||||
{0, NULL}
|
||||
};
|
||||
#endif
|
||||
|
||||
#if (AGESA_ENTRY_INIT_MID == TRUE)
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
#ifndef OPTION_GNB_CABLESAFE
|
||||
#define OPTION_GNB_CABLESAFE TRUE
|
||||
#endif
|
||||
#if (OPTION_GNB_CABLESAFE == TRUE) && (GNB_TYPE_LN == TRUE)
|
||||
OPTION_GNB_FEATURE GnbCableSafeEntry;
|
||||
#define OPTION_GNBCABLESAFEENTRY_ENTRY {AMD_FAMILY_LN, GnbCableSafeEntry},
|
||||
#else
|
||||
#define OPTION_GNBCABLESAFEENTRY_ENTRY
|
||||
#endif
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
#ifndef OPTION_NB_LCLK_NCLK_RATIO
|
||||
#define OPTION_NB_LCLK_NCLK_RATIO TRUE
|
||||
#endif
|
||||
#if (OPTION_NB_LCLK_NCLK_RATIO == TRUE) && (GNB_TYPE_ON == TRUE)
|
||||
OPTION_GNB_FEATURE F14NbLclkNclkRatioFeature;
|
||||
#define OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY {AMD_FAMILY_ON, F14NbLclkNclkRatioFeature},
|
||||
#else
|
||||
#define OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY
|
||||
#endif
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
#ifndef OPTION_NB_LCLK_DPM_INIT
|
||||
#define OPTION_NB_LCLK_DPM_INIT TRUE
|
||||
#endif
|
||||
#if (OPTION_NB_LCLK_DPM_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
|
||||
OPTION_GNB_FEATURE NbLclkDpmFeature;
|
||||
#define OPTION_NBLCLKDPMFEATURE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , NbLclkDpmFeature},
|
||||
#else
|
||||
#define OPTION_NBLCLKDPMFEATURE_ENTRY
|
||||
#endif
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
#ifndef OPTION_PCIE_POWER_GATE
|
||||
#define OPTION_PCIE_POWER_GATE TRUE
|
||||
#endif
|
||||
#if (OPTION_PCIE_POWER_GATE == TRUE) && (GNB_TYPE_LN == TRUE)
|
||||
OPTION_GNB_FEATURE PciePowerGateFeature;
|
||||
#define OPTION_PCIEPOWERGATEFEATURE_ENTRY {AMD_FAMILY_LN, PciePowerGateFeature},
|
||||
#else
|
||||
#define OPTION_PCIEPOWERGATEFEATURE_ENTRY
|
||||
#endif
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
#ifndef OPTION_GFX_MID_INIT
|
||||
#define OPTION_GFX_MID_INIT TRUE
|
||||
#endif
|
||||
#if (OPTION_GFX_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
|
||||
OPTION_GNB_FEATURE GfxInitAtMidPost;
|
||||
#define OPTION_GFXINITATMIDPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , GfxInitAtMidPost},
|
||||
#else
|
||||
#define OPTION_GFXINITATMIDPOST_ENTRY
|
||||
#endif
|
||||
#if (OPTION_GFX_MID_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
|
||||
OPTION_GNB_FEATURE GfxMidInterfaceTN;
|
||||
#define OPTION_GFXMIDINTERFACETN_ENTRY {AMD_FAMILY_TN, GfxMidInterfaceTN},
|
||||
#else
|
||||
#define OPTION_GFXMIDINTERFACETN_ENTRY
|
||||
#endif
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
#ifndef OPTION_GFX_INTEGRATED_TABLE_INIT
|
||||
#define OPTION_GFX_INTEGRATED_TABLE_INIT TRUE
|
||||
#endif
|
||||
#if (OPTION_GFX_INTEGRATED_TABLE_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
|
||||
OPTION_GNB_FEATURE GfxIntegratedInfoTableEntry;
|
||||
#define OPTION_GFXINTEGRATEDINFOTABLE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , GfxIntegratedInfoTableEntry},
|
||||
#else
|
||||
#define OPTION_GFXINTEGRATEDINFOTABLE_ENTRY
|
||||
#endif
|
||||
#if (OPTION_GFX_INTEGRATED_TABLE_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
|
||||
OPTION_GNB_FEATURE GfxIntInfoTableInterfaceTN;
|
||||
#define OPTION_GFXINTINFOTABLEINTERFACETN_ENTRY {AMD_FAMILY_TN, GfxIntInfoTableInterfaceTN},
|
||||
#else
|
||||
#define OPTION_GFXINTINFOTABLEINTERFACETN_ENTRY
|
||||
#endif
|
||||
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
#ifndef OPTION_PCIe_MID_INIT
|
||||
#define OPTION_PCIe_MID_INIT TRUE
|
||||
#endif
|
||||
#if (OPTION_PCIe_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
|
||||
OPTION_GNB_FEATURE PcieInitAtMid;
|
||||
#define OPTION_PCIEINITATMID_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , PcieInitAtMid},
|
||||
#else
|
||||
#define OPTION_PCIEINITATMID_ENTRY
|
||||
#endif
|
||||
#if (OPTION_PCIe_MID_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
|
||||
OPTION_GNB_FEATURE PcieMidInterfaceTN;
|
||||
#define OPTION_PCIEMIDINTERFACETN_ENTRY {AMD_FAMILY_TN, PcieMidInterfaceTN},
|
||||
#else
|
||||
#define OPTION_PCIEMIDINTERFACETN_ENTRY
|
||||
#endif
|
||||
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
#ifndef OPTION_NB_MID_INIT
|
||||
#define OPTION_NB_MID_INIT TRUE
|
||||
#endif
|
||||
#if (OPTION_NB_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
|
||||
OPTION_GNB_FEATURE NbInitAtLatePost;
|
||||
#define OPTION_NBINITATLATEPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , NbInitAtLatePost},
|
||||
#else
|
||||
#define OPTION_NBINITATLATEPOST_ENTRY
|
||||
#endif
|
||||
#if (OPTION_NB_MID_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
|
||||
OPTION_GNB_FEATURE GnbMidInterfaceTN;
|
||||
#define OPTION_GNBMIDINTERFACETN_ENTRY {AMD_FAMILY_TN, GnbMidInterfaceTN},
|
||||
#else
|
||||
#define OPTION_GNBMIDINTERFACETN_ENTRY
|
||||
#endif
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
#ifndef OPTION_GFX_CONFIG_POST_INIT
|
||||
#define OPTION_GFX_CONFIG_POST_INIT TRUE
|
||||
#endif
|
||||
#if (OPTION_GFX_CONFIG_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_TN == TRUE || GNB_TYPE_ON == TRUE)
|
||||
OPTION_GNB_FEATURE GfxConfigMidInterface;
|
||||
#define OPTION_GFXCONFIGMIDINTERFACE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_TN | GNB_TYPE_ON, GfxConfigMidInterface},
|
||||
#else
|
||||
#define OPTION_GFXCONFIGMIDINTERFACE_ENTRY
|
||||
#endif
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
#ifndef OPTION_PCIE_CLK_PM_INTERFACE
|
||||
#define OPTION_PCIE_CLK_PM_INTERFACE FALSE
|
||||
#if (GNB_TYPE_ON == TRUE )
|
||||
#undef OPTION_PCIE_CLK_PM_INTERFACE
|
||||
#define OPTION_PCIE_CLK_PM_INTERFACE TRUE
|
||||
#endif
|
||||
#if (GNB_TYPE_TN == TRUE && (OPTION_FS1_SOCKET_SUPPORT == TRUE || OPTION_FP1_SOCKET_SUPPORT == TRUE))
|
||||
#undef OPTION_PCIE_CLK_PM_INTERFACE
|
||||
#define OPTION_PCIE_CLK_PM_INTERFACE TRUE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (OPTION_PCIE_CLK_PM_INTERFACE == TRUE) && (GNB_TYPE_TN == TRUE || GNB_TYPE_ON == TRUE )
|
||||
OPTION_GNB_FEATURE PcieClkPmInterface;
|
||||
#define OPTION_PCIECLKPMINTERFACE_ENTRY {AMD_FAMILY_TN | AMD_FAMILY_ON, PcieClkPmInterface},
|
||||
#else
|
||||
#define OPTION_PCIECLKPMINTERFACE_ENTRY
|
||||
#endif
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
#ifndef OPTION_PCIE_ASPM_INTERFACE
|
||||
#define OPTION_PCIE_ASPM_INTERFACE TRUE
|
||||
#endif
|
||||
#if (OPTION_PCIE_ASPM_INTERFACE == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE || GNB_TYPE_TN == TRUE )
|
||||
OPTION_GNB_FEATURE PcieAspmInterface;
|
||||
#define OPTION_PCIEASPMINTERFACE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON | AMD_FAMILY_TN , PcieAspmInterface},
|
||||
#else
|
||||
#define OPTION_PCIEASPMINTERFACE_ENTRY
|
||||
#endif
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
#ifndef OPTION_GNB_IOAPIC_INTERFACE
|
||||
#define OPTION_GNB_IOAPIC_INTERFACE TRUE
|
||||
#endif
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
OPTION_GNB_CONFIGURATION GnbMidFeatureTable[] = {
|
||||
OPTION_GFXCONFIGMIDINTERFACE_ENTRY
|
||||
OPTION_GFXINITATMIDPOST_ENTRY
|
||||
OPTION_GFXMIDINTERFACETN_ENTRY
|
||||
OPTION_GFXINTEGRATEDINFOTABLE_ENTRY
|
||||
OPTION_GFXINTINFOTABLEINTERFACETN_ENTRY
|
||||
OPTION_GNBCABLESAFEENTRY_ENTRY
|
||||
OPTION_PCIEINITATMID_ENTRY
|
||||
OPTION_PCIEMIDINTERFACETN_ENTRY
|
||||
OPTION_NBINITATLATEPOST_ENTRY
|
||||
OPTION_GNBMIDINTERFACETN_ENTRY
|
||||
OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY
|
||||
OPTION_NBLCLKDPMFEATURE_ENTRY
|
||||
OPTION_PCIEPOWERGATEFEATURE_ENTRY
|
||||
OPTION_PCIECLKPMINTERFACE_ENTRY
|
||||
OPTION_PCIEASPMINTERFACE_ENTRY
|
||||
{0, NULL}
|
||||
};
|
||||
#endif
|
||||
|
||||
#if (AGESA_ENTRY_INIT_LATE == TRUE)
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
#ifndef OPTION_ALIB
|
||||
#define OPTION_ALIB FALSE
|
||||
#endif
|
||||
#if (OPTION_ALIB == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE || GNB_TYPE_TN == TRUE)
|
||||
extern F_ALIB_UPDATE PcieAlibUpdatePcieMmioInfo;
|
||||
#if (GNB_TYPE_LN == TRUE)
|
||||
#if (OPTION_FM1_SOCKET_SUPPORT == TRUE)
|
||||
extern F_ALIB_GET PcieAlibGetBaseTableLNFM1;
|
||||
F_ALIB_GET *AlibGetBaseTable = PcieAlibGetBaseTableLNFM1;
|
||||
#define ALIB_CALL_TABLE PcieAlibUpdatePcieMmioInfo
|
||||
#else
|
||||
extern F_ALIB_GET PcieAlibGetBaseTableLNFS1;
|
||||
F_ALIB_GET *AlibGetBaseTable = PcieAlibGetBaseTableLNFS1;
|
||||
extern F_ALIB_UPDATE PcieAlibUpdateVoltageInfo;
|
||||
extern F_ALIB_UPDATE PcieAlibUpdatePcieInfo;
|
||||
extern F_ALIB_UPDATE PcieAlibBuildAcpiTableLNFS1;
|
||||
#define ALIB_CALL_TABLE PcieAlibUpdatePcieMmioInfo, \
|
||||
PcieAlibUpdateVoltageInfo, \
|
||||
PcieAlibUpdatePcieInfo, \
|
||||
PcieAlibBuildAcpiTableLNFS1
|
||||
#endif
|
||||
#elif (GNB_TYPE_TN == TRUE)
|
||||
#if (OPTION_FM2_SOCKET_SUPPORT == TRUE)
|
||||
extern F_ALIB_GET PcieAlibGetBaseTableTNFM2;
|
||||
F_ALIB_GET *AlibGetBaseTable = PcieAlibGetBaseTableTNFM2;
|
||||
#define ALIB_CALL_TABLE PcieAlibUpdatePcieMmioInfo
|
||||
#else
|
||||
extern F_ALIB_GET PcieAlibGetBaseTableTNFS1;
|
||||
F_ALIB_GET *AlibGetBaseTable = PcieAlibGetBaseTableTNFS1;
|
||||
extern F_ALIB_UPDATE PcieAlibUpdateVoltageInfo;
|
||||
extern F_ALIB_UPDATE PcieAlibUpdatePcieInfo;
|
||||
extern F_ALIB_UPDATE PcieAlibBuildAcpiTableLNFS2;
|
||||
#define ALIB_CALL_TABLE PcieAlibUpdatePcieMmioInfo, \
|
||||
PcieAlibUpdateVoltageInfo, \
|
||||
PcieAlibUpdatePcieInfo
|
||||
|
||||
#endif
|
||||
#else
|
||||
extern F_ALIB_GET PcieAlibGetBaseTable;
|
||||
F_ALIB_GET *AlibGetBaseTable = PcieAlibGetBaseTable;
|
||||
extern F_ALIB_UPDATE PcieAlibUpdateVoltageInfo;
|
||||
extern F_ALIB_UPDATE PcieAlibUpdatePcieInfo;
|
||||
extern F_ALIB_UPDATE PcieFmAlibBuildAcpiTable;
|
||||
#define ALIB_CALL_TABLE PcieAlibUpdatePcieMmioInfo, \
|
||||
PcieAlibUpdateVoltageInfo, \
|
||||
PcieAlibUpdatePcieInfo, \
|
||||
PcieFmAlibBuildAcpiTable
|
||||
#endif
|
||||
F_ALIB_UPDATE* AlibDispatchTable [] = {
|
||||
ALIB_CALL_TABLE,
|
||||
NULL
|
||||
};
|
||||
OPTION_GNB_FEATURE PcieAlibFeature;
|
||||
#define OPTION_PCIEALIBFEATURE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON | AMD_FAMILY_TN, PcieAlibFeature},
|
||||
#else
|
||||
F_ALIB_GET *AlibGetBaseTable = NULL;
|
||||
F_ALIB_UPDATE* AlibDispatchTable [] = {
|
||||
NULL
|
||||
};
|
||||
#define OPTION_PCIEALIBFEATURE_ENTRY
|
||||
#endif
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
#ifndef OPTION_IOMMU_ACPI_IVRS
|
||||
#if (CFG_IOMMU_SUPPORT == TRUE)
|
||||
#define OPTION_IOMMU_ACPI_IVRS TRUE
|
||||
#else
|
||||
#define OPTION_IOMMU_ACPI_IVRS FALSE
|
||||
#endif
|
||||
#endif
|
||||
#if (OPTION_IOMMU_ACPI_IVRS == TRUE) && (GNB_TYPE_TN == TRUE )
|
||||
OPTION_GNB_FEATURE GnbIommuIvrsTable;
|
||||
#define OPTIONIOMMUACPIIVRSLATE_ENTRY {AMD_FAMILY_TN, GnbIommuIvrsTable},
|
||||
#else
|
||||
#define OPTIONIOMMUACPIIVRSLATE_ENTRY
|
||||
#endif
|
||||
#if (CFG_IOMMU_SUPPORT == TRUE) && (GNB_TYPE_TN == TRUE )
|
||||
OPTION_GNB_FEATURE GnbIommuScratchMemoryRangeInterface;
|
||||
#define OPTIONIOMMUSCRATCHMEMORYLATE_ENTRY {AMD_FAMILY_TN , GnbIommuScratchMemoryRangeInterface},
|
||||
#else
|
||||
#define OPTIONIOMMUSCRATCHMEMORYLATE_ENTRY
|
||||
#endif
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
OPTION_GNB_CONFIGURATION GnbLateFeatureTable[] = {
|
||||
OPTION_PCIEALIBFEATURE_ENTRY
|
||||
OPTIONIOMMUSCRATCHMEMORYLATE_ENTRY
|
||||
OPTIONIOMMUACPIIVRSLATE_ENTRY
|
||||
{0, NULL}
|
||||
};
|
||||
#endif
|
||||
|
||||
#if (AGESA_ENTRY_INIT_S3SAVE == TRUE)
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
#ifndef OPTION_GFX_INIT_SVIEW
|
||||
#define OPTION_GFX_INIT_SVIEW TRUE
|
||||
#endif
|
||||
#if (OPTION_GFX_INIT_SVIEW == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_TN == TRUE || GNB_TYPE_ON == TRUE)
|
||||
OPTION_GNB_FEATURE GfxInitSview;
|
||||
#define OPTION_GFXINITSVIEW_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_TN, GfxInitSview},
|
||||
#else
|
||||
#define OPTION_GFXINITSVIEW_ENTRY
|
||||
#endif
|
||||
|
||||
OPTION_GNB_CONFIGURATION GnbS3SaveFeatureTable[] = {
|
||||
OPTION_GFXINITSVIEW_ENTRY
|
||||
{0, NULL}
|
||||
};
|
||||
#endif
|
||||
#if (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
|
||||
S3_DISPATCH_FUNCTION NbSmuServiceRequestS3Script;
|
||||
S3_DISPATCH_FUNCTION PcieLateRestoreS3Script;
|
||||
S3_DISPATCH_FUNCTION NbSmuIndirectWriteS3Script;
|
||||
#define GNB_S3_DISPATCH_FUNCTION_TABLE \
|
||||
{NbSmuIndirectWriteS3Script_ID, NbSmuIndirectWriteS3Script}, \
|
||||
{NbSmuServiceRequestS3Script_ID, NbSmuServiceRequestS3Script}, \
|
||||
{PcieLateRestoreS3Script_ID, PcieLateRestoreS3Script},
|
||||
#endif
|
||||
|
||||
|
||||
#if (GNB_TYPE_TN == TRUE )
|
||||
S3_DISPATCH_FUNCTION GnbSmuServiceRequestV4S3Script;
|
||||
S3_DISPATCH_FUNCTION GnbLibStallS3Script;
|
||||
#define PCIELATERESTORETN
|
||||
#define GFXSCLKRESTORETN
|
||||
#if (GNB_TYPE_TN == TRUE)
|
||||
S3_DISPATCH_FUNCTION PcieLateRestoreInitTNS3Script;
|
||||
S3_DISPATCH_FUNCTION GfxRequestSclkTNS3Script;
|
||||
#undef PCIELATERESTORETN
|
||||
#define PCIELATERESTORETN {PcieLateRestoreTNS3Script_ID, PcieLateRestoreInitTNS3Script},
|
||||
#undef GFXSCLKRESTORETN
|
||||
#define GFXSCLKRESTORETN {GfxRequestSclkTNS3Script_ID, GfxRequestSclkTNS3Script },
|
||||
#endif
|
||||
#define GNB_S3_DISPATCH_FUNCTION_TABLE \
|
||||
{GnbSmuServiceRequestV4S3Script_ID, GnbSmuServiceRequestV4S3Script}, \
|
||||
PCIELATERESTORETN \
|
||||
GFXSCLKRESTORETN \
|
||||
{GnbLibStallS3Script_ID, GnbLibStallS3Script},
|
||||
/*these three line should be 1261-1263*/
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
#endif // _OPTION_GNB_INSTALL_H_
|
||||
365
src/vendorcode/amd/agesa/f15tn/Include/OptionHtInstall.h
Normal file
365
src/vendorcode/amd/agesa/f15tn/Include/OptionHtInstall.h
Normal file
@ -0,0 +1,365 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* Install of build option: Ht
|
||||
*
|
||||
* Contains AMD AGESA install macros and test conditions. Output is the
|
||||
* defaults tables reflecting the User's build options selection.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: Options
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef _OPTION_HT_INSTALL_H_
|
||||
#define _OPTION_HT_INSTALL_H_
|
||||
|
||||
#include "Topology.h"
|
||||
#include "htFeat.h"
|
||||
#include "htInterface.h"
|
||||
#include "htNb.h"
|
||||
#include "htTopologies.h"
|
||||
/*
|
||||
* Advanced Option only, hardware socket naming is the preferred method.
|
||||
*/
|
||||
#ifdef BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP
|
||||
#define CFG_SYSTEM_PHYSICAL_SOCKET_MAP (BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP)
|
||||
#else
|
||||
#define CFG_SYSTEM_PHYSICAL_SOCKET_MAP (NULL)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* OPTION_IS_RECOVERY_HT is true if Basic API is being used.
|
||||
*/
|
||||
#ifndef OPTION_IS_RECOVERY_HT
|
||||
#define OPTION_IS_RECOVERY_HT TRUE
|
||||
#endif
|
||||
|
||||
/* This option is designed to be included into the platform solution install
|
||||
* file. The platform solution install file will define the options status.
|
||||
* Check to validate the definition.
|
||||
*/
|
||||
|
||||
#ifndef OPTION_MULTISOCKET
|
||||
#error BLDOPT: Option not defined: "OPTION_MULTISOCKET"
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Based on user level options, set Ht internal options.
|
||||
* For now, Family 10h support will assume single module. For multi module,
|
||||
* this will have to be changed to not set non-coherent only.
|
||||
*/
|
||||
#define OPTION_HT_NON_COHERENT_ONLY FALSE
|
||||
|
||||
#if (OPTION_FAMILY15H_TN == TRUE)
|
||||
/* Families with only PCIe do not need a non-coherent only option. */
|
||||
#else
|
||||
// Process Family 10h and 15h Models 00h-0Fh by socket, applying the MultiSocket option where it is allowable.
|
||||
#if OPTION_G34_SOCKET_SUPPORT == FALSE
|
||||
// Hydra has coherent support, other Family 10h should follow MultiSocket support.
|
||||
#if OPTION_MULTISOCKET == FALSE
|
||||
#undef OPTION_HT_NON_COHERENT_ONLY
|
||||
#define OPTION_HT_NON_COHERENT_ONLY TRUE
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Macros will generate the correct item reference based on options
|
||||
*/
|
||||
#if AGESA_ENTRY_INIT_EARLY == TRUE
|
||||
// Select the interface and features
|
||||
#if ((OPTION_FAMILY15H_TN == TRUE))
|
||||
#define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL
|
||||
#define INTERNAL_HT_OPTION_FEATURES &HtFeaturesNone
|
||||
#define INTERNAL_HT_OPTION_INTERFACE &HtInterfaceMapsOnly
|
||||
#else
|
||||
#if (FALSE)
|
||||
#else
|
||||
// Family 10h and 15h Models 00h-0Fh
|
||||
#if OPTION_HT_NON_COHERENT_ONLY == FALSE
|
||||
#define INTERNAL_HT_OPTION_FEATURES &HtFeaturesDefault
|
||||
#define INTERNAL_HT_OPTION_INTERFACE &HtInterfaceDefault
|
||||
#else
|
||||
#define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL
|
||||
#define INTERNAL_HT_OPTION_FEATURES &HtFeaturesNonCoherentOnly
|
||||
#define INTERNAL_HT_OPTION_INTERFACE &HtInterfaceNonCoherentOnly
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
// Select Northbridge components
|
||||
#if OPTION_FAMILY10H == TRUE
|
||||
#if OPTION_HT_NON_COHERENT_ONLY == TRUE
|
||||
#define INTERNAL_HT_OPTION_FAM10_NB &HtFam10NbNonCoherentOnly, &HtFam10RevDNbNonCoherentOnly, &HtFam10RevENbNonCoherentOnly,
|
||||
#else
|
||||
#define INTERNAL_HT_OPTION_FAM10_NB &HtFam10NbDefault, &HtFam10RevDNbDefault, &HtFam10RevENbDefault,
|
||||
#endif
|
||||
#else
|
||||
#define INTERNAL_HT_OPTION_FAM10_NB
|
||||
#endif
|
||||
|
||||
#if OPTION_FAMILY12H == TRUE
|
||||
#define INTERNAL_HT_OPTION_FAM12_NB &HtFam12Nb,
|
||||
#else
|
||||
#define INTERNAL_HT_OPTION_FAM12_NB
|
||||
#endif
|
||||
|
||||
#if OPTION_FAMILY14H == TRUE
|
||||
#define INTERNAL_HT_OPTION_FAM14_NB &HtFam14Nb,
|
||||
#else
|
||||
#define INTERNAL_HT_OPTION_FAM14_NB
|
||||
#endif
|
||||
|
||||
#if OPTION_FAMILY15H == TRUE
|
||||
#if OPTION_FAMILY15H_OR == TRUE
|
||||
#if OPTION_HT_NON_COHERENT_ONLY == TRUE
|
||||
#define INTERNAL_HT_OPTION_FAM15_NB &HtFam15NbNonCoherentOnly,
|
||||
#else
|
||||
#define INTERNAL_HT_OPTION_FAM15_NB &HtFam15NbDefault,
|
||||
#endif
|
||||
#else
|
||||
#define INTERNAL_HT_OPTION_FAM15_NB
|
||||
#endif
|
||||
#if OPTION_FAMILY15H_TN == TRUE
|
||||
#define INTERNAL_HT_OPTION_FAM15TN_NB &HtFam15Mod1xNb,
|
||||
#else
|
||||
#define INTERNAL_HT_OPTION_FAM15TN_NB
|
||||
#endif
|
||||
// #if OPTION_FAMILY15H_KM == TRUE
|
||||
// #define INTERNAL_HT_OPTION_FAM15KM_NB &HtFam15Mod2xNbDefault,
|
||||
// #else
|
||||
// #define INTERNAL_HT_OPTION_FAM15KM_NB
|
||||
// #endif
|
||||
// #if OPTION_FAMILY15H_KV == TRUE
|
||||
// #define INTERNAL_HT_OPTION_FAM15KV_NB &HtFam15Mod1xNb,
|
||||
// #else
|
||||
// #define INTERNAL_HT_OPTION_FAM15KV_NB
|
||||
// #endif
|
||||
#else
|
||||
#define INTERNAL_HT_OPTION_FAM15_NB
|
||||
#define INTERNAL_HT_OPTION_FAM15TN_NB
|
||||
//#define INTERNAL_HT_OPTION_FAM15KM_NB
|
||||
//#define INTERNAL_HT_OPTION_FAM15KV_NB
|
||||
#endif
|
||||
|
||||
#define INTERNAL_ONLY_NB_LIST_ITEM INTERNAL_ONLY_HT_OPTION_SUPPORTED_NBS,
|
||||
#ifndef INTERNAL_ONLY_HT_OPTION_SUPPORTED_NBS
|
||||
#undef INTERNAL_ONLY_NB_LIST_ITEM
|
||||
#define INTERNAL_ONLY_NB_LIST_ITEM
|
||||
#endif
|
||||
|
||||
/* Install the correct set of northbridge implementations. Each item provides its own comma, the last item
|
||||
* is ok to have a comma because the final item (NULL) is added below.
|
||||
*/
|
||||
#define INTERNAL_HT_OPTION_SUPPORTED_NBS \
|
||||
INTERNAL_ONLY_NB_LIST_ITEM \
|
||||
INTERNAL_HT_OPTION_FAM10_NB \
|
||||
INTERNAL_HT_OPTION_FAM15_NB \
|
||||
INTERNAL_HT_OPTION_FAM12_NB \
|
||||
INTERNAL_HT_OPTION_FAM14_NB \
|
||||
INTERNAL_HT_OPTION_FAM15TN_NB
|
||||
|
||||
#else
|
||||
// Not Init Early
|
||||
#define INTERNAL_HT_OPTION_FEATURES NULL
|
||||
#define INTERNAL_HT_OPTION_INTERFACE NULL
|
||||
#define INTERNAL_HT_OPTION_SUPPORTED_NBS NULL
|
||||
#define HT_OPTIONS_PLATFORM NULL
|
||||
#define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL
|
||||
#endif
|
||||
|
||||
#ifdef AGESA_ENTRY_INIT_EARLY
|
||||
#if AGESA_ENTRY_INIT_EARLY == TRUE
|
||||
|
||||
extern HT_FEATURES HtFeaturesDefault;
|
||||
extern HT_FEATURES HtFeaturesNonCoherentOnly;
|
||||
extern HT_FEATURES HtFeaturesCoherentOnly;
|
||||
extern HT_FEATURES HtFeaturesNone;
|
||||
extern HT_INTERFACE HtInterfaceDefault;
|
||||
extern HT_INTERFACE HtInterfaceNonCoherentOnly;
|
||||
extern HT_INTERFACE HtInterfaceCoherentOnly;
|
||||
extern HT_INTERFACE HtInterfaceMapsOnly;
|
||||
extern HT_INTERFACE HtInterfaceNone;
|
||||
extern NORTHBRIDGE HtFam10NbDefault;
|
||||
extern NORTHBRIDGE HtFam10RevDNbDefault;
|
||||
extern NORTHBRIDGE HtFam10NbNonCoherentOnly;
|
||||
extern NORTHBRIDGE HtFam10RevDNbNonCoherentOnly;
|
||||
extern NORTHBRIDGE HtFam10RevENbDefault;
|
||||
extern NORTHBRIDGE HtFam10RevENbNonCoherentOnly;
|
||||
extern NORTHBRIDGE HtFam12Nb;
|
||||
extern NORTHBRIDGE HtFam14Nb;
|
||||
extern NORTHBRIDGE HtFam10NbNone;
|
||||
extern NORTHBRIDGE HtFam15NbDefault;
|
||||
extern NORTHBRIDGE HtFam15NbNonCoherentOnly;
|
||||
extern NORTHBRIDGE HtFam15Mod1xNb;
|
||||
|
||||
CONST VOID * CONST ROMDATA HtInstalledFamilyNorthbridgeList[] = {
|
||||
INTERNAL_HT_OPTION_SUPPORTED_NBS
|
||||
NULL
|
||||
};
|
||||
|
||||
STATIC CONST AMD_HT_INTERFACE ROMDATA HtOptionsPlatform =
|
||||
{
|
||||
CFG_STARTING_BUSNUM, CFG_MAXIMUM_BUSNUM, CFG_ALLOCATED_BUSNUM,
|
||||
(MANUAL_BUID_SWAP_LIST *)CFG_BUID_SWAP_LIST,
|
||||
(DEVICE_CAP_OVERRIDE *)CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST,
|
||||
(CPU_TO_CPU_PCB_LIMITS *)CFG_HTFABRIC_LIMITS_LIST,
|
||||
(IO_PCB_LIMITS *)CFG_HTCHAIN_LIMITS_LIST,
|
||||
(OVERRIDE_BUS_NUMBERS *)CFG_BUS_NUMBERS_LIST,
|
||||
(IGNORE_LINK *)CFG_IGNORE_LINK_LIST,
|
||||
(SKIP_REGANG *)CFG_LINK_SKIP_REGANG_LIST,
|
||||
(UINT8 **)CFG_ADDITIONAL_TOPOLOGIES_LIST,
|
||||
(SYSTEM_PHYSICAL_SOCKET_MAP *)CFG_SYSTEM_PHYSICAL_SOCKET_MAP
|
||||
};
|
||||
#ifndef HT_OPTIONS_PLATFORM
|
||||
#define HT_OPTIONS_PLATFORM &HtOptionsPlatform
|
||||
#endif
|
||||
|
||||
/**
|
||||
* A list of all the supported topologies.
|
||||
*
|
||||
*/
|
||||
#ifndef INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES
|
||||
CONST UINT8 *CONST ROMDATA AmdTopolist[] =
|
||||
{
|
||||
amdHtTopologySingleNode,
|
||||
amdHtTopologyDualNode,
|
||||
amdHtTopologyThreeLine,
|
||||
amdHtTopologyTriangle,
|
||||
amdHtTopologyFourLine,
|
||||
amdHtTopologyFourStar,
|
||||
amdHtTopologyFourDegenerate,
|
||||
amdHtTopologyFourSquare,
|
||||
amdHtTopologyFourKite,
|
||||
amdHtTopologyFourFully,
|
||||
amdHtTopologyFiveFully,
|
||||
amdHtTopologyFiveTwistedLadder,
|
||||
amdHtTopologySixFully,
|
||||
amdHtTopologySixDoubloonLower,
|
||||
amdHtTopologySixDoubloonUpper,
|
||||
amdHtTopologySixTwistedLadder,
|
||||
amdHtTopologySevenFully,
|
||||
amdHtTopologySevenTwistedLadder,
|
||||
amdHtTopologyEightFully,
|
||||
amdHtTopologyEightDoubloon,
|
||||
amdHtTopologyEightTwistedLadder,
|
||||
amdHtTopologyEightStraightLadder,
|
||||
amdHtTopologySixTwinTriangles,
|
||||
amdHtTopologyEightTwinFullyFourWays,
|
||||
NULL
|
||||
};
|
||||
#define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES AmdTopolist
|
||||
#endif
|
||||
|
||||
/**
|
||||
* Declare the instance of the Ht option configuration structure
|
||||
*/
|
||||
CONST OPTION_HT_CONFIGURATION ROMDATA OptionHtConfiguration = {
|
||||
OPTION_IS_RECOVERY_HT,
|
||||
CFG_SET_HTCRC_SYNC_FLOOD,
|
||||
CFG_USE_UNIT_ID_CLUMPING,
|
||||
HT_OPTIONS_PLATFORM,
|
||||
INTERNAL_HT_OPTION_INTERFACE,
|
||||
INTERNAL_HT_OPTION_FEATURES,
|
||||
&HtInstalledFamilyNorthbridgeList,
|
||||
INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES
|
||||
};
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef OPTION_HT_INIIT_RESET_ENTRY
|
||||
|
||||
#define OPTION_HT_INIIT_RESET_ENTRY AmdHtInitReset
|
||||
#define OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY AmdHtResetConstructor
|
||||
|
||||
#if ((OPTION_FAMILY15H_TN == TRUE) )
|
||||
#undef OPTION_HT_INIIT_RESET_ENTRY
|
||||
#undef OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY
|
||||
#define OPTION_HT_INIIT_RESET_ENTRY NULL
|
||||
#define OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY NULL
|
||||
#endif
|
||||
|
||||
#if ((OPTION_FAMILY10H == TRUE) || (OPTION_FAMILY15H_OR == TRUE))
|
||||
#undef OPTION_HT_INIIT_RESET_ENTRY
|
||||
#undef OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY
|
||||
#define OPTION_HT_INIIT_RESET_ENTRY AmdHtInitReset
|
||||
#define OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY AmdHtResetConstructor
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef AGESA_ENTRY_INIT_RESET
|
||||
#if AGESA_ENTRY_INIT_RESET == TRUE
|
||||
|
||||
CONST AMD_HT_RESET_INTERFACE ROMDATA HtOptionResetDefaults = {
|
||||
(MANUAL_BUID_SWAP_LIST *)CFG_BUID_SWAP_LIST,
|
||||
0 // Unused by options
|
||||
};
|
||||
|
||||
CONST OPTION_HT_INIT_RESET ROMDATA HtOptionInitReset = {
|
||||
OPTION_HT_INIIT_RESET_ENTRY,
|
||||
OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY
|
||||
};
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#endif // _OPTION_HT_INSTALL_H_
|
||||
113
src/vendorcode/amd/agesa/f15tn/Include/OptionHtcInstall.h
Normal file
113
src/vendorcode/amd/agesa/f15tn/Include/OptionHtcInstall.h
Normal file
@ -0,0 +1,113 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* Install of build option: Hardware Thermal Control (HTC).
|
||||
*
|
||||
* Contains AMD AGESA install macros and test conditions. Output is the
|
||||
* defaults tables reflecting the User's build options selection.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: Options
|
||||
* @e \$Revision: 63692 $ @e \$Date: 2012-01-03 22:13:28 -0600 (Tue, 03 Jan 2012) $
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef _OPTION_HTC_INSTALL_H_
|
||||
#define _OPTION_HTC_INSTALL_H_
|
||||
|
||||
#include "cpuHtc.h"
|
||||
|
||||
/* This option is designed to be included into the platform solution install
|
||||
* file. The platform solution install file will define the options status.
|
||||
* Check to validate the definition
|
||||
*/
|
||||
#define OPTION_CPU_HTC_FEAT
|
||||
#define F15_TN_HTC_SUPPORT
|
||||
|
||||
#if OPTION_CPU_HTC == TRUE
|
||||
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
|
||||
// Family 15h
|
||||
#ifdef OPTION_FAMILY15H
|
||||
#if OPTION_FAMILY15H == TRUE
|
||||
#if OPTION_FAMILY15H_TN == TRUE
|
||||
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureHtc;
|
||||
#undef OPTION_CPU_HTC_FEAT
|
||||
#define OPTION_CPU_HTC_FEAT &CpuFeatureHtc,
|
||||
extern CONST HTC_FAMILY_SERVICES ROMDATA F15TnHtcSupport;
|
||||
#undef F15_TN_HTC_SUPPORT
|
||||
#define F15_TN_HTC_SUPPORT {AMD_FAMILY_15_TN, &F15TnHtcSupport},
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA HtcFamilyServiceArray[] =
|
||||
{
|
||||
F15_TN_HTC_SUPPORT
|
||||
{0, NULL}
|
||||
};
|
||||
|
||||
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA HtcFamilyServiceTable =
|
||||
{
|
||||
(sizeof (HtcFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
|
||||
&HtcFamilyServiceArray[0]
|
||||
};
|
||||
|
||||
#endif // _OPTION_HTC_INSTALL_H_
|
||||
107
src/vendorcode/amd/agesa/f15tn/Include/OptionHwC1eInstall.h
Normal file
107
src/vendorcode/amd/agesa/f15tn/Include/OptionHwC1eInstall.h
Normal file
@ -0,0 +1,107 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* Install of build option: HW C1e
|
||||
*
|
||||
* Contains AMD AGESA install macros and test conditions. Output is the
|
||||
* defaults tables reflecting the User's build options selection.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: Options
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef _OPTION_HW_C1E_INSTALL_H_
|
||||
#define _OPTION_HW_C1E_INSTALL_H_
|
||||
|
||||
#include "cpuHwC1e.h"
|
||||
|
||||
/* This option is designed to be included into the platform solution install
|
||||
* file. The platform solution install file will define the options status.
|
||||
* Check to validate the definition
|
||||
*/
|
||||
#define OPTION_HW_C1E_FEAT
|
||||
#define F10_HW_C1E_SUPPORT
|
||||
#if AGESA_ENTRY_INIT_EARLY == TRUE
|
||||
#ifdef OPTION_FAMILY10H
|
||||
#if OPTION_FAMILY10H == TRUE
|
||||
#if (OPTION_FAMILY10H_BL == TRUE) || (OPTION_FAMILY10H_DA == TRUE) || (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_PH == TRUE)
|
||||
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureHwC1e;
|
||||
#undef OPTION_HW_C1E_FEAT
|
||||
#define OPTION_HW_C1E_FEAT &CpuFeatureHwC1e,
|
||||
extern CONST HW_C1E_FAMILY_SERVICES ROMDATA F10HwC1e;
|
||||
#undef F10_HW_C1E_SUPPORT
|
||||
#define F10_HW_C1E_SUPPORT {(AMD_FAMILY_10_BL | AMD_FAMILY_10_DA | AMD_FAMILY_10_RB | AMD_FAMILY_10_PH), &F10HwC1e},
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA HwC1eFamilyServiceArray[] =
|
||||
{
|
||||
F10_HW_C1E_SUPPORT
|
||||
{0, NULL}
|
||||
};
|
||||
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA HwC1eFamilyServiceTable =
|
||||
{
|
||||
(sizeof (HwC1eFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
|
||||
&HwC1eFamilyServiceArray[0]
|
||||
};
|
||||
#endif
|
||||
|
||||
#endif // _OPTION_HW_C1E_INSTALL_H_
|
||||
666
src/vendorcode/amd/agesa/f15tn/Include/OptionIdsInstall.h
Normal file
666
src/vendorcode/amd/agesa/f15tn/Include/OptionIdsInstall.h
Normal file
@ -0,0 +1,666 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* IDS Option Install File
|
||||
*
|
||||
* This file generates the defaults tables for family 10h model 5 processors.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: Core
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
*
|
||||
***************************************************************************/
|
||||
#ifndef _OPTION_IDS_INSTALL_H_
|
||||
#define _OPTION_IDS_INSTALL_H_
|
||||
#include "Ids.h"
|
||||
#include "IdsHt.h"
|
||||
#include "IdsLib.h"
|
||||
#include "IdsDebugPrint.h"
|
||||
#ifdef __IDS_EXTENDED__
|
||||
#include OPTION_IDS_EXT_INSTALL_FILE
|
||||
#endif
|
||||
|
||||
#define IDS_LATE_RUN_AP_TASK
|
||||
|
||||
#define M_HTIDS_PORT_OVERRIDE_HOOK (PF_HtIdsGetPortOverride)CommonVoid
|
||||
#if (IDSOPT_IDS_ENABLED == TRUE)
|
||||
#if (IDSOPT_CONTROL_ENABLED == TRUE)
|
||||
// Check for all families which include HT Features.
|
||||
#if ((OPTION_FAMILY10H == TRUE) || (OPTION_FAMILY15H_OR == TRUE) || ) && (AGESA_ENTRY_INIT_POST == TRUE)
|
||||
#undef M_HTIDS_PORT_OVERRIDE_HOOK
|
||||
#define M_HTIDS_PORT_OVERRIDE_HOOK HtIdsGetPortOverride
|
||||
#endif
|
||||
#endif
|
||||
#endif // OPTION_IDS_LEVEL
|
||||
CONST PF_HtIdsGetPortOverride ROMDATA pf_HtIdsGetPortOverride = M_HTIDS_PORT_OVERRIDE_HOOK;
|
||||
|
||||
#if (IDSOPT_IDS_ENABLED == TRUE)
|
||||
#if (AGESA_ENTRY_INIT_LATE == TRUE)
|
||||
#undef IDS_LATE_RUN_AP_TASK
|
||||
#define IDS_LATE_RUN_AP_TASK {IDS_LATE_RUN_AP_TASK_ID, (IMAGE_ENTRY)AmdIdsRunApTaskLate},
|
||||
#endif
|
||||
#endif // OPTION_IDS_LEVEL
|
||||
|
||||
#if (IDSOPT_TRACING_ENABLED == TRUE)
|
||||
#if (AGESA_ENTRY_INIT_POST == TRUE)
|
||||
#include <mu.h>
|
||||
CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
|
||||
{ (UINT32) /*(UINT64)*/ MemUWriteCachelines, "WriteCl(PhyAddrLo,BufferAddr,ClCnt)"},
|
||||
{ (UINT32) /*(UINT64)*/ MemUReadCachelines, "ReadCl(BufferAddr,PhyAddrLo,ClCnt)"},
|
||||
{ (UINT32) /*(UINT64)*/ MemUFlushPattern, "FlushCl(PhyAddrLo,ClCnt)"}
|
||||
};
|
||||
#elif (AGESA_ENTRY_INIT_RECOVERY == TRUE)
|
||||
#include <mru.h>
|
||||
CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
|
||||
{ (UINT32) (UINT64) MemRecUWrite1CL, "Write1Cl(PhyAddrLo,BufferAddr)"},
|
||||
{ (UINT32) (UINT64) MemRecURead1CL, "Read1Cl(BufferAddr,PhyAddrLo)"},
|
||||
{ (UINT32) (UINT64) MemRecUFlushPattern, "Flush1Cl(PhyAddrLo)"}
|
||||
};
|
||||
#else
|
||||
CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
|
||||
{ (UINT32) (UINT64) CommonReturnFalse, "DefRet()"},
|
||||
{ (UINT32) (UINT64) CommonReturnFalse, "DefRet()"},
|
||||
{ (UINT32) (UINT64) CommonReturnFalse, "DefRet()"}
|
||||
};
|
||||
#endif
|
||||
#else
|
||||
CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
|
||||
{ (UINT32) /*(UINT64)*/ CommonReturnFalse, "DefRet()"},
|
||||
{ (UINT32) /*(UINT64)*/ CommonReturnFalse, "DefRet()"},
|
||||
{ (UINT32) /*(UINT64)*/ CommonReturnFalse, "DefRet()"}
|
||||
};
|
||||
#endif
|
||||
|
||||
|
||||
#define NV_TO_CMOS(Len, NV_ID) {Len, NV_ID},
|
||||
#define OPTION_IDS_NV_TO_CMOS_END NV_TO_CMOS (IDS_NV_TO_CMOS_LEN_END, IDS_NV_TO_CMOS_ID_END)
|
||||
#if (IDSOPT_IDS_ENABLED == TRUE)
|
||||
#if ((IDSOPT_CONTROL_ENABLED == TRUE) && \
|
||||
((AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_ENV == TRUE) || \
|
||||
(AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || \
|
||||
(AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)))
|
||||
#if (IDSOPT_CONTROL_NV_TO_CMOS == TRUE)
|
||||
#define OPTION_IDS_NV_TO_CMOS_COMMON
|
||||
|
||||
#ifdef OPTION_FAMILY10H
|
||||
#if OPTION_FAMILY10H == TRUE
|
||||
#define OPTION_IDS_NV_TO_CMOS_F10
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef OPTION_FAMILY12H
|
||||
#if OPTION_FAMILY12H == TRUE
|
||||
#define OPTION_IDS_NV_TO_CMOS_F12
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef OPTION_FAMILY14H
|
||||
#if OPTION_FAMILY14H == TRUE
|
||||
#define OPTION_IDS_NV_TO_CMOS_F14
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef OPTION_FAMILY15H_OR
|
||||
#if OPTION_FAMILY15H_OR == TRUE
|
||||
#define OPTION_IDS_NV_TO_CMOS_F15_OR
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef OPTION_FAMILY15H_TN
|
||||
#if OPTION_FAMILY15H_TN == TRUE
|
||||
#define OPTION_IDS_NV_TO_CMOS_F15_TN\
|
||||
{IDS_NV_TO_CMOS_LEN_BYTE, AGESA_IDS_NV_UCODE},
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef OPTION_IDS_NV_TO_CMOS_F10
|
||||
#define OPTION_IDS_NV_TO_CMOS_F10
|
||||
#endif
|
||||
|
||||
#ifndef OPTION_IDS_NV_TO_CMOS_F12
|
||||
#define OPTION_IDS_NV_TO_CMOS_F12
|
||||
#endif
|
||||
|
||||
#ifndef OPTION_IDS_NV_TO_CMOS_F14
|
||||
#define OPTION_IDS_NV_TO_CMOS_F14
|
||||
#endif
|
||||
|
||||
#ifndef OPTION_IDS_NV_TO_CMOS_F15_OR
|
||||
#define OPTION_IDS_NV_TO_CMOS_F15_OR
|
||||
#endif
|
||||
|
||||
#ifndef OPTION_IDS_NV_TO_CMOS_F15_TN
|
||||
#define OPTION_IDS_NV_TO_CMOS_F15_TN
|
||||
#endif
|
||||
|
||||
#ifndef OPTION_IDS_NV_TO_CMOS_EXTEND
|
||||
#define OPTION_IDS_NV_TO_CMOS_EXTEND
|
||||
#endif
|
||||
|
||||
IDS_NV_TO_CMOS gIdsNVToCmos[] = {
|
||||
OPTION_IDS_NV_TO_CMOS_COMMON
|
||||
OPTION_IDS_NV_TO_CMOS_F10
|
||||
OPTION_IDS_NV_TO_CMOS_F12
|
||||
OPTION_IDS_NV_TO_CMOS_F14
|
||||
OPTION_IDS_NV_TO_CMOS_F15_OR
|
||||
OPTION_IDS_NV_TO_CMOS_F15_TN
|
||||
OPTION_IDS_NV_TO_CMOS_EXTEND
|
||||
OPTION_IDS_NV_TO_CMOS_END
|
||||
};
|
||||
#else
|
||||
IDS_NV_TO_CMOS gIdsNVToCmos[] = {
|
||||
OPTION_IDS_NV_TO_CMOS_END
|
||||
};
|
||||
#endif
|
||||
#else
|
||||
IDS_NV_TO_CMOS gIdsNVToCmos[] = {
|
||||
OPTION_IDS_NV_TO_CMOS_END
|
||||
};
|
||||
#endif
|
||||
#else
|
||||
IDS_NV_TO_CMOS gIdsNVToCmos[] = {
|
||||
OPTION_IDS_NV_TO_CMOS_END
|
||||
};
|
||||
#endif
|
||||
|
||||
///Ids Feat Options
|
||||
#if ((IDSOPT_IDS_ENABLED == TRUE) && \
|
||||
((AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_ENV == TRUE) || \
|
||||
(AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || \
|
||||
(AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)))
|
||||
#if (IDSOPT_CONTROL_ENABLED == TRUE)
|
||||
#ifndef OPTION_IDS_EXTEND_FEATS
|
||||
#define OPTION_IDS_EXTEND_FEATS
|
||||
#endif
|
||||
|
||||
#define OPTION_IDS_FEAT_ECCCTRL\
|
||||
OPTION_IDS_FEAT_ECCCTRL_F10 \
|
||||
OPTION_IDS_FEAT_ECCCTRL_F12 \
|
||||
OPTION_IDS_FEAT_ECCCTRL_F15_OR
|
||||
|
||||
#define OPTION_IDS_FEAT_GNB_PLATFORMCFG\
|
||||
OPTION_IDS_FEAT_GNB_PLATFORMCFGF12 \
|
||||
OPTION_IDS_FEAT_GNB_PLATFORMCFGF14 \
|
||||
OPTION_IDS_FEAT_GNB_PLATFORMCFGF15TN
|
||||
|
||||
#define OPTION_IDS_FEAT_CPB_CTRL\
|
||||
OPTION_IDS_FEAT_CPB_CTRL_F12
|
||||
|
||||
#define OPTION_IDS_FEAT_HTC_CTRL\
|
||||
OPTION_IDS_FEAT_HTC_CTRL_F15_OR \
|
||||
OPTION_IDS_FEAT_HTC_CTRL_F15_TN
|
||||
|
||||
#define OPTION_IDS_FEAT_MEMORY_MAPPING\
|
||||
OPTION_IDS_FEAT_MEMORY_MAPPING_F12 \
|
||||
OPTION_IDS_FEAT_MEMORY_MAPPING_F15_OR \
|
||||
OPTION_IDS_FEAT_MEMORY_MAPPING_F15_TN
|
||||
|
||||
#define OPTION_IDS_FEAT_HT_ASSIST\
|
||||
OPTION_IDS_FEAT_HT_ASSIST_F10HY \
|
||||
OPTION_IDS_FEAT_HT_ASSIST_F15_OR
|
||||
|
||||
#define OPTION_IDS_FEAT_ECCSYMBOLSIZE\
|
||||
OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10 \
|
||||
OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15_OR
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* Family 10 feat blocks
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
#define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10
|
||||
#define OPTION_IDS_FEAT_ECCCTRL_F10
|
||||
#ifdef OPTION_FAMILY10H
|
||||
#if OPTION_FAMILY10H == TRUE
|
||||
//Ecc symbol size
|
||||
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatEccSymbolSizeBlockF10;
|
||||
#undef OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10
|
||||
#define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10 &IdsFeatEccSymbolSizeBlockF10,
|
||||
|
||||
//ECC scrub control
|
||||
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatEccCtrlBlockF10;
|
||||
#undef OPTION_IDS_FEAT_ECCCTRL_F10
|
||||
#define OPTION_IDS_FEAT_ECCCTRL_F10 &IdsFeatEccCtrlBlockF10,
|
||||
#endif
|
||||
#endif
|
||||
|
||||
//Misc Features
|
||||
#define OPTION_IDS_FEAT_HT_ASSIST_F10HY
|
||||
#ifdef OPTION_FAMILY10H_HY
|
||||
#if OPTION_FAMILY10H_HY == TRUE
|
||||
#undef OPTION_IDS_FEAT_HT_ASSIST_F10HY
|
||||
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHtAssistBlockPlatformCfgF10Hy;
|
||||
|
||||
#define OPTION_IDS_FEAT_HT_ASSIST_F10HY \
|
||||
&IdsFeatHtAssistBlockPlatformCfgF10Hy,
|
||||
#endif
|
||||
#endif
|
||||
/*----------------------------------------------------------------------------
|
||||
* Family 12 feat blocks
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
#define OPTION_IDS_FEAT_GNB_PLATFORMCFGF12
|
||||
#define OPTION_IDS_FEAT_ECCCTRL_F12
|
||||
#define OPTION_IDS_FEAT_CPB_CTRL_F12
|
||||
#define OPTION_IDS_FEAT_MEMORY_MAPPING_F12
|
||||
#ifdef OPTION_FAMILY12H
|
||||
#if OPTION_FAMILY12H == TRUE
|
||||
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatGnbPlatformCfgBlockF12;
|
||||
#undef OPTION_IDS_FEAT_GNB_PLATFORMCFGF12
|
||||
#define OPTION_IDS_FEAT_GNB_PLATFORMCFGF12 &IdsFeatGnbPlatformCfgBlockF12,
|
||||
|
||||
//ECC scrub control
|
||||
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatEccCtrlBlockF12;
|
||||
#undef OPTION_IDS_FEAT_ECCCTRL_F12
|
||||
#define OPTION_IDS_FEAT_ECCCTRL_F12 &IdsFeatEccCtrlBlockF12,
|
||||
|
||||
#undef OPTION_IDS_FEAT_CPB_CTRL_F12
|
||||
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatCpbCtrlBlockF12;
|
||||
#define OPTION_IDS_FEAT_CPB_CTRL_F12 &IdsFeatCpbCtrlBlockF12,
|
||||
|
||||
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatMemoryChIntlvPostBeforeBlockF12;
|
||||
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingChIntlvBlockF12;
|
||||
#undef OPTION_IDS_FEAT_MEMORY_MAPPING_F12
|
||||
#define OPTION_IDS_FEAT_MEMORY_MAPPING_F12 \
|
||||
&IdsFeatMemoryChIntlvPostBeforeBlockF12, \
|
||||
&IdsFeatMemoryMappingChIntlvBlockF12,
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* Family 14 ON feat blocks
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
#define OPTION_IDS_FEAT_GNB_PLATFORMCFGF14
|
||||
#ifdef OPTION_FAMILY14H_ON
|
||||
#if OPTION_FAMILY14H_ON == TRUE
|
||||
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatGnbPlatformCfgBlockF14;
|
||||
#undef OPTION_IDS_FEAT_GNB_PLATFORMCFGF14
|
||||
#define OPTION_IDS_FEAT_GNB_PLATFORMCFGF14 &IdsFeatGnbPlatformCfgBlockF14,
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* Family 15 OR feat blocks
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
#define OPTION_IDS_FEAT_HTC_CTRL_F15_OR
|
||||
#define OPTION_IDS_FEAT_MEMORY_MAPPING_F15_OR
|
||||
#define OPTION_IDS_FEAT_HT_ASSIST_F15_OR
|
||||
#define OPTION_IDS_FEAT_ECCCTRL_F15_OR
|
||||
#define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15_OR
|
||||
#ifdef OPTION_FAMILY15H_OR
|
||||
#if OPTION_FAMILY15H_OR == TRUE
|
||||
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHtcControlBlockF15Or;
|
||||
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHtcControlLateBlockF15Or;
|
||||
#undef OPTION_IDS_FEAT_HTC_CTRL_F15_OR
|
||||
#define OPTION_IDS_FEAT_HTC_CTRL_F15_OR\
|
||||
&IdsFeatHtcControlBlockF15Or,\
|
||||
&IdsFeatHtcControlLateBlockF15Or,
|
||||
|
||||
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingPostBeforeBlockF15Or;
|
||||
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingChIntlvBlockF15Or;
|
||||
#undef OPTION_IDS_FEAT_MEMORY_MAPPING_F15_OR
|
||||
#define OPTION_IDS_FEAT_MEMORY_MAPPING_F15_OR\
|
||||
&IdsFeatMemoryMappingPostBeforeBlockF15Or,\
|
||||
&IdsFeatMemoryMappingChIntlvBlockF15Or,
|
||||
|
||||
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHtAssistBlockPlatformCfgF15Or;
|
||||
#undef OPTION_IDS_FEAT_HT_ASSIST_F15_OR
|
||||
#define OPTION_IDS_FEAT_HT_ASSIST_F15_OR\
|
||||
&IdsFeatHtAssistBlockPlatformCfgF15Or,
|
||||
|
||||
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatEccCtrlBlockF15Or;
|
||||
#undef OPTION_IDS_FEAT_ECCCTRL_F15_OR
|
||||
#define OPTION_IDS_FEAT_ECCCTRL_F15_OR &IdsFeatEccCtrlBlockF15Or,
|
||||
|
||||
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatEccSymbolSizeBlockF15Or;
|
||||
#undef OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15_OR
|
||||
#define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15_OR &IdsFeatEccSymbolSizeBlockF15Or,
|
||||
|
||||
#endif
|
||||
#endif
|
||||
/*----------------------------------------------------------------------------
|
||||
* Family 15 TN feat blocks
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
#define OPTION_IDS_FEAT_HTC_CTRL_F15_TN
|
||||
#define OPTION_IDS_FEAT_MEMORY_MAPPING_F15_TN
|
||||
#define OPTION_IDS_FEAT_GNB_PLATFORMCFGF15TN
|
||||
#ifdef OPTION_FAMILY15H_TN
|
||||
#if OPTION_FAMILY15H_TN == TRUE
|
||||
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHtcControlBlockF15Tn;
|
||||
#undef OPTION_IDS_FEAT_HTC_CTRL_F15_TN
|
||||
#define OPTION_IDS_FEAT_HTC_CTRL_F15_TN\
|
||||
&IdsFeatHtcControlBlockF15Tn,
|
||||
|
||||
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingPostBeforeBlockF15Tn;
|
||||
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingChIntlvBlockF15Tn;
|
||||
#undef OPTION_IDS_FEAT_MEMORY_MAPPING_F15_TN
|
||||
#define OPTION_IDS_FEAT_MEMORY_MAPPING_F15_TN\
|
||||
&IdsFeatMemoryMappingPostBeforeBlockF15Tn,\
|
||||
&IdsFeatMemoryMappingChIntlvBlockF15Tn,
|
||||
|
||||
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatGnbPlatformCfgBlockF15Tn;
|
||||
#undef OPTION_IDS_FEAT_GNB_PLATFORMCFGF15TN
|
||||
#define OPTION_IDS_FEAT_GNB_PLATFORMCFGF15TN &IdsFeatGnbPlatformCfgBlockF15Tn,
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define OPTION_IDS_FEAT_NV_TO_CMOS
|
||||
#if IDSOPT_CONTROL_NV_TO_CMOS == TRUE
|
||||
#undef OPTION_IDS_FEAT_NV_TO_CMOS
|
||||
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatNvToCmosSaveBlock;
|
||||
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatNvToCmosRestoreBlock;
|
||||
#define OPTION_IDS_FEAT_NV_TO_CMOS\
|
||||
&IdsFeatNvToCmosSaveBlock, \
|
||||
&IdsFeatNvToCmosRestoreBlock,
|
||||
|
||||
#endif
|
||||
CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatUcodeBlock =
|
||||
{
|
||||
IDS_FEAT_UCODE_UPDATE,
|
||||
IDS_ALL_CORES,
|
||||
IDS_UCODE,
|
||||
IDS_FAMILY_ALL,
|
||||
IdsSubUCode
|
||||
};
|
||||
|
||||
CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatPowerPolicyBlock =
|
||||
{
|
||||
IDS_FEAT_POWER_POLICY,
|
||||
IDS_ALL_CORES,
|
||||
IDS_PLATFORMCFG_OVERRIDE,
|
||||
IDS_FAMILY_ALL,
|
||||
IdsSubPowerPolicyOverride
|
||||
};
|
||||
|
||||
CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatTargetPstateBlock =
|
||||
{
|
||||
IDS_FEAT_TARGET_PSTATE,
|
||||
IDS_BSP_ONLY,
|
||||
IDS_INIT_LATE_AFTER,
|
||||
IDS_FAMILY_ALL,
|
||||
IdsSubTargetPstate
|
||||
};
|
||||
|
||||
CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatPostPstateBlock =
|
||||
{
|
||||
IDS_FEAT_POSTPSTATE,
|
||||
IDS_ALL_CORES,
|
||||
IDS_CPU_Early_Override,
|
||||
IDS_FAMILY_ALL,
|
||||
IdsSubPostPState
|
||||
};
|
||||
|
||||
//Dram controller Features
|
||||
CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatDctAllMemClkBlock =
|
||||
{
|
||||
IDS_FEAT_DCT_ALLMEMCLK,
|
||||
IDS_BSP_ONLY,
|
||||
IDS_ALL_MEMORY_CLOCK,
|
||||
IDS_FAMILY_ALL,
|
||||
IdsSubAllMemClkEn
|
||||
};
|
||||
|
||||
CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatDctGangModeBlock =
|
||||
{
|
||||
IDS_FEAT_DCT_GANGMODE,
|
||||
IDS_BSP_ONLY,
|
||||
IDS_GANGING_MODE,
|
||||
IDS_FAMILY_ALL,
|
||||
IdsSubGangingMode
|
||||
};
|
||||
|
||||
CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatDctBurstLengthBlock =
|
||||
{
|
||||
IDS_FEAT_DCT_BURSTLENGTH,
|
||||
IDS_BSP_ONLY,
|
||||
IDS_BURST_LENGTH32,
|
||||
AMD_FAMILY_10,
|
||||
IdsSubBurstLength32
|
||||
};
|
||||
|
||||
CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatDctPowerDownCtrlBlock =
|
||||
{
|
||||
IDS_FEAT_DCT_POWERDOWN,
|
||||
IDS_BSP_ONLY,
|
||||
IDS_INIT_POST_BEFORE,
|
||||
IDS_FAMILY_ALL,
|
||||
IdsSubPowerDownCtrl
|
||||
};
|
||||
|
||||
CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatDctDllShutDownBlock =
|
||||
{
|
||||
IDS_FEAT_DCT_DLLSHUTDOWN,
|
||||
IDS_BSP_ONLY,
|
||||
IDS_DLL_SHUT_DOWN,
|
||||
IDS_FAMILY_ALL,
|
||||
IdsSubDllShutDownSR
|
||||
};
|
||||
|
||||
|
||||
CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatDctPowerDownModeBlock =
|
||||
{
|
||||
IDS_FEAT_DCT_POWERDOWN,
|
||||
IDS_BSP_ONLY,
|
||||
IDS_POWERDOWN_MODE,
|
||||
IDS_FAMILY_ALL,
|
||||
IdsSubPowerDownMode
|
||||
};
|
||||
|
||||
CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHdtOutBlock =
|
||||
{
|
||||
IDS_FEAT_HDTOUT,
|
||||
IDS_BSP_ONLY,
|
||||
IDS_INIT_EARLY_BEFORE,
|
||||
IDS_FAMILY_ALL,
|
||||
IdsSubHdtOut
|
||||
};
|
||||
|
||||
CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHtSettingBlock =
|
||||
{
|
||||
IDS_FEAT_HT_SETTING,
|
||||
IDS_BSP_ONLY,
|
||||
IDS_HT_CONTROL,
|
||||
IDS_FAMILY_ALL,
|
||||
IdsSubHtLinkControl
|
||||
};
|
||||
|
||||
CONST IDS_FAMILY_FEAT_STRUCT* ROMDATA IdsContorlFeats[] =
|
||||
{
|
||||
&IdsFeatUcodeBlock,
|
||||
&IdsFeatPowerPolicyBlock,
|
||||
|
||||
&IdsFeatTargetPstateBlock,
|
||||
|
||||
&IdsFeatPostPstateBlock,
|
||||
|
||||
OPTION_IDS_FEAT_NV_TO_CMOS
|
||||
|
||||
OPTION_IDS_FEAT_ECCSYMBOLSIZE
|
||||
|
||||
OPTION_IDS_FEAT_ECCCTRL
|
||||
|
||||
&IdsFeatDctAllMemClkBlock,
|
||||
|
||||
&IdsFeatDctGangModeBlock,
|
||||
|
||||
&IdsFeatDctBurstLengthBlock,
|
||||
|
||||
&IdsFeatDctPowerDownCtrlBlock,
|
||||
|
||||
&IdsFeatDctPowerDownModeBlock,
|
||||
|
||||
&IdsFeatDctPowerDownModeBlock,
|
||||
|
||||
OPTION_IDS_FEAT_HT_ASSIST
|
||||
|
||||
&IdsFeatHdtOutBlock,
|
||||
|
||||
&IdsFeatHtSettingBlock,
|
||||
|
||||
OPTION_IDS_FEAT_GNB_PLATFORMCFG
|
||||
|
||||
OPTION_IDS_FEAT_CPB_CTRL
|
||||
|
||||
OPTION_IDS_FEAT_HTC_CTRL
|
||||
|
||||
OPTION_IDS_FEAT_MEMORY_MAPPING
|
||||
|
||||
OPTION_IDS_EXTEND_FEATS
|
||||
|
||||
NULL
|
||||
};
|
||||
#else
|
||||
CONST IDS_FAMILY_FEAT_STRUCT* ROMDATA IdsContorlFeats[] =
|
||||
{
|
||||
NULL
|
||||
};
|
||||
#endif//IDSOPT_CONTROL_ENABLED
|
||||
|
||||
#define OPTION_IDS_FAM_REGACC_F15TN
|
||||
#ifdef OPTION_FAMILY15H_TN
|
||||
#if OPTION_FAMILY15H_TN == TRUE
|
||||
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatRegGmmxF15Tn;
|
||||
#undef OPTION_IDS_FAM_REGACC_F15TN
|
||||
#define OPTION_IDS_FAM_REGACC_F15TN \
|
||||
&IdsFeatRegGmmxF15Tn,
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
CONST IDS_FAMILY_FEAT_STRUCT* ROMDATA IdsRegAccessTbl[] =
|
||||
{
|
||||
OPTION_IDS_FAM_REGACC_F15TN
|
||||
NULL
|
||||
};
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* IDS TRACING SERVICES
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
#if IDSOPT_TRACING_ENABLED == TRUE
|
||||
#define IDS_TRACING_CONSOLE_HDTOUT
|
||||
#define IDS_TRACING_CONSOLE_SERIALPORT
|
||||
#define IDS_TRACING_CONSOLE_REDIRECT_IO
|
||||
|
||||
#ifdef IDSOPT_TRACING_CONSOLE_HDTOUT
|
||||
#if IDSOPT_TRACING_CONSOLE_HDTOUT == TRUE
|
||||
#undef IDS_TRACING_CONSOLE_HDTOUT
|
||||
extern CONST IDS_DEBUG_PRINT ROMDATA IdsDebugPrintHdtoutInstance;
|
||||
#define IDS_TRACING_CONSOLE_HDTOUT &IdsDebugPrintHdtoutInstance,
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef IDSOPT_TRACING_CONSOLE_SERIALPORT
|
||||
#if IDSOPT_TRACING_CONSOLE_SERIALPORT == TRUE
|
||||
#undef IDS_TRACING_CONSOLE_SERIALPORT
|
||||
extern CONST IDS_DEBUG_PRINT ROMDATA IdsDebugPrintSerialInstance;
|
||||
#define IDS_TRACING_CONSOLE_SERIALPORT &IdsDebugPrintSerialInstance,
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef IDSOPT_TRACING_CONSOLE_REDIRECT_IO
|
||||
#if IDSOPT_TRACING_CONSOLE_REDIRECT_IO == TRUE
|
||||
#undef IDS_TRACING_CONSOLE_REDIRECT_IO
|
||||
extern CONST IDS_DEBUG_PRINT ROMDATA IdsDebugPrintRedirectIoInstance;
|
||||
#define IDS_TRACING_CONSOLE_REDIRECT_IO &IdsDebugPrintRedirectIoInstance,
|
||||
#endif
|
||||
#endif
|
||||
|
||||
CONST IDS_DEBUG_PRINT* ROMDATA IdsDebugPrint[] =
|
||||
{
|
||||
IDS_TRACING_CONSOLE_SERIALPORT
|
||||
IDS_TRACING_CONSOLE_HDTOUT
|
||||
IDS_TRACING_CONSOLE_REDIRECT_IO
|
||||
NULL
|
||||
};
|
||||
#else
|
||||
CONST IDS_DEBUG_PRINT* ROMDATA IdsDebugPrint[] =
|
||||
{
|
||||
NULL
|
||||
};
|
||||
#endif
|
||||
|
||||
#else
|
||||
CONST IDS_FAMILY_FEAT_STRUCT* ROMDATA IdsContorlFeats[] =
|
||||
{
|
||||
NULL
|
||||
};
|
||||
|
||||
CONST IDS_FAMILY_FEAT_STRUCT* ROMDATA IdsRegAccessTbl[] =
|
||||
{
|
||||
NULL
|
||||
};
|
||||
|
||||
CONST IDS_DEBUG_PRINT* ROMDATA IdsDebugPrint[] =
|
||||
{
|
||||
NULL
|
||||
};
|
||||
#endif// IDSOPT_IDS_ENABLED
|
||||
|
||||
#endif
|
||||
171
src/vendorcode/amd/agesa/f15tn/Include/OptionIoCstateInstall.h
Normal file
171
src/vendorcode/amd/agesa/f15tn/Include/OptionIoCstateInstall.h
Normal file
@ -0,0 +1,171 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* Install of build option: IO C-state
|
||||
*
|
||||
* Contains AMD AGESA install macros and test conditions. Output is the
|
||||
* defaults tables reflecting the User's build options selection.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: Options
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef _OPTION_IO_CSTATE_INSTALL_H_
|
||||
#define _OPTION_IO_CSTATE_INSTALL_H_
|
||||
|
||||
#include "cpuIoCstate.h"
|
||||
|
||||
/* This option is designed to be included into the platform solution install
|
||||
* file. The platform solution install file will define the options status.
|
||||
* Check to validate the definition
|
||||
*/
|
||||
|
||||
#define OPTION_IO_CSTATE_FEAT
|
||||
#define F10_IO_CSTATE_SUPPORT
|
||||
#define F12_IO_CSTATE_SUPPORT
|
||||
#define F14_IO_CSTATE_SUPPORT
|
||||
#define F15_OR_IO_CSTATE_SUPPORT
|
||||
#define F15_TN_IO_CSTATE_SUPPORT
|
||||
|
||||
#if OPTION_IO_CSTATE == TRUE
|
||||
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
|
||||
#ifdef OPTION_FAMILY10H
|
||||
#if OPTION_FAMILY10H == TRUE
|
||||
#if OPTION_FAMILY10H_PH == TRUE
|
||||
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate;
|
||||
#undef OPTION_IO_CSTATE_FEAT
|
||||
#define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate,
|
||||
extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F10IoCstateSupport;
|
||||
#undef F10_IO_CSTATE_SUPPORT
|
||||
#define F10_IO_CSTATE_SUPPORT {AMD_FAMILY_10_PH, &F10IoCstateSupport},
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef OPTION_FAMILY12H
|
||||
#if OPTION_FAMILY12H == TRUE
|
||||
#if OPTION_FAMILY12H_LN == TRUE
|
||||
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate;
|
||||
#undef OPTION_IO_CSTATE_FEAT
|
||||
#define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate,
|
||||
extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F12IoCstateSupport;
|
||||
#undef F12_IO_CSTATE_SUPPORT
|
||||
#define F12_IO_CSTATE_SUPPORT {AMD_FAMILY_12_LN, &F12IoCstateSupport},
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef OPTION_FAMILY14H
|
||||
#if OPTION_FAMILY14H == TRUE
|
||||
#if (OPTION_FAMILY14H_ON == TRUE)
|
||||
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate;
|
||||
#undef OPTION_IO_CSTATE_FEAT
|
||||
#define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate,
|
||||
extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F14IoCstateSupport;
|
||||
#undef F14_IO_CSTATE_SUPPORT
|
||||
#define F14_IO_CSTATE_SUPPORT {AMD_FAMILY_14, &F14IoCstateSupport},
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef OPTION_FAMILY15H
|
||||
#if OPTION_FAMILY15H == TRUE
|
||||
#if OPTION_FAMILY15H_OR == TRUE
|
||||
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate;
|
||||
#undef OPTION_IO_CSTATE_FEAT
|
||||
#define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate,
|
||||
extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F15OrIoCstateSupport;
|
||||
#undef F15_OR_IO_CSTATE_SUPPORT
|
||||
#define F15_OR_IO_CSTATE_SUPPORT {AMD_FAMILY_15_OR, &F15OrIoCstateSupport},
|
||||
#endif
|
||||
|
||||
#if OPTION_FAMILY15H_TN == TRUE
|
||||
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate;
|
||||
#undef OPTION_IO_CSTATE_FEAT
|
||||
#define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate,
|
||||
extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F15TnIoCstateSupport;
|
||||
#undef F15_TN_IO_CSTATE_SUPPORT
|
||||
#define F15_TN_IO_CSTATE_SUPPORT {AMD_FAMILY_15_TN, &F15TnIoCstateSupport},
|
||||
#endif
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA IoCstateFamilyServiceArray[] =
|
||||
{
|
||||
F10_IO_CSTATE_SUPPORT
|
||||
F12_IO_CSTATE_SUPPORT
|
||||
F14_IO_CSTATE_SUPPORT
|
||||
F15_OR_IO_CSTATE_SUPPORT
|
||||
F15_TN_IO_CSTATE_SUPPORT
|
||||
{0, NULL}
|
||||
};
|
||||
|
||||
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA IoCstateFamilyServiceTable =
|
||||
{
|
||||
(sizeof (IoCstateFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
|
||||
&IoCstateFamilyServiceArray[0]
|
||||
};
|
||||
|
||||
#endif // _OPTION_IO_CSTATE_INSTALL_H_
|
||||
133
src/vendorcode/amd/agesa/f15tn/Include/OptionL3FeaturesInstall.h
Normal file
133
src/vendorcode/amd/agesa/f15tn/Include/OptionL3FeaturesInstall.h
Normal file
@ -0,0 +1,133 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* Install of build option: L3 Dependent Features
|
||||
*
|
||||
* Contains AMD AGESA install macros and test conditions. Output is the
|
||||
* defaults tables reflecting the User's build options selection.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: Options
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef _OPTION_L3_FEATURES_INSTALL_H_
|
||||
#define _OPTION_L3_FEATURES_INSTALL_H_
|
||||
|
||||
#include "cpuL3Features.h"
|
||||
|
||||
/* This option is designed to be included into the platform solution install
|
||||
* file. The platform solution install file will define the options status.
|
||||
* Check to validate the definition
|
||||
*/
|
||||
#define OPTION_L3_FEAT
|
||||
#define F10_L3_FEAT_SUPPORT
|
||||
#define F15_OR_L3_FEAT_SUPPORT
|
||||
#define L3_FEAT_AP_DISABLE_CACHE
|
||||
#define L3_FEAT_AP_ENABLE_CACHE
|
||||
|
||||
#if (OPTION_HT_ASSIST == TRUE || OPTION_ATM_MODE == TRUE)
|
||||
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)
|
||||
#ifdef OPTION_FAMILY10H
|
||||
#if OPTION_FAMILY10H == TRUE
|
||||
#if OPTION_FAMILY10H_HY == TRUE
|
||||
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuL3Features;
|
||||
#undef OPTION_L3_FEAT
|
||||
#define OPTION_L3_FEAT &CpuL3Features,
|
||||
extern CONST L3_FEATURE_FAMILY_SERVICES ROMDATA F10L3Features;
|
||||
#undef F10_L3_FEAT_SUPPORT
|
||||
#define F10_L3_FEAT_SUPPORT {AMD_FAMILY_10_HY, &F10L3Features},
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef OPTION_FAMILY15H_OR
|
||||
#if OPTION_FAMILY15H_OR == TRUE
|
||||
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuL3Features;
|
||||
#undef OPTION_L3_FEAT
|
||||
#define OPTION_L3_FEAT &CpuL3Features,
|
||||
extern CONST L3_FEATURE_FAMILY_SERVICES ROMDATA F15OrL3Features;
|
||||
#undef F15_OR_L3_FEAT_SUPPORT
|
||||
#define F15_OR_L3_FEAT_SUPPORT {AMD_FAMILY_15_OR, &F15OrL3Features},
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#undef AGESA_ENTRY_LATE_RUN_AP_TASK
|
||||
#define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE
|
||||
#undef L3_FEAT_AP_DISABLE_CACHE
|
||||
#define L3_FEAT_AP_DISABLE_CACHE {AP_LATE_TASK_DISABLE_CACHE, (IMAGE_ENTRY) DisableAllCaches},
|
||||
#undef L3_FEAT_AP_ENABLE_CACHE
|
||||
#define L3_FEAT_AP_ENABLE_CACHE {AP_LATE_TASK_ENABLE_CACHE, (IMAGE_ENTRY) EnableAllCaches},
|
||||
#endif
|
||||
#endif
|
||||
|
||||
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA L3FeatureFamilyServiceArray[] =
|
||||
{
|
||||
F10_L3_FEAT_SUPPORT
|
||||
F15_OR_L3_FEAT_SUPPORT
|
||||
{0, NULL}
|
||||
};
|
||||
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA L3FeatureFamilyServiceTable =
|
||||
{
|
||||
(sizeof (L3FeatureFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
|
||||
&L3FeatureFamilyServiceArray[0]
|
||||
};
|
||||
|
||||
#endif // _OPTION_L3_FEATURES_INSTALL_H_
|
||||
@ -0,0 +1,115 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* Install of build option: Low Power Pstate for PROCHOT_L Throttling.
|
||||
*
|
||||
* Contains AMD AGESA install macros and test conditions. Output is the
|
||||
* defaults tables reflecting the User's build options selection.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: Options
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef _OPTION_LOW_PWR_PSTATE_INSTALL_H_
|
||||
#define _OPTION_LOW_PWR_PSTATE_INSTALL_H_
|
||||
|
||||
#include "cpuLowPwrPstate.h"
|
||||
|
||||
/* This option is designed to be included into the platform solution install
|
||||
* file. The platform solution install file will define the options status.
|
||||
* Check to validate the definition
|
||||
*/
|
||||
#define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT
|
||||
#define F15_OR_LOW_PWR_PSTATE_SUPPORT
|
||||
|
||||
#if OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT == TRUE
|
||||
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
|
||||
// Family 15h
|
||||
#ifdef OPTION_FAMILY15H
|
||||
#if OPTION_FAMILY15H == TRUE
|
||||
#if OPTION_FAMILY15H_OR == TRUE
|
||||
#if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE)
|
||||
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureLowPwrPstate;
|
||||
#undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT
|
||||
#define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT &CpuFeatureLowPwrPstate,
|
||||
extern CONST LOW_PWR_PSTATE_FAMILY_SERVICES ROMDATA F15OrLowPwrPstateSupport;
|
||||
#undef F15_OR_LOW_PWR_PSTATE_SUPPORT
|
||||
#define F15_OR_LOW_PWR_PSTATE_SUPPORT {AMD_FAMILY_15_OR, &F15OrLowPwrPstateSupport},
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA LowPwrPstateFamilyServiceArray[] =
|
||||
{
|
||||
F15_OR_LOW_PWR_PSTATE_SUPPORT
|
||||
{0, NULL}
|
||||
};
|
||||
|
||||
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA LowPwrPstateFamilyServiceTable =
|
||||
{
|
||||
(sizeof (LowPwrPstateFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
|
||||
&LowPwrPstateFamilyServiceArray[0]
|
||||
};
|
||||
|
||||
#endif // _OPTION_LOW_PWR_PSTATE_INSTALL_H_
|
||||
384
src/vendorcode/amd/agesa/f15tn/Include/OptionMemory.h
Normal file
384
src/vendorcode/amd/agesa/f15tn/Include/OptionMemory.h
Normal file
@ -0,0 +1,384 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* AMD Memory option API.
|
||||
*
|
||||
* Contains structures and values used to control the Memory option code.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: OPTION
|
||||
* @e \$Revision: 64574 $ @e \$Date: 2012-01-25 01:01:51 -0600 (Wed, 25 Jan 2012) $
|
||||
*
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef _OPTION_MEMORY_H_
|
||||
#define _OPTION_MEMORY_H_
|
||||
|
||||
/* Memory Includes */
|
||||
#include "mm.h"
|
||||
#include "mn.h"
|
||||
#include "mt.h"
|
||||
#include "ma.h"
|
||||
#include "mp.h"
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* D E F I N I T I O N S A N D M A C R O S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#define MAX_FF_TYPES 6 ///< Maximum number of DDR Form factors (UDIMMs, RDIMMMs, SODIMMS) supported
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* T Y P E D E F S, S T R U C T U R E S, E N U M S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*
|
||||
* STANDARD MEMORY FEATURE FUNCTION POINTER
|
||||
*/
|
||||
|
||||
typedef BOOLEAN OPTION_MEM_FEATURE_NB (
|
||||
IN OUT MEM_NB_BLOCK *NBPtr
|
||||
);
|
||||
|
||||
typedef BOOLEAN MEM_TECH_FEAT (
|
||||
IN OUT MEM_TECH_BLOCK *TechPtr
|
||||
);
|
||||
|
||||
typedef UINT8 MEM_TABLE_FEAT (
|
||||
IN OUT MEM_TABLE_ALIAS **MTPtr
|
||||
);
|
||||
|
||||
#define MEM_FEAT_BLOCK_NB_STRUCT_VERSION 0x01
|
||||
|
||||
/**
|
||||
* MEMORY FEATURE BLOCK - This structure serves as a vector table for standard
|
||||
* memory feature implementation functions. It contains vectors for all of the
|
||||
* features that are supported by the various Northbridge devices supported by
|
||||
* AGESA.
|
||||
*/
|
||||
typedef struct _MEM_FEAT_BLOCK_NB {
|
||||
UINT16 OptMemFeatVersion; ///< Version of memory feature block.
|
||||
OPTION_MEM_FEATURE_NB *OnlineSpare; ///< Online spare support.
|
||||
OPTION_MEM_FEATURE_NB *InterleaveBanks; ///< Bank (Chip select) interleaving support.
|
||||
OPTION_MEM_FEATURE_NB *UndoInterleaveBanks; ///< Undo Bank (Chip Select) interleaving.
|
||||
OPTION_MEM_FEATURE_NB *CheckInterleaveNodes; ///< Check for Node interleaving support.
|
||||
OPTION_MEM_FEATURE_NB *InterleaveNodes; ///< Node interleaving support.
|
||||
OPTION_MEM_FEATURE_NB *InterleaveChannels; ///< Channel interleaving support.
|
||||
OPTION_MEM_FEATURE_NB *InterleaveRegion; ///< Interleave Region support.
|
||||
OPTION_MEM_FEATURE_NB *CheckEcc; ///< Check for ECC support.
|
||||
OPTION_MEM_FEATURE_NB *InitEcc; ///< ECC support.
|
||||
OPTION_MEM_FEATURE_NB *Training; ///< Choose the type of training (Parallel, standard or hardcoded).
|
||||
OPTION_MEM_FEATURE_NB *LvDdr3; ///< Low voltage DDR3 dimm support
|
||||
OPTION_MEM_FEATURE_NB *OnDimmThermal; ///< On-Dimm thermal management
|
||||
MEM_TECH_FEAT *DramInit; ///< Choose the type of Dram init (hardware based or software based).
|
||||
OPTION_MEM_FEATURE_NB *ExcludeDIMM; ///< Exclude a dimm.
|
||||
OPTION_MEM_FEATURE_NB *excel221;
|
||||
OPTION_MEM_FEATURE_NB *InitCPG; ///< Continuous pattern generation.
|
||||
OPTION_MEM_FEATURE_NB *InitHwRxEn; ///< Hardware Receiver Enable Training Initilization.
|
||||
} MEM_FEAT_BLOCK_NB;
|
||||
|
||||
typedef AGESA_STATUS MEM_MAIN_FLOW_CONTROL (
|
||||
IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
|
||||
);
|
||||
|
||||
typedef BOOLEAN OPTION_MEM_FEATURE_MAIN (
|
||||
IN MEM_MAIN_DATA_BLOCK *MMPtr
|
||||
);
|
||||
|
||||
typedef BOOLEAN MEM_NB_CONSTRUCTOR (
|
||||
IN OUT MEM_NB_BLOCK *NBPtr,
|
||||
IN OUT MEM_DATA_STRUCT *MemPtr,
|
||||
IN MEM_FEAT_BLOCK_NB *FeatPtr,
|
||||
IN MEM_SHARED_DATA *mmSharedPtr, ///< Pointer to Memory scratchpad
|
||||
IN UINT8 NodeID
|
||||
);
|
||||
|
||||
typedef BOOLEAN MEM_TECH_CONSTRUCTOR (
|
||||
IN OUT MEM_TECH_BLOCK *TechPtr,
|
||||
IN OUT MEM_NB_BLOCK *NBPtr
|
||||
);
|
||||
|
||||
typedef VOID MEM_INITIALIZER (
|
||||
IN OUT MEM_DATA_STRUCT *MemPtr
|
||||
);
|
||||
|
||||
typedef AGESA_STATUS MEM_PLATFORM_CFG (
|
||||
IN struct _MEM_DATA_STRUCT *MemData,
|
||||
IN UINT8 SocketID,
|
||||
IN CH_DEF_STRUCT *CurrentChannel
|
||||
);
|
||||
|
||||
typedef BOOLEAN MEM_IDENDIMM_CONSTRUCTOR (
|
||||
IN OUT MEM_NB_BLOCK *NBPtr,
|
||||
IN OUT MEM_DATA_STRUCT *MemPtr,
|
||||
IN UINT8 NodeID
|
||||
);
|
||||
|
||||
typedef VOID MEM_TECH_TRAINING_FEAT (
|
||||
IN OUT MEM_TECH_BLOCK *TechPtr,
|
||||
IN UINT8 Pass
|
||||
);
|
||||
|
||||
typedef BOOLEAN MEM_RESUME_CONSTRUCTOR (
|
||||
IN OUT VOID *S3NBPtr,
|
||||
IN OUT MEM_DATA_STRUCT *MemPtr,
|
||||
IN UINT8 NodeID
|
||||
);
|
||||
|
||||
typedef AGESA_STATUS MEM_PLAT_SPEC_CFG (
|
||||
IN struct _MEM_DATA_STRUCT *MemData,
|
||||
IN OUT CH_DEF_STRUCT *CurrentChannel,
|
||||
IN OUT MEM_PS_BLOCK *PsPtr
|
||||
);
|
||||
|
||||
typedef AGESA_STATUS MEM_FLOW_CFG (
|
||||
IN OUT MEM_MAIN_DATA_BLOCK *MemData
|
||||
);
|
||||
|
||||
#define MEM_FEAT_BLOCK_MAIN_STRUCT_VERSION 0x01
|
||||
|
||||
/**
|
||||
* MAIN FEATURE BLOCK - This structure serves as vector table for memory features
|
||||
* that shared between all northbridge devices.
|
||||
*/
|
||||
typedef struct _MEM_FEAT_BLOCK_MAIN {
|
||||
UINT16 OptMemFeatVersion; ///< Version of main feature block.
|
||||
OPTION_MEM_FEATURE_MAIN *Training; ///< Training features.
|
||||
OPTION_MEM_FEATURE_MAIN *ExcludeDIMM; ///< Exclude a dimm.
|
||||
OPTION_MEM_FEATURE_MAIN *OnlineSpare; ///< On-line spare.
|
||||
OPTION_MEM_FEATURE_MAIN *InterleaveNodes; ///< Node interleave.
|
||||
OPTION_MEM_FEATURE_MAIN *InitEcc; ///< Initialize ECC on all nodes if they all support it.
|
||||
OPTION_MEM_FEATURE_MAIN *MemClr; ///< Memory Clear.
|
||||
OPTION_MEM_FEATURE_MAIN *MemDmi; ///< Memory DMI Support.
|
||||
OPTION_MEM_FEATURE_MAIN *excel222;
|
||||
OPTION_MEM_FEATURE_MAIN *LvDDR3; ///< Low voltage DDR3 support.
|
||||
OPTION_MEM_FEATURE_MAIN *UmaAllocation; ///< Uma Allocation.
|
||||
OPTION_MEM_FEATURE_MAIN *MemSave; ///< Memory Context Save
|
||||
OPTION_MEM_FEATURE_MAIN *MemRestore; ///< Memory Context Restore
|
||||
} MEM_FEAT_BLOCK_MAIN;
|
||||
|
||||
#define MEM_NB_SUPPORT_STRUCT_VERSION 0x01
|
||||
#define MEM_TECH_FEAT_BLOCK_STRUCT_VERSION 0x01
|
||||
#define MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION 0x01
|
||||
#define MEM_TECH_LRDIMM_STRUCT_VERSION 0x01
|
||||
/**
|
||||
* MEMORY TECHNOLOGY FEATURE BLOCK - This structure serves as a vector table for standard
|
||||
* memory feature implementation functions. It contains vectors for all of the
|
||||
* features that are supported by the various Technology features supported by
|
||||
* AGESA.
|
||||
*/
|
||||
typedef struct _MEM_TECH_FEAT_BLOCK {
|
||||
UINT16 OptMemTechFeatVersion; ///< Version of memory Tech feature block.
|
||||
MEM_TECH_FEAT *EnterHardwareTraining; ///<Enter HW WL Training
|
||||
MEM_TECH_FEAT *SwWLTraining; ///<SW Write Levelization training
|
||||
MEM_TECH_FEAT *HwBasedWLTrainingPart1; ///<HW based write levelization Training Part 1
|
||||
MEM_TECH_FEAT *HwBasedDQSReceiverEnableTrainingPart1; ///<HW based DQS receiver Enabled Training Part 1
|
||||
MEM_TECH_FEAT *HwBasedWLTrainingPart2; ///<HW based write levelization Training Part 2
|
||||
MEM_TECH_FEAT *HwBasedDQSReceiverEnableTrainingPart2; ///<HW based DQS receiver Enabled Training Part 2
|
||||
MEM_TECH_FEAT *TrainExitHwTrn; ///<Exit HW WL Training
|
||||
MEM_TECH_FEAT *NonOptimizedSWDQSRecEnTrainingPart1; ///< Non-Optimized Software based receiver Enable Training part 1
|
||||
MEM_TECH_FEAT *OptimizedSwDqsRecEnTrainingPart1; ///< Optimized Software based receiver Enable Training part 1
|
||||
MEM_TECH_FEAT *NonOptimizedSRdWrPosTraining; ///< Non-Optimized Rd Wr Position training
|
||||
MEM_TECH_FEAT *OptimizedSRdWrPosTraining; ///< Optimized Rd Wr Position training
|
||||
MEM_TECH_FEAT *MaxRdLatencyTraining; ///< MaxReadLatency Training
|
||||
MEM_TECH_FEAT *RdPosTraining; ///< HW Rx En Seed Training
|
||||
} MEM_TECH_FEAT_BLOCK;
|
||||
|
||||
/**
|
||||
* MEMORY TECHNOLOGY LRDIMM BLOCK - This structure serves as a vector table for standard
|
||||
* memory feature implementation functions. It contains vectors for all of the
|
||||
* features that are supported by the various LRDIMM features supported by
|
||||
* AGESA.
|
||||
*/
|
||||
typedef struct _MEM_TECH_LRDIMM {
|
||||
UINT16 OptMemTechLrdimmVersion; ///< Version of memory Tech feature block.
|
||||
MEM_TECH_FEAT *MemTInitializeLrdimm; ///< LRDIMM initialization
|
||||
} MEM_TECH_LRDIMM;
|
||||
/**
|
||||
* MEMORY NORTHBRIDGE SUPPORT STRUCT - This structure groups the Northbridge dependent
|
||||
* options together in a list to provide a single access point for all code to use
|
||||
* and to ensure that everything corresponding to the same NB type is grouped together.
|
||||
*
|
||||
* The Technology Block pointers are not included in this structure because DRAM technology
|
||||
* needs to be decoupled from the northbridge type.
|
||||
*
|
||||
*/
|
||||
typedef struct _MEM_NB_SUPPORT {
|
||||
UINT16 MemNBSupportVersion; ///< Version of northbridge support.
|
||||
MEM_NB_CONSTRUCTOR *MemConstructNBBlock; ///< NorthBridge block constructor.
|
||||
MEM_INITIALIZER *MemNInitDefaults; ///< Default value initialization for MEM_DATA_STRUCT.
|
||||
MEM_FEAT_BLOCK_NB *MemFeatBlock; ///< Memory feature block.
|
||||
MEM_RESUME_CONSTRUCTOR *MemS3ResumeConstructNBBlock; ///< S3 memory initialization northbridge block constructor.
|
||||
MEM_IDENDIMM_CONSTRUCTOR *MemIdentifyDimmConstruct; ///< Constructor for address to dimm identification.
|
||||
} MEM_NB_SUPPORT;
|
||||
|
||||
/*
|
||||
* MEMORY Non-Training FEATURES - This structure serves as a vector table for standard
|
||||
* memory non-training feature implementation functions. It contains vectors for all of the
|
||||
* features that are supported by the various Technology devices supported by
|
||||
* AGESA.
|
||||
*/
|
||||
|
||||
/**
|
||||
* MAIN TRAINING SEQUENCE LIST - This structure serves as vector table for memory features
|
||||
* that shared between all northbridge devices.
|
||||
*/
|
||||
typedef struct _MEM_FEAT_TRAIN_SEQ {
|
||||
UINT16 OptMemTrainingSequenceListVersion; ///< Version of main feature block.
|
||||
OPTION_MEM_FEATURE_NB *TrainingSequence; ///< Training Sequence function.
|
||||
OPTION_MEM_FEATURE_NB *TrainingSequenceEnabled; ///< Enable function.
|
||||
MEM_TECH_FEAT_BLOCK *MemTechFeatBlock; ///< Memory feature block.
|
||||
} MEM_FEAT_TRAIN_SEQ;
|
||||
|
||||
/**
|
||||
* PLATFORM SPECIFIC CONFIGURATION BLOCK - This structure groups various PSC table
|
||||
* entries which are used by PSC engine
|
||||
*/
|
||||
typedef struct _MEM_PSC_TABLE_BLOCK {
|
||||
PSC_TBL_ENTRY **TblEntryOfMaxFreq; ///< Table entry of MaxFreq.
|
||||
PSC_TBL_ENTRY **TblEntryOfDramTerm; ///< Table entry of Dram Term.
|
||||
PSC_TBL_ENTRY **TblEntryOfODTPattern; ///< Table entry of ODT Pattern.
|
||||
PSC_TBL_ENTRY **TblEntryOfSAO; ///< Table entry of Slow access mode, AddrTmg and ODC..
|
||||
PSC_TBL_ENTRY **TblEntryOfMR0WR; ///< Table entry of MR0[WR].
|
||||
PSC_TBL_ENTRY **TblEntryOfMR0CL; ///< Table entry of MR0[CL].
|
||||
PSC_TBL_ENTRY **TblEntryOfRC2IBT; ///< Table entry of RC2 IBT.
|
||||
PSC_TBL_ENTRY **TblEntryOfRC10OpSpeed; ///< Table entry of RC10[operating speed].
|
||||
PSC_TBL_ENTRY **TblEntryOfLRIBT;///< Table entry of LRDIMM IBT
|
||||
PSC_TBL_ENTRY **TblEntryOfLRNPR; ///< Table entry of LRDIMM F0RC13[NumPhysicalRanks].
|
||||
PSC_TBL_ENTRY **TblEntryOfLRNLR; ///< Table entry of LRDIMM F0RC13[NumLogicalRanks].
|
||||
PSC_TBL_ENTRY **TblEntryOfGen; ///< Table entry of CLKDis map and CKE, ODT as well as ChipSel tri-state map.
|
||||
PSC_TBL_ENTRY **excel224;
|
||||
PSC_TBL_ENTRY **TblEntryOfWLSeed; ///< Table entry of WL seed
|
||||
PSC_TBL_ENTRY **TblEntryOfHWRxENSeed; ///< Table entry of HW RxEN seed
|
||||
} MEM_PSC_TABLE_BLOCK;
|
||||
|
||||
typedef BOOLEAN MEM_PSC_FLOW (
|
||||
IN OUT MEM_NB_BLOCK *NBPtr,
|
||||
IN MEM_PSC_TABLE_BLOCK *EntryOfTables
|
||||
);
|
||||
|
||||
/**
|
||||
* PLATFORM SPECIFIC CONFIGURATION FLOW BLOCK - Pointers to the sub-engines of platform
|
||||
* specific configuration.
|
||||
*/
|
||||
typedef struct _MEM_PSC_FLOW_BLOCK {
|
||||
MEM_PSC_TABLE_BLOCK *EntryOfTables; ///<Entry of NB specific MEM_PSC_TABLE_BLOCK
|
||||
MEM_PSC_FLOW *MaxFrequency; ///< Sub-engine which performs "Max Frequency" value extraction.
|
||||
MEM_PSC_FLOW *DramTerm; ///< Sub-engine which performs "Dram Term" value extraction.
|
||||
MEM_PSC_FLOW *ODTPattern; ///< Sub-engine which performs "ODT Pattern" value extraction.
|
||||
MEM_PSC_FLOW *SAO; ///< Sub-engine which performs "Slow access mode, AddrTmg and ODC" value extraction.
|
||||
MEM_PSC_FLOW *MR0WrCL; ///< Sub-engine which performs "MR0[WR] and MR0[CL]" value extraction.
|
||||
MEM_PSC_FLOW *RC2IBT; ///< Sub-engine "RC2 IBT" value extraction.
|
||||
MEM_PSC_FLOW *RC10OpSpeed; ///< Sub-engine "RC10[operating speed]" value extraction.
|
||||
MEM_PSC_FLOW *LRIBT; ///< Sub-engine "LRDIMM IBT" value extraction.
|
||||
MEM_PSC_FLOW *LRNPR; ///< Sub-engine "LRDIMM F0RC13[NumPhysicalRanks]" value extraction.
|
||||
MEM_PSC_FLOW *LRNLR; ///< Sub-engine "LRDIMM F0RC13[NumLogicalRanks]" value extraction.
|
||||
MEM_PSC_FLOW *excel225;
|
||||
MEM_PSC_FLOW *TrainingSeedVal; ///< Sub-engine for WL and HW RxEn pass1 seed value extraction
|
||||
} MEM_PSC_FLOW_BLOCK;
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* F U N C T I O N P R O T O T Y P E
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
/* Feature Default Return */
|
||||
BOOLEAN MemFDefRet (
|
||||
IN OUT MEM_NB_BLOCK *NBPtr
|
||||
);
|
||||
|
||||
BOOLEAN MemMDefRet (
|
||||
IN MEM_MAIN_DATA_BLOCK *MMPtr
|
||||
);
|
||||
|
||||
BOOLEAN MemMDefRetFalse (
|
||||
IN MEM_MAIN_DATA_BLOCK *MMPtr
|
||||
);
|
||||
|
||||
/* Table Feature Default Return */
|
||||
UINT8 MemFTableDefRet (
|
||||
IN OUT MEM_TABLE_ALIAS **MTPtr
|
||||
);
|
||||
/* S3 Feature Default Return */
|
||||
BOOLEAN MemFS3DefConstructorRet (
|
||||
IN OUT VOID *S3NBPtr,
|
||||
IN OUT MEM_DATA_STRUCT *MemPtr,
|
||||
IN UINT8 NodeID
|
||||
);
|
||||
|
||||
BOOLEAN MemNIdentifyDimmConstructorRetDef (
|
||||
IN OUT MEM_NB_BLOCK *NBPtr,
|
||||
IN OUT MEM_DATA_STRUCT *MemPtr,
|
||||
IN UINT8 NodeID
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
MemProcessConditionalOverrides (
|
||||
IN PSO_TABLE *PlatformMemoryConfiguration,
|
||||
IN OUT MEM_NB_BLOCK *NBPtr,
|
||||
IN UINT8 PsoAction,
|
||||
IN UINT8 Dimm
|
||||
);
|
||||
|
||||
#endif // _OPTION_MEMORY_H_
|
||||
4888
src/vendorcode/amd/agesa/f15tn/Include/OptionMemoryInstall.h
Normal file
4888
src/vendorcode/amd/agesa/f15tn/Include/OptionMemoryInstall.h
Normal file
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,89 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* AMD Memory option API.
|
||||
*
|
||||
* Contains structures and values used to control the Memory option code.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: OPTION
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef _OPTION_MEMORY_RECOVERY_H_
|
||||
#define _OPTION_MEMORY_RECOVERY_H_
|
||||
|
||||
#include "mm.h"
|
||||
#include "mn.h"
|
||||
#include "mt.h"
|
||||
|
||||
typedef BOOLEAN MEM_REC_NB_CONSTRUCTOR (
|
||||
IN OUT MEM_NB_BLOCK *NBPtr,
|
||||
IN OUT MEM_DATA_STRUCT *MemPtr,
|
||||
IN UINT8 NodeID
|
||||
);
|
||||
|
||||
typedef VOID MEM_REC_TECH_CONSTRUCTOR (
|
||||
IN OUT MEM_TECH_BLOCK *TechPtr,
|
||||
IN OUT MEM_NB_BLOCK *NBPtr
|
||||
);
|
||||
|
||||
#endif // _OPTION_MEMORY_H_
|
||||
@ -0,0 +1,419 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* Install of build option: Memory
|
||||
*
|
||||
* Contains AMD AGESA install macros and test conditions. Output is the
|
||||
* defaults tables reflecting the User's build options selection.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: Options
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef _OPTION_MEMORY_RECOVERY_INSTALL_H_
|
||||
#define _OPTION_MEMORY_RECOVERY_INSTALL_H_
|
||||
|
||||
#if (AGESA_ENTRY_INIT_RECOVERY == TRUE)
|
||||
|
||||
#if (OPTION_MEMCTLR_DR == TRUE)
|
||||
extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockDR;
|
||||
#define MEM_REC_NB_SUPPORT_DR MemRecConstructNBBlockDR,
|
||||
#else
|
||||
#define MEM_REC_NB_SUPPORT_DR
|
||||
#endif
|
||||
#if (OPTION_MEMCTLR_RB == TRUE)
|
||||
extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockRb;
|
||||
#define MEM_REC_NB_SUPPORT_RB MemRecConstructNBBlockRb,
|
||||
#else
|
||||
#define MEM_REC_NB_SUPPORT_RB
|
||||
#endif
|
||||
#if (OPTION_MEMCTLR_DA == TRUE)
|
||||
extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockDA;
|
||||
#define MEM_REC_NB_SUPPORT_DA MemRecConstructNBBlockDA,
|
||||
#else
|
||||
#define MEM_REC_NB_SUPPORT_DA
|
||||
#endif
|
||||
#if (OPTION_MEMCTLR_NI == TRUE)
|
||||
extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockNi;
|
||||
#define MEM_REC_NB_SUPPORT_NI MemRecConstructNBBlockNi,
|
||||
#else
|
||||
#define MEM_REC_NB_SUPPORT_NI
|
||||
#endif
|
||||
#if (OPTION_MEMCTLR_PH == TRUE)
|
||||
extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockPh;
|
||||
#define MEM_REC_NB_SUPPORT_PH MemRecConstructNBBlockPh,
|
||||
#else
|
||||
#define MEM_REC_NB_SUPPORT_PH
|
||||
#endif
|
||||
#if (OPTION_MEMCTLR_HY == TRUE)
|
||||
extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockHY;
|
||||
#define MEM_REC_NB_SUPPORT_HY MemRecConstructNBBlockHY,
|
||||
#else
|
||||
#define MEM_REC_NB_SUPPORT_HY
|
||||
#endif
|
||||
#if (OPTION_MEMCTLR_C32 == TRUE)
|
||||
extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockC32;
|
||||
#define MEM_REC_NB_SUPPORT_C32 MemRecConstructNBBlockC32,
|
||||
#else
|
||||
#define MEM_REC_NB_SUPPORT_C32
|
||||
#endif
|
||||
#if (OPTION_MEMCTLR_LN == TRUE)
|
||||
extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockLN;
|
||||
#define MEM_REC_NB_SUPPORT_LN MemRecConstructNBBlockLN,
|
||||
#else
|
||||
#define MEM_REC_NB_SUPPORT_LN
|
||||
#endif
|
||||
#if (OPTION_MEMCTLR_OR == TRUE)
|
||||
extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockOr;
|
||||
#define MEM_REC_NB_SUPPORT_OR MemRecConstructNBBlockOr,
|
||||
#else
|
||||
#define MEM_REC_NB_SUPPORT_OR
|
||||
#endif
|
||||
#if (OPTION_MEMCTLR_ON == TRUE)
|
||||
extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockON;
|
||||
#define MEM_REC_NB_SUPPORT_ON MemRecConstructNBBlockON,
|
||||
#else
|
||||
#define MEM_REC_NB_SUPPORT_ON
|
||||
#endif
|
||||
#if (OPTION_MEMCTLR_TN == TRUE)
|
||||
extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockTN;
|
||||
#define MEM_REC_NB_SUPPORT_TN MemRecConstructNBBlockTN,
|
||||
#else
|
||||
#define MEM_REC_NB_SUPPORT_TN
|
||||
#endif
|
||||
|
||||
MEM_REC_NB_CONSTRUCTOR* MemRecNBInstalled[] = {
|
||||
MEM_REC_NB_SUPPORT_DR
|
||||
MEM_REC_NB_SUPPORT_RB
|
||||
MEM_REC_NB_SUPPORT_DA
|
||||
MEM_REC_NB_SUPPORT_PH
|
||||
MEM_REC_NB_SUPPORT_HY
|
||||
MEM_REC_NB_SUPPORT_C32
|
||||
MEM_REC_NB_SUPPORT_LN
|
||||
MEM_REC_NB_SUPPORT_OR
|
||||
MEM_REC_NB_SUPPORT_ON
|
||||
MEM_REC_NB_SUPPORT_NI
|
||||
MEM_REC_NB_SUPPORT_TN
|
||||
NULL
|
||||
};
|
||||
|
||||
#define MEM_REC_TECH_CONSTRUCTOR_DDR2
|
||||
#if (OPTION_DDR3 == TRUE)
|
||||
extern MEM_REC_TECH_CONSTRUCTOR MemRecConstructTechBlock3;
|
||||
#define MEM_REC_TECH_CONSTRUCTOR_DDR3 MemRecConstructTechBlock3,
|
||||
#else
|
||||
#define MEM_REC_TECH_CONSTRUCTOR_DDR3
|
||||
#endif
|
||||
|
||||
MEM_REC_TECH_CONSTRUCTOR* MemRecTechInstalled[] = {
|
||||
MEM_REC_TECH_CONSTRUCTOR_DDR3
|
||||
MEM_REC_TECH_CONSTRUCTOR_DDR2
|
||||
NULL
|
||||
};
|
||||
|
||||
#if OPTION_MEMCTLR_DR
|
||||
#define PSC_REC_DR_UDIMM_DDR2
|
||||
#define PSC_REC_DR_UDIMM_DDR3 MemRecNGetPsCfgUDIMM3Nb,
|
||||
#define PSC_REC_DR_RDIMM_DDR2
|
||||
#define PSC_REC_DR_RDIMM_DDR3 MemRecNGetPsCfgRDIMM3Nb,
|
||||
#define PSC_REC_DR_SODIMM_DDR2
|
||||
#define PSC_REC_DR_SODIMM_DDR3 MemRecNGetPsCfgSODIMM3Nb,
|
||||
#endif
|
||||
#if ((OPTION_MEMCTLR_DA == TRUE) || (OPTION_MEMCTLR_Ni == TRUE) || (OPTION_MEMCTLR_PH == TRUE) || (OPTION_MEMCTLR_RB == TRUE))
|
||||
#define PSC_REC_DA_UDIMM_DDR3 MemRecNGetPsCfgUDIMM3Nb,
|
||||
#define PSC_REC_DA_SODIMM_DDR2
|
||||
#define PSC_REC_DA_SODIMM_DDR3 MemRecNGetPsCfgSODIMM3Nb,
|
||||
#endif
|
||||
#if OPTION_MEMCTLR_HY
|
||||
#define PSC_REC_HY_UDIMM_DDR3 MemRecNGetPsCfgUDIMM3Nb,
|
||||
#define PSC_REC_HY_RDIMM_DDR3 MemRecNGetPsCfgRDIMM3Nb,
|
||||
#endif
|
||||
#if OPTION_MEMCTLR_C32
|
||||
#define PSC_REC_C32_UDIMM_DDR3 MemRecNGetPsCfgUDIMM3Nb,
|
||||
#define PSC_REC_C32_RDIMM_DDR3 MemRecNGetPsCfgRDIMM3Nb,
|
||||
#endif
|
||||
#if OPTION_MEMCTLR_OR
|
||||
#define PSC_REC_OR_UDIMM_DDR3 //MemRecNGetPsCfgUDIMM3OR,
|
||||
#define PSC_REC_OR_RDIMM_DDR3 //MemRecNGetPsCfgRDIMM3OR,
|
||||
#endif
|
||||
#if OPTION_MEMCTLR_TN
|
||||
#define PSC_REC_OR_UDIMM_DDR3 //MemRecNGetPsCfgUDIMM3OR,
|
||||
#define PSC_REC_OR_RDIMM_DDR3 //MemRecNGetPsCfgRDIMM3OR,
|
||||
#endif
|
||||
|
||||
#ifndef PSC_REC_DR_UDIMM_DDR2
|
||||
#define PSC_REC_DR_UDIMM_DDR2
|
||||
#endif
|
||||
#ifndef PSC_REC_DR_UDIMM_DDR3
|
||||
#define PSC_REC_DR_UDIMM_DDR3
|
||||
#endif
|
||||
#ifndef PSC_REC_DR_RDIMM_DDR2
|
||||
#define PSC_REC_DR_RDIMM_DDR2
|
||||
#endif
|
||||
#ifndef PSC_REC_DR_RDIMM_DDR3
|
||||
#define PSC_REC_DR_RDIMM_DDR3
|
||||
#endif
|
||||
#ifndef PSC_REC_DR_SODIMM_DDR2
|
||||
#define PSC_REC_DR_SODIMM_DDR2
|
||||
#endif
|
||||
#ifndef PSC_REC_DR_SODIMM_DDR3
|
||||
#define PSC_REC_DR_SODIMM_DDR3
|
||||
#endif
|
||||
#ifndef PSC_REC_DA_UDIMM_DDR3
|
||||
#define PSC_REC_DA_UDIMM_DDR3
|
||||
#endif
|
||||
#ifndef PSC_REC_DA_SODIMM_DDR2
|
||||
#define PSC_REC_DA_SODIMM_DDR2
|
||||
#endif
|
||||
#ifndef PSC_REC_DA_SODIMM_DDR3
|
||||
#define PSC_REC_DA_SODIMM_DDR3
|
||||
#endif
|
||||
#ifndef PSC_REC_HY_UDIMM_DDR3
|
||||
#define PSC_REC_HY_UDIMM_DDR3
|
||||
#endif
|
||||
#ifndef PSC_REC_HY_RDIMM_DDR3
|
||||
#define PSC_REC_HY_RDIMM_DDR3
|
||||
#endif
|
||||
#ifndef PSC_REC_C32_UDIMM_DDR3
|
||||
#define PSC_REC_C32_UDIMM_DDR3
|
||||
#endif
|
||||
#ifndef PSC_REC_C32_RDIMM_DDR3
|
||||
#define PSC_REC_C32_RDIMM_DDR3
|
||||
#endif
|
||||
#ifndef PSC_REC_OR_UDIMM_DDR3
|
||||
#define PSC_REC_OR_UDIMM_DDR3
|
||||
#endif
|
||||
#ifndef PSC_REC_OR_RDIMM_DDR3
|
||||
#define PSC_REC_OR_RDIMM_DDR3
|
||||
#endif
|
||||
|
||||
MEM_PLATFORM_CFG* memRecPlatformTypeInstalled[] = {
|
||||
PSC_REC_DR_UDIMM_DDR2
|
||||
PSC_REC_DR_RDIMM_DDR2
|
||||
PSC_REC_DR_SODIMM_DDR2
|
||||
PSC_REC_DR_UDIMM_DDR3
|
||||
PSC_REC_DR_RDIMM_DDR3
|
||||
PSC_REC_DR_SODIMM_DDR3
|
||||
PSC_REC_DA_SODIMM_DDR2
|
||||
PSC_REC_DA_UDIMM_DDR3
|
||||
PSC_REC_DA_SODIMM_DDR3
|
||||
PSC_REC_HY_UDIMM_DDR3
|
||||
PSC_REC_HY_RDIMM_DDR3
|
||||
PSC_REC_C32_UDIMM_DDR3
|
||||
PSC_REC_C32_RDIMM_DDR3
|
||||
PSC_REC_OR_UDIMM_DDR3
|
||||
PSC_REC_OR_RDIMM_DDR3
|
||||
NULL
|
||||
};
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------
|
||||
* EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION
|
||||
*
|
||||
*
|
||||
*---------------------------------------------------------------------------------------------------
|
||||
*/
|
||||
#define MEM_PSC_REC_FLOW_BLOCK_END NULL
|
||||
#define PSC_REC_TBL_END NULL
|
||||
#define MEM_REC_PSC_FLOW_DEFTRUE (BOOLEAN (*) (MEM_NB_BLOCK*, MEM_PSC_TABLE_BLOCK *)) MemRecDefTrue
|
||||
|
||||
#if OPTION_MEMCTLR_TN
|
||||
#if OPTION_UDIMMS
|
||||
extern PSC_TBL_ENTRY RecTNDramTermTblEntU;
|
||||
#define PSC_REC_TBL_TN_UDIMM3_DRAM_TERM &RecTNDramTermTblEntU,
|
||||
extern PSC_TBL_ENTRY RecTNSAOTblEntU3;
|
||||
#define PSC_REC_TBL_TN_UDIMM3_SAO &RecTNSAOTblEntU3,
|
||||
#endif
|
||||
#if OPTION_SODIMMS
|
||||
extern PSC_TBL_ENTRY RecTNSAOTblEntSO3;
|
||||
#define PSC_REC_TBL_TN_SODIMM3_SAO &RecTNSAOTblEntSO3,
|
||||
extern PSC_TBL_ENTRY RecTNDramTermTblEntSO;
|
||||
#define PSC_REC_TBL_TN_SODIMM3_DRAM_TERM &RecTNDramTermTblEntSO,
|
||||
#endif
|
||||
extern PSC_TBL_ENTRY RecTNMR0WrTblEntry;
|
||||
extern PSC_TBL_ENTRY RecTNMR0CLTblEntry;
|
||||
extern PSC_TBL_ENTRY RecTNDdr3CKETriEnt;
|
||||
extern PSC_TBL_ENTRY RecTNOdtPatTblEnt;
|
||||
|
||||
#ifndef PSC_REC_TBL_TN_UDIMM3_DRAM_TERM
|
||||
#define PSC_REC_TBL_TN_UDIMM3_DRAM_TERM
|
||||
#endif
|
||||
#ifndef PSC_REC_TBL_TN_SODIMM3_DRAM_TERM
|
||||
#define PSC_REC_TBL_TN_SODIMM3_DRAM_TERM
|
||||
#endif
|
||||
#ifndef PSC_REC_TBL_TN_SODIMM3_SAO
|
||||
#define PSC_REC_TBL_TN_SODIMM3_SAO
|
||||
#endif
|
||||
#ifndef PSC_REC_TBL_TN_UDIMM3_SAO
|
||||
#define PSC_REC_TBL_TN_UDIMM3_SAO
|
||||
#endif
|
||||
|
||||
PSC_TBL_ENTRY* memRecPSCTblDramTermArrayTN[] = {
|
||||
PSC_REC_TBL_TN_UDIMM3_DRAM_TERM
|
||||
PSC_REC_TBL_TN_SODIMM3_DRAM_TERM
|
||||
PSC_REC_TBL_END
|
||||
};
|
||||
|
||||
PSC_TBL_ENTRY* memRecPSCTblODTPatArrayTN[] = {
|
||||
&RecTNOdtPatTblEnt,
|
||||
PSC_REC_TBL_END
|
||||
};
|
||||
|
||||
PSC_TBL_ENTRY* memRecPSCTblSAOArrayTN[] = {
|
||||
PSC_REC_TBL_TN_SODIMM3_SAO
|
||||
PSC_REC_TBL_TN_UDIMM3_SAO
|
||||
PSC_REC_TBL_END
|
||||
};
|
||||
|
||||
PSC_TBL_ENTRY* memRecPSCTblMR0WRArrayTN[] = {
|
||||
&RecTNMR0WrTblEntry,
|
||||
PSC_REC_TBL_END
|
||||
};
|
||||
|
||||
PSC_TBL_ENTRY* memRecPSCTblMR0CLArrayTN[] = {
|
||||
&RecTNMR0CLTblEntry,
|
||||
PSC_REC_TBL_END
|
||||
};
|
||||
|
||||
MEM_PSC_TABLE_BLOCK memRecPSCTblBlockTN = {
|
||||
NULL,
|
||||
(PSC_TBL_ENTRY **)&memRecPSCTblDramTermArrayTN,
|
||||
(PSC_TBL_ENTRY **)&memRecPSCTblODTPatArrayTN,
|
||||
(PSC_TBL_ENTRY **)&memRecPSCTblSAOArrayTN,
|
||||
(PSC_TBL_ENTRY **)&memRecPSCTblMR0WRArrayTN,
|
||||
(PSC_TBL_ENTRY **)&memRecPSCTblMR0CLArrayTN,
|
||||
NULL,
|
||||
NULL,
|
||||
NULL,
|
||||
NULL,
|
||||
NULL,
|
||||
NULL,
|
||||
NULL
|
||||
};
|
||||
extern MEM_PSC_FLOW MemPRecGetRttNomWr;
|
||||
#define PSC_REC_FLOW_TN_DRAM_TERM MemPRecGetRttNomWr
|
||||
extern MEM_PSC_FLOW MemPRecGetODTPattern;
|
||||
#define PSC_REC_FLOW_TN_ODT_PATTERN MemPRecGetODTPattern
|
||||
extern MEM_PSC_FLOW MemPRecGetSAO;
|
||||
#define PSC_REC_FLOW_TN_SAO MemPRecGetSAO
|
||||
extern MEM_PSC_FLOW MemPRecGetMR0WrCL;
|
||||
#define PSC_REC_FLOW_TN_MR0_WRCL MemPRecGetMR0WrCL
|
||||
|
||||
MEM_PSC_FLOW_BLOCK memRecPlatSpecFlowTN = {
|
||||
&memRecPSCTblBlockTN,
|
||||
MEM_REC_PSC_FLOW_DEFTRUE,
|
||||
PSC_REC_FLOW_TN_DRAM_TERM,
|
||||
PSC_REC_FLOW_TN_ODT_PATTERN,
|
||||
PSC_REC_FLOW_TN_SAO,
|
||||
PSC_REC_FLOW_TN_MR0_WRCL,
|
||||
MEM_REC_PSC_FLOW_DEFTRUE,
|
||||
MEM_REC_PSC_FLOW_DEFTRUE,
|
||||
MEM_REC_PSC_FLOW_DEFTRUE,
|
||||
MEM_REC_PSC_FLOW_DEFTRUE,
|
||||
MEM_REC_PSC_FLOW_DEFTRUE,
|
||||
MEM_REC_PSC_FLOW_DEFTRUE
|
||||
};
|
||||
#define MEM_PSC_REC_FLOW_BLOCK_TN &memRecPlatSpecFlowTN,
|
||||
#else
|
||||
#define MEM_PSC_REC_FLOW_BLOCK_TN
|
||||
#endif
|
||||
|
||||
MEM_PSC_FLOW_BLOCK* memRecPlatSpecFlowArray[] = {
|
||||
MEM_PSC_REC_FLOW_BLOCK_TN
|
||||
MEM_PSC_REC_FLOW_BLOCK_END
|
||||
};
|
||||
|
||||
#else
|
||||
/*---------------------------------------------------------------------------------------------------
|
||||
* DEFAULT TECHNOLOGY BLOCK
|
||||
*
|
||||
*
|
||||
*---------------------------------------------------------------------------------------------------
|
||||
*/
|
||||
MEM_TECH_CONSTRUCTOR* MemRecTechInstalled[] = { // Types of technology installed
|
||||
NULL
|
||||
};
|
||||
/*---------------------------------------------------------------------------------------------------
|
||||
* DEFAULT NORTHBRIDGE SUPPORT LIST
|
||||
*
|
||||
*
|
||||
*---------------------------------------------------------------------------------------------------
|
||||
*/
|
||||
MEM_REC_NB_CONSTRUCTOR* MemRecNBInstalled[] = {
|
||||
NULL
|
||||
};
|
||||
/*----------------------------------------------------------------------
|
||||
* DEFAULT PSCFG DEFINITIONS
|
||||
*
|
||||
*----------------------------------------------------------------------
|
||||
*/
|
||||
MEM_PLATFORM_CFG* memRecPlatformTypeInstalled[] = {
|
||||
NULL
|
||||
};
|
||||
/*----------------------------------------------------------------------
|
||||
* EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION
|
||||
*
|
||||
*----------------------------------------------------------------------
|
||||
*/
|
||||
MEM_PSC_FLOW_BLOCK* memRecPlatSpecFlowArray[] = {
|
||||
NULL
|
||||
};
|
||||
#endif
|
||||
#endif // _OPTION_MEMORY_RECOVERY_INSTALL_H_
|
||||
109
src/vendorcode/amd/agesa/f15tn/Include/OptionMmioMapInstall.h
Normal file
109
src/vendorcode/amd/agesa/f15tn/Include/OptionMmioMapInstall.h
Normal file
@ -0,0 +1,109 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* Install of build option: MMIO map manager
|
||||
*
|
||||
* Contains AMD AGESA install macros and test conditions. Output is the
|
||||
* defaults tables reflecting the User's build options selection.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: Options
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef _OPTION_MMIO_MAP_INSTALL_H_
|
||||
#define _OPTION_MMIO_MAP_INSTALL_H_
|
||||
|
||||
#include "mmioMapManager.h"
|
||||
|
||||
/* This option is designed to be included into the platform solution install
|
||||
* file. The platform solution install file will define the options status.
|
||||
* Check to validate the definition
|
||||
*/
|
||||
|
||||
#define F15_MMIO_MAP_SUPPORT
|
||||
|
||||
#if ((AGESA_ENTRY_INIT_ENV == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
|
||||
// Family 15h
|
||||
#ifdef OPTION_FAMILY15H
|
||||
#if OPTION_FAMILY15H == TRUE
|
||||
extern CONST MMIO_MAP_FAMILY_SERVICES ROMDATA F15MmioMapSupport;
|
||||
#undef F15_MMIO_MAP_SUPPORT
|
||||
#define F15_MMIO_MAP_SUPPORT {(AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , &F15MmioMapSupport},
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA MmioMapFamilyServiceArray[] =
|
||||
{
|
||||
F15_MMIO_MAP_SUPPORT
|
||||
{0, NULL}
|
||||
};
|
||||
|
||||
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA MmioMapFamilyServiceTable =
|
||||
{
|
||||
(sizeof (MmioMapFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
|
||||
&MmioMapFamilyServiceArray[0]
|
||||
};
|
||||
|
||||
#endif // _OPTION_MMIO_MAP_INSTALL_H_
|
||||
@ -0,0 +1,143 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* Install of build option: Message-Based C1e
|
||||
*
|
||||
* Contains AMD AGESA install macros and test conditions. Output is the
|
||||
* defaults tables reflecting the User's build options selection.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: Options
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef _OPTION_MSG_BASED_C1E_INSTALL_H_
|
||||
#define _OPTION_MSG_BASED_C1E_INSTALL_H_
|
||||
|
||||
#include "cpuMsgBasedC1e.h"
|
||||
|
||||
/* This option is designed to be included into the platform solution install
|
||||
* file. The platform solution install file will define the options status.
|
||||
* Check to validate the definition
|
||||
*/
|
||||
#define OPTION_MSG_BASED_C1E_FEAT
|
||||
#define F10_MSG_BASED_C1E_SUPPORT
|
||||
#define F15_OR_MSG_BASED_C1E_SUPPORT
|
||||
#if OPTION_MSG_BASED_C1E == TRUE
|
||||
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE)
|
||||
|
||||
#ifdef OPTION_FAMILY10H
|
||||
#if OPTION_FAMILY10H == TRUE
|
||||
#if OPTION_FAMILY10H_HY == TRUE
|
||||
#if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE)
|
||||
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureMsgBasedC1e;
|
||||
#undef OPTION_MSG_BASED_C1E_FEAT
|
||||
#define OPTION_MSG_BASED_C1E_FEAT &CpuFeatureMsgBasedC1e,
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef OPTION_FAMILY15H_OR
|
||||
#if OPTION_FAMILY15H_OR == TRUE
|
||||
#if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE || OPTION_AM3_SOCKET_SUPPORT == TRUE)
|
||||
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureMsgBasedC1e;
|
||||
#undef OPTION_MSG_BASED_C1E_FEAT
|
||||
#define OPTION_MSG_BASED_C1E_FEAT &CpuFeatureMsgBasedC1e,
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef OPTION_FAMILY10H
|
||||
#if OPTION_FAMILY10H == TRUE
|
||||
#if OPTION_FAMILY10H_HY == TRUE
|
||||
#if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE)
|
||||
extern CONST MSG_BASED_C1E_FAMILY_SERVICES ROMDATA F10MsgBasedC1e;
|
||||
#undef F10_MSG_BASED_C1E_SUPPORT
|
||||
#define F10_MSG_BASED_C1E_SUPPORT {AMD_FAMILY_10_HY, &F10MsgBasedC1e},
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef OPTION_FAMILY15H_OR
|
||||
#if OPTION_FAMILY15H_OR == TRUE
|
||||
#if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE || OPTION_AM3_SOCKET_SUPPORT == TRUE)
|
||||
extern CONST MSG_BASED_C1E_FAMILY_SERVICES ROMDATA F15OrMsgBasedC1e;
|
||||
#undef F15_OR_MSG_BASED_C1E_SUPPORT
|
||||
#define F15_OR_MSG_BASED_C1E_SUPPORT {AMD_FAMILY_15_OR, &F15OrMsgBasedC1e},
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA MsgBasedC1eFamilyServiceArray[] =
|
||||
{
|
||||
F10_MSG_BASED_C1E_SUPPORT
|
||||
F15_OR_MSG_BASED_C1E_SUPPORT
|
||||
{0, NULL}
|
||||
};
|
||||
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA MsgBasedC1eFamilyServiceTable =
|
||||
{
|
||||
(sizeof (MsgBasedC1eFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
|
||||
&MsgBasedC1eFamilyServiceArray[0]
|
||||
};
|
||||
#endif
|
||||
#endif
|
||||
#endif // _OPTION_MSG_BASED_C1E_INSTALL_H_
|
||||
242
src/vendorcode/amd/agesa/f15tn/Include/OptionMultiSocket.h
Normal file
242
src/vendorcode/amd/agesa/f15tn/Include/OptionMultiSocket.h
Normal file
@ -0,0 +1,242 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* AMD Multi-socket option API.
|
||||
*
|
||||
* Contains structures and values used to control the multi-socket option code.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: OPTION
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef _OPTION_MULTISOCKET_H_
|
||||
#define _OPTION_MULTISOCKET_H_
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* D E F I N I T I O N S A N D M A C R O S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* T Y P E D E F S, S T R U C T U R E S, E N U M S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/**
|
||||
* This function loops through all possible socket locations, gathering the number
|
||||
* of power management steps each populated socket requires, and returns the
|
||||
* highest number.
|
||||
*
|
||||
* @param[out] NumSystemSteps Maximum number of system steps required
|
||||
* @param[in] StdHeader Config handle for library and services
|
||||
*
|
||||
*/
|
||||
typedef VOID OPTION_MULTISOCKET_PM_STEPS (
|
||||
OUT UINT8 *NumSystemSteps,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
/**
|
||||
* This function loops through all possible socket locations, starting core 0 of
|
||||
* each populated socket to perform the passed in AP_TASK. After starting all
|
||||
* other core 0s, the BSC will perform the AP_TASK as well. This must be run by
|
||||
* the system BSC only.
|
||||
*
|
||||
* @param[in] TaskPtr Function descriptor
|
||||
* @param[in] StdHeader Config handle for library and services
|
||||
* @param[in] ConfigParams AMD entry point's CPU parameter structure
|
||||
*
|
||||
* @return The most severe error code from AP_TASK
|
||||
*
|
||||
*/
|
||||
typedef AGESA_STATUS OPTION_MULTISOCKET_PM_CORE0_TASK (
|
||||
IN VOID *TaskPtr,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader,
|
||||
IN VOID *ConfigParams
|
||||
);
|
||||
|
||||
/**
|
||||
* This function loops through all possible socket locations, comparing the
|
||||
* maximum NB frequencies to determine the slowest. This function also
|
||||
* determines if all coherent NB frequencies are equivalent.
|
||||
*
|
||||
* @param[in] NbPstate NB P-state number to check (0 = fastest)
|
||||
* @param[in] PlatformConfig Platform profile/build option config structure.
|
||||
* @param[out] SystemNbCofNumerator NB frequency numerator for the system in MHz
|
||||
* @param[out] SystemNbCofDenominator NB frequency denominator for the system
|
||||
* @param[out] SystemNbCofsMatch Whether or not all NB frequencies are equivalent
|
||||
* @param[out] NbPstateIsEnabledOnAllCPUs Whether or not NbPstate is valid on all CPUs
|
||||
* @param[in] StdHeader Config handle for library and services
|
||||
*
|
||||
* @retval TRUE At least one processor has NbPstate enabled.
|
||||
* @retval FALSE NbPstate is disabled on all CPUs
|
||||
*/
|
||||
typedef BOOLEAN OPTION_MULTISOCKET_PM_NB_COF (
|
||||
IN UINT32 NbPstate,
|
||||
IN PLATFORM_CONFIGURATION *PlatformConfig,
|
||||
OUT UINT32 *SystemNbCofNumerator,
|
||||
OUT UINT32 *SystemNbCofDenominator,
|
||||
OUT BOOLEAN *SystemNbCofsMatch,
|
||||
OUT BOOLEAN *NbPstateIsEnabledOnAllCPUs,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
/**
|
||||
* This function loops through all possible socket locations, checking whether
|
||||
* any populated sockets require NB COF VID programming.
|
||||
*
|
||||
* @param[in] StdHeader Config handle for library and services
|
||||
*
|
||||
*/
|
||||
typedef BOOLEAN OPTION_MULTISOCKET_PM_NB_COF_UPDATE (
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
/**
|
||||
* This function loops through all possible socket locations, collecting any
|
||||
* power management initialization errors that may have occurred. These errors
|
||||
* are transferred from the core 0s of the socket in which the errors occurred
|
||||
* to the BSC's heap. The BSC's heap is then searched for the most severe error
|
||||
* that occurred, and returns it. This function must be called by the BSC only.
|
||||
*
|
||||
* @param[in] StdHeader Config handle for library and services
|
||||
*
|
||||
*/
|
||||
typedef AGESA_STATUS OPTION_MULTISOCKET_PM_GET_EVENTS (
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
/**
|
||||
* This function loops through all possible socket locations and Nb Pstates,
|
||||
* comparing the NB frequencies to determine the slowest NB P0 and NB Pmin in
|
||||
* the system.
|
||||
*
|
||||
* @param[in] PlatformConfig Platform profile/build option config structure.
|
||||
* @param[out] MinSysNbFreq NB frequency numerator for the system in MHz
|
||||
* @param[out] MinP0NbFreq NB frequency numerator for P0 in MHz
|
||||
* @param[in] StdHeader Config handle for library and services
|
||||
*/
|
||||
typedef VOID OPTION_MULTISOCKET_PM_NB_MIN_COF (
|
||||
IN PLATFORM_CONFIGURATION *PlatformConfig,
|
||||
OUT UINT32 *MinSysNbFreq,
|
||||
OUT UINT32 *MinP0NbFreq,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
/**
|
||||
* This function returns the current running core's PCI Config Space address.
|
||||
*
|
||||
* @param[out] PciAddress The Processor's PCI Config Space address (Function 0, Register 0)
|
||||
* @param[in] StdHeader Header for library and services.
|
||||
*/
|
||||
typedef BOOLEAN OPTION_MULTISOCKET_GET_PCI_ADDRESS (
|
||||
OUT PCI_ADDR *PciAddress,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
/**
|
||||
* This function writes to all nodes on the executing core's socket.
|
||||
*
|
||||
* @param[in] PciAddress The Function and Register to update
|
||||
* @param[in] Mask The bitwise AND mask to apply to the current register value
|
||||
* @param[in] Data The bitwise OR mask to apply to the current register value
|
||||
* @param[in] StdHeader Header for library and services.
|
||||
*
|
||||
*/
|
||||
typedef VOID OPTION_MULTISOCKET_MODIFY_CURR_SOCKET_PCI (
|
||||
IN PCI_ADDR *PciAddress,
|
||||
IN UINT32 Mask,
|
||||
IN UINT32 Data,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
#define MULTISOCKET_STRUCT_VERSION 0x01
|
||||
|
||||
/**
|
||||
* Provide build configuration of cpu multi-socket or single socket support.
|
||||
*
|
||||
*/
|
||||
typedef struct {
|
||||
UINT16 OptMultiSocketVersion; ///< Table version
|
||||
OPTION_MULTISOCKET_PM_STEPS *GetNumberOfSystemPmSteps; ///< Method: Get number of power mgt tasks
|
||||
OPTION_MULTISOCKET_PM_CORE0_TASK *BscRunCodeOnAllSystemCore0s; ///< Method: Perform tasks on Core 0 of each processor
|
||||
OPTION_MULTISOCKET_PM_NB_COF *GetSystemNbPstateSettings; ///< Method: Find the Northbridge frequency for the specified Nb Pstate in the system.
|
||||
OPTION_MULTISOCKET_PM_NB_COF_UPDATE *GetSystemNbCofVidUpdate; ///< Method: Determine if any Northbridges in the system need to update their COF/VID.
|
||||
OPTION_MULTISOCKET_PM_GET_EVENTS *BscRetrievePmEarlyInitErrors; ///< Method: Gathers error information from all Core 0s.
|
||||
OPTION_MULTISOCKET_PM_NB_MIN_COF *GetMinNbCof; ///< Method: Get the minimum system and minimum P0 Northbridge frequency.
|
||||
OPTION_MULTISOCKET_GET_PCI_ADDRESS *GetCurrPciAddr; ///< Method: Get PCI Config Space Address for the current running core.
|
||||
OPTION_MULTISOCKET_MODIFY_CURR_SOCKET_PCI *ModifyCurrSocketPci; ///< Method: Writes to all nodes on the executing core's socket.
|
||||
} OPTION_MULTISOCKET_CONFIGURATION;
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* F U N C T I O N P R O T O T Y P E
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
|
||||
#endif // _OPTION_MULTISOCKET_H_
|
||||
@ -0,0 +1,131 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* Install of build option: Multiple Socket Support
|
||||
*
|
||||
* Contains AMD AGESA install macros and test conditions. Output is the
|
||||
* defaults tables reflecting the User's build options selection.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: Options
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef _OPTION_MULTISOCKET_INSTALL_H_
|
||||
#define _OPTION_MULTISOCKET_INSTALL_H_
|
||||
|
||||
/* This option is designed to be included into the platform solution install
|
||||
* file. The platform solution install file will define the options status.
|
||||
* Check to validate the definition
|
||||
*/
|
||||
#ifndef OPTION_MULTISOCKET
|
||||
#error BLDOPT: Option not defined: "OPTION_MULTISOCKET"
|
||||
#endif
|
||||
|
||||
#if OPTION_MULTISOCKET == TRUE
|
||||
OPTION_MULTISOCKET_PM_STEPS GetNumberOfSystemPmStepsPtrMulti;
|
||||
#define GET_NUM_PM_STEPS GetNumberOfSystemPmStepsPtrMulti
|
||||
OPTION_MULTISOCKET_PM_CORE0_TASK RunCodeOnAllSystemCore0sMulti;
|
||||
#define CORE0_PM_TASK RunCodeOnAllSystemCore0sMulti
|
||||
OPTION_MULTISOCKET_PM_NB_COF GetSystemNbCofMulti;
|
||||
#define GET_SYS_NB_COF GetSystemNbCofMulti
|
||||
OPTION_MULTISOCKET_PM_NB_COF_UPDATE GetSystemNbCofVidUpdateMulti;
|
||||
#define GET_SYS_NB_COF_UPDATE GetSystemNbCofVidUpdateMulti
|
||||
OPTION_MULTISOCKET_PM_GET_EVENTS GetEarlyPmErrorsMulti;
|
||||
#define GET_EARLY_PM_ERRORS GetEarlyPmErrorsMulti
|
||||
OPTION_MULTISOCKET_PM_NB_MIN_COF GetMinNbCofMulti;
|
||||
#define GET_MIN_NB_COF GetMinNbCofMulti
|
||||
OPTION_MULTISOCKET_GET_PCI_ADDRESS GetCurrPciAddrMulti;
|
||||
#define GET_PCI_ADDRESS GetCurrPciAddrMulti
|
||||
OPTION_MULTISOCKET_MODIFY_CURR_SOCKET_PCI ModifyCurrSocketPciMulti;
|
||||
#define MODIFY_CURR_SOCKET_PCI ModifyCurrSocketPciMulti
|
||||
#else
|
||||
OPTION_MULTISOCKET_PM_STEPS GetNumberOfSystemPmStepsPtrSingle;
|
||||
#define GET_NUM_PM_STEPS GetNumberOfSystemPmStepsPtrSingle
|
||||
OPTION_MULTISOCKET_PM_CORE0_TASK RunCodeOnAllSystemCore0sSingle;
|
||||
#define CORE0_PM_TASK RunCodeOnAllSystemCore0sSingle
|
||||
OPTION_MULTISOCKET_PM_NB_COF GetSystemNbCofSingle;
|
||||
#define GET_SYS_NB_COF GetSystemNbCofSingle
|
||||
OPTION_MULTISOCKET_PM_NB_COF_UPDATE GetSystemNbCofVidUpdateSingle;
|
||||
#define GET_SYS_NB_COF_UPDATE GetSystemNbCofVidUpdateSingle
|
||||
OPTION_MULTISOCKET_PM_GET_EVENTS GetEarlyPmErrorsSingle;
|
||||
#define GET_EARLY_PM_ERRORS GetEarlyPmErrorsSingle
|
||||
OPTION_MULTISOCKET_PM_NB_MIN_COF GetMinNbCofSingle;
|
||||
#define GET_MIN_NB_COF GetMinNbCofSingle
|
||||
OPTION_MULTISOCKET_GET_PCI_ADDRESS GetCurrPciAddrSingle;
|
||||
#define GET_PCI_ADDRESS GetCurrPciAddrSingle
|
||||
OPTION_MULTISOCKET_MODIFY_CURR_SOCKET_PCI ModifyCurrSocketPciSingle;
|
||||
#define MODIFY_CURR_SOCKET_PCI ModifyCurrSocketPciSingle
|
||||
#endif
|
||||
|
||||
/* Declare the instance of the multisocket option configuration structure */
|
||||
OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration = {
|
||||
MULTISOCKET_STRUCT_VERSION,
|
||||
GET_NUM_PM_STEPS,
|
||||
CORE0_PM_TASK,
|
||||
GET_SYS_NB_COF,
|
||||
GET_SYS_NB_COF_UPDATE,
|
||||
GET_EARLY_PM_ERRORS,
|
||||
GET_MIN_NB_COF,
|
||||
GET_PCI_ADDRESS,
|
||||
MODIFY_CURR_SOCKET_PCI
|
||||
};
|
||||
|
||||
#endif // _OPTION_MULTISOCKET_INSTALL_H_
|
||||
@ -0,0 +1,149 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* Install of build option: Preserve Mailbox
|
||||
*
|
||||
* Contains AMD AGESA install macros and test conditions. Output is the
|
||||
* defaults tables reflecting the User's build options selection.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: Options
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef _OPTION_PRESERVE_MAILBOX_INSTALL_H_
|
||||
#define _OPTION_PRESERVE_MAILBOX_INSTALL_H_
|
||||
|
||||
#include "PreserveMailbox.h"
|
||||
|
||||
/* This option is designed to be included into the platform solution install
|
||||
* file. The platform solution install file will define the options status.
|
||||
* Check to validate the definition
|
||||
*/
|
||||
#define OPTION_PRESERVE_MAILBOX_FEAT
|
||||
#define F10_PRESERVE_MAILBOX_SUPPORT
|
||||
#define F15_PRESERVE_MAILBOX_SUPPORT
|
||||
|
||||
#if ((AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE))
|
||||
#if ((OPTION_FAMILY10H == TRUE) || ((OPTION_FAMILY15H == TRUE) && ((OPTION_FAMILY15H_OR == TRUE))))
|
||||
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeaturePreserveAroundMailbox;
|
||||
#undef OPTION_PRESERVE_MAILBOX_FEAT
|
||||
#define OPTION_PRESERVE_MAILBOX_FEAT &CpuFeaturePreserveAroundMailbox,
|
||||
#endif
|
||||
#if OPTION_FAMILY10H == TRUE
|
||||
CONST PRESERVE_MAILBOX_FAMILY_REGISTER ROMDATA F10PreserveMailboxRegisters [] = {
|
||||
{
|
||||
MAKE_SBDFO (0, 0, 0, 3, 0x168),
|
||||
0x00000FFF
|
||||
},
|
||||
{
|
||||
MAKE_SBDFO (0, 0, 0, 3, 0x170),
|
||||
0x00000FFF
|
||||
},
|
||||
{
|
||||
ILLEGAL_SBDFO,
|
||||
0
|
||||
}
|
||||
};
|
||||
CONST PRESERVE_MAILBOX_FAMILY_SERVICES ROMDATA F10PreserveMailboxServices = {
|
||||
0,
|
||||
TRUE,
|
||||
(PRESERVE_MAILBOX_FAMILY_REGISTER *)&F10PreserveMailboxRegisters
|
||||
};
|
||||
#undef F10_PRESERVE_MAILBOX_SUPPORT
|
||||
#define F10_PRESERVE_MAILBOX_SUPPORT {AMD_FAMILY_10, &F10PreserveMailboxServices},
|
||||
#endif
|
||||
#if (OPTION_FAMILY15H == TRUE) && (OPTION_FAMILY15H_OR == TRUE)
|
||||
CONST PRESERVE_MAILBOX_FAMILY_REGISTER ROMDATA F15PreserveMailboxRegisters [] = {
|
||||
{
|
||||
MAKE_SBDFO (0, 0, 0, 3, 0x168),
|
||||
0x00000FFF
|
||||
},
|
||||
{
|
||||
MAKE_SBDFO (0, 0, 0, 3, 0x170),
|
||||
0x00000FFF
|
||||
},
|
||||
{
|
||||
ILLEGAL_SBDFO,
|
||||
0
|
||||
}
|
||||
};
|
||||
CONST PRESERVE_MAILBOX_FAMILY_SERVICES ROMDATA F15PreserveMailboxServices = {
|
||||
0,
|
||||
TRUE,
|
||||
(PRESERVE_MAILBOX_FAMILY_REGISTER *)&F15PreserveMailboxRegisters
|
||||
};
|
||||
#undef F15_PRESERVE_MAILBOX_SUPPORT
|
||||
#define F15_PRESERVE_MAILBOX_SUPPORT {(AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , &F15PreserveMailboxServices},
|
||||
#endif
|
||||
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PreserveMailboxFamilyServiceArray[] =
|
||||
{
|
||||
F10_PRESERVE_MAILBOX_SUPPORT
|
||||
F15_PRESERVE_MAILBOX_SUPPORT
|
||||
{0, NULL}
|
||||
};
|
||||
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PreserveMailboxFamilyServiceTable =
|
||||
{
|
||||
(sizeof (PreserveMailboxFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
|
||||
&PreserveMailboxFamilyServiceArray[0]
|
||||
};
|
||||
#endif
|
||||
|
||||
#endif // _OPTION_PRESERVE_MAILBOX_INSTALL_H_
|
||||
113
src/vendorcode/amd/agesa/f15tn/Include/OptionPsiInstall.h
Normal file
113
src/vendorcode/amd/agesa/f15tn/Include/OptionPsiInstall.h
Normal file
@ -0,0 +1,113 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* Install of build option: Power Status Indicator (PSI).
|
||||
*
|
||||
* Contains AMD AGESA install macros and test conditions. Output is the
|
||||
* defaults tables reflecting the User's build options selection.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: Options
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef _OPTION_PSI_INSTALL_H_
|
||||
#define _OPTION_PSI_INSTALL_H_
|
||||
|
||||
#include "cpuPsi.h"
|
||||
|
||||
/* This option is designed to be included into the platform solution install
|
||||
* file. The platform solution install file will define the options status.
|
||||
* Check to validate the definition
|
||||
*/
|
||||
#define OPTION_CPU_PSI_FEAT
|
||||
#define F15_TN_PSI_SUPPORT
|
||||
|
||||
#if OPTION_CPU_PSI == TRUE
|
||||
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
|
||||
// Family 15h
|
||||
#ifdef OPTION_FAMILY15H
|
||||
#if OPTION_FAMILY15H == TRUE
|
||||
#if OPTION_FAMILY15H_TN == TRUE
|
||||
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeaturePsi;
|
||||
#undef OPTION_CPU_PSI_FEAT
|
||||
#define OPTION_CPU_PSI_FEAT &CpuFeaturePsi,
|
||||
extern CONST PSI_FAMILY_SERVICES ROMDATA F15TnPsiSupport;
|
||||
#undef F15_TN_PSI_SUPPORT
|
||||
#define F15_TN_PSI_SUPPORT {AMD_FAMILY_15_TN, &F15TnPsiSupport},
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PsiFamilyServiceArray[] =
|
||||
{
|
||||
F15_TN_PSI_SUPPORT
|
||||
{0, NULL}
|
||||
};
|
||||
|
||||
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PsiFamilyServiceTable =
|
||||
{
|
||||
(sizeof (PsiFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
|
||||
&PsiFamilyServiceArray[0]
|
||||
};
|
||||
|
||||
#endif // _OPTION_PSI_INSTALL_H_
|
||||
142
src/vendorcode/amd/agesa/f15tn/Include/OptionPstate.h
Normal file
142
src/vendorcode/amd/agesa/f15tn/Include/OptionPstate.h
Normal file
@ -0,0 +1,142 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* AMD ACPI PState option API.
|
||||
*
|
||||
* Contains structures and values used to control the PStates option code.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: OPTION
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef _OPTION_PSTATE_H_
|
||||
#define _OPTION_PSTATE_H_
|
||||
|
||||
#include "cpuPstateTables.h"
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* D E F I N I T I O N S A N D M A C R O S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* T Y P E D E F S, S T R U C T U R E S, E N U M S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
typedef AGESA_STATUS OPTION_SSDT_FEATURE (
|
||||
IN AMD_CONFIG_PARAMS *StdHeader,
|
||||
IN PLATFORM_CONFIGURATION *PlatformConfig,
|
||||
IN OUT VOID **AcpiPstatePtr
|
||||
);
|
||||
|
||||
typedef UINT32 OPTION_ACPI_FEATURE (
|
||||
IN PLATFORM_CONFIGURATION *PlatformConfig,
|
||||
IN PSTATE_LEVELING *PStateLevelingBuffer,
|
||||
IN OUT VOID **AcpiPStatePtr,
|
||||
IN UINT8 LocalApicId,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
typedef AGESA_STATUS OPTION_PSTATE_GATHER (
|
||||
IN AMD_CONFIG_PARAMS *StdHeader,
|
||||
IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr
|
||||
);
|
||||
|
||||
typedef AGESA_STATUS OPTION_PSTATE_LEVELING (
|
||||
IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
#define PSTATE_STRUCT_VERSION 0x01
|
||||
|
||||
/// Indirection vectors for POST/PEI PState code
|
||||
typedef struct {
|
||||
UINT16 OptPstateVersion; ///< revision of this structure
|
||||
OPTION_PSTATE_GATHER *PstateGather; ///< vector for data gathering routine
|
||||
OPTION_PSTATE_LEVELING *PstateLeveling; ///< vector for leveling routine
|
||||
} OPTION_PSTATE_POST_CONFIGURATION;
|
||||
|
||||
/// Indirection vectors for LATE/DXE PState code
|
||||
typedef struct {
|
||||
UINT16 OptPstateVersion; ///< revision of this structure
|
||||
OPTION_SSDT_FEATURE *SsdtFeature; ///< vector for routine to generate SSDT
|
||||
OPTION_ACPI_FEATURE *PstateFeature; ///< vector for routine to generate ACPI PState Objects
|
||||
OPTION_ACPI_FEATURE *CstateFeature; ///< vector for routine to generate ACPI CState Objects
|
||||
BOOLEAN CfgPstatePpc; ///< boolean for creating _PPC method
|
||||
BOOLEAN CfgPstatePct; ///< boolean for creating _PCT method
|
||||
BOOLEAN CfgPstatePsd; ///< boolean for creating _PSD method
|
||||
BOOLEAN CfgPstatePss; ///< boolean for creating _PSS method
|
||||
BOOLEAN CfgPstateXpss; ///< boolean for creating _XPSS method
|
||||
} OPTION_PSTATE_LATE_CONFIGURATION;
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* F U N C T I O N P R O T O T Y P E
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#endif // _OPTION_PSTATE_H_
|
||||
@ -0,0 +1,112 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* Install of build option: Pstate HPC mode.
|
||||
*
|
||||
* Contains AMD AGESA install macros and test conditions. Output is the
|
||||
* defaults tables reflecting the User's build options selection.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: Options
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef _OPTION_PSTATE_HPC_MODE_INSTALL_H_
|
||||
#define _OPTION_PSTATE_HPC_MODE_INSTALL_H_
|
||||
|
||||
#include "cpuPstateHpcMode.h"
|
||||
|
||||
/* This option is designed to be included into the platform solution install
|
||||
* file. The platform solution install file will define the options status.
|
||||
* Check to validate the definition
|
||||
*/
|
||||
#define OPTION_CPU_PSTATE_HPC_MODE_FEAT
|
||||
#define F15_PSTATE_HPC_MODE_SUPPORT
|
||||
|
||||
#if (AGESA_ENTRY_INIT_POST == TRUE)
|
||||
// Family 15h
|
||||
#ifdef OPTION_FAMILY15H
|
||||
#if OPTION_FAMILY15H == TRUE
|
||||
// Orochi
|
||||
#if (OPTION_FAMILY15H_OR == TRUE)
|
||||
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeaturePstateHpcMode;
|
||||
#undef OPTION_CPU_PSTATE_HPC_MODE_FEAT
|
||||
#define OPTION_CPU_PSTATE_HPC_MODE_FEAT &CpuFeaturePstateHpcMode,
|
||||
extern CONST PSTATE_HPC_MODE_FAMILY_SERVICES ROMDATA F15PstateHpcSupport;
|
||||
#undef F15_PSTATE_HPC_MODE_SUPPORT
|
||||
#define F15_PSTATE_HPC_MODE_SUPPORT {AMD_FAMILY_15_OR, &F15PstateHpcSupport},
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PstateHpcModeFamilyServiceArray[] =
|
||||
{
|
||||
F15_PSTATE_HPC_MODE_SUPPORT
|
||||
{0, NULL}
|
||||
};
|
||||
|
||||
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PstateHpcModeFamilyServiceTable =
|
||||
{
|
||||
(sizeof (PstateHpcModeFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
|
||||
&PstateHpcModeFamilyServiceArray[0]
|
||||
};
|
||||
|
||||
#endif // _OPTION_PSTATE_HPC_MODE_INSTALL_H_
|
||||
281
src/vendorcode/amd/agesa/f15tn/Include/OptionPstateInstall.h
Normal file
281
src/vendorcode/amd/agesa/f15tn/Include/OptionPstateInstall.h
Normal file
@ -0,0 +1,281 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* Install of build option: PState
|
||||
*
|
||||
* Contains AMD AGESA install macros and test conditions. Output is the
|
||||
* defaults tables reflecting the User's build options selection.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: Options
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef _OPTION_PSTATE_INSTALL_H_
|
||||
#define _OPTION_PSTATE_INSTALL_H_
|
||||
|
||||
#include "cpuPstateTables.h"
|
||||
|
||||
/* This option is designed to be included into the platform solution install
|
||||
* file. The platform solution install file will define the options status.
|
||||
* Check to validate the definition
|
||||
*/
|
||||
|
||||
#define F10_PSTATE_SERVICE_SUPPORT
|
||||
#define F12_PSTATE_SERVICE_SUPPORT
|
||||
#define F14_PSTATE_SERVICE_SUPPORT
|
||||
#define F15_OR_PSTATE_SERVICE_SUPPORT
|
||||
#define F15_TN_PSTATE_SERVICE_SUPPORT
|
||||
|
||||
|
||||
#if ((AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE))
|
||||
//
|
||||
//Define Pstate CPU Family service
|
||||
//
|
||||
#ifdef OPTION_FAMILY10H
|
||||
#if OPTION_FAMILY10H == TRUE
|
||||
extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F10PstateServices;
|
||||
#undef F10_PSTATE_SERVICE_SUPPORT
|
||||
#define F10_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_10, &F10PstateServices},
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef OPTION_FAMILY12H
|
||||
#if OPTION_FAMILY12H == TRUE
|
||||
extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F12PstateServices;
|
||||
#undef F12_PSTATE_SERVICE_SUPPORT
|
||||
#define F12_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_12, &F12PstateServices},
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef OPTION_FAMILY14H
|
||||
#if OPTION_FAMILY14H == TRUE
|
||||
extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F14PstateServices;
|
||||
#undef F14_PSTATE_SERVICE_SUPPORT
|
||||
#define F14_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_14, &F14PstateServices},
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef OPTION_FAMILY15H
|
||||
#if OPTION_FAMILY15H == TRUE
|
||||
#ifdef OPTION_FAMILY15H_OR
|
||||
#if OPTION_FAMILY15H_OR == TRUE
|
||||
extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F15OrPstateServices;
|
||||
#undef F15_OR_PSTATE_SERVICE_SUPPORT
|
||||
#define F15_OR_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_15_OR, &F15OrPstateServices},
|
||||
#endif
|
||||
#endif
|
||||
#ifdef OPTION_FAMILY15H_TN
|
||||
#if OPTION_FAMILY15H_TN == TRUE
|
||||
extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F15TnPstateServices;
|
||||
#undef F15_TN_PSTATE_SERVICE_SUPPORT
|
||||
#define F15_TN_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_15_TN, &F15TnPstateServices},
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
//
|
||||
//Define ACPI Pstate objects.
|
||||
//
|
||||
#ifndef OPTION_ACPI_PSTATES
|
||||
#error BLDOPT: Option not defined: "OPTION_ACPI_PSTATES"
|
||||
#endif
|
||||
#if (OPTION_ACPI_PSTATES == TRUE)
|
||||
OPTION_SSDT_FEATURE GenerateSsdt;
|
||||
#define USER_SSDT_MAIN GenerateSsdt
|
||||
#ifndef OPTION_MULTISOCKET
|
||||
#error BLDOPT: Option not defined: "OPTION_MULTISOCKET"
|
||||
#endif
|
||||
|
||||
OPTION_ACPI_FEATURE CreatePStateAcpiTables;
|
||||
OPTION_PSTATE_GATHER PStateGatherMain;
|
||||
#if ((OPTION_MULTISOCKET == TRUE) && (AGESA_ENTRY_INIT_POST == TRUE))
|
||||
OPTION_PSTATE_LEVELING PStateLevelingMain;
|
||||
#define USER_PSTATE_OPTION_LEVEL PStateLevelingMain
|
||||
#else
|
||||
OPTION_PSTATE_LEVELING PStateLevelingStub;
|
||||
#define USER_PSTATE_OPTION_LEVEL PStateLevelingStub
|
||||
#endif
|
||||
#if AGESA_ENTRY_INIT_LATE == TRUE
|
||||
#define USER_PSTATE_OPTION_MAIN CreatePStateAcpiTables
|
||||
#else
|
||||
OPTION_ACPI_FEATURE CreateAcpiTablesStub;
|
||||
#define USER_PSTATE_OPTION_MAIN CreateAcpiTablesStub
|
||||
#endif
|
||||
#if AGESA_ENTRY_INIT_POST == TRUE
|
||||
#define USER_PSTATE_OPTION_GATHER PStateGatherMain
|
||||
#else
|
||||
OPTION_PSTATE_GATHER PStateGatherStub;
|
||||
#define USER_PSTATE_OPTION_GATHER PStateGatherStub
|
||||
#endif
|
||||
#if CFG_ACPI_PSTATES_PPC == TRUE
|
||||
#define USER_PSTATE_CFG_PPC TRUE
|
||||
#else
|
||||
#define USER_PSTATE_CFG_PPC FALSE
|
||||
#endif
|
||||
#if CFG_ACPI_PSTATES_PCT == TRUE
|
||||
#define USER_PSTATE_CFG_PCT TRUE
|
||||
#else
|
||||
#define USER_PSTATE_CFG_PCT FALSE
|
||||
#endif
|
||||
#if CFG_ACPI_PSTATES_PSD == TRUE
|
||||
#define USER_PSTATE_CFG_PSD TRUE
|
||||
#else
|
||||
#define USER_PSTATE_CFG_PSD FALSE
|
||||
#endif
|
||||
#if CFG_ACPI_PSTATES_PSS == TRUE
|
||||
#define USER_PSTATE_CFG_PSS TRUE
|
||||
#else
|
||||
#define USER_PSTATE_CFG_PSS FALSE
|
||||
#endif
|
||||
#if CFG_ACPI_PSTATES_XPSS == TRUE
|
||||
#define USER_PSTATE_CFG_XPSS TRUE
|
||||
#else
|
||||
#define USER_PSTATE_CFG_XPSS FALSE
|
||||
#endif
|
||||
|
||||
#if OPTION_IO_CSTATE == TRUE
|
||||
OPTION_ACPI_FEATURE CreateCStateAcpiTables;
|
||||
#define USER_CSTATE_OPTION_MAIN CreateCStateAcpiTables
|
||||
#else
|
||||
OPTION_ACPI_FEATURE CreateAcpiTablesStub;
|
||||
#define USER_CSTATE_OPTION_MAIN CreateAcpiTablesStub
|
||||
#endif
|
||||
#else
|
||||
OPTION_SSDT_FEATURE GenerateSsdtStub;
|
||||
OPTION_ACPI_FEATURE CreateAcpiTablesStub;
|
||||
OPTION_PSTATE_GATHER PStateGatherStub;
|
||||
OPTION_PSTATE_LEVELING PStateLevelingStub;
|
||||
#define USER_SSDT_MAIN GenerateSsdtStub
|
||||
#define USER_PSTATE_OPTION_MAIN CreateAcpiTablesStub
|
||||
#define USER_CSTATE_OPTION_MAIN CreateAcpiTablesStub
|
||||
#define USER_PSTATE_OPTION_GATHER PStateGatherStub
|
||||
#define USER_PSTATE_OPTION_LEVEL PStateLevelingStub
|
||||
#define USER_PSTATE_CFG_PPC FALSE
|
||||
#define USER_PSTATE_CFG_PCT FALSE
|
||||
#define USER_PSTATE_CFG_PSD FALSE
|
||||
#define USER_PSTATE_CFG_PSS FALSE
|
||||
#define USER_PSTATE_CFG_XPSS FALSE
|
||||
|
||||
// If ACPI Objects are disabled for PStates, we still need to check
|
||||
// whether ACPI Objects are enabled for CStates
|
||||
#if OPTION_IO_CSTATE == TRUE
|
||||
OPTION_SSDT_FEATURE GenerateSsdt;
|
||||
OPTION_PSTATE_GATHER PStateGatherMain;
|
||||
OPTION_ACPI_FEATURE CreateCStateAcpiTables;
|
||||
#undef USER_SSDT_MAIN
|
||||
#define USER_SSDT_MAIN GenerateSsdt
|
||||
#undef USER_PSTATE_OPTION_GATHER
|
||||
#define USER_PSTATE_OPTION_GATHER PStateGatherMain
|
||||
#undef USER_CSTATE_OPTION_MAIN
|
||||
#define USER_CSTATE_OPTION_MAIN CreateCStateAcpiTables
|
||||
#endif
|
||||
#endif
|
||||
#else
|
||||
OPTION_SSDT_FEATURE GenerateSsdtStub;
|
||||
OPTION_ACPI_FEATURE CreateAcpiTablesStub;
|
||||
OPTION_PSTATE_GATHER PStateGatherStub;
|
||||
OPTION_PSTATE_LEVELING PStateLevelingStub;
|
||||
#define USER_SSDT_MAIN GenerateSsdtStub
|
||||
#define USER_PSTATE_OPTION_MAIN CreateAcpiTablesStub
|
||||
#define USER_CSTATE_OPTION_MAIN CreateAcpiTablesStub
|
||||
#define USER_PSTATE_OPTION_GATHER PStateGatherStub
|
||||
#define USER_PSTATE_OPTION_LEVEL PStateLevelingStub
|
||||
#define USER_PSTATE_CFG_PPC FALSE
|
||||
#define USER_PSTATE_CFG_PCT FALSE
|
||||
#define USER_PSTATE_CFG_PSD FALSE
|
||||
#define USER_PSTATE_CFG_PSS FALSE
|
||||
#define USER_PSTATE_CFG_XPSS FALSE
|
||||
#endif
|
||||
|
||||
/* Declare the instance of the PSTATE option configuration structure */
|
||||
OPTION_PSTATE_POST_CONFIGURATION OptionPstatePostConfiguration = {
|
||||
PSTATE_STRUCT_VERSION,
|
||||
USER_PSTATE_OPTION_GATHER,
|
||||
USER_PSTATE_OPTION_LEVEL
|
||||
};
|
||||
|
||||
OPTION_PSTATE_LATE_CONFIGURATION OptionPstateLateConfiguration = {
|
||||
PSTATE_STRUCT_VERSION,
|
||||
USER_SSDT_MAIN,
|
||||
USER_PSTATE_OPTION_MAIN,
|
||||
USER_CSTATE_OPTION_MAIN,
|
||||
USER_PSTATE_CFG_PPC,
|
||||
USER_PSTATE_CFG_PCT,
|
||||
USER_PSTATE_CFG_PSD,
|
||||
USER_PSTATE_CFG_PSS,
|
||||
USER_PSTATE_CFG_XPSS
|
||||
};
|
||||
|
||||
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PstateCpuFamilyServiceArray[] =
|
||||
{
|
||||
F10_PSTATE_SERVICE_SUPPORT
|
||||
F12_PSTATE_SERVICE_SUPPORT
|
||||
F14_PSTATE_SERVICE_SUPPORT
|
||||
F15_OR_PSTATE_SERVICE_SUPPORT
|
||||
F15_TN_PSTATE_SERVICE_SUPPORT
|
||||
{0, NULL}
|
||||
};
|
||||
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PstateFamilyServiceTable =
|
||||
{
|
||||
(sizeof (PstateCpuFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
|
||||
&PstateCpuFamilyServiceArray[0]
|
||||
};
|
||||
#endif // _OPTION_PSTATE_INSTALL_H_
|
||||
118
src/vendorcode/amd/agesa/f15tn/Include/OptionS3ScriptInstall.h
Normal file
118
src/vendorcode/amd/agesa/f15tn/Include/OptionS3ScriptInstall.h
Normal file
@ -0,0 +1,118 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* Install of build option: S3SCRIPT
|
||||
*
|
||||
* Contains AMD AGESA install macros and test conditions. Output is the
|
||||
* defaults tables reflecting the User's build options selection.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: Options
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef _OPTION_S3SCRIPT_INSTALL_H_
|
||||
#define _OPTION_S3SCRIPT_INSTALL_H_
|
||||
|
||||
#include "S3SaveState.h"
|
||||
/* This option is designed to be included into the platform solution install
|
||||
* file. The platform solution install file will define the options status.
|
||||
* Check to validate the definition
|
||||
*/
|
||||
#ifndef OPTION_S3SCRIPT
|
||||
#define OPTION_S3SCRIPT FALSE //if not define assume PI not use script
|
||||
#endif
|
||||
|
||||
#if (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_ENV == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE)
|
||||
#if OPTION_S3SCRIPT == TRUE
|
||||
#define P_S3_SCRIPT_INIT S3ScriptInitState
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
|
||||
#if OPTION_S3SCRIPT == TRUE
|
||||
#define P_S3_SCRIPT_RESTORE S3ScriptRestoreState
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef P_S3_SCRIPT_INIT
|
||||
#define P_S3_SCRIPT_INIT S3ScriptInitStateStub
|
||||
#endif
|
||||
|
||||
#ifndef P_S3_SCRIPT_RESTORE
|
||||
#define P_S3_SCRIPT_RESTORE S3ScriptInitStateStub
|
||||
#undef GNB_S3_DISPATCH_FUNCTION_TABLE
|
||||
#endif
|
||||
|
||||
#ifndef GNB_S3_DISPATCH_FUNCTION_TABLE
|
||||
#define GNB_S3_DISPATCH_FUNCTION_TABLE
|
||||
#endif
|
||||
|
||||
/* Declare the instance of the S3SCRIPT option configuration structure */
|
||||
S3_SCRIPT_CONFIGURATION OptionS3ScriptConfiguration = {
|
||||
P_S3_SCRIPT_INIT,
|
||||
P_S3_SCRIPT_RESTORE
|
||||
};
|
||||
|
||||
S3_DISPATCH_FUNCTION_ENTRY S3DispatchFunctionTable [] = {
|
||||
GNB_S3_DISPATCH_FUNCTION_TABLE
|
||||
{0, NULL}
|
||||
};
|
||||
#endif // _OPTION_S3SCRIPT_INSTALL_H_
|
||||
123
src/vendorcode/amd/agesa/f15tn/Include/OptionSlit.h
Normal file
123
src/vendorcode/amd/agesa/f15tn/Include/OptionSlit.h
Normal file
@ -0,0 +1,123 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* AMD SLIT option API.
|
||||
*
|
||||
* Contains structures and values used to control the SLIT option code.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: OPTION
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef _OPTION_SLIT_H_
|
||||
#define _OPTION_SLIT_H_
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* D E F I N I T I O N S A N D M A C R O S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* T Y P E D E F S, S T R U C T U R E S, E N U M S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/**
|
||||
* Create the ACPI System Locality Distance Information Table.
|
||||
*
|
||||
*/
|
||||
typedef AGESA_STATUS OPTION_SLIT_FEATURE (
|
||||
IN OUT AMD_CONFIG_PARAMS *StdHeader,
|
||||
IN PLATFORM_CONFIGURATION *PlatformConfig,
|
||||
IN OUT VOID **SlitPtr
|
||||
);
|
||||
|
||||
/**
|
||||
* Clean up DRAM used during SLIT creation.
|
||||
*
|
||||
*/
|
||||
typedef AGESA_STATUS OPTION_SLIT_RELEASE_BUFFER (
|
||||
IN OUT AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
#define SLIT_STRUCT_VERSION 0x01
|
||||
|
||||
/// The Option Configuration of SLIT
|
||||
typedef struct {
|
||||
UINT16 OptSlitVersion; ///< The version number of SLIT
|
||||
OPTION_SLIT_FEATURE *SlitFeature; ///< The Option Feature of SLIT
|
||||
OPTION_SLIT_RELEASE_BUFFER *SlitReleaseBuffer; ///< Release buffer
|
||||
} OPTION_SLIT_CONFIGURATION;
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* F U N C T I O N P R O T O T Y P E
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
|
||||
#endif // _OPTION_SLIT_H_
|
||||
106
src/vendorcode/amd/agesa/f15tn/Include/OptionSlitInstall.h
Normal file
106
src/vendorcode/amd/agesa/f15tn/Include/OptionSlitInstall.h
Normal file
@ -0,0 +1,106 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* Install of build option: SLIT
|
||||
*
|
||||
* Contains AMD AGESA install macros and test conditions. Output is the
|
||||
* defaults tables reflecting the User's build options selection.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: Options
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef _OPTION_SLIT_INSTALL_H_
|
||||
#define _OPTION_SLIT_INSTALL_H_
|
||||
|
||||
/* This option is designed to be included into the platform solution install
|
||||
* file. The platform solution install file will define the options status.
|
||||
* Check to validate the definition
|
||||
*/
|
||||
#if AGESA_ENTRY_INIT_LATE == TRUE
|
||||
#ifndef OPTION_SLIT
|
||||
#error BLDOPT: Option not defined: "OPTION_SLIT"
|
||||
#endif
|
||||
#if OPTION_SLIT == TRUE
|
||||
OPTION_SLIT_FEATURE GetAcpiSlitMain;
|
||||
OPTION_SLIT_RELEASE_BUFFER ReleaseSlitBuffer;
|
||||
#define USER_SLIT_OPTION GetAcpiSlitMain
|
||||
#define USER_SLIT_RELEASE_BUFFER ReleaseSlitBuffer
|
||||
#else
|
||||
OPTION_SLIT_FEATURE GetAcpiSlitStub;
|
||||
OPTION_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub;
|
||||
#define USER_SLIT_OPTION GetAcpiSlitStub
|
||||
#define USER_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub
|
||||
#endif
|
||||
#else
|
||||
OPTION_SLIT_FEATURE GetAcpiSlitStub;
|
||||
OPTION_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub;
|
||||
#define USER_SLIT_OPTION GetAcpiSlitStub
|
||||
#define USER_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub
|
||||
#endif
|
||||
/* Declare the instance of the SLIT option configuration structure */
|
||||
OPTION_SLIT_CONFIGURATION OptionSlitConfiguration = {
|
||||
SLIT_STRUCT_VERSION,
|
||||
USER_SLIT_OPTION,
|
||||
USER_SLIT_RELEASE_BUFFER
|
||||
};
|
||||
|
||||
#endif // _OPTION_SLIT_INSTALL_H_
|
||||
109
src/vendorcode/amd/agesa/f15tn/Include/OptionSrat.h
Normal file
109
src/vendorcode/amd/agesa/f15tn/Include/OptionSrat.h
Normal file
@ -0,0 +1,109 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* AMD SRAT option API.
|
||||
*
|
||||
* Contains structures and values used to control the SRAT option code.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: OPTION
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef _OPTION_SRAT_H_
|
||||
#define _OPTION_SRAT_H_
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* D E F I N I T I O N S A N D M A C R O S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* T Y P E D E F S, S T R U C T U R E S, E N U M S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
typedef AGESA_STATUS OPTION_SRAT_FEATURE (
|
||||
IN OUT AMD_CONFIG_PARAMS *StdHeader,
|
||||
IN OUT VOID **SratPtr
|
||||
);
|
||||
|
||||
#define SRAT_STRUCT_VERSION 0x01
|
||||
|
||||
/// The Option Configuration of SRAT
|
||||
typedef struct {
|
||||
UINT16 OptSratVersion; ///< The version number of SRAT
|
||||
OPTION_SRAT_FEATURE *SratFeature; ///< The Option Feature of SRAT
|
||||
} OPTION_SRAT_CONFIGURATION;
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* F U N C T I O N P R O T O T Y P E
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
|
||||
#endif // _OPTION_SRAT_H_
|
||||
100
src/vendorcode/amd/agesa/f15tn/Include/OptionSratInstall.h
Normal file
100
src/vendorcode/amd/agesa/f15tn/Include/OptionSratInstall.h
Normal file
@ -0,0 +1,100 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* Install of build option: SRAT
|
||||
*
|
||||
* Contains AMD AGESA install macros and test conditions. Output is the
|
||||
* defaults tables reflecting the User's build options selection.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: Options
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef _OPTION_SRAT_INSTALL_H_
|
||||
#define _OPTION_SRAT_INSTALL_H_
|
||||
|
||||
/* This option is designed to be included into the platform solution install
|
||||
* file. The platform solution install file will define the options status.
|
||||
* Check to validate the definition
|
||||
*/
|
||||
#if AGESA_ENTRY_INIT_LATE == TRUE
|
||||
#ifndef OPTION_SRAT
|
||||
#error BLDOPT: Option not defined: "OPTION_SRAT"
|
||||
#endif
|
||||
#if OPTION_SRAT == TRUE
|
||||
OPTION_SRAT_FEATURE GetAcpiSratMain;
|
||||
#define USER_SRAT_OPTION GetAcpiSratMain
|
||||
#else
|
||||
OPTION_SRAT_FEATURE GetAcpiSratStub;
|
||||
#define USER_SRAT_OPTION GetAcpiSratStub
|
||||
#endif
|
||||
#else
|
||||
OPTION_SRAT_FEATURE GetAcpiSratStub;
|
||||
#define USER_SRAT_OPTION GetAcpiSratStub
|
||||
#endif
|
||||
|
||||
/* Declare the instance of the WHEA option configuration structure */
|
||||
OPTION_SRAT_CONFIGURATION OptionSratConfiguration = {
|
||||
SRAT_STRUCT_VERSION,
|
||||
USER_SRAT_OPTION
|
||||
};
|
||||
|
||||
#endif // _OPTION_WHEA_INSTALL_H_
|
||||
107
src/vendorcode/amd/agesa/f15tn/Include/OptionSwC1eInstall.h
Normal file
107
src/vendorcode/amd/agesa/f15tn/Include/OptionSwC1eInstall.h
Normal file
@ -0,0 +1,107 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* Install of build option: SW C1e
|
||||
*
|
||||
* Contains AMD AGESA install macros and test conditions. Output is the
|
||||
* defaults tables reflecting the User's build options selection.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: Options
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef _OPTION_SW_C1E_INSTALL_H_
|
||||
#define _OPTION_SW_C1E_INSTALL_H_
|
||||
|
||||
#include "cpuSwC1e.h"
|
||||
|
||||
/* This option is designed to be included into the platform solution install
|
||||
* file. The platform solution install file will define the options status.
|
||||
* Check to validate the definition
|
||||
*/
|
||||
#define OPTION_SW_C1E_FEAT
|
||||
#define F10_SW_C1E_SUPPORT
|
||||
#if AGESA_ENTRY_INIT_EARLY == TRUE
|
||||
#ifdef OPTION_FAMILY10H
|
||||
#if OPTION_FAMILY10H == TRUE
|
||||
#if (OPTION_FAMILY10H_BL == TRUE) || (OPTION_FAMILY10H_DA == TRUE) || (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_PH == TRUE)
|
||||
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureSwC1e;
|
||||
#undef OPTION_SW_C1E_FEAT
|
||||
#define OPTION_SW_C1E_FEAT &CpuFeatureSwC1e,
|
||||
extern CONST SW_C1E_FAMILY_SERVICES ROMDATA F10SwC1e;
|
||||
#undef F10_SW_C1E_SUPPORT
|
||||
#define F10_SW_C1E_SUPPORT {(AMD_FAMILY_10_BL | AMD_FAMILY_10_DA | AMD_FAMILY_10_RB | AMD_FAMILY_10_PH), &F10SwC1e},
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA SwC1eFamilyServiceArray[] =
|
||||
{
|
||||
F10_SW_C1E_SUPPORT
|
||||
{0, NULL}
|
||||
};
|
||||
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA SwC1eFamilyServiceTable =
|
||||
{
|
||||
(sizeof (SwC1eFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
|
||||
&SwC1eFamilyServiceArray[0]
|
||||
};
|
||||
#endif
|
||||
|
||||
#endif // _OPTION_SW_C1E_INSTALL_H_
|
||||
110
src/vendorcode/amd/agesa/f15tn/Include/OptionWhea.h
Normal file
110
src/vendorcode/amd/agesa/f15tn/Include/OptionWhea.h
Normal file
@ -0,0 +1,110 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* AMD WHEA option API.
|
||||
*
|
||||
* Contains structures and values used to control the WHEA option code.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: OPTION
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef _OPTION_WHEA_H_
|
||||
#define _OPTION_WHEA_H_
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* D E F I N I T I O N S A N D M A C R O S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* T Y P E D E F S, S T R U C T U R E S, E N U M S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
typedef AGESA_STATUS OPTION_WHEA_FEATURE (
|
||||
IN OUT AMD_CONFIG_PARAMS *StdHeader,
|
||||
IN OUT VOID **WheaMcePtr,
|
||||
IN OUT VOID **WheaCmcPtr
|
||||
);
|
||||
|
||||
#define WHEA_STRUCT_VERSION 0x01
|
||||
|
||||
/// The Option Configuration of WHEA
|
||||
typedef struct {
|
||||
UINT16 OptWheaVersion; ///< The version number of WHEA
|
||||
OPTION_WHEA_FEATURE *WheaFeature; ///< The Option Feature of WHEA
|
||||
} OPTION_WHEA_CONFIGURATION;
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* F U N C T I O N P R O T O T Y P E
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
|
||||
#endif // _OPTION_WHEA_H_
|
||||
101
src/vendorcode/amd/agesa/f15tn/Include/OptionWheaInstall.h
Normal file
101
src/vendorcode/amd/agesa/f15tn/Include/OptionWheaInstall.h
Normal file
@ -0,0 +1,101 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* Install of build option: WHEA
|
||||
*
|
||||
* Contains AMD AGESA install macros and test conditions. Output is the
|
||||
* defaults tables reflecting the User's build options selection.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: Options
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef _OPTION_WHEA_INSTALL_H_
|
||||
#define _OPTION_WHEA_INSTALL_H_
|
||||
|
||||
/* This option is designed to be included into the platform solution install
|
||||
* file. The platform solution install file will define the options status.
|
||||
* Check to validate the definition
|
||||
*/
|
||||
#if AGESA_ENTRY_INIT_LATE == TRUE
|
||||
#ifndef OPTION_WHEA
|
||||
#error BLDOPT: Option not defined: "OPTION_WHEA"
|
||||
#endif
|
||||
#if OPTION_WHEA == TRUE
|
||||
OPTION_WHEA_FEATURE GetAcpiWheaMain;
|
||||
#define USER_WHEA_OPTION GetAcpiWheaMain
|
||||
#else
|
||||
OPTION_WHEA_FEATURE GetAcpiWheaStub;
|
||||
#define USER_WHEA_OPTION GetAcpiWheaStub
|
||||
#endif
|
||||
|
||||
#else
|
||||
OPTION_WHEA_FEATURE GetAcpiWheaStub;
|
||||
#define USER_WHEA_OPTION GetAcpiWheaStub
|
||||
#endif
|
||||
|
||||
/* Declare the instance of the WHEA option configuration structure */
|
||||
OPTION_WHEA_CONFIGURATION OptionWheaConfiguration = {
|
||||
WHEA_STRUCT_VERSION,
|
||||
USER_WHEA_OPTION
|
||||
};
|
||||
|
||||
#endif // _OPTION_WHEA_INSTALL_H_
|
||||
124
src/vendorcode/amd/agesa/f15tn/Include/Options.h
Normal file
124
src/vendorcode/amd/agesa/f15tn/Include/Options.h
Normal file
@ -0,0 +1,124 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* AGESA options structures
|
||||
*
|
||||
* Contains options control structures for the AGESA build options
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: Core
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
|
||||
#ifndef _OPTIONS_H_
|
||||
#define _OPTIONS_H_
|
||||
|
||||
/**
|
||||
* Provide topology limits for loops and runtime, based on supported families.
|
||||
*/
|
||||
typedef struct {
|
||||
UINT32 PlatformNumberOfSockets; ///< The limit to the number of processors based on
|
||||
///< supported families and other build options.
|
||||
UINT32 PlatformNumberOfModules; ///< The limit to the number of modules in a processor, based
|
||||
///< on supported families.
|
||||
} OPTIONS_CONFIG_TOPOLOGY;
|
||||
|
||||
/**
|
||||
* Dispatch Table.
|
||||
*
|
||||
* The push high dispatcher uses this table to find what entries are currently in the build image.
|
||||
*/
|
||||
typedef struct {
|
||||
UINT32 FunctionId; ///< The function id specified.
|
||||
IMAGE_ENTRY EntryPoint; ///< The corresponding entry point to call.
|
||||
} DISPATCH_TABLE;
|
||||
|
||||
#ifdef BLDCFG_PLATFORM_POWER_POLICY_MODE
|
||||
#define CFG_PLATFORM_POWER_POLICY_MODE (BLDCFG_PLATFORM_POWER_POLICY_MODE)
|
||||
#else
|
||||
#define CFG_PLATFORM_POWER_POLICY_MODE (Performance)
|
||||
#endif
|
||||
|
||||
#ifdef BLDCFG_PCI_MMIO_BASE
|
||||
#define CFG_PCI_MMIO_BASE (BLDCFG_PCI_MMIO_BASE)
|
||||
#else
|
||||
#define CFG_PCI_MMIO_BASE (0)
|
||||
#endif
|
||||
|
||||
#ifdef BLDCFG_PCI_MMIO_SIZE
|
||||
#define CFG_PCI_MMIO_SIZE (BLDCFG_PCI_MMIO_SIZE)
|
||||
#else
|
||||
#define CFG_PCI_MMIO_SIZE (0)
|
||||
#endif
|
||||
|
||||
#ifdef BLDCFG_AP_MTRR_SETTINGS_LIST
|
||||
#define CFG_AP_MTRR_SETTINGS_LIST (BLDCFG_AP_MTRR_SETTINGS_LIST)
|
||||
#else
|
||||
#define CFG_AP_MTRR_SETTINGS_LIST (NULL)
|
||||
#endif
|
||||
|
||||
#ifdef BLDCFG_IOMMU_EXCLUSION_RANGE_LIST
|
||||
#define CFG_IOMMU_EXCLUSION_RANGE_LIST (BLDCFG_IOMMU_EXCLUSION_RANGE_LIST)
|
||||
#else
|
||||
#define CFG_IOMMU_EXCLUSION_RANGE_LIST (NULL)
|
||||
#endif
|
||||
|
||||
#endif // _OPTIONS_H_
|
||||
136
src/vendorcode/amd/agesa/f15tn/Include/OptionsHt.h
Normal file
136
src/vendorcode/amd/agesa/f15tn/Include/OptionsHt.h
Normal file
@ -0,0 +1,136 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* AMD HyperTransport option API.
|
||||
*
|
||||
* Contains option pre-compile logic. This file is used by the options
|
||||
* installer and internally by the HT code initializers.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: OPTION
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef _OPTION_HT_H_
|
||||
#define _OPTION_HT_H_
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* D E F I N I T I O N S A N D M A C R O S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* T Y P E D E F S, S T R U C T U R E S, E N U M S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/**
|
||||
* Provide HT build option results
|
||||
*/
|
||||
typedef struct {
|
||||
CONST BOOLEAN IsUsingRecoveryHt; ///< Manual BUID Swap List processing should assume that HT Recovery was used.
|
||||
CONST BOOLEAN IsSetHtCrcFlood; ///< Enable setting of HT CRC Flood.
|
||||
///< Build-time only customizable - @BldCfgItem{BLDCFG_SET_HTCRC_SYNC_FLOOD}
|
||||
CONST BOOLEAN IsUsingUnitIdClumping; ///< Enable automatically HT Spec compliant Unit Id Clumping.
|
||||
///< Build-time only customizable - @BldCfgItem{BLDCFG_USE_UNIT_ID_CLUMPING}
|
||||
CONST AMD_HT_INTERFACE *HtOptionPlatformDefaults; ///< A set of build time options for HT constructor.
|
||||
CONST VOID *HtOptionInternalInterface; ///< Use this internal interface initializer.
|
||||
CONST VOID *HtOptionInternalFeatures; ///< Use this internal feature set initializer.
|
||||
CONST VOID *HtOptionFamilyNorthbridgeList; ///< Use this list of northbridge initializers.
|
||||
CONST UINT8 *CONST *HtOptionBuiltinTopologies; ///< Use this list of built-in topologies.
|
||||
} OPTION_HT_CONFIGURATION;
|
||||
|
||||
typedef AGESA_STATUS
|
||||
F_OPTION_HT_INIT_RESET (
|
||||
IN AMD_CONFIG_PARAMS *StdHeader,
|
||||
IN AMD_HT_RESET_INTERFACE *AmdHtResetInterface
|
||||
);
|
||||
|
||||
typedef F_OPTION_HT_INIT_RESET *PF_OPTION_HT_INIT_RESET;
|
||||
|
||||
typedef AGESA_STATUS
|
||||
F_OPTION_HT_RESET_CONSTRUCTOR (
|
||||
IN AMD_CONFIG_PARAMS *StdHeader,
|
||||
IN AMD_HT_RESET_INTERFACE *AmdHtResetInterface
|
||||
);
|
||||
|
||||
typedef F_OPTION_HT_RESET_CONSTRUCTOR *PF_OPTION_HT_RESET_CONSTRUCTOR;
|
||||
|
||||
/**
|
||||
* Provide HT reset initialization build option results
|
||||
*/
|
||||
typedef struct {
|
||||
PF_OPTION_HT_INIT_RESET HtInitReset; ///< Method: HT reset initialization.
|
||||
PF_OPTION_HT_RESET_CONSTRUCTOR HtResetConstructor; ///< Method: HT reset initialization.
|
||||
} OPTION_HT_INIT_RESET;
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* F U N C T I O N P R O T O T Y P E
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#endif // _OPTION_HT_H_
|
||||
402
src/vendorcode/amd/agesa/f15tn/Include/OptionsPage.h
Normal file
402
src/vendorcode/amd/agesa/f15tn/Include/OptionsPage.h
Normal file
@ -0,0 +1,402 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* Create outline and references for Build Configuration and Options Component mainpage documentation.
|
||||
*
|
||||
* Design guides, maintenance guides, and general documentation, are
|
||||
* collected using this file onto the documentation mainpage.
|
||||
* This file contains doxygen comment blocks, only.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: Documentation
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*
|
||||
*/
|
||||
/*
|
||||
******************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/**
|
||||
* @page optionmain Build Configuration and Options Documentation
|
||||
*
|
||||
* Additional documentation for the Build Configuration and Options component consists of
|
||||
*
|
||||
* - Introduction and Overview to Build Options
|
||||
* - @subpage platforminstall "Platform Build Options"
|
||||
* - @subpage bldcfg "Build Configuration Item Cross Reference"
|
||||
* - @subpage examplecustomizations "Customization Examples"
|
||||
* - Maintenance Guides:
|
||||
* - For debug of the Options system, use compiler options
|
||||
* @n <tt> /P /EP /C /FAs </tt> @n
|
||||
* PreProcessor output is produced in an .i file in the directory where the project
|
||||
* file is located.
|
||||
* - Design Guides:
|
||||
* - add here >>>
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
* @page platforminstall Platform Build Options.
|
||||
*
|
||||
* Build options are boolean constants. The purpose of build options is to remove code
|
||||
* from the build to reduce the overall code size present in the ROM image. Unless
|
||||
* otherwise specified, the default action is to include all options. If a build option is
|
||||
* not specifically listed as disabled, then it is included into the build.
|
||||
*
|
||||
* The documented build options are imported from a user controlled file for
|
||||
* processing. The build options for all platform solutions are listed below:
|
||||
*
|
||||
* @anchor BLDOPT_REMOVE_UDIMMS_SUPPORT
|
||||
* @li @e BLDOPT_REMOVE_UDIMMS_SUPPORT @n
|
||||
* If unbuffered DIMMs are NOT expected to be required in the system, the code that
|
||||
* handles unbuffered DIMMs can be removed from the build.
|
||||
*
|
||||
* @anchor BLDOPT_REMOVE_RDIMMS_SUPPORT
|
||||
* @li @e BLDOPT_REMOVE_RDIMMS_SUPPORT @n
|
||||
* If registered DIMMs are NOT expected to be required in the system, the code
|
||||
* that handles registered DIMMs can be removed from the build.
|
||||
*
|
||||
* @anchor BLDOPT_REMOVE_LRDIMMS_SUPPORT
|
||||
* @li @e BLDOPT_REMOVE_LRDIMMS_SUPPORT @n
|
||||
* If Load Reduced DIMMs are NOT expected to be required in the system, the code
|
||||
* that handles Load Reduced DIMMs can be removed from the build.
|
||||
*
|
||||
* @note The above three options operate independently from each other; however, at
|
||||
* least one of the unbuffered , registered or load reduced DIMM options must be present in the build.
|
||||
*
|
||||
* @anchor BLDOPT_REMOVE_ECC_SUPPORT
|
||||
* @li @e BLDOPT_REMOVE_ECC_SUPPORT @n
|
||||
* Use this option to remove the code for Error Checking & Correction.
|
||||
*
|
||||
* @anchor BLDOPT_REMOVE_BANK_INTERLEAVE
|
||||
* @li @e BLDOPT_REMOVE_BANK_INTERLEAVE @n
|
||||
* Interleaving is a mechanism to do performance fine tuning. This option
|
||||
* interleaves memory between banks on a DIMM.
|
||||
*
|
||||
* @anchor BLDOPT_REMOVE_DCT_INTERLEAVE
|
||||
* @li @e BLDOPT_REMOVE_DCT_INTERLEAVE @n
|
||||
* Interleaving is a mechanism to do performance fine tuning. This option
|
||||
* interleaves memory from two DRAM controllers.
|
||||
*
|
||||
* @anchor BLDOPT_REMOVE_NODE_INTERLEAVE
|
||||
* @li @e BLDOPT_REMOVE_NODE_INTERLEAVE @n
|
||||
* Interleaving is a mechanism to do performance fine tuning. This option
|
||||
* interleaves memory from two HyperTransport nodes.
|
||||
*
|
||||
* @anchor BLDOPT_REMOVE_PARALLEL_TRAINING
|
||||
* @li @e BLDOPT_REMOVE_PARALLEL_TRAINING @n
|
||||
* For multi-socket systems, training memory in parallel can reduce the time
|
||||
* needed to boot.
|
||||
*
|
||||
* @anchor BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT
|
||||
* @li @e BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT @n
|
||||
* Online Spare support is removed by this option.
|
||||
*
|
||||
* @anchor BLDOPT_REMOVE_MULTISOCKET_SUPPORT
|
||||
* @li @e BLDOPT_REMOVE_MULTISOCKET_SUPPORT @n
|
||||
* Many systems use only a single socket and may benefit in code space to remove
|
||||
* this code. However, certain processors have multiple HyperTransport nodes
|
||||
* within a single socket. For these processors, the multi-node support is
|
||||
* required and this option has no effect.
|
||||
*
|
||||
* @anchor BLDOPT_REMOVE_ACPI_PSTATES
|
||||
* @li @e BLDOPT_REMOVE_ACPI_PSTATES @n
|
||||
* This option removes the code that generates the ACPI tables used in power
|
||||
* management.
|
||||
*
|
||||
* @anchor BLDCFG_PSTATE_HPC_MODE
|
||||
* @li @e BLDCFG_PSTATE_HPC_MODE @n
|
||||
* This option enables PStates high performance computing mode (HPC mode)
|
||||
*
|
||||
*
|
||||
* @anchor BLDOPT_REMOVE_SRAT
|
||||
* @li @e BLDOPT_REMOVE_SRAT @n
|
||||
* This option removes the code that generates the SRAT tables used in performance
|
||||
* tuning.
|
||||
*
|
||||
* @anchor BLDOPT_REMOVE_SLIT
|
||||
* @li @e BLDOPT_REMOVE_SLIT @n
|
||||
* This option removes the code that generates the SLIT tables used in performance
|
||||
* tuning.
|
||||
*
|
||||
* @anchor BLDOPT_REMOVE_WHEA
|
||||
* @li @e BLDOPT_REMOVE_WHEA @n
|
||||
* This option removes the code that generates the WHEA tables used in error
|
||||
* handling and reporting.
|
||||
*
|
||||
* @anchor BLDOPT_REMOVE_DMI
|
||||
* @li @e BLDOPT_REMOVE_DMI @n
|
||||
* This option removes the code that generates the DMI tables used in system
|
||||
* management.
|
||||
*
|
||||
* @anchor BLDOPT_REMOVE_DQS_TRAINING
|
||||
* @li @e BLDOPT_REMOVE_DQS_TRAINING @n
|
||||
* This option removes the code used in memory performance tuning.
|
||||
*
|
||||
*
|
||||
* @anchor BLDOPT_REMOVE_HT_ASSIST
|
||||
* @li @e BLDOPT_REMOVE_HT_ASSIST @n
|
||||
* This option removes the code which implements the HT Assist feature.
|
||||
*
|
||||
* @anchor BLDOPT_REMOVE_ATM_MODE
|
||||
* @li @e BLDOPT_REMOVE_ATM_MODE @n
|
||||
* This option removes the code which implements the ATM feature.
|
||||
*
|
||||
* @anchor BLDOPT_REMOVE_MSG_BASED_C1E
|
||||
* @li @e BLDOPT_REMOVE_MSG_BASED_C1E @n
|
||||
* This option removes the code which implements the Message Based C1e feature.
|
||||
*
|
||||
* @anchor BLDOPT_REMOVE_C6_STATE
|
||||
* @li @e BLDOPT_REMOVE_C6_STATE @n
|
||||
* This option removes the code which implements the C6 C-state feature.
|
||||
*
|
||||
* @anchor BLDOPT_REMOVE_MEM_RESTORE_SUPPORT
|
||||
* @li @e BLDOPT_REMOVE_MEM_RESTORE_SUPPORT @n
|
||||
* This option removes the memory context restore feature.
|
||||
*
|
||||
* @anchor BLDOPT_REMOVE_FAMILY_10_SUPPORT
|
||||
* @li @e BLDOPT_REMOVE_FAMILY_10_SUPPORT @n
|
||||
* If the package contains support for family 10h processors, remove that support.
|
||||
*
|
||||
* @anchor BLDOPT_REMOVE_FAMILY_12_SUPPORT
|
||||
* @li @e BLDOPT_REMOVE_FAMILY_12_SUPPORT @n
|
||||
* If the package contains support for family 10h processors, remove that support.
|
||||
*
|
||||
* @anchor BLDOPT_REMOVE_FAMILY_14_SUPPORT
|
||||
* @li @e BLDOPT_REMOVE_FAMILY_14_SUPPORT @n
|
||||
* If the package contains support for family 14h processors, remove that support.
|
||||
*
|
||||
* @anchor BLDOPT_REMOVE_FAMILY_15_SUPPORT
|
||||
* @li @e BLDOPT_REMOVE_FAMILY_15_SUPPORT @n
|
||||
* If the package contains support for family 15h processors, remove that support.
|
||||
*
|
||||
* @anchor BLDOPT_REMOVE_AM3_SOCKET_SUPPORT
|
||||
* @li @e BLDOPT_REMOVE_AM3_SOCKET_SUPPORT @n
|
||||
* This option removes the code which implements support for processors packaged for AM3 sockets.
|
||||
*
|
||||
* @anchor BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT
|
||||
* @li @e BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT @n
|
||||
* This option removes the code which implements support for processors packaged for ASB2 sockets.
|
||||
*
|
||||
* @anchor BLDOPT_REMOVE_C32_SOCKET_SUPPORT
|
||||
* @li @e BLDOPT_REMOVE_C32_SOCKET_SUPPORT @n
|
||||
* This option removes the code which implements support for processors packaged for C32 sockets.
|
||||
*
|
||||
* @anchor BLDOPT_REMOVE_FM1_SOCKET_SUPPORT
|
||||
* @li @e BLDOPT_REMOVE_FM1_SOCKET_SUPPORT @n
|
||||
* This option removes the code which implements support for processors packaged for FM1 sockets.
|
||||
*
|
||||
* @anchor BLDOPT_REMOVE_FP1_SOCKET_SUPPORT
|
||||
* @li @e BLDOPT_REMOVE_FP1_SOCKET_SUPPORT @n
|
||||
* This option removes the code which implements support for processors packaged for FP1 sockets.
|
||||
*
|
||||
* @anchor BLDOPT_REMOVE_FS1_SOCKET_SUPPORT
|
||||
* @li @e BLDOPT_REMOVE_FS1_SOCKET_SUPPORT @n
|
||||
* This option removes the code which implements support for processors packaged for FS1 sockets.
|
||||
*
|
||||
* @anchor BLDOPT_REMOVE_FT1_SOCKET_SUPPORT
|
||||
* @li @e BLDOPT_REMOVE_FT1_SOCKET_SUPPORT @n
|
||||
* This option removes the code which implements support for processors packaged for FT1 sockets.
|
||||
*
|
||||
* @anchor BLDOPT_REMOVE_G34_SOCKET_SUPPORT
|
||||
* @li @e BLDOPT_REMOVE_G34_SOCKET_SUPPORT @n
|
||||
* This option removes the code which implements support for processors packaged for G34 sockets.
|
||||
*
|
||||
* @anchor BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT
|
||||
* @li @e BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT @n
|
||||
* This option removes the code which implements support for processors packaged for S1G3 sockets.
|
||||
*
|
||||
* @anchor BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT
|
||||
* @li @e BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT @n
|
||||
* This option removes the code which implements support for processors packaged for S1G4 sockets.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @page examplecustomizations Customization Examples
|
||||
*
|
||||
* The Addendum \<plat\>Options.c file for each platform contains the minimum required
|
||||
* customizations for that platform. That is, it contains settings which would be needed
|
||||
* to boot a SimNow! bsd for that platform.
|
||||
* However, each individual product based on that platform will have customizations necessary for
|
||||
* that hardware. Since the actual customizations needed vary so much, they are not included in
|
||||
* the \<plat\>Options.c. This section provides examples of useful customizations that you can use or
|
||||
* modify to suit your needs.
|
||||
*
|
||||
* @par
|
||||
*
|
||||
* Source for the examples shown can be found at Addendum\\Examples. @n
|
||||
*
|
||||
* - @ref DeemphasisExamples "Deemphasis List Examples"
|
||||
* - @ref FrequencyLimitExamples "Frequency Limit Examples"
|
||||
* - @ref PerfPerWattHt "A performance-per-watt optimization Example"
|
||||
*
|
||||
* @anchor DeemphasisExamples
|
||||
* @par Deemphasis List Examples
|
||||
*
|
||||
* These examples customize PLATFORM_CONFIGURATION.PlatformDeemphasisList.
|
||||
* Source for the deemphasis list examples can be found in DeemphasisExamples.c. @n
|
||||
* @dontinclude DeemphasisExamples.c
|
||||
* <ul>
|
||||
* <li>
|
||||
* The following deemphasis list provides an example for a 2P MCM Max Performance configuration.
|
||||
* High Speed HT frequencies are supported. There is only one non-coherent chain. Note the technique of
|
||||
* putting specified link matches before all uses of match any. It often works well to specify the non-coherent links
|
||||
* and use match any for the coherent links.
|
||||
* @skip DinarDeemphasisList
|
||||
* @until {
|
||||
* The non-coherent chain can run up to 2600 MHz. The chain is located on Socket 0, package Link 2.
|
||||
* @until {
|
||||
* @line }
|
||||
* @line {
|
||||
* @line }
|
||||
* The coherent links can run up to 3200 MHz.
|
||||
* @until HT_FREQUENCY_MAX
|
||||
* @line }
|
||||
* end of list:
|
||||
* @until }
|
||||
* Make this list the build time customized deemphasis list.
|
||||
* @line define
|
||||
*
|
||||
* </li><li>
|
||||
*
|
||||
* The following deemphasis list provides an example for a 4P MCM Max Performance configuration.
|
||||
* This system has a backplane with connectors for CPU cards and an IO board. So trace lengths are long.
|
||||
* There can be one to four IO Chains, depending on the IO board.
|
||||
* @skipline DoubloonDeemphasisList
|
||||
* @until DoubloonDeemphasisList
|
||||
*
|
||||
* </li><li>
|
||||
*
|
||||
* The following deemphasis list further illustrates complex coherent system deemphasis. This is the same
|
||||
* Dinar system as in an earlier example, but this time all the coherent links are explicitly customized (as
|
||||
* might be needed if each link has unique characterization). For this example, we skip the non-coherent chains.
|
||||
* (A real system would have to include them, see example above.)
|
||||
* @skip DinarPerLinkDeemphasisList
|
||||
* @until {
|
||||
* Provide deemphasis settings for the 16 bit, ganged, links, Socket 0 links 0, 1 and Socket 1 links 1 and 2.
|
||||
* Provide entries to customize all HT3 frequencies at which the links may run. This example covers all HT3 speeds.
|
||||
* @until {
|
||||
* @until DcvLevelMinus6
|
||||
* @until DcvLevelMinus6
|
||||
* @until DcvLevelMinus6
|
||||
* @until DcvLevelMinus6
|
||||
* Link 3 on both sockets connects different internal die: sublink 0 connects the internal node zeroes, and
|
||||
* sublink 1 connects the internal node ones. So the link is unganged and both sublinks must be specifically
|
||||
* customized.
|
||||
* @until {
|
||||
* @until DcvLevelMinus6
|
||||
* @until DcvLevelMinus6
|
||||
* @until DcvLevelMinus6
|
||||
* @until DcvLevelMinus6
|
||||
* end of list:
|
||||
* @until define
|
||||
*
|
||||
* </ul>
|
||||
*
|
||||
* @anchor FrequencyLimitExamples
|
||||
* @par Frequency Limit Examples
|
||||
*
|
||||
* These examples customize AMD_HT_INTERFACE.CpuToCpuPcbLimitsList and AMD_HT_INTERFACE.IoPcbLimitsList.
|
||||
* Source for the frequency limit examples can be found in FrequencyLimitExamples.c. @n
|
||||
* @dontinclude FrequencyLimitExamples.c
|
||||
* <ul>
|
||||
* <li>
|
||||
* The following list provides an example for limiting all coherent links to non-extended frequencies,
|
||||
* that is, to 2600 MHz or less.
|
||||
* @skipline NonExtendedCpuToCpuLimitList
|
||||
* @until {
|
||||
* Provide the limit customization. Match links from any socket, any package link, to any socket, any package link. Width is not limited.
|
||||
* @until HT_FREQUENCY_LIMIT_2600M
|
||||
* End of list:
|
||||
* @until ;
|
||||
* Customize the build to use this cpu to cpu frequency limit.
|
||||
* @until NonExtendedCpuToCpuLimitList
|
||||
* @n </li>
|
||||
* <li>
|
||||
* The following list provides an example for limiting all coherent links to HT 1 frequencies,
|
||||
* that is, to 1000 MHz or less. This is sometimes useful for test and debug.
|
||||
* @skipline Ht1CpuToCpuLimitList
|
||||
* @until Ht1CpuToCpuLimitList
|
||||
* @n </li>
|
||||
* <li>
|
||||
* The following list provides an example for limiting all non-coherent links to 2400 MHz or less.
|
||||
* The chain is matched by host processor Socket and package Link. The depth can be used to select a particular device
|
||||
* to device link on the chain. In this example, the chain consists of a single cave device and depth can be set to match any.
|
||||
* @skipline No2600MhzIoLimitList
|
||||
* @until No2600MhzIoLimitList
|
||||
* @n </li>
|
||||
* <li>
|
||||
* The following list provides an example for limiting all non-coherent links to the minimum HT 3 frequency,
|
||||
* that is, to 1200 MHz or less. This can be useful for test and debug.
|
||||
* @skipline MinHt3IoLimitList
|
||||
* @until MinHt3IoLimitList
|
||||
* @n </li>
|
||||
*
|
||||
* </ul>
|
||||
*
|
||||
* @anchor PerfPerWattHt
|
||||
* @par Performance-per-Watt Optimization Example
|
||||
*
|
||||
* This example customizes AMD_HT_INTERFACE.SkipRegangList.
|
||||
* Source for the Performance-per-watt Optimization example can be found in PerfPerWatt.c. @n
|
||||
* @dontinclude PerfPerWatt.c
|
||||
* To implement a performance-per-watt optimization for MCM processors, use the skip regang structure shown. @n
|
||||
* @skipline PerfPerWatt
|
||||
* @until PerfPerWatt
|
||||
*
|
||||
*/
|
||||
3254
src/vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h
Normal file
3254
src/vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h
Normal file
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,529 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* AMD Platform Specific Memory Configuration
|
||||
*
|
||||
* Contains Definitions and Macros for control of AGESA Memory code on a per platform basis
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: OPTION
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef _PLATFORM_MEMORY_CONFIGURATION_H_
|
||||
#define _PLATFORM_MEMORY_CONFIGURATION_H_
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
#ifndef PSO_ENTRY
|
||||
#define PSO_ENTRY UINT8
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* D E F I N I T I O N S A N D M A C R O S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* T Y P E D E F S, S T R U C T U R E S, E N U M S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* PLATFORM SPECIFIC MEMORY DEFINITIONS
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
///
|
||||
/// Memory Speed and DIMM Population Masks
|
||||
///
|
||||
///< DDR Speed Masks
|
||||
///< Specifies the DDR Speed on a memory channel
|
||||
///
|
||||
#define ANY_SPEED 0xFFFFFFFFul
|
||||
#define DDR400 ((UINT32) 1 << (DDR400_FREQUENCY / 66))
|
||||
#define DDR533 ((UINT32) 1 << (DDR533_FREQUENCY / 66))
|
||||
#define DDR667 ((UINT32) 1 << (DDR667_FREQUENCY / 66))
|
||||
#define DDR800 ((UINT32) 1 << (DDR800_FREQUENCY / 66))
|
||||
#define DDR1066 ((UINT32) 1 << (DDR1066_FREQUENCY / 66))
|
||||
#define DDR1333 ((UINT32) 1 << (DDR1333_FREQUENCY / 66))
|
||||
#define DDR1600 ((UINT32) 1 << (DDR1600_FREQUENCY / 66))
|
||||
#define DDR1866 ((UINT32) 1 << (DDR1866_FREQUENCY / 66))
|
||||
#define DDR2133 ((UINT32) 1 << (DDR2133_FREQUENCY / 66))
|
||||
#define DDR2400 ((UINT32) 1 << (DDR2400_FREQUENCY / 66))
|
||||
///
|
||||
///< DIMM POPULATION MASKS
|
||||
///< Specifies the DIMM Population on a channel (can be added together to specify configuration).
|
||||
///< ex. SR_DIMM0 + SR_DIMM1 : Single Rank Dimm in slot 0 AND Slot 1
|
||||
///< SR_DIMM0 + DR_DIMM0 + SR_DIMM1 +DR_DIMM1 : Single OR Dual rank in Slot 0 AND Single OR Dual rank in Slot 1
|
||||
///
|
||||
#define ANY_ 0xFF ///< Any dimm configuration the current channel
|
||||
#define SR_DIMM0 0x0001 ///< Single rank dimm in slot 0 on the current channel
|
||||
#define SR_DIMM1 0x0010 ///< Single rank dimm in slot 1 on the current channel
|
||||
#define SR_DIMM2 0x0100 ///< Single rank dimm in slot 2 on the current channel
|
||||
#define SR_DIMM3 0x1000 ///< Single rank dimm in slot 3 on the current channel
|
||||
#define DR_DIMM0 0x0002 ///< Dual rank dimm in slot 0 on the current channel
|
||||
#define DR_DIMM1 0x0020 ///< Dual rank dimm in slot 1 on the current channel
|
||||
#define DR_DIMM2 0x0200 ///< Dual rank dimm in slot 2 on the current channel
|
||||
#define DR_DIMM3 0x2000 ///< Dual rank dimm in slot 3 on the current channel
|
||||
#define QR_DIMM0 0x0004 ///< Quad rank dimm in slot 0 on the current channel
|
||||
#define QR_DIMM1 0x0040 ///< Quad rank dimm in slot 1 on the current channel
|
||||
#define QR_DIMM2 0x0400 ///< Quad rank dimm in slot 2 on the current channel
|
||||
#define QR_DIMM3 0x4000 ///< Quad rank dimm in slot 3 on the current channel
|
||||
#define LR_DIMM0 0x0001 ///< Lrdimm in slot 0 on the current channel
|
||||
#define LR_DIMM1 0x0010 ///< Lrdimm in slot 1 on the current channel
|
||||
#define LR_DIMM2 0x0100 ///< Lrdimm in slot 2 on the current channel
|
||||
#define LR_DIMM3 0x1000 ///< Lrdimm in slot 3 on the current channel
|
||||
#define ANY_DIMM0 0x000F ///< Any Dimm combination in slot 0 on the current channel
|
||||
#define ANY_DIMM1 0x00F0 ///< Any Dimm combination in slot 1 on the current channel
|
||||
#define ANY_DIMM2 0x0F00 ///< Any Dimm combination in slot 2 on the current channel
|
||||
#define ANY_DIMM3 0xF000 ///< Any Dimm combination in slot 3 on the current channel
|
||||
///
|
||||
///< CS POPULATION MASKS
|
||||
///< Specifies the CS Population on a channel (can be added together to specify configuration).
|
||||
///< ex. CS0 + CS1 : CS0 and CS1 apply to the setting
|
||||
///
|
||||
#define CS_ANY_ 0xFF ///< Any CS configuration
|
||||
#define CS0_ 0x01 ///< CS0 bit map mask
|
||||
#define CS1_ 0x02 ///< CS1 bit map mask
|
||||
#define CS2_ 0x04 ///< CS2 bit map mask
|
||||
#define CS3_ 0x08 ///< CS3 bit map mask
|
||||
#define CS4_ 0x10 ///< CS4 bit map mask
|
||||
#define CS5_ 0x20 ///< CS5 bit map mask
|
||||
#define CS6_ 0x40 ///< CS6 bit map mask
|
||||
#define CS7_ 0x80 ///< CS7 bit map mask
|
||||
///
|
||||
///< Number of Dimms on the current channel
|
||||
///< This is a mask used to indicate the number of dimms in a channel
|
||||
///< They can be added to indicate multiple conditions (i.e 1 OR 2 Dimms)
|
||||
///
|
||||
#define ANY_NUM 0xFF ///< Any number of Dimms
|
||||
#define NO_DIMM 0x00 ///< No Dimms present
|
||||
#define ONE_DIMM 0x01 ///< One dimm Poulated on the current channel
|
||||
#define TWO_DIMM 0x02 ///< Two dimms Poulated on the current channel
|
||||
#define THREE_DIMM 0x04 ///< Three dimms Poulated on the current channel
|
||||
#define FOUR_DIMM 0x08 ///< Four dimms Poulated on the current channel
|
||||
|
||||
///
|
||||
///< DIMM VOLTAGE MASKS
|
||||
///
|
||||
#define VOLT_ANY_ 0xFF ///< Any voltage configuration
|
||||
#define VOLT1_5_ 0x01 ///< Voltage 1.5V bit map mask
|
||||
#define VOLT1_35_ 0x02 ///< Voltage 1.35V bit map mask
|
||||
#define VOLT1_25_ 0x04 ///< Voltage 1.25V bit map mask
|
||||
|
||||
//
|
||||
// < Not applicable
|
||||
//
|
||||
#define NA_ 0 ///< Not applicable
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
*
|
||||
* Platform Specific Override Definitions for Socket, Channel and Dimm
|
||||
* This indicates where a platform override will be applied.
|
||||
*
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
///
|
||||
///< SOCKET MASKS
|
||||
///< Indicates associated processor sockets to apply override settings
|
||||
///
|
||||
#define ANY_SOCKET 0xFF ///< Apply to all sockets
|
||||
#define SOCKET0 0x01 ///< Apply to socket 0
|
||||
#define SOCKET1 0x02 ///< Apply to socket 1
|
||||
#define SOCKET2 0x04 ///< Apply to socket 2
|
||||
#define SOCKET3 0x08 ///< Apply to socket 3
|
||||
#define SOCKET4 0x10 ///< Apply to socket 4
|
||||
#define SOCKET5 0x20 ///< Apply to socket 5
|
||||
#define SOCKET6 0x40 ///< Apply to socket 6
|
||||
#define SOCKET7 0x80 ///< Apply to socket 7
|
||||
///
|
||||
///< CHANNEL MASKS
|
||||
///< Indicates Memory channels where override should be applied
|
||||
///
|
||||
#define ANY_CHANNEL 0xFF ///< Apply to all Memory channels
|
||||
#define CHANNEL_A 0x01 ///< Apply to Channel A
|
||||
#define CHANNEL_B 0x02 ///< Apply to Channel B
|
||||
#define CHANNEL_C 0x04 ///< Apply to Channel C
|
||||
#define CHANNEL_D 0x08 ///< Apply to Channel D
|
||||
///
|
||||
/// DIMM MASKS
|
||||
/// Indicates Dimm Slots where override should be applied
|
||||
///
|
||||
#define ALL_DIMMS 0xFF ///< Apply to all dimm slots
|
||||
#define DIMM0 0x01 ///< Apply to Dimm Slot 0
|
||||
#define DIMM1 0x02 ///< Apply to Dimm Slot 1
|
||||
#define DIMM2 0x04 ///< Apply to Dimm Slot 2
|
||||
#define DIMM3 0x08 ///< Apply to Dimm Slot 3
|
||||
///
|
||||
/// REGISTER ACCESS MASKS
|
||||
/// Not supported as an at this time
|
||||
///
|
||||
#define ACCESS_NB0 0x0
|
||||
#define ACCESS_NB1 0x1
|
||||
#define ACCESS_NB2 0x2
|
||||
#define ACCESS_NB3 0x3
|
||||
#define ACCESS_NB4 0x4
|
||||
#define ACCESS_PHY 0x5
|
||||
#define ACCESS_DCT_XT 0x6
|
||||
/*----------------------------------------------------------------------------------------
|
||||
*
|
||||
* Platform Specific Overriding Table Definitions
|
||||
*
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#define PSO_END 0 ///< Table End
|
||||
#define PSO_CKE_TRI 1 ///< CKE Tristate Map
|
||||
#define PSO_ODT_TRI 2 ///< ODT Tristate Map
|
||||
#define PSO_CS_TRI 3 ///< CS Tristate Map
|
||||
#define PSO_MAX_DIMMS 4 ///< Max Dimms per channel
|
||||
#define PSO_CLK_SPEED 5 ///< Clock Speed
|
||||
#define PSO_DIMM_TYPE 6 ///< Dimm Type
|
||||
#define PSO_MEMCLK_DIS 7 ///< MEMCLK Disable Map
|
||||
#define PSO_MAX_CHNLS 8 ///< Max Channels per Socket
|
||||
#define PSO_BUS_SPEED 9 ///< Max Memory Bus Speed
|
||||
#define PSO_MAX_CHIPSELS 10 ///< Max Chipsel per Channel
|
||||
#define PSO_MEM_TECH 11 ///< Channel Memory Type
|
||||
#define PSO_WL_SEED 12 ///< DDR3 Write Levelization Seed delay
|
||||
#define PSO_RXEN_SEED 13 ///< Hardwared based RxEn seed
|
||||
#define PSO_NO_LRDIMM_CS67_ROUTING 14 ///< CS6 and CS7 are not Routed to all Memoy slots on a channel for LRDIMMs
|
||||
#define PSO_SOLDERED_DOWN_SODIMM_TYPE 15 ///< Soldered down SODIMM type
|
||||
#define PSO_LVDIMM_VOLT1_5_SUPPORT 16 ///< Force LvDimm voltage to 1.5V
|
||||
#define PSO_MIN_RD_WR_DATAEYE_WIDTH 17 ///< Min RD/WR dataeye width
|
||||
#define PSO_CPU_FAMILY_TO_OVERRIDE 18 ///< CPU family signature to tell following PSO macros are CPU family dependent
|
||||
#define PSO_MAX_SOLDERED_DOWN_DIMMS 19 ///< Max Soldered-down Dimms per channel
|
||||
#define PSO_MEMORY_POWER_POLICY 20 ///< Memory power policy override
|
||||
|
||||
/*----------------------------------
|
||||
* CONDITIONAL PSO SPECIFIC ENTRIES
|
||||
*---------------------------------*/
|
||||
// Condition Types
|
||||
#define CONDITIONAL_PSO_MIN 100 ///< Start of Conditional Entry Types
|
||||
#define PSO_CONDITION_AND 100 ///< And Block - Start of Conditional block
|
||||
#define PSO_CONDITION_LOC 101 ///< Location - Specify Socket, Channel, Dimms to be affected
|
||||
#define PSO_CONDITION_SPD 102 ///< SPD - Specify a specific SPD value on a Dimm on the channel
|
||||
#define PSO_CONDITION_REG 103 // Reserved
|
||||
#define PSO_CONDITION_MAX 103 ///< End Of Condition Entry Types
|
||||
// Action Types
|
||||
#define PSO_ACTION_MIN 120 ///< Start of Action Entry Types
|
||||
#define PSO_ACTION_ODT 120 ///< ODT values to override
|
||||
#define PSO_ACTION_ADDRTMG 121 ///< Address/Timing values to override
|
||||
#define PSO_ACTION_ODCCONTROL 122 ///< ODC Control values to override
|
||||
#define PSO_ACTION_SLEWRATE 123 ///< Slew Rate value to override
|
||||
#define PSO_ACTION_REG 124 // Reserved
|
||||
#define PSO_ACTION_SPEEDLIMIT 125 ///< Memory Bus speed Limit based on configuration
|
||||
#define PSO_ACTION_MAX 125 ///< End of Action Entry Types
|
||||
#define CONDITIONAL_PSO_MAX 139 ///< End of Conditional Entry Types
|
||||
|
||||
/*----------------------------------
|
||||
* TABLE DRIVEN PSO SPECIFIC ENTRIES
|
||||
*---------------------------------*/
|
||||
// Condition descriptor
|
||||
#define PSO_TBLDRV_CONFIG 200 ///< Configuration Descriptor
|
||||
|
||||
// Overriding entry types
|
||||
#define PSO_TBLDRV_START 210 ///< Start of Table Driven Overriding Entry Types
|
||||
#define PSO_TBLDRV_SPEEDLIMIT 210 ///< Speed Limit
|
||||
#define PSO_TBLDRV_ODT_RTTNOM 211 ///< RttNom
|
||||
#define PSO_TBLDRV_ODT_RTTWR 212 ///< RttWr
|
||||
#define PSO_TBLDRV_ODTPATTERN 213 ///< Odt Patterns
|
||||
#define PSO_TBLDRV_ADDRTMG 214 ///< Address/Timing values
|
||||
#define PSO_TBLDRV_ODCCTRL 215 ///< ODC Control values
|
||||
#define PSO_TBLDRV_SLOWACCMODE 216 ///< Slow Access Mode
|
||||
#define PSO_TBLDRV_MR0_CL 217 ///< MR0[CL]
|
||||
#define PSO_TBLDRV_MR0_WR 218 ///< MR0[WR]
|
||||
#define PSO_TBLDRV_RC2_IBT 219 ///< RC2[IBT]
|
||||
#define PSO_TBLDRV_RC10_OPSPEED 220 ///< RC10[Opearting Speed]
|
||||
#define PSO_TBLDRV_LRDIMM_IBT 221 ///< LrDIMM IBT
|
||||
#define PSO_TBLDRV_INVALID_TYPE 223 ///< Invalid Type
|
||||
#define PSO_TBLDRV_END 223 ///< End of Table Driven Overriding Entry Types
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* CONDITIONAL OVERRIDE TABLE MACROS
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
#define CPU_FAMILY_TO_OVERRIDE(CpuFamilyRevision) \
|
||||
PSO_CPU_FAMILY_TO_OVERRIDE, 4, \
|
||||
((CpuFamilyRevision) & 0x0FF), (((CpuFamilyRevision) >> 8)& 0x0FF), (((CpuFamilyRevision) >> 16)& 0x0FF), (((CpuFamilyRevision) >> 24)& 0x0FF)
|
||||
|
||||
#define MEMCLK_DIS_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map) \
|
||||
PSO_MEMCLK_DIS, 11, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map \
|
||||
, Bit7Map
|
||||
|
||||
#define CKE_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map) \
|
||||
PSO_CKE_TRI, 5, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map
|
||||
|
||||
#define ODT_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map) \
|
||||
PSO_ODT_TRI, 7, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map, Bit2Map, Bit3Map
|
||||
|
||||
#define CS_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map) \
|
||||
PSO_CS_TRI, 11, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map
|
||||
|
||||
#define NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) \
|
||||
PSO_MAX_DIMMS, 4, SocketID, ChannelID, ALL_DIMMS, NumberOfDimmSlotsPerChannel
|
||||
|
||||
#define NUMBER_OF_SOLDERED_DOWN_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfSolderedDownDimmsPerChannel) \
|
||||
PSO_MAX_SOLDERED_DOWN_DIMMS, 4, SocketID, ChannelID, ALL_DIMMS, NumberOfSolderedDownDimmsPerChannel
|
||||
|
||||
#define NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) \
|
||||
PSO_MAX_CHIPSELS, 4, SocketID, ChannelID, ALL_DIMMS, NumberOfChipSelectsPerChannel
|
||||
|
||||
#define NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) \
|
||||
PSO_MAX_CHNLS, 4, SocketID, ANY_CHANNEL, ALL_DIMMS, NumberOfChannelsPerSocket
|
||||
|
||||
#define OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, TimingMode, BusSpeed) \
|
||||
PSO_BUS_SPEED, 11, SocketID, ChannelID, ALL_DIMMS, TimingMode, (TimingMode >> 8), (TimingMode >> 16), (TimingMode >> 24), \
|
||||
BusSpeed, (BusSpeed >> 8), (BusSpeed >> 16), (BusSpeed >> 24)
|
||||
|
||||
#define DRAM_TECHNOLOGY(SocketID, MemTechType) \
|
||||
PSO_MEM_TECH, 7, SocketID, ANY_CHANNEL, ALL_DIMMS, MemTechType, (MemTechType >> 8), (MemTechType >> 16), (MemTechType >> 24)
|
||||
|
||||
#define WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \
|
||||
Byte6Seed, Byte7Seed, ByteEccSeed) \
|
||||
PSO_WL_SEED, 12, SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \
|
||||
Byte6Seed, Byte7Seed, ByteEccSeed
|
||||
|
||||
#define HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \
|
||||
Byte6Seed, Byte7Seed, ByteEccSeed) \
|
||||
PSO_RXEN_SEED, 21, SocketID, ChannelID, DimmID, Byte0Seed, (Byte0Seed >> 8), Byte1Seed, (Byte1Seed >> 8), Byte2Seed, (Byte2Seed >> 8), \
|
||||
Byte3Seed, (Byte3Seed >> 8), Byte4Seed, (Byte4Seed >> 8), Byte5Seed, (Byte5Seed >> 8), Byte6Seed, (Byte6Seed >> 8), \
|
||||
Byte7Seed, (Byte7Seed >> 8), ByteEccSeed, (ByteEccSeed >> 8)
|
||||
|
||||
#define NO_LRDIMM_CS67_ROUTING(SocketID, ChannelID) \
|
||||
PSO_NO_LRDIMM_CS67_ROUTING, 4, SocketID, ChannelID, ALL_DIMMS, TRUE
|
||||
|
||||
#define SOLDERED_DOWN_SODIMM_TYPE(SocketID, ChannelID) \
|
||||
PSO_SOLDERED_DOWN_SODIMM_TYPE, 4, SocketID, ChannelID, ALL_DIMMS, TRUE
|
||||
|
||||
#define LVDIMM_FORCE_VOLT1_5_FOR_D0 \
|
||||
PSO_LVDIMM_VOLT1_5_SUPPORT, 4, ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS, TRUE
|
||||
|
||||
#define MIN_RD_WR_DATAEYE_WIDTH(SocketID, ChannelID, MinRdDataeyeWidth, MinWrDataeyeWidth) \
|
||||
PSO_MIN_RD_WR_DATAEYE_WIDTH, 5, SocketID, ChannelID, ALL_DIMMS, MinRdDataeyeWidth, MinWrDataeyeWidth
|
||||
|
||||
#define MEMORY_POWER_POLICY_OVERRIDE(PowerPolicy) \
|
||||
PSO_MEMORY_POWER_POLICY, 4, ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS, PowerPolicy
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* CONDITIONAL OVERRIDE TABLE MACROS
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
#define CONDITION_AND \
|
||||
PSO_CONDITION_AND, 0
|
||||
|
||||
#define COND_LOC(SocketMsk, ChannelMsk, DimmMsk) \
|
||||
PSO_CONDITION_LOC, 3, SocketMsk, ChannelMsk, DimmMsk
|
||||
|
||||
#define COND_SPD(Byte, Mask, Value) \
|
||||
PSO_CONDITION_SPD, 3, Byte, Mask, Value
|
||||
|
||||
#define COND_REG(Access, Offset, Mask, Value) \
|
||||
PSO_CONDITION_REG, 11, Access, (Offset & 0x0FF), (Offset >> 8), \
|
||||
((Mask) & 0x0FF), (((Mask) >> 8) & 0x0FF), (((Mask) >> 16) & 0x0FF), (((Mask) >> 24) & 0x0FF), \
|
||||
((Value) & 0x0FF), (((Value) >> 8) & 0x0FF), (((Value) >> 16) & 0x0FF), (((Value) >> 24) & 0x0FF)
|
||||
|
||||
#define ACTION_ODT(Frequency, Dimms, QrDimms, DramOdt, QrDramOdt, DramDynOdt) \
|
||||
PSO_ACTION_ODT, 9, \
|
||||
((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), ((Frequency >> 24)& 0x0FF), \
|
||||
Dimms, QrDimms, DramOdt, QrDramOdt, DramDynOdt
|
||||
|
||||
#define ACTION_ADDRTMG(Frequency, DimmConfig, AddrTmg) \
|
||||
PSO_ACTION_ADDRTMG, 10, \
|
||||
((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
|
||||
((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
|
||||
(AddrTmg & 0x0FF), ((AddrTmg >> 8)& 0x0FF), ((AddrTmg >> 16)& 0x0FF), ((AddrTmg >> 24)& 0x0FF)
|
||||
|
||||
#define ACTION_ODCCTRL(Frequency, DimmConfig, OdcCtrl) \
|
||||
PSO_ACTION_ODCCONTROL, 10, \
|
||||
((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
|
||||
((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
|
||||
(OdcCtrl & 0x0FF), ((OdcCtrl >> 8)& 0x0FF), ((OdcCtrl >> 16)& 0x0FF), ((OdcCtrl >> 24)& 0x0FF)
|
||||
|
||||
#define ACTION_SLEWRATE(Frequency, DimmConfig, SlewRate) \
|
||||
PSO_ACTION_SLEWRATE, 10, \
|
||||
((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
|
||||
((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
|
||||
(SlewRate & 0x0FF), ((SlewRate >> 8)& 0x0FF), ((SlewRate >> 16)& 0x0FF), ((SlewRate >> 24)& 0x0FF)
|
||||
|
||||
#define ACTION_SPEEDLIMIT(DimmConfig, Dimms, SpeedLimit15, SpeedLimit135, SpeedLimit125) \
|
||||
PSO_ACTION_SPEEDLIMIT, 9, \
|
||||
((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), Dimms, \
|
||||
(SpeedLimit15 & 0x0FF), ((SpeedLimit15 >> 8)& 0x0FF), \
|
||||
(SpeedLimit135 & 0x0FF), ((SpeedLimit135 >> 8)& 0x0FF), \
|
||||
(SpeedLimit125 & 0x0FF), ((SpeedLimit125 >> 8)& 0x0FF)
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* END OF CONDITIONAL OVERRIDE TABLE MACROS
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* TABLE DRIVEN OVERRIDE MACROS
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
/// Configuration sub-descriptors
|
||||
typedef enum {
|
||||
CONFIG_GENERAL, ///< CONFIG_GENERAL
|
||||
CONFIG_SPEEDLIMIT, ///< CONFIG_SPEEDLIMIT
|
||||
CONFIG_RC2IBT, ///< CONFIG_RC2IBT
|
||||
CONFIG_DONT_CARE, ///< CONFIG_DONT_CARE
|
||||
} Config_Type;
|
||||
|
||||
// ====================
|
||||
// Configuration Macros
|
||||
// ====================
|
||||
#define TBLDRV_CONFIG_TO_OVERRIDE(DimmPerCH, Frequency, DimmVolt, DimmConfig) \
|
||||
PSO_TBLDRV_CONFIG, 9, \
|
||||
CONFIG_GENERAL, \
|
||||
DimmPerCH, DimmVolt, \
|
||||
((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
|
||||
((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF)
|
||||
|
||||
#define TBLDRV_SPEEDLIMIT_CONFIG_TO_OVERRIDE(DimmPerCH, Dimms, NumOfSR, NumOfDR, NumOfQR, NumOfLRDimm) \
|
||||
PSO_TBLDRV_CONFIG, 7, \
|
||||
CONFIG_SPEEDLIMIT, \
|
||||
DimmPerCH, Dimms, NumOfSR, NumOfDR, NumOfQR, NumOfLRDimm
|
||||
|
||||
#define TBLDRV_RC2IBT_CONFIG_TO_OVERRIDE(DimmPerCH, Frequency, DimmVolt, DimmConfig, NumOfReg) \
|
||||
PSO_TBLDRV_CONFIG, 10, \
|
||||
CONFIG_RC2IBT, \
|
||||
DimmPerCH, DimmVolt, \
|
||||
((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
|
||||
((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
|
||||
NumOfReg
|
||||
|
||||
//==================
|
||||
// Overriding Macros
|
||||
//==================
|
||||
#define TBLDRV_CONFIG_ENTRY_SPEEDLIMIT(SpeedLimit1_5, SpeedLimit1_35, SpeedLimit1_25) \
|
||||
PSO_TBLDRV_SPEEDLIMIT, 6, \
|
||||
(SpeedLimit1_5 & 0x0FF), ((SpeedLimit1_5 >> 8)& 0x0FF), \
|
||||
(SpeedLimit1_35 & 0x0FF), ((SpeedLimit1_35 >> 8)& 0x0FF), \
|
||||
(SpeedLimit1_25 & 0x0FF), ((SpeedLimit1_25 >> 8)& 0x0FF)
|
||||
|
||||
#define TBLDRV_CONFIG_ENTRY_ODT_RTTNOM(TgtCS, RttNom) \
|
||||
PSO_TBLDRV_ODT_RTTNOM, 2, \
|
||||
TgtCS, RttNom
|
||||
|
||||
#define TBLDRV_CONFIG_ENTRY_ODT_RTTWR(TgtCS, RttWr) \
|
||||
PSO_TBLDRV_ODT_RTTWR, 2, \
|
||||
TgtCS, RttWr
|
||||
|
||||
#define TBLDRV_CONFIG_ENTRY_ODTPATTERN(RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow) \
|
||||
PSO_TBLDRV_ODTPATTERN, 16, \
|
||||
((RdODTCSHigh) & 0x0FF), (((RdODTCSHigh) >> 8)& 0x0FF), (((RdODTCSHigh) >> 16)& 0x0FF), (((RdODTCSHigh) >> 24)& 0x0FF), \
|
||||
((RdODTCSLow) & 0x0FF), (((RdODTCSLow) >> 8)& 0x0FF), (((RdODTCSLow) >> 16)& 0x0FF), (((RdODTCSLow) >> 24)& 0x0FF), \
|
||||
((WrODTCSHigh) & 0x0FF), (((WrODTCSHigh) >> 8)& 0x0FF), (((WrODTCSHigh) >> 16)& 0x0FF), (((WrODTCSHigh) >> 24)& 0x0FF), \
|
||||
((WrODTCSLow) & 0x0FF), (((WrODTCSLow) >> 8)& 0x0FF), (((WrODTCSLow) >> 16)& 0x0FF), (((WrODTCSLow) >> 24)& 0x0FF)
|
||||
|
||||
#define TBLDRV_CONFIG_ENTRY_ADDRTMG(AddrTmg) \
|
||||
PSO_TBLDRV_ADDRTMG, 4, \
|
||||
((AddrTmg) & 0x0FF), (((AddrTmg) >> 8)& 0x0FF), (((AddrTmg) >> 16)& 0x0FF), (((AddrTmg) >> 24)& 0x0FF)
|
||||
|
||||
#define TBLDRV_CONFIG_ENTRY_ODCCTRL(OdcCtrl) \
|
||||
PSO_TBLDRV_ODCCTRL, 4, \
|
||||
((OdcCtrl) & 0x0FF), (((OdcCtrl) >> 8)& 0x0FF), (((OdcCtrl) >> 16)& 0x0FF), (((OdcCtrl) >> 24)& 0x0FF)
|
||||
|
||||
#define TBLDRV_CONFIG_ENTRY_SLOWACCMODE(SlowAccMode) \
|
||||
PSO_TBLDRV_SLOWACCMODE, 1, \
|
||||
SlowAccMode
|
||||
|
||||
#define TBLDRV_CONFIG_ENTRY_RC2_IBT(TgtDimm, IBT) \
|
||||
PSO_TBLDRV_RC2_IBT, 2, \
|
||||
TgtDimm, IBT
|
||||
|
||||
#define TBLDRV_OVERRIDE_MR0_CL(RegValOfTcl, MR0CL13, MR0CL0) \
|
||||
PSO_TBLDRV_CONFIG, 1, \
|
||||
CONFIG_DONT_CARE, \
|
||||
PSO_TBLDRV_MR0_CL, 3, \
|
||||
RegValOfTcl, MR0CL13, MR0CL0
|
||||
|
||||
#define TBLDRV_OVERRIDE_MR0_WR(RegValOfTwr, MR0WR) \
|
||||
PSO_TBLDRV_CONFIG, 1, \
|
||||
CONFIG_DONT_CARE, \
|
||||
PSO_TBLDRV_MR0_WR, 2, \
|
||||
RegValOfTwr, MR0WR
|
||||
|
||||
#define TBLDRV_OVERRIDE_RC10_OPSPEED(Frequency, MR10OPSPEED) \
|
||||
PSO_TBLDRV_CONFIG, 1, \
|
||||
CONFIG_DONT_CARE, \
|
||||
PSO_TBLDRV_RC10_OPSPEED, 5, \
|
||||
((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
|
||||
MR10OPSPEED
|
||||
|
||||
#define TBLDRV_CONFIG_ENTRY_LRDMM_IBT(F0RC8, F1RC0, F1RC1, F1RC2) \
|
||||
PSO_TBLDRV_LRDIMM_IBT, 4, \
|
||||
F0RC8, F1RC0, F1RC1, F1RC2
|
||||
|
||||
|
||||
//============================
|
||||
// Macros for removing entries
|
||||
//============================
|
||||
#define INVALID_CONFIG_FLAG 0x8000
|
||||
|
||||
#define TBLDRV_INVALID_CONFIG \
|
||||
PSO_TBLDRV_INVALID_TYPE, 0
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* END OF TABLE DRIVEN OVERRIDE MACROS
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#endif // _PLATFORM_MEMORY_CONFIGURATION_H_
|
||||
189
src/vendorcode/amd/agesa/f15tn/Include/Topology.h
Normal file
189
src/vendorcode/amd/agesa/f15tn/Include/Topology.h
Normal file
@ -0,0 +1,189 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* Topology interface definitions.
|
||||
*
|
||||
* Contains AMD AGESA internal interface for topology related data which
|
||||
* is consumed by code other than HyperTransport init (and produced by
|
||||
* HyperTransport init.)
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: Core
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef _TOPOLOGY_H_
|
||||
#define _TOPOLOGY_H_
|
||||
|
||||
// Defines for limiting data structure maximum allocation and limit checking.
|
||||
#define MAX_NODES 8
|
||||
#define MAX_SOCKETS MAX_NODES
|
||||
#define MAX_DIES 2
|
||||
|
||||
// Defines useful with package link
|
||||
#define HT_LIST_MATCH_INTERNAL_LINK_0 0xFA
|
||||
#define HT_LIST_MATCH_INTERNAL_LINK_1 0xFB
|
||||
#define HT_LIST_MATCH_INTERNAL_LINK_2 0xFC
|
||||
|
||||
/**
|
||||
* Hop Count Table.
|
||||
* This is a heap data structure. The Hops array is filled as a size x size matrix.
|
||||
* The unused space, if any, is all at the end.
|
||||
*/
|
||||
typedef struct {
|
||||
UINT8 Size; ///< The row and column size of actual hop count data */
|
||||
UINT8 Hops[MAX_NODES * MAX_NODES]; ///< Room for a dynamic two dimensional array of [size][size] */
|
||||
} HOP_COUNT_TABLE;
|
||||
|
||||
/**
|
||||
* Socket and Module to Node Map Item.
|
||||
* Provide the Node Id and core id range for each module in each processor.
|
||||
*/
|
||||
typedef struct {
|
||||
UINT8 Node; ///< The module's Node id.
|
||||
UINT8 LowCore; ///< The lowest processor core id for this module.
|
||||
UINT8 HighCore; ///< The highest processor core id for this module.
|
||||
UINT8 EnabledComputeUnits; ///< The value of Enabled for this processor module.
|
||||
UINT8 DualCoreComputeUnits; ///< The value of DualCore for this processor module.
|
||||
} SOCKET_DIE_TO_NODE_ITEM;
|
||||
|
||||
/**
|
||||
* Socket and Module to Node Map.
|
||||
* This type is a pointer to the actual map, it can be used for a struct item or
|
||||
* for typecasting a heap buffer pointer.
|
||||
*/
|
||||
typedef SOCKET_DIE_TO_NODE_ITEM (*SOCKET_DIE_TO_NODE_MAP)[MAX_SOCKETS][MAX_DIES];
|
||||
|
||||
/**
|
||||
* Node id to Socket Die Map Item.
|
||||
*/
|
||||
typedef struct {
|
||||
UINT8 Socket; ///< socket of the processor containing the Node.
|
||||
UINT8 Die; ///< the module in the processor which is Node.
|
||||
} NODE_TO_SOCKET_DIE_ITEM;
|
||||
|
||||
/**
|
||||
* Node id to Socket Die Map.
|
||||
*/
|
||||
typedef NODE_TO_SOCKET_DIE_ITEM (*NODE_TO_SOCKET_DIE_MAP)[MAX_NODES];
|
||||
|
||||
/**
|
||||
* Provide AP core with socket and node context at start up.
|
||||
* This information is posted to the AP cores using a register as a mailbox.
|
||||
*/
|
||||
typedef struct {
|
||||
UINT32 Node:4; ///< The node id of Core's node.
|
||||
UINT32 Socket:4; ///< The socket of this Core's node.
|
||||
UINT32 Module:2; ///< The internal module number for Core's node.
|
||||
UINT32 ModuleType:2; ///< Single Module = 0, Multi-module = 1.
|
||||
UINT32 :20; ///< Reserved
|
||||
} AP_MAIL_INFO_FIELDS;
|
||||
|
||||
/**
|
||||
* AP info fields can be written and read to a register.
|
||||
*/
|
||||
typedef union {
|
||||
UINT32 Info; ///< Just a number for register access, or opaque passing.
|
||||
AP_MAIL_INFO_FIELDS Fields; ///< access to the info fields.
|
||||
} AP_MAIL_INFO;
|
||||
|
||||
/**
|
||||
* Provide AP core with system degree and system core number at start up.
|
||||
* This information is posted to the AP cores using a register as a mailbox.
|
||||
*/
|
||||
typedef struct {
|
||||
UINT32 SystemDegree:3; ///< The number of connected links
|
||||
UINT32 :3; ///< Reserved
|
||||
UINT32 HeapIndex:6; ///< The zero-based system core number
|
||||
UINT32 :20; ///< Reserved
|
||||
} AP_MAIL_EXT_INFO_FIELDS;
|
||||
|
||||
/**
|
||||
* AP info fields can be written and read to a register.
|
||||
*/
|
||||
typedef union {
|
||||
UINT32 Info; ///< Just a number for register access, or opaque passing.
|
||||
AP_MAIL_EXT_INFO_FIELDS Fields; ///< access to the info fields.
|
||||
} AP_MAIL_EXT_INFO;
|
||||
|
||||
/**
|
||||
* AP Info mailbox set.
|
||||
*/
|
||||
typedef struct {
|
||||
AP_MAIL_INFO ApMailInfo; ///< The AP mail info
|
||||
AP_MAIL_EXT_INFO ApMailExtInfo; ///< The extended AP mail info
|
||||
} AP_MAILBOXES;
|
||||
|
||||
/**
|
||||
* Provide a northbridge to package mapping for link assignments.
|
||||
*
|
||||
*/
|
||||
typedef struct {
|
||||
UINT8 Link; ///< The Node's link
|
||||
UINT8 Module; ///< The internal module position of Node
|
||||
UINT8 PackageLink; ///< The corresponding package link
|
||||
} PACKAGE_HTLINK_MAP_ITEM;
|
||||
|
||||
/**
|
||||
* A Processor's complete set of link assignments
|
||||
*/
|
||||
typedef PACKAGE_HTLINK_MAP_ITEM (*PACKAGE_HTLINK_MAP)[];
|
||||
|
||||
#endif // _TOPOLOGY_H_
|
||||
171
src/vendorcode/amd/agesa/f15tn/Include/VirgoInstall.h
Normal file
171
src/vendorcode/amd/agesa/f15tn/Include/VirgoInstall.h
Normal file
@ -0,0 +1,171 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* Install of build options for a Virgo platform solution
|
||||
*
|
||||
* This file generates the defaults tables for the "Virgo" platform solution
|
||||
* set of processors. The documented build options are imported from a user
|
||||
* controlled file for processing.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: Core
|
||||
* @e \$Revision: 65876 $ @e \$Date: 2012-02-26 21:30:10 -0600 (Sun, 26 Feb 2012) $
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
#include "cpuRegisters.h"
|
||||
#include "cpuFamRegisters.h"
|
||||
#include "cpuFamilyTranslation.h"
|
||||
#include "AdvancedApi.h"
|
||||
#include "heapManager.h"
|
||||
#include "CreateStruct.h"
|
||||
#include "cpuFeatures.h"
|
||||
#include "Table.h"
|
||||
#include "CommonReturns.h"
|
||||
#include "cpuEarlyInit.h"
|
||||
#include "cpuLateInit.h"
|
||||
#include "GnbInterface.h"
|
||||
|
||||
/*****************************************************************************
|
||||
* Define the RELEASE VERSION string
|
||||
*
|
||||
* The Release Version string should identify the next planned release.
|
||||
* When a branch is made in preparation for a release, the release manager
|
||||
* should change/confirm that the branch version of this file contains the
|
||||
* string matching the desired version for the release. The trunk version of
|
||||
* the file should always contain a trailing 'X'. This will make sure that a
|
||||
* development build from trunk will not be confused for a released version.
|
||||
* The release manager will need to remove the trailing 'X' and update the
|
||||
* version string as appropriate for the release. The trunk copy of this file
|
||||
* should also be updated/incremented for the next expected version, + trailing 'X'
|
||||
****************************************************************************/
|
||||
// This is the delivery package title, "TrinyPI "
|
||||
// This string MUST be exactly 8 characters long
|
||||
#define AGESA_PACKAGE_STRING {'T', 'r', 'i', 'n', 'y', 'P', 'I', ' '}
|
||||
|
||||
// This is the release version number of the AGESA component
|
||||
// This string MUST be exactly 12 characters long
|
||||
#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '2', ' ', ' ', ' ', ' '}
|
||||
|
||||
|
||||
// The Virgo solution is defined to be family 0x15 models 0x10 - 0x1F in the FM2 socket.
|
||||
#define INSTALL_FM2_SOCKET_SUPPORT TRUE
|
||||
#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
|
||||
|
||||
|
||||
// The following definitions specify the default values for various parameters in which there are
|
||||
// no clearly defined defaults to be used in the common file. The values below are based on product
|
||||
// and BKDG content, please consult the AGESA Memory team for consultation.
|
||||
#define DFLT_SCRUB_DRAM_RATE (0)
|
||||
#define DFLT_SCRUB_L2_RATE (0)
|
||||
#define DFLT_SCRUB_L3_RATE (0)
|
||||
#define DFLT_SCRUB_IC_RATE (0)
|
||||
#define DFLT_SCRUB_DC_RATE (0)
|
||||
#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
|
||||
#define DFLT_VRM_SLEW_RATE (5000)
|
||||
|
||||
|
||||
#define DFLT_SMBUS0_BASE_ADDRESS 0xB00
|
||||
#define DFLT_SMBUS1_BASE_ADDRESS 0xB20
|
||||
#define DFLT_SIO_PME_BASE_ADDRESS 0xE00
|
||||
#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400
|
||||
#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404
|
||||
#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x408
|
||||
#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410
|
||||
#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x420
|
||||
#define DFLT_SPI_BASE_ADDRESS 0xFEC10000ul
|
||||
#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0ul
|
||||
#define DFLT_HPET_BASE_ADDRESS 0xFED00000ul
|
||||
#define DFLT_SMI_CMD_PORT 0xB0
|
||||
#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00
|
||||
#define DFLT_GEC_BASE_ADDRESS 0xFED61000ul
|
||||
#define DFLT_SMBUS_SSID 0x780B1022ul
|
||||
#define DFLT_IDE_SSID 0x780C1022ul
|
||||
#define DFLT_SATA_AHCI_SSID 0x78011022ul
|
||||
#define DFLT_SATA_IDE_SSID 0x78001022ul
|
||||
#define DFLT_SATA_RAID5_SSID 0x78031022ul
|
||||
#define DFLT_SATA_RAID_SSID 0x78021022ul
|
||||
#define DFLT_EHCI_SSID 0x78081022ul
|
||||
#define DFLT_OHCI_SSID 0x78071022ul
|
||||
#define DFLT_LPC_SSID 0x780E1022ul
|
||||
#define DFLT_SD_SSID 0x78061022ul
|
||||
#define DFLT_XHCI_SSID 0x78121022ul
|
||||
#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE
|
||||
#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
|
||||
#define DFLT_FCH_GPP_LINK_CONFIG PortA4
|
||||
#define DFLT_FCH_GPP_PORT0_PRESENT FALSE
|
||||
#define DFLT_FCH_GPP_PORT1_PRESENT FALSE
|
||||
#define DFLT_FCH_GPP_PORT2_PRESENT FALSE
|
||||
#define DFLT_FCH_GPP_PORT3_PRESENT FALSE
|
||||
#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE
|
||||
#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
|
||||
#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
|
||||
#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
|
||||
|
||||
#ifdef BLDCFG_VRM_INRUSH_CURRENT_LIMIT
|
||||
#error BLDCFG: BLDCFG_VRM_INRUSH_CURRENT_LIMIT is deprecated. Use BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT instead.
|
||||
#endif
|
||||
|
||||
#ifdef BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT
|
||||
#error BLDCFG: BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT is deprecated. Use BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT instead.
|
||||
#endif
|
||||
|
||||
// Instantiate all solution relevant data.
|
||||
#include "PlatformInstall.h"
|
||||
|
||||
624
src/vendorcode/amd/agesa/f15tn/Include/gcc-intrin.h
Normal file
624
src/vendorcode/amd/agesa/f15tn/Include/gcc-intrin.h
Normal file
@ -0,0 +1,624 @@
|
||||
/*
|
||||
* Copyright (c) 2011, Advanced Micro Devices, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#if defined (__GNUC__)
|
||||
|
||||
/* I/O intrin functions. */
|
||||
static __inline__ __attribute__((always_inline)) unsigned char __inbyte(unsigned short Port)
|
||||
{
|
||||
unsigned char value;
|
||||
|
||||
__asm__ __volatile__ (
|
||||
"in %%dx, %%al"
|
||||
: "=a" (value)
|
||||
: "d" (Port)
|
||||
);
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned short __inword(unsigned short Port)
|
||||
{
|
||||
unsigned short value;
|
||||
|
||||
__asm__ __volatile__ (
|
||||
"in %%dx, %%ax"
|
||||
: "=a" (value)
|
||||
: "d" (Port)
|
||||
);
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __indword(unsigned short Port)
|
||||
{
|
||||
unsigned long value;
|
||||
|
||||
__asm__ __volatile__ (
|
||||
"in %%dx, %%eax"
|
||||
: "=a" (value)
|
||||
: "d" (Port)
|
||||
);
|
||||
return value;
|
||||
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outbyte(unsigned short Port,unsigned char Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"out %%al, %%dx"
|
||||
:
|
||||
: "a" (Data), "d" (Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outword(unsigned short Port,unsigned short Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"out %%ax, %%dx"
|
||||
:
|
||||
: "a" (Data), "d" (Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outdword(unsigned short Port,unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"out %%eax, %%dx"
|
||||
:
|
||||
: "a" (Data), "d" (Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __inbytestring(unsigned short Port,unsigned char *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"cld ; rep ; insb "
|
||||
: "=D" (Buffer), "=c" (Count)
|
||||
: "d"(Port), "0"(Buffer), "1" (Count)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __inwordstring(unsigned short Port,unsigned short *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"cld ; rep ; insw "
|
||||
: "=D" (Buffer), "=c" (Count)
|
||||
: "d"(Port), "0"(Buffer), "1" (Count)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __indwordstring(unsigned short Port,unsigned long *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"cld ; rep ; insl "
|
||||
: "=D" (Buffer), "=c" (Count)
|
||||
: "d"(Port), "0"(Buffer), "1" (Count)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outbytestring(unsigned short Port,unsigned char *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"cld ; rep ; outsb "
|
||||
: "=S" (Buffer), "=c" (Count)
|
||||
: "d"(Port), "0"(Buffer), "1" (Count)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outwordstring(unsigned short Port,unsigned short *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"cld ; rep ; outsw "
|
||||
: "=S" (Buffer), "=c" (Count)
|
||||
: "d"(Port), "0"(Buffer), "1" (Count)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outdwordstring(unsigned short Port,unsigned long *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"cld ; rep ; outsl "
|
||||
: "=S" (Buffer), "=c" (Count)
|
||||
: "d"(Port), "0"(Buffer), "1" (Count)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr0(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%dr0, %[value]"
|
||||
: [value] "=a" (value)
|
||||
);
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr1(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%dr1, %[value]"
|
||||
: [value] "=a" (value)
|
||||
);
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr2(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%dr2, %[value]"
|
||||
: [value] "=a" (value)
|
||||
);
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr3(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%dr3, %[value]"
|
||||
: [value] "=a" (value)
|
||||
);
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr7(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%dr7, %[value]"
|
||||
: [value] "=a" (value)
|
||||
);
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr(unsigned long reg)
|
||||
{
|
||||
switch (reg){
|
||||
case 0:
|
||||
return __readdr0 ();
|
||||
break;
|
||||
|
||||
case 1:
|
||||
return __readdr1 ();
|
||||
break;
|
||||
|
||||
case 2:
|
||||
return __readdr2 ();
|
||||
break;
|
||||
|
||||
case 3:
|
||||
return __readdr3 ();
|
||||
break;
|
||||
|
||||
case 7:
|
||||
return __readdr7 ();
|
||||
break;
|
||||
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr0(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %%eax, %%dr0"
|
||||
:
|
||||
: "a" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr1(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %%eax, %%dr1"
|
||||
:
|
||||
: "a" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr2(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %%eax, %%dr2"
|
||||
:
|
||||
: "a" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr3(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %%eax, %%dr3"
|
||||
:
|
||||
: "a" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr7(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %%eax, %%dr7"
|
||||
:
|
||||
: "a" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr(unsigned long reg, unsigned long Data)
|
||||
{
|
||||
switch (reg){
|
||||
case 0:
|
||||
__writedr0 (Data);
|
||||
break;
|
||||
|
||||
case 1:
|
||||
__writedr1 (Data);
|
||||
break;
|
||||
|
||||
case 2:
|
||||
__writedr2 (Data);
|
||||
break;
|
||||
|
||||
case 3:
|
||||
__writedr3 (Data);
|
||||
break;
|
||||
|
||||
case 7:
|
||||
__writedr7 (Data);
|
||||
break;
|
||||
|
||||
default:
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr0(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%cr0, %[value]"
|
||||
: [value] "=a" (value));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr2(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%cr2, %[value]"
|
||||
: [value] "=a" (value));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr3(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%cr3, %[value]"
|
||||
: [value] "=a" (value));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr4(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%cr4, %[value]"
|
||||
: [value] "=a" (value));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr8(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%cr8, %[value]"
|
||||
: [value] "=a" (value));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr(unsigned long reg)
|
||||
{
|
||||
switch (reg){
|
||||
case 0:
|
||||
return __readcr0 ();
|
||||
break;
|
||||
|
||||
case 2:
|
||||
return __readcr2 ();
|
||||
break;
|
||||
|
||||
case 3:
|
||||
return __readcr3 ();
|
||||
break;
|
||||
|
||||
case 4:
|
||||
return __readcr4 ();
|
||||
break;
|
||||
|
||||
case 8:
|
||||
return __readcr8 ();
|
||||
break;
|
||||
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr0(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %%eax, %%cr0"
|
||||
:
|
||||
: "a" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr2(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %%eax, %%cr2"
|
||||
:
|
||||
: "a" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr3(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %%eax, %%cr3"
|
||||
:
|
||||
: "a" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr4(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %%eax, %%cr4"
|
||||
:
|
||||
: "a" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr8(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %%eax, %%cr8"
|
||||
:
|
||||
: "a" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr(unsigned long reg, unsigned long Data)
|
||||
{
|
||||
switch (reg){
|
||||
case 0:
|
||||
__writecr0 (Data);
|
||||
break;
|
||||
|
||||
case 2:
|
||||
__writecr2 (Data);
|
||||
break;
|
||||
|
||||
case 3:
|
||||
__writecr3 (Data);
|
||||
break;
|
||||
|
||||
case 4:
|
||||
__writecr4 (Data);
|
||||
break;
|
||||
|
||||
case 8:
|
||||
__writecr8 (Data);
|
||||
break;
|
||||
|
||||
default:
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) UINT64 __readmsr(UINT32 msr)
|
||||
{
|
||||
UINT64 retval;
|
||||
__asm__ __volatile__(
|
||||
"rdmsr\n\t"
|
||||
: "=A" (retval)
|
||||
: "c" (msr)
|
||||
);
|
||||
return retval;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writemsr (UINT32 msr, UINT64 Value)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"wrmsr\n\t"
|
||||
:
|
||||
: "c" (msr), "A" (Value)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) UINT64 __rdtsc(void)
|
||||
{
|
||||
UINT64 retval;
|
||||
__asm__ __volatile__ (
|
||||
"rdtsc"
|
||||
: "=A" (retval));
|
||||
return retval;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __cpuid(int CPUInfo[], const int InfoType)
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
"cpuid"
|
||||
:"=a" (CPUInfo[0]), "=b" (CPUInfo[1]), "=c" (CPUInfo[2]), "=d" (CPUInfo[3])
|
||||
: "a" (InfoType)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void _disable(void)
|
||||
{
|
||||
__asm__ __volatile__ ("cli");
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void _enable(void)
|
||||
{
|
||||
__asm__ __volatile__ ("sti");
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __halt(void)
|
||||
{
|
||||
__asm__ __volatile__ ("hlt");
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __debugbreak(void)
|
||||
{
|
||||
__asm__ __volatile__ ("int3");
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __wbinvd(void)
|
||||
{
|
||||
__asm__ __volatile__ ("wbinvd");
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __lidt(void *Source)
|
||||
{
|
||||
__asm__ __volatile__("lidt %0" : : "m"(*(short*)Source));
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writefsbyte(const unsigned long Offset, const unsigned char Data)
|
||||
{
|
||||
__asm__("movb %b[Data], %%fs:%a[Offset]" : : [Offset] "ir" (Offset), [Data] "iq" (Data));
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writefsword(const unsigned long Offset, const unsigned short Data)
|
||||
{
|
||||
__asm__("movw %w[Data], %%fs:%a[Offset]" : : [Offset] "ir" (Offset), [Data] "iq" (Data));
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writefsdword(const unsigned long Offset, const unsigned long Data)
|
||||
{
|
||||
__asm__("movl %k[Data], %%fs:%a[Offset]" : : [Offset] "ir" (Offset), [Data] "iq" (Data));
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned char __readfsbyte(const unsigned long Offset)
|
||||
{
|
||||
unsigned char value;
|
||||
__asm__("movb %%fs:%a[Offset], %b[value]" : [value] "=q" (value) : [Offset] "irm" (Offset));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned short __readfsword(const unsigned long Offset)
|
||||
{
|
||||
unsigned short value;
|
||||
__asm__("movw %%fs:%a[Offset], %w[value]" : [value] "=q" (value) : [Offset] "irm" (Offset));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long long __readfsdword(unsigned long long Offset)
|
||||
{
|
||||
unsigned long long value;
|
||||
__asm__("movl %%fs:%a[Offset], %k[value]" : [value] "=q" (value) : [Offset] "irm" (Offset));
|
||||
return value;
|
||||
}
|
||||
|
||||
#ifdef __SSE3__
|
||||
typedef long long __v2di __attribute__ ((__vector_size__ (16)));
|
||||
typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__));
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void _mm_stream_si128_fs2 (void *__A, __m128i __B)
|
||||
{
|
||||
__asm__(".byte 0x64"); // fs prefix
|
||||
__builtin_ia32_movntdq ((__v2di *)__A, (__v2di)__B);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void _mm_stream_si128_fs (void *__A, void *__B)
|
||||
{
|
||||
__m128i data;
|
||||
data = (__m128i) __builtin_ia32_lddqu ((char const *)__B);
|
||||
_mm_stream_si128_fs2 (__A, data);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void _mm_clflush_fs (void *__A)
|
||||
{
|
||||
__asm__(".byte 0x64"); // fs prefix
|
||||
__builtin_ia32_clflush (__A);
|
||||
}
|
||||
|
||||
static __inline __attribute__(( __always_inline__)) void _mm_mfence (void)
|
||||
{
|
||||
__builtin_ia32_mfence ();
|
||||
}
|
||||
|
||||
static __inline __attribute__(( __always_inline__)) void _mm_sfence (void)
|
||||
{
|
||||
__builtin_ia32_sfence ();
|
||||
}
|
||||
#endif
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __stosb(unsigned char *dest, unsigned char data, size_t count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"cld ; rep ; stosb "
|
||||
: "=D" (dest), "=c" (count)
|
||||
: "a"(data), "0"(dest), "1" (count)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __movsb(unsigned char *dest, unsigned char *data, size_t count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"cld ; rep ; movsb "
|
||||
: "=D" (dest), "=S"(data), "=c" (count)
|
||||
: "S"(data), "0"(dest), "1" (count)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline))
|
||||
void debug_point ( unsigned short Port, unsigned long Data )
|
||||
{
|
||||
__outdword (Port, Data);
|
||||
__asm__ __volatile__ (".word 0xfeeb");
|
||||
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline))
|
||||
void delay_point ( unsigned short Port, unsigned long Data, unsigned long delayTime )
|
||||
{
|
||||
UINTN Index;
|
||||
Index = 0;
|
||||
__outdword (Port, Data);
|
||||
while (Index < delayTime * 600000) {
|
||||
__outdword (0xE0, 0);
|
||||
Index ++;
|
||||
}
|
||||
}
|
||||
#endif // defined (__GNUC__)
|
||||
@ -0,0 +1,715 @@
|
||||
; ****************************************************************************
|
||||
; *
|
||||
; * @file
|
||||
; *
|
||||
; * AMD Platform Specific Memory Configuration
|
||||
; *
|
||||
; * Contains AMD AGESA Memory Configuration Override Interface
|
||||
; *
|
||||
; * @xrefitem bom "File Content Label" "Release Content"
|
||||
; * @e project: AGESA
|
||||
; * @e sub-project: Include
|
||||
; * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
;
|
||||
; ****************************************************************************
|
||||
; *
|
||||
; * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
; *
|
||||
; * AMD is granting you permission to use this software (the Materials)
|
||||
; * pursuant to the terms and conditions of your Software License Agreement
|
||||
; * with AMD. This header does *NOT* give you permission to use the Materials
|
||||
; * or any rights under AMD's intellectual property. Your use of any portion
|
||||
; * of these Materials shall constitute your acceptance of those terms and
|
||||
; * conditions. If you do not agree to the terms and conditions of the Software
|
||||
; * License Agreement, please do not use any portion of these Materials.
|
||||
; *
|
||||
; * CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
; * confidential and provided to you by AMD shall be kept confidential in
|
||||
; * accordance with the terms and conditions of the Software License Agreement.
|
||||
; *
|
||||
; * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
; * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
; * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
; * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
; * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
; * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
; * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
; * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
; * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
; * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
; * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
; * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
; * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
; *
|
||||
; * AMD does not assume any responsibility for any errors which may appear in
|
||||
; * the Materials or any other related information provided to you by AMD, or
|
||||
; * result from use of the Materials or any related information.
|
||||
; *
|
||||
; * You agree that you will not reverse engineer or decompile the Materials.
|
||||
; *
|
||||
; * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
; * further information, software, technical information, know-how, or show-how
|
||||
; * available to you. Additionally, AMD retains the right to modify the
|
||||
; * Materials at any time, without notice, and is not obligated to provide such
|
||||
; * modified Materials to you.
|
||||
; *
|
||||
; * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
; * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
; * subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
; * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
; * Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
; *
|
||||
; * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
; * direct product thereof will be exported directly or indirectly, into any
|
||||
; * country prohibited by the United States Export Administration Act and the
|
||||
; * regulations thereunder, without the required authorization from the U.S.
|
||||
; * government nor will be used for any purpose prohibited by the same.
|
||||
; *
|
||||
; **************************************************************************
|
||||
IFNDEF PSO_ENTRY
|
||||
PSO_ENTRY TEXTEQU <UINT8>; < Platform Configuration Table Entry
|
||||
ENDIF
|
||||
; *****************************************************************************************
|
||||
; *
|
||||
; * PLATFORM SPECIFIC MEMORY DEFINITIONS
|
||||
; *
|
||||
; *****************************************************************************************
|
||||
; */
|
||||
;
|
||||
; < Memory Speed and DIMM Population Masks
|
||||
;
|
||||
; < DDR Speed Masks
|
||||
;
|
||||
ANY_SPEED EQU 0FFFFFFFFh
|
||||
DDR400 EQU ( 1 SHL (DDR400_FREQUENCY / 66))
|
||||
DDR533 EQU ( 1 SHL (DDR533_FREQUENCY / 66))
|
||||
DDR667 EQU ( 1 SHL (DDR667_FREQUENCY / 66))
|
||||
DDR800 EQU ( 1 SHL (DDR800_FREQUENCY / 66))
|
||||
DDR1066 EQU ( 1 SHL (DDR1066_FREQUENCY / 66))
|
||||
DDR1333 EQU ( 1 SHL (DDR1333_FREQUENCY / 66))
|
||||
DDR1600 EQU ( 1 SHL (DDR1600_FREQUENCY / 66))
|
||||
DDR1866 EQU ( 1 SHL (DDR1866_FREQUENCY / 66))
|
||||
DDR2133 EQU ( 1 SHL (DDR2133_FREQUENCY / 66))
|
||||
DDR2400 EQU ( 1 SHL (DDR2400_FREQUENCY / 66))
|
||||
; <
|
||||
; < DIMM POPULATION MASKS
|
||||
;
|
||||
ANY_ EQU 0FFh
|
||||
SR_DIMM0 EQU 0001h
|
||||
SR_DIMM1 EQU 0010h
|
||||
SR_DIMM2 EQU 0100h
|
||||
SR_DIMM3 EQU 1000h
|
||||
DR_DIMM0 EQU 0002h
|
||||
DR_DIMM1 EQU 0020h
|
||||
DR_DIMM2 EQU 0200h
|
||||
DR_DIMM3 EQU 2000h
|
||||
QR_DIMM0 EQU 0004h
|
||||
QR_DIMM1 EQU 0040h
|
||||
QR_DIMM2 EQU 0400h
|
||||
QR_DIMM3 EQU 4000h
|
||||
LR_DIMM0 EQU 0001h
|
||||
LR_DIMM1 EQU 0010h
|
||||
LR_DIMM2 EQU 0100h
|
||||
LR_DIMM3 EQU 1000h
|
||||
ANY_DIMM0 EQU 000Fh
|
||||
ANY_DIMM1 EQU 00F0h
|
||||
ANY_DIMM2 EQU 0F00h
|
||||
ANY_DIMM3 EQU 0F000h
|
||||
; <
|
||||
; < CS POPULATION MASKS
|
||||
;
|
||||
CS_ANY_ EQU 0FFh
|
||||
CS0_ EQU 01h
|
||||
CS1_ EQU 02h
|
||||
CS2_ EQU 04h
|
||||
CS3_ EQU 08h
|
||||
CS4_ EQU 10h
|
||||
CS5_ EQU 20h
|
||||
CS6_ EQU 40h
|
||||
CS7_ EQU 80h
|
||||
;
|
||||
; Number of Dimms
|
||||
;
|
||||
ANY_NUM EQU 0FFh
|
||||
NO_DIMM EQU 00h
|
||||
ONE_DIMM EQU 01h
|
||||
TWO_DIMM EQU 02h
|
||||
THREE_DIMM EQU 04h
|
||||
FOUR_DIMM EQU 08h
|
||||
;
|
||||
; DIMM VOLTAGE MASK
|
||||
;
|
||||
VOLT_ANY_ EQU 0FFh
|
||||
VOLT1_5_ EQU 01h
|
||||
VOLT1_35_ EQU 02h
|
||||
VOLT1_25_ EQU 04h
|
||||
;
|
||||
; NOT APPLICIABLE
|
||||
;
|
||||
NA_ EQU 00h
|
||||
; *****************************************************************************************
|
||||
; *
|
||||
; * Platform Specific Override Definitions for Socket, Channel and Dimm
|
||||
; * This indicates where a platform override will be applied.
|
||||
; *
|
||||
; *****************************************************************************************
|
||||
;
|
||||
; SOCKET MASKS
|
||||
;
|
||||
ANY_SOCKET EQU 0FFh
|
||||
SOCKET0 EQU 01h
|
||||
SOCKET1 EQU 02h
|
||||
SOCKET2 EQU 04h
|
||||
SOCKET3 EQU 08h
|
||||
SOCKET4 EQU 10h
|
||||
SOCKET5 EQU 20h
|
||||
SOCKET6 EQU 40h
|
||||
SOCKET7 EQU 80h
|
||||
;
|
||||
; CHANNEL MASKS
|
||||
;
|
||||
ANY_CHANNEL EQU 0FFh
|
||||
CHANNEL_A EQU 01h
|
||||
CHANNEL_B EQU 02h
|
||||
CHANNEL_C EQU 04h
|
||||
CHANNEL_D EQU 08h
|
||||
;
|
||||
; DIMM MASKS
|
||||
;
|
||||
ALL_DIMMS EQU 0FFh
|
||||
DIMM0 EQU 01h
|
||||
DIMM1 EQU 02h
|
||||
DIMM2 EQU 04h
|
||||
DIMM3 EQU 08h
|
||||
;
|
||||
; REGISTER ACCESS MASKS
|
||||
;
|
||||
ACCESS_NB0 EQU 0h
|
||||
ACCESS_NB1 EQU 01h
|
||||
ACCESS_NB2 EQU 02h
|
||||
ACCESS_NB3 EQU 03h
|
||||
ACCESS_NB4 EQU 04h
|
||||
ACCESS_PHY EQU 05h
|
||||
ACCESS_DCT_XT EQU 06h
|
||||
; *****************************************************************************************
|
||||
; *
|
||||
; * Platform Specific Overriding Table Definitions
|
||||
; *
|
||||
; *****************************************************************************************
|
||||
PSO_END EQU 0 ; < Table End
|
||||
PSO_CKE_TRI EQU 1 ; < CKE Tristate Map
|
||||
PSO_ODT_TRI EQU 2 ; < ODT Tristate Map
|
||||
PSO_CS_TRI EQU 3 ; < CS Tristate Map
|
||||
PSO_MAX_DIMMS EQU 4 ; < Max Dimms per channel
|
||||
PSO_CLK_SPEED EQU 5 ; < Clock Speed
|
||||
PSO_DIMM_TYPE EQU 6 ; < Dimm Type
|
||||
PSO_MEMCLK_DIS EQU 7 ; < MEMCLK Disable Map
|
||||
PSO_MAX_CHNLS EQU 8 ; < Max Channels per Socket
|
||||
PSO_BUS_SPEED EQU 9 ; < Max Memory Bus Speed
|
||||
PSO_MAX_CHIPSELS EQU 10 ; < Max Chipsel per Channel
|
||||
PSO_MEM_TECH EQU 11 ; < Channel Memory Type
|
||||
PSO_WL_SEED EQU 12 ; < DDR3 Write Levelization Seed delay
|
||||
PSO_RXEN_SEED EQU 13 ; < Hardwared based RxEn seed
|
||||
PSO_NO_LRDIMM_CS67_ROUTING EQU 14 ; < CS6 and CS7 are not Routed to all Memoy slots on a channel for LRDIMMs
|
||||
PSO_SOLDERED_DOWN_SODIMM_TYPE EQU 15 ; < Soldered down SODIMM type
|
||||
PSO_LVDIMM_VOLT1_5_SUPPORT EQU 16 ; < Force LvDimm voltage to 1.5V
|
||||
PSO_MIN_RD_WR_DATAEYE_WIDTH EQU 17 ; < Min RD/WR dataeye width
|
||||
PSO_CPU_FAMILY_TO_OVERRIDE EQU 18 ; < CPU family signature to tell following PSO macros are CPU family dependent
|
||||
PSO_MAX_SOLDERED_DOWN_DIMMS EQU 19 ; < Max Soldered-down Dimms per channel
|
||||
PSO_MEMORY_POWER_POLICY EQU 20 ; < Memory power policy override
|
||||
; **********************************
|
||||
; * CONDITIONAL PSO SPECIFIC ENTRIES
|
||||
; **********************************
|
||||
; Condition Types
|
||||
CONDITIONAL_PSO_MIN EQU 100 ; < Start of Conditional Entry Types
|
||||
PSO_CONDITION_AND EQU 100 ; < And Block - Start of Conditional block
|
||||
PSO_CONDITION_LOC EQU 101 ; < Location - Specify Socket, Channel, Dimms to be affected
|
||||
PSO_CONDITION_SPD EQU 102 ; < SPD - Specify a specific SPD value on a Dimm on the channel
|
||||
PSO_CONDITION_REG EQU 103 ; Reserved
|
||||
PSO_CONDITION_MAX EQU 103 ; < End Of Condition Entry Types
|
||||
; Action Types
|
||||
PSO_ACTION_MIN EQU 120 ; < Start of Action Entry Types
|
||||
PSO_ACTION_ODT EQU 120 ; < ODT values to override
|
||||
PSO_ACTION_ADDRTMG EQU 121 ; < Address/Timing values to override
|
||||
PSO_ACTION_ODCCONTROL EQU 122 ; < ODC Control values to override
|
||||
PSO_ACTION_SLEWRATE EQU 123 ; < Slew Rate value to override
|
||||
PSO_ACTION_REG EQU 124 ; Reserved
|
||||
PSO_ACTION_SPEEDLIMIT EQU 125 ; < Memory Bus speed Limit based on configuration
|
||||
PSO_ACTION_MAX EQU 125 ; < End of Action Entry Types
|
||||
CONDITIONAL_PSO_MAX EQU 139 ; < End of Conditional Entry Types
|
||||
; **********************************
|
||||
; * TABLE DRIVEN PSO SPECIFIC ENTRIES
|
||||
; **********************************
|
||||
; Condition descriptor
|
||||
PSO_TBLDRV_CONFIG EQU 200 ; < Configuration Descriptor
|
||||
|
||||
; Overriding entry types
|
||||
PSO_TBLDRV_START EQU 210 ; < Start of Table Driven Overriding Entry Types
|
||||
PSO_TBLDRV_SPEEDLIMIT EQU 210 ; < Speed Limit
|
||||
PSO_TBLDRV_ODT_RTTNOM EQU 211 ; < RttNom
|
||||
PSO_TBLDRV_ODT_RTTWR EQU 212 ; < RttWr
|
||||
PSO_TBLDRV_ODTPATTERN EQU 213 ; < Odt Patterns
|
||||
PSO_TBLDRV_ADDRTMG EQU 214 ; < Address/Timing values
|
||||
PSO_TBLDRV_ODCCTRL EQU 215 ; < ODC Control values
|
||||
PSO_TBLDRV_SLOWACCMODE EQU 216 ; < Slow Access Mode
|
||||
PSO_TBLDRV_MR0_CL EQU 217 ; < MR0[CL]
|
||||
PSO_TBLDRV_MR0_WR EQU 218 ; < MR0[WR]
|
||||
PSO_TBLDRV_RC2_IBT EQU 219 ; < RC2[IBT]
|
||||
PSO_TBLDRV_RC10_OPSPEED EQU 220 ; < RC10[Opearting Speed]
|
||||
PSO_TBLDRV_LRDIMM_IBT EQU 221 ; < LrDIMM IBT
|
||||
;del PSO_TBLDRV_2D_TRAINING EQU 222 ; < 2D training
|
||||
PSO_TBLDRV_INVALID_TYPE EQU 223 ; < Invalid Type
|
||||
PSO_TBLDRV_END EQU 223 ; < End of Table Driven Overriding Entry Types
|
||||
|
||||
|
||||
; *****************************************************************************************
|
||||
; *
|
||||
; * CONDITIONAL OVERRIDE TABLE MACROS
|
||||
; *
|
||||
; *****************************************************************************************
|
||||
CPU_FAMILY_TO_OVERRIDE MACRO CpuFamilyRevision:REQ
|
||||
DB PSO_CPU_FAMILY_TO_OVERRIDE
|
||||
DB 4
|
||||
DD CpuFamilyRevision
|
||||
ENDM
|
||||
|
||||
MEMCLK_DIS_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ, Bit4Map:REQ, Bit5Map:REQ, Bit6Map:REQ, Bit7Map:REQ
|
||||
DB PSO_MEMCLK_DIS
|
||||
DB 11
|
||||
DB SocketID
|
||||
DB ChannelID
|
||||
DB ALL_DIMMS
|
||||
DB Bit0Map
|
||||
DB Bit1Map
|
||||
DB Bit2Map
|
||||
DB Bit3Map
|
||||
DB Bit4Map
|
||||
DB Bit5Map
|
||||
DB Bit6Map
|
||||
DB Bit7Map
|
||||
ENDM
|
||||
|
||||
CKE_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ
|
||||
DB PSO_CKE_TRI
|
||||
DB 5
|
||||
DB SocketID
|
||||
DB ChannelID
|
||||
DB ALL_DIMMS
|
||||
DB Bit0Map
|
||||
DB Bit1Map
|
||||
ENDM
|
||||
|
||||
ODT_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ
|
||||
DB PSO_ODT_TRI
|
||||
DB 7
|
||||
DB SocketID
|
||||
DB ChannelID
|
||||
DB ALL_DIMMS
|
||||
DB Bit0Map
|
||||
DB Bit1Map
|
||||
DB Bit2Map
|
||||
DB Bit3Map
|
||||
ENDM
|
||||
|
||||
CS_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ, Bit4Map:REQ, Bit5Map:REQ, Bit6Map:REQ, Bit7Map:REQ
|
||||
DB PSO_CS_TRI
|
||||
DB 11
|
||||
DB SocketID
|
||||
DB ChannelID
|
||||
DB ALL_DIMMS
|
||||
DB Bit0Map
|
||||
DB Bit1Map
|
||||
DB Bit2Map
|
||||
DB Bit3Map
|
||||
DB Bit4Map
|
||||
DB Bit5Map
|
||||
DB Bit6Map
|
||||
DB Bit7Map
|
||||
ENDM
|
||||
|
||||
NUMBER_OF_DIMMS_SUPPORTED MACRO SocketID:REQ, ChannelID:REQ, NumberOfDimmSlotsPerChannel:REQ
|
||||
DB PSO_MAX_DIMMS
|
||||
DB 4
|
||||
DB SocketID
|
||||
DB ChannelID
|
||||
DB ALL_DIMMS
|
||||
DB NumberOfDimmSlotsPerChannel
|
||||
ENDM
|
||||
|
||||
NUMBER_OF_SOLDERED_DOWN_DIMMS_SUPPORTED MACRO SocketID:REQ, ChannelID:REQ, NumberOfSolderedDownDimmsPerChannel:REQ
|
||||
DB PSO_MAX_SOLDERED_DOWN_DIMMS
|
||||
DB 4
|
||||
DB SocketID
|
||||
DB ChannelID
|
||||
DB ALL_DIMMS
|
||||
DB NumberOfSolderedDownDimmsPerChannel
|
||||
ENDM
|
||||
|
||||
NUMBER_OF_CHIP_SELECTS_SUPPORTED MACRO SocketID:REQ, ChannelID:REQ, NumberOfChipSelectsPerChannel:REQ
|
||||
DB PSO_MAX_CHIPSELS
|
||||
DB 4
|
||||
DB SocketID
|
||||
DB ChannelID
|
||||
DB ALL_DIMMS
|
||||
DB NumberOfChipSelectsPerChannel
|
||||
ENDM
|
||||
|
||||
NUMBER_OF_CHANNELS_SUPPORTED MACRO SocketID:REQ, NumberOfChannelsPerSocket:REQ
|
||||
DB PSO_MAX_CHNLS
|
||||
DB 4
|
||||
DB SocketID
|
||||
DB ANY_CHANNEL
|
||||
DB ALL_DIMMS
|
||||
DB NumberOfChannelsPerSocket
|
||||
ENDM
|
||||
|
||||
OVERRIDE_DDR_BUS_SPEED MACRO SocketID:REQ, ChannelID:REQ, TimingMode:REQ, BusSpeed:REQ
|
||||
PSO_BUS_SPEED
|
||||
DB 11
|
||||
DB SocketID
|
||||
DB ChannelID
|
||||
DB ALL_DIMMS
|
||||
DD TimingMode
|
||||
DD BusSpeed
|
||||
ENDM
|
||||
|
||||
DRAM_TECHNOLOGY MACRO SocketID:REQ, MemTechType:REQ
|
||||
DB PSO_MEM_TECH
|
||||
DB 7
|
||||
DB SocketID
|
||||
DB ANY_CHANNEL
|
||||
DB ALL_DIMMS
|
||||
DD MemTechType
|
||||
ENDM
|
||||
|
||||
WRITE_LEVELING_SEED MACRO SocketID:REQ, ChannelID:REQ, DimmID:REQ, Byte0Seed:REQ, Byte1Seed:REQ, Byte2Seed:REQ, Byte3Seed:REQ, Byte4Seed:REQ, Byte5Seed:REQ, \
|
||||
Byte6Seed:REQ, Byte7Seed:REQ, ByteEccSeed:REQ
|
||||
DB PSO_WL_SEED
|
||||
DB 12
|
||||
DB SocketID
|
||||
DB ChannelID
|
||||
DB DimmID
|
||||
DB Byte0Seed
|
||||
DB Byte1Seed
|
||||
DB Byte2Seed
|
||||
DB Byte3Seed
|
||||
DB Byte4Seed
|
||||
DB Byte5Seed
|
||||
DB Byte6Seed
|
||||
DB Byte7Seed
|
||||
DB ByteEccSeed
|
||||
ENDM
|
||||
|
||||
HW_RXEN_SEED MACRO SocketID:REQ, ChannelID:REQ, DimmID: REQ, Byte0Seed:REQ, Byte1Seed:REQ, Byte2Seed:REQ, Byte3Seed:REQ, Byte4Seed:REQ, Byte5Seed:REQ, \
|
||||
Byte6Seed:REQ, Byte7Seed:REQ, ByteEccSeed:REQ
|
||||
DB PSO_RXEN_SEED
|
||||
DB 21
|
||||
DB SocketID
|
||||
DB ChannelID
|
||||
DB DimmID
|
||||
DW Byte0Seed
|
||||
DW Byte1Seed
|
||||
DW Byte2Seed
|
||||
DW Byte3Seed
|
||||
DW Byte4Seed
|
||||
DW Byte5Seed
|
||||
DW Byte6Seed
|
||||
DW Byte7Seed
|
||||
DW ByteEccSeed
|
||||
ENDM
|
||||
|
||||
NO_LRDIMM_CS67_ROUTING MACRO SocketID:REQ, ChannelID:REQ
|
||||
DB PSO_NO_LRDIMM_CS67_ROUTING
|
||||
DB 4
|
||||
DB SocketID
|
||||
DB ChannelID
|
||||
DB ALL_DIMMS
|
||||
DB 1
|
||||
ENDM
|
||||
|
||||
SOLDERED_DOWN_SODIMM_TYPE MACRO SocketID:REQ, ChannelID:REQ
|
||||
DB PSO_SOLDERED_DOWN_SODIMM_TYPE
|
||||
DB 4
|
||||
DB SocketID
|
||||
DB ChannelID
|
||||
DB ALL_DIMMS
|
||||
DB 1
|
||||
ENDM
|
||||
|
||||
LVDIMM_FORCE_VOLT1_5_FOR_D0 MACRO
|
||||
DB PSO_LVDIMM_VOLT1_5_SUPPORT
|
||||
DB 4
|
||||
DB ANY_SOCKET
|
||||
DB ANY_CHANNEL
|
||||
DB ALL_DIMMS
|
||||
DB 1
|
||||
ENDM
|
||||
|
||||
MIN_RD_WR_DATAEYE_WIDTH MACRO SocketID:REQ, ChannelID:REQ, MinRdDataeyeWidth:REQ, MinWrDataeyeWidth:REQ
|
||||
DB PSO_MIN_RD_WR_DATAEYE_WIDTH
|
||||
DB 5
|
||||
DB SocketID
|
||||
DB ChannelID
|
||||
DB ALL_DIMMS
|
||||
DB MinRdDataeyeWidth
|
||||
DB MinWrDataeyeWidth
|
||||
ENDM
|
||||
|
||||
MEMORY_POWER_POLICY_OVERRIDE MACRO PowerPolicy:REQ
|
||||
DB PSO_MEMORY_POWER_POLICY
|
||||
DB 4
|
||||
DB ANY_SOCKET
|
||||
DB ANY_CHANNEL
|
||||
DB ALL_DIMMS
|
||||
DB PowerPolicy
|
||||
ENDM
|
||||
; *****************************************************************************************
|
||||
; *
|
||||
; * CONDITIONAL OVERRIDE TABLE MACROS
|
||||
; *
|
||||
; *****************************************************************************************
|
||||
CONDITION_AND MACRO
|
||||
DB PSO_CONDITION_AND
|
||||
DB 0
|
||||
ENDM
|
||||
|
||||
COND_LOC MACRO SocketMsk:REQ, ChannelMsk:REQ, DimmMsk:REQ
|
||||
DB PSO_CONDITION_LOC
|
||||
DB 3
|
||||
DB SocketMsk
|
||||
DB ChannelMsk
|
||||
DB DimmMsk
|
||||
ENDM
|
||||
|
||||
COND_SPD MACRO Byte:REQ, Mask:REQ, Value:REQ
|
||||
DB PSO_CONDITION_SPD
|
||||
DB 3
|
||||
DB Byte
|
||||
DB Mask
|
||||
DB Value
|
||||
ENDM
|
||||
|
||||
COND_REG MACRO Access:REQ, Offset:REQ, Mask:REQ, Value:REQ
|
||||
DB PSO_CONDITION_REG
|
||||
DB 11
|
||||
DB Access
|
||||
DW Offset
|
||||
DD Mask
|
||||
DD Value
|
||||
ENDM
|
||||
|
||||
ACTION_ODT MACRO Frequency:REQ, Dimms:REQ, QrDimms:REQ, DramOdt:REQ, QrDramOdt:REQ, DramDynOdt:REQ
|
||||
DB PSO_ACTION_ODT
|
||||
DB 9
|
||||
DD Frequency
|
||||
DB Dimms
|
||||
DB QrDimms
|
||||
DB DramOdt
|
||||
DB QrDramOdt
|
||||
DB DramDynOdt
|
||||
ENDM
|
||||
|
||||
ACTION_ADDRTMG MACRO Frequency:REQ, DimmConfig:REQ, AddrTmg:REQ
|
||||
DB PSO_ACTION_ADDRTMG
|
||||
DB 10
|
||||
DD Frequency
|
||||
DW DimmConfig
|
||||
DD AddrTmg
|
||||
ENDM
|
||||
|
||||
ACTION_ODCCTRL MACRO Frequency:REQ, DimmConfig:REQ, OdcCtrl:REQ
|
||||
DB PSO_ACTION_ODCCONTROL
|
||||
DB 10
|
||||
DD Frequency
|
||||
DW DimmConfig
|
||||
DD OdcCtrl
|
||||
ENDM
|
||||
|
||||
ACTION_SLEWRATE MACRO Frequency:REQ, DimmConfig:REQ, SlewRate:REQ
|
||||
DB PSO_ACTION_SLEWRATE
|
||||
DB 10
|
||||
DD Frequency
|
||||
DW DimmConfig
|
||||
DD SlewRate
|
||||
ENDM
|
||||
|
||||
ACTION_SPEEDLIMIT MACRO DimmConfig:REQ, Dimms:REQ, SpeedLimit15:REQ, SpeedLimit135:REQ, SpeedLimit125:REQ
|
||||
DB PSO_ACTION_SPEEDLIMIT
|
||||
DB 9
|
||||
DW DimmConfig
|
||||
DB Dimms
|
||||
DW SpeedLimit15
|
||||
DW SpeedLimit135
|
||||
DW SpeedLimit125
|
||||
ENDM
|
||||
|
||||
; *****************************************************************************************
|
||||
; *
|
||||
; * END OF CONDITIONAL OVERRIDE TABLE MACROS
|
||||
; *
|
||||
; *****************************************************************************************
|
||||
; *****************************************************************************************
|
||||
; *
|
||||
; * TABLE DRIVEN OVERRIDE MACROS
|
||||
; *
|
||||
; *****************************************************************************************
|
||||
; Configuration sub-descriptors
|
||||
CONFIG_GENERAL EQU 0
|
||||
CONFIG_SPEEDLIMIT EQU 1
|
||||
CONFIG_RC2IBT EQU 2
|
||||
CONFIG_DONT_CARE EQU 3
|
||||
Config_Type TEXTEQU <DWORD>
|
||||
;
|
||||
; Configuration Macros
|
||||
;
|
||||
TBLDRV_CONFIG_TO_OVERRIDE MACRO DimmPerCH:REQ, Frequency:REQ, DimmVolt:REQ, DimmConfig:REQ
|
||||
DB PSO_TBLDRV_CONFIG
|
||||
DB 9
|
||||
DB CONFIG_GENERAL
|
||||
DB DimmPerCH
|
||||
DB DimmVolt
|
||||
DD Frequency
|
||||
DW DimmConfig
|
||||
ENDM
|
||||
|
||||
TBLDRV_SPEEDLIMIT_CONFIG_TO_OVERRIDE MACRO DimmPerCH:REQ, Dimms:REQ, NumOfSR:REQ, NumOfDR:REQ, NumOfQR:REQ, NumOfLRDimm:REQ
|
||||
DB PSO_TBLDRV_CONFIG
|
||||
DB 7
|
||||
DB CONFIG_SPEEDLIMIT
|
||||
DB DimmPerCH
|
||||
DB Dimms
|
||||
DB NumOfSR
|
||||
DB NumOfDR
|
||||
DB NumOfQR
|
||||
DB NumOfLRDimm
|
||||
ENDM
|
||||
|
||||
TBLDRV_RC2IBT_CONFIG_TO_OVERRIDE MACRO DimmPerCH:REQ, Frequency:REQ, DimmVolt:REQ, DimmConfig:REQ, NumOfReg:REQ
|
||||
DB PSO_TBLDRV_CONFIG
|
||||
DB 10
|
||||
DB CONFIG_RC2IBT
|
||||
DB DimmPerCH
|
||||
DB DimmVolt
|
||||
DD Frequency
|
||||
DW DimmConfig
|
||||
DB NumOfReg
|
||||
ENDM
|
||||
;
|
||||
; Overriding Macros
|
||||
;
|
||||
TBLDRV_CONFIG_ENTRY_SPEEDLIMIT MACRO SpeedLimit1_5:REQ, SpeedLimit1_35:REQ, SpeedLimit1_25:REQ
|
||||
DB PSO_TBLDRV_SPEEDLIMIT
|
||||
DB 6
|
||||
DW SpeedLimit1_5
|
||||
DW SpeedLimit1_35
|
||||
DW SpeedLimit1_25
|
||||
ENDM
|
||||
|
||||
TBLDRV_CONFIG_ENTRY_ODT_RTTNOM MACRO TgtCS:REQ, RttNom:REQ
|
||||
DB PSO_TBLDRV_ODT_RTTNOM
|
||||
DB 2
|
||||
DB TgtCS
|
||||
DB RttNom
|
||||
ENDM
|
||||
|
||||
TBLDRV_CONFIG_ENTRY_ODT_RTTWR MACRO TgtCS:REQ, RttWr:REQ
|
||||
DB PSO_TBLDRV_ODT_RTTWR
|
||||
DB 2
|
||||
DB TgtCS
|
||||
DB RttWr
|
||||
ENDM
|
||||
|
||||
TBLDRV_CONFIG_ENTRY_ODTPATTERN MACRO RdODTCSHigh:REQ, RdODTCSLow:REQ, WrODTCSHigh:REQ, WrODTCSLow:REQ
|
||||
DB PSO_TBLDRV_ODTPATTERN
|
||||
DB 16
|
||||
DD RdODTCSHigh
|
||||
DD RdODTCSLow
|
||||
DD WrODTCSHigh
|
||||
DD WrODTCSLow
|
||||
ENDM
|
||||
|
||||
TBLDRV_CONFIG_ENTRY_ADDRTMG MACRO AddrTmg:REQ
|
||||
DB PSO_TBLDRV_ADDRTMG
|
||||
DB 4
|
||||
DD AddrTmg
|
||||
ENDM
|
||||
|
||||
TBLDRV_CONFIG_ENTRY_ODCCTRL MACRO OdcCtrl:REQ
|
||||
DB PSO_TBLDRV_ODCCTRL
|
||||
DB 4
|
||||
DD OdcCtrl
|
||||
ENDM
|
||||
|
||||
TBLDRV_CONFIG_ENTRY_SLOWACCMODE MACRO SlowAccMode:REQ
|
||||
DB PSO_TBLDRV_SLOWACCMODE
|
||||
DB 1
|
||||
DB SlowAccMode
|
||||
ENDM
|
||||
|
||||
TBLDRV_CONFIG_ENTRY_RC2_IBT MACRO TgtDimm:REQ, IBT:REQ
|
||||
DB PSO_TBLDRV_RC2_IBT
|
||||
DB 2
|
||||
DB TgtDimm
|
||||
DB IBT
|
||||
ENDM
|
||||
|
||||
TBLDRV_OVERRIDE_MR0_CL MACRO RegValOfTcl:REQ, MR0CL13:REQ, MR0CL0:REQ
|
||||
DB PSO_TBLDRV_CONFIG
|
||||
DB 1
|
||||
DB CONFIG_DONT_CARE
|
||||
DB PSO_TBLDRV_MR0_CL
|
||||
DB 3
|
||||
DB RegValOfTcl
|
||||
DB MR0CL13
|
||||
DB MR0CL0
|
||||
ENDM
|
||||
|
||||
TBLDRV_OVERRIDE_MR0_WR MACRO RegValOfTwr:REQ, MR0WR:REQ
|
||||
DB PSO_TBLDRV_CONFIG
|
||||
DB 1
|
||||
DB CONFIG_DONT_CARE
|
||||
DB PSO_TBLDRV_MR0_WR
|
||||
DB 2
|
||||
DB RegValOfTcl
|
||||
DB MR0WR
|
||||
ENDM
|
||||
|
||||
TBLDRV_OVERRIDE_RC10_OPSPEED MACRO Frequency:REQ, MR10OPSPEED:REQ
|
||||
DB PSO_TBLDRV_CONFIG
|
||||
DB 1
|
||||
DB CONFIG_DONT_CARE
|
||||
DB PSO_TBLDRV_RC10_OPSPEED
|
||||
DB 5
|
||||
DD Frequency
|
||||
DB MR10OPSPEED
|
||||
ENDM
|
||||
|
||||
TBLDRV_CONFIG_ENTRY_LRDMM_IBT MACRO F0RC8:REQ, F1RC0:REQ, F1RC1:REQ, F1RC2:REQ
|
||||
DB PSO_TBLDRV_LRDIMM_IBT
|
||||
DB 4
|
||||
DB F0RC8
|
||||
DB F1RC0
|
||||
DB F1RC1
|
||||
DB F1RC2
|
||||
ENDM
|
||||
|
||||
;del TBLDRV_CONFIG_ENTRY_2D_TRAINING MACRO Training2dMode:REQ
|
||||
;del DB PSO_TBLDRV_2D_TRAINING
|
||||
;del DB 1
|
||||
;del DB Training2dMode
|
||||
;del ENDM
|
||||
|
||||
;
|
||||
; Macros for removing entries
|
||||
;
|
||||
INVALID_CONFIG_FLAG EQU 8000h
|
||||
|
||||
TBLDRV_INVALID_CONFIG MACRO
|
||||
DB PSO_TBLDRV_INVALID_TYPE
|
||||
DB 0
|
||||
ENDM
|
||||
; *****************************************************************************************
|
||||
; *
|
||||
; * END OF TABLE DRIVEN OVERRIDE MACROS
|
||||
; *
|
||||
; *****************************************************************************************
|
||||
185
src/vendorcode/amd/agesa/f15tn/Legacy/Proc/Dispatcher.c
Normal file
185
src/vendorcode/amd/agesa/f15tn/Legacy/Proc/Dispatcher.c
Normal file
@ -0,0 +1,185 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* AMD binary block interface
|
||||
*
|
||||
* Contains the block entry function dispatcher
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: Legacy
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
* ***************************************************************************
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* M O D U L E S U S E D
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
#include "AGESA.h"
|
||||
#include "amdlib.h"
|
||||
#include "Dispatcher.h"
|
||||
#include "Options.h"
|
||||
#include "Filecode.h"
|
||||
CODE_GROUP (G1_PEICC)
|
||||
RDATA_GROUP (G1_PEICC)
|
||||
|
||||
#define FILECODE LEGACY_PROC_DISPATCHER_FILECODE
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* D E F I N I T I O N S A N D M A C R O S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
extern CONST DISPATCH_TABLE DispatchTable[];
|
||||
extern AMD_MODULE_HEADER mCpuModuleID;
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* The Dispatcher is the entry point into the AGESA software. It takes a function
|
||||
* number as entry parameter in order to invoke the published function
|
||||
*
|
||||
* @param[in,out] ConfigPtr
|
||||
*
|
||||
* @return AGESA Status.
|
||||
*
|
||||
*/
|
||||
AGESA_STATUS
|
||||
CALLCONV
|
||||
AmdAgesaDispatcher (
|
||||
IN OUT VOID *ConfigPtr
|
||||
)
|
||||
{
|
||||
AGESA_STATUS Status;
|
||||
IMAGE_ENTRY ImageEntry;
|
||||
MODULE_ENTRY ModuleEntry;
|
||||
DISPATCH_TABLE *Entry;
|
||||
UINT32 ImageStart;
|
||||
UINT32 ImageEnd;
|
||||
AMD_IMAGE_HEADER* AltImagePtr;
|
||||
|
||||
Status = AGESA_UNSUPPORTED;
|
||||
ImageEntry = NULL;
|
||||
ModuleEntry = NULL;
|
||||
ImageStart = 0xFFF00000;
|
||||
ImageEnd = 0xFFFFFFFF;
|
||||
AltImagePtr = NULL;
|
||||
|
||||
Entry = (DISPATCH_TABLE *) DispatchTable;
|
||||
while (Entry->FunctionId != 0) {
|
||||
if ((((AMD_CONFIG_PARAMS *) ConfigPtr)->Func) == Entry->FunctionId) {
|
||||
Status = Entry->EntryPoint (ConfigPtr);
|
||||
break;
|
||||
}
|
||||
Entry++;
|
||||
}
|
||||
|
||||
// 2. Try next dispatcher if possible, and we have not already got status back
|
||||
if ((mCpuModuleID.NextBlock != NULL) && (Status == AGESA_UNSUPPORTED)) {
|
||||
ModuleEntry = (MODULE_ENTRY) /* (UINT64) */ mCpuModuleID.NextBlock->ModuleDispatcher;
|
||||
if (ModuleEntry != NULL) {
|
||||
Status = (*ModuleEntry) (ConfigPtr);
|
||||
}
|
||||
}
|
||||
|
||||
// 3. If not this image specific function, see if we can find alternative image instead
|
||||
if (Status == AGESA_UNSUPPORTED) {
|
||||
if ((((AMD_CONFIG_PARAMS *)ConfigPtr)->AltImageBasePtr != 0xFFFFFFFF ) || (((AMD_CONFIG_PARAMS *)ConfigPtr)->AltImageBasePtr != 0)) {
|
||||
ImageStart = ((AMD_CONFIG_PARAMS *)ConfigPtr)->AltImageBasePtr;
|
||||
ImageEnd = ImageStart + 4;
|
||||
// Locate/test image base that matches this component
|
||||
AltImagePtr = LibAmdLocateImage ((VOID *) /* (UINT64) */ImageStart, (VOID *) /* (UINT64) */ImageEnd, 4096, (CHAR8 *) AGESA_ID);
|
||||
if (AltImagePtr != NULL) {
|
||||
//Invoke alternative Image
|
||||
ImageEntry = (IMAGE_ENTRY) (/* (UINT64) */ AltImagePtr + AltImagePtr->EntryPointAddress);
|
||||
Status = (*ImageEntry) (ConfigPtr);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return (Status);
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* The host environment interface of callout.
|
||||
*
|
||||
* @param[in] Func
|
||||
* @param[in] Data
|
||||
* @param[in,out] ConfigPtr
|
||||
*
|
||||
* @return The AGESA Status returned from the callout.
|
||||
*
|
||||
*/
|
||||
AGESA_STATUS
|
||||
CALLCONV
|
||||
AmdAgesaCallout (
|
||||
IN UINT32 Func,
|
||||
IN UINT32 Data,
|
||||
IN OUT VOID *ConfigPtr
|
||||
)
|
||||
{
|
||||
UINT32 Result;
|
||||
Result = AGESA_UNSUPPORTED;
|
||||
if (((AMD_CONFIG_PARAMS *) ConfigPtr)->CalloutPtr == NULL) {
|
||||
return Result;
|
||||
}
|
||||
|
||||
Result = (((AMD_CONFIG_PARAMS *) ConfigPtr)->CalloutPtr) (Func, Data, ConfigPtr);
|
||||
return (Result);
|
||||
}
|
||||
487
src/vendorcode/amd/agesa/f15tn/Legacy/Proc/agesaCallouts.c
Normal file
487
src/vendorcode/amd/agesa/f15tn/Legacy/Proc/agesaCallouts.c
Normal file
@ -0,0 +1,487 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* AMD CPU AGESA Callout Functions
|
||||
*
|
||||
* Contains code to set / get useful platform information.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: Common
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*
|
||||
*/
|
||||
/*****************************************************************************
|
||||
* AMD Generic Encapsulated Software Architecture
|
||||
*
|
||||
* Description: agesaCallouts.c - AGESA Call out functions
|
||||
*
|
||||
******************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* M O D U L E S U S E D
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
#include "AGESA.h"
|
||||
#include "cpuRegisters.h"
|
||||
#include "Dispatcher.h"
|
||||
#include "cpuServices.h"
|
||||
#include "Ids.h"
|
||||
#include "Filecode.h"
|
||||
#include "FchPlatform.h"
|
||||
#define FILECODE LEGACY_PROC_AGESACALLOUTS_FILECODE
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* D E F I N I T I O N S A N D M A C R O S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* T Y P E D E F S A N D S T R U C T U R E S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* E X P O R T E D F U N C T I O N S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* E X P O R T E D F U N C T I O N S - (AGESA ONLY)
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
*
|
||||
* Call the host environment interface to do the warm or cold reset.
|
||||
*
|
||||
* @param[in] ResetType Warm or Cold Reset is requested
|
||||
* @param[in,out] StdHeader Config header
|
||||
*
|
||||
*/
|
||||
VOID
|
||||
AgesaDoReset (
|
||||
IN UINTN ResetType,
|
||||
IN OUT AMD_CONFIG_PARAMS *StdHeader
|
||||
)
|
||||
{
|
||||
AGESA_STATUS Status;
|
||||
WARM_RESET_REQUEST Request;
|
||||
|
||||
// Clear warm request bit and set state bits to the current post stage
|
||||
GetWarmResetFlag (StdHeader, &Request);
|
||||
Request.RequestBit = FALSE;
|
||||
Request.StateBits = Request.PostStage;
|
||||
SetWarmResetFlag (StdHeader, &Request);
|
||||
|
||||
Status = AmdAgesaCallout (AGESA_DO_RESET, (UINT32)ResetType, (VOID *) StdHeader);
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
*
|
||||
* Call the host environment interface to allocate buffer in main system memory.
|
||||
*
|
||||
* @param[in] FcnData
|
||||
* @param[in,out] AllocParams Heap manager parameters
|
||||
*
|
||||
* @return The AGESA Status returned from the callout.
|
||||
*
|
||||
*/
|
||||
AGESA_STATUS
|
||||
AgesaAllocateBuffer (
|
||||
IN UINTN FcnData,
|
||||
IN OUT AGESA_BUFFER_PARAMS *AllocParams
|
||||
)
|
||||
{
|
||||
AGESA_STATUS Status;
|
||||
|
||||
Status = AmdAgesaCallout (AGESA_ALLOCATE_BUFFER, (UINT32)FcnData, (VOID *) AllocParams);
|
||||
|
||||
return Status;
|
||||
}
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Call the host environment interface to deallocate buffer in main system memory.
|
||||
*
|
||||
* @param[in] FcnData
|
||||
* @param[in,out] DeallocParams Heap Manager parameters
|
||||
*
|
||||
* @return The AGESA Status returned from the callout.
|
||||
*/
|
||||
AGESA_STATUS
|
||||
AgesaDeallocateBuffer (
|
||||
IN UINTN FcnData,
|
||||
IN OUT AGESA_BUFFER_PARAMS *DeallocParams
|
||||
)
|
||||
{
|
||||
AGESA_STATUS Status;
|
||||
|
||||
Status = AmdAgesaCallout (AGESA_DEALLOCATE_BUFFER, (UINT32)FcnData, (VOID *) DeallocParams);
|
||||
|
||||
return Status;
|
||||
}
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
*
|
||||
* Call the host environment interface to Locate buffer Pointer in main system memory
|
||||
*
|
||||
* @param[in] FcnData
|
||||
* @param[in,out] LocateParams Heap manager parameters
|
||||
*
|
||||
* @return The AGESA Status returned from the callout.
|
||||
*
|
||||
*/
|
||||
AGESA_STATUS
|
||||
AgesaLocateBuffer (
|
||||
IN UINTN FcnData,
|
||||
IN OUT AGESA_BUFFER_PARAMS *LocateParams
|
||||
)
|
||||
{
|
||||
AGESA_STATUS Status;
|
||||
|
||||
Status = AmdAgesaCallout (AGESA_LOCATE_BUFFER, (UINT32)FcnData, (VOID *) LocateParams);
|
||||
|
||||
return Status;
|
||||
}
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Call the host environment interface to launch APs
|
||||
*
|
||||
* @param[in] ApicIdOfCore
|
||||
* @param[in,out] LaunchApParams
|
||||
*
|
||||
* @return The AGESA Status returned from the callout.
|
||||
*
|
||||
*/
|
||||
AGESA_STATUS
|
||||
AgesaRunFcnOnAp (
|
||||
IN UINTN ApicIdOfCore,
|
||||
IN AP_EXE_PARAMS *LaunchApParams
|
||||
)
|
||||
{
|
||||
AGESA_STATUS Status;
|
||||
|
||||
Status = AmdAgesaCallout (AGESA_RUNFUNC_ONAP, (UINT32)ApicIdOfCore, (VOID *) LaunchApParams);
|
||||
|
||||
return Status;
|
||||
}
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Call the host environment interface to read an SPD's content.
|
||||
*
|
||||
* @param[in] FcnData
|
||||
* @param[in,out] ReadSpd
|
||||
*
|
||||
* @return The AGESA Status returned from the callout.
|
||||
*
|
||||
*/
|
||||
AGESA_STATUS
|
||||
AgesaReadSpd (
|
||||
IN UINTN FcnData,
|
||||
IN OUT AGESA_READ_SPD_PARAMS *ReadSpd
|
||||
)
|
||||
{
|
||||
AGESA_STATUS Status;
|
||||
|
||||
Status = AmdAgesaCallout (AGESA_READ_SPD, (UINT32)FcnData, ReadSpd);
|
||||
|
||||
return Status;
|
||||
}
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Call the host environment interface to read an SPD's content.
|
||||
*
|
||||
* @param[in] FcnData
|
||||
* @param[in,out] ReadSpd
|
||||
*
|
||||
* @return The AGESA Status returned from the callout.
|
||||
*
|
||||
*/
|
||||
AGESA_STATUS
|
||||
AgesaReadSpdRecovery (
|
||||
IN UINTN FcnData,
|
||||
IN OUT AGESA_READ_SPD_PARAMS *ReadSpd
|
||||
)
|
||||
{
|
||||
AGESA_STATUS Status;
|
||||
|
||||
Status = AmdAgesaCallout (AGESA_READ_SPD_RECOVERY, (UINT32)FcnData, ReadSpd);
|
||||
|
||||
return Status;
|
||||
}
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Call the host environment interface to provide a user hook opportunity.
|
||||
*
|
||||
* @param[in] FcnData
|
||||
* @param[in,out] MemData
|
||||
*
|
||||
* @return The AGESA Status returned from the callout.
|
||||
*
|
||||
*/
|
||||
AGESA_STATUS
|
||||
AgesaHookBeforeDramInitRecovery (
|
||||
IN UINTN FcnData,
|
||||
IN OUT MEM_DATA_STRUCT *MemData
|
||||
)
|
||||
{
|
||||
AGESA_STATUS Status;
|
||||
|
||||
Status = AmdAgesaCallout (AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, (UINT32)FcnData, MemData);
|
||||
|
||||
return Status;
|
||||
}
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Call the host environment interface to provide a user hook opportunity.
|
||||
*
|
||||
* @param[in] SocketIdModuleId - (SocketID << 8) | ModuleId
|
||||
* @param[in,out] MemData
|
||||
*
|
||||
* @return The AGESA Status returned from the callout.
|
||||
*
|
||||
*/
|
||||
AGESA_STATUS
|
||||
AgesaHookBeforeDramInit (
|
||||
IN UINTN SocketIdModuleId,
|
||||
IN OUT MEM_DATA_STRUCT *MemData
|
||||
)
|
||||
{
|
||||
AGESA_STATUS Status;
|
||||
|
||||
Status = AmdAgesaCallout (AGESA_HOOKBEFORE_DRAM_INIT, (UINT32)SocketIdModuleId, MemData);
|
||||
|
||||
return Status;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Call the host environment interface to provide a user hook opportunity.
|
||||
*
|
||||
* @param[in] SocketIdModuleId - (SocketID << 8) | ModuleId
|
||||
* @param[in,out] MemData
|
||||
*
|
||||
* @return The AGESA Status returned from the callout.
|
||||
*
|
||||
*/
|
||||
AGESA_STATUS
|
||||
AgesaHookBeforeDQSTraining (
|
||||
IN UINTN SocketIdModuleId,
|
||||
IN OUT MEM_DATA_STRUCT *MemData
|
||||
)
|
||||
{
|
||||
AGESA_STATUS Status;
|
||||
|
||||
Status = AmdAgesaCallout (AGESA_HOOKBEFORE_DQS_TRAINING, (UINT32)SocketIdModuleId, MemData);
|
||||
|
||||
return Status;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Call the host environment interface to provide a user hook opportunity.
|
||||
*
|
||||
* @param[in] FcnData
|
||||
* @param[in,out] MemData
|
||||
*
|
||||
* @return The AGESA Status returned from the callout.
|
||||
*
|
||||
*/
|
||||
AGESA_STATUS
|
||||
AgesaHookBeforeExitSelfRefresh (
|
||||
IN UINTN FcnData,
|
||||
IN OUT MEM_DATA_STRUCT *MemData
|
||||
)
|
||||
{
|
||||
AGESA_STATUS Status;
|
||||
|
||||
Status = AmdAgesaCallout (AGESA_HOOKBEFORE_EXIT_SELF_REF, (UINT32)FcnData, MemData);
|
||||
|
||||
return Status;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Call the host environment interface to provide a user hook opportunity.
|
||||
*
|
||||
* @param[in] Data
|
||||
* @param[in,out] IdsCalloutData
|
||||
*
|
||||
* @return The AGESA Status returned from the callout.
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
AGESA_STATUS
|
||||
AgesaGetIdsData (
|
||||
IN UINTN Data,
|
||||
IN OUT IDS_CALLOUT_STRUCT *IdsCalloutData
|
||||
)
|
||||
{
|
||||
AGESA_STATUS Status;
|
||||
|
||||
Status = AmdAgesaCallout (AGESA_GET_IDS_INIT_DATA, (UINT32)Data, IdsCalloutData);
|
||||
|
||||
return Status;
|
||||
}
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* PCIE slot reset control
|
||||
*
|
||||
*
|
||||
*
|
||||
* @param[in] FcnData Function data
|
||||
* @param[in] ResetInfo Reset information
|
||||
* @retval Status Agesa status
|
||||
*/
|
||||
|
||||
AGESA_STATUS
|
||||
AgesaPcieSlotResetControl (
|
||||
IN UINTN FcnData,
|
||||
IN PCIe_SLOT_RESET_INFO *ResetInfo
|
||||
)
|
||||
{
|
||||
AGESA_STATUS Status;
|
||||
Status = AmdAgesaCallout (AGESA_GNB_PCIE_SLOT_RESET, (UINT32) FcnData, ResetInfo);
|
||||
return Status;
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Get VBIOS image
|
||||
*
|
||||
*
|
||||
*
|
||||
* @param[in] FcnData Function data
|
||||
* @param[in] VbiosImageInfo VBIOS image info
|
||||
* @retval Status Agesa status
|
||||
*/
|
||||
|
||||
AGESA_STATUS
|
||||
AgesaGetVbiosImage (
|
||||
IN UINTN FcnData,
|
||||
IN OUT GFX_VBIOS_IMAGE_INFO *VbiosImageInfo
|
||||
)
|
||||
{
|
||||
AGESA_STATUS Status;
|
||||
Status = AmdAgesaCallout (AGESA_GNB_GFX_GET_VBIOS_IMAGE, (UINT32) FcnData, VbiosImageInfo);
|
||||
return Status;
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* OEM callout function for FCH data override
|
||||
*
|
||||
*
|
||||
* @param[in] FchData FCH data pointer
|
||||
* @retval Status This feature is not supported
|
||||
*/
|
||||
|
||||
AGESA_STATUS
|
||||
AgesaFchOemCallout (
|
||||
IN VOID *FchData
|
||||
)
|
||||
{
|
||||
AGESA_STATUS Status; Status = AmdAgesaCallout(AGESA_FCH_OEM_CALLOUT, (UINT32)FchData, ((FCH_DATA_BLOCK *)FchData)->StdHeader); return Status; //return AGESA_UNSUPPORTED;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
*
|
||||
* @param[in] SocketIdModuleId - (SocketID << 8) | ModuleId
|
||||
* @param[in,out] MemData
|
||||
*
|
||||
* @return The AGESA Status returned from the callout.
|
||||
*
|
||||
*/
|
||||
AGESA_STATUS
|
||||
excel331 (
|
||||
IN UINTN SocketIdModuleId,
|
||||
IN OUT MEM_DATA_STRUCT *MemData
|
||||
)
|
||||
{
|
||||
AGESA_STATUS Status;
|
||||
|
||||
Status = AmdAgesaCallout (0x00028146ul , (UINT32)SocketIdModuleId, MemData);
|
||||
|
||||
return Status;
|
||||
}
|
||||
2702
src/vendorcode/amd/agesa/f15tn/Legacy/Proc/arch2008.asm
Normal file
2702
src/vendorcode/amd/agesa/f15tn/Legacy/Proc/arch2008.asm
Normal file
File diff suppressed because it is too large
Load Diff
419
src/vendorcode/amd/agesa/f15tn/Legacy/Proc/hobTransfer.c
Normal file
419
src/vendorcode/amd/agesa/f15tn/Legacy/Proc/hobTransfer.c
Normal file
@ -0,0 +1,419 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* AMD Hob Transfer functions.
|
||||
*
|
||||
* Contains code that copy Heap to temp memory or main memory.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: CPU
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*
|
||||
*/
|
||||
/*
|
||||
******************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* M O D U L E S U S E D
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#include "AGESA.h"
|
||||
#include "amdlib.h"
|
||||
#include "Ids.h"
|
||||
#include "cpuRegisters.h"
|
||||
#include "GeneralServices.h"
|
||||
#include "cpuServices.h"
|
||||
#include "cpuCacheInit.h"
|
||||
#include "cpuFamilyTranslation.h"
|
||||
#include "heapManager.h"
|
||||
#include "cpuLateInit.h"
|
||||
#include "Filecode.h"
|
||||
CODE_GROUP (G1_PEICC)
|
||||
RDATA_GROUP (G1_PEICC)
|
||||
|
||||
#define FILECODE LEGACY_PROC_HOBTRANSFER_FILECODE
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* D E F I N I T I O N S A N D M A C R O S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* T Y P E D E F S A N D S T R U C T U R E S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* P U B L I C F U N C T I O N S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* E X P O R T E D F U N C T I O N S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
extern BUILD_OPT_CFG UserOptions;
|
||||
|
||||
/* -----------------------------------------------------------------------------*/
|
||||
/**
|
||||
*
|
||||
* CopyHeapToTempRamAtPost
|
||||
*
|
||||
* This function copies BSP heap content to RAM
|
||||
*
|
||||
* @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct.
|
||||
*
|
||||
* @retval AGESA_STATUS
|
||||
*
|
||||
*/
|
||||
AGESA_STATUS
|
||||
CopyHeapToTempRamAtPost (
|
||||
IN OUT AMD_CONFIG_PARAMS *StdHeader
|
||||
)
|
||||
{
|
||||
UINT8 *BaseAddressInCache;
|
||||
UINT8 *BaseAddressInTempMem;
|
||||
UINT8 *Source;
|
||||
UINT8 *Destination;
|
||||
UINT8 AlignTo16ByteInCache;
|
||||
UINT8 AlignTo16ByteInTempMem;
|
||||
UINT8 Ignored;
|
||||
UINT32 SizeOfNodeData;
|
||||
UINT32 TotalSize;
|
||||
UINT32 HeapRamFixMtrr;
|
||||
UINT32 HeapRamVariableMtrr;
|
||||
UINT32 HeapInCacheOffset;
|
||||
UINT64 MsrData;
|
||||
UINT64 VariableMtrrBase;
|
||||
UINT64 VariableMtrrMask;
|
||||
UINTN AmdHeapRamAddress;
|
||||
AGESA_STATUS IgnoredStatus;
|
||||
BUFFER_NODE *HeapInCache;
|
||||
BUFFER_NODE *HeapInTempMem;
|
||||
HEAP_MANAGER *HeapManagerInCache;
|
||||
HEAP_MANAGER *HeapManagerInTempMem;
|
||||
CACHE_INFO *CacheInfoPtr;
|
||||
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
|
||||
|
||||
AmdHeapRamAddress = (UINTN) UserOptions.CfgHeapDramAddress;
|
||||
//
|
||||
//If the user define address above 1M, Mem Init has already set
|
||||
//whole available memory as WB cacheable.
|
||||
//
|
||||
if (AmdHeapRamAddress < 0x100000) {
|
||||
// Region below 1MB
|
||||
// Fixed MTTR region
|
||||
// turn on modification bit
|
||||
LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
|
||||
MsrData |= 0x80000;
|
||||
LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader);
|
||||
|
||||
if (AmdHeapRamAddress >= 0xC0000) {
|
||||
//
|
||||
// 0xC0000 ~ 0xFFFFF
|
||||
//
|
||||
HeapRamFixMtrr = (UINT32) (AMD_MTRR_FIX4k_C0000 + (((AmdHeapRamAddress >> 16) & 0x3) * 2));
|
||||
MsrData = AMD_MTRR_FIX4K_UC_DRAM;
|
||||
LibAmdMsrWrite (HeapRamFixMtrr, &MsrData, StdHeader);
|
||||
LibAmdMsrWrite ((HeapRamFixMtrr + 1), &MsrData, StdHeader);
|
||||
} else if (AmdHeapRamAddress >= 0x80000) {
|
||||
//
|
||||
// 0x80000~0xBFFFF
|
||||
//
|
||||
HeapRamFixMtrr = (UINT32) (AMD_MTRR_FIX16k_80000 + ((AmdHeapRamAddress >> 17) & 0x1));
|
||||
MsrData = AMD_MTRR_FIX16K_UC_DRAM;
|
||||
LibAmdMsrWrite (HeapRamFixMtrr, &MsrData, StdHeader);
|
||||
} else {
|
||||
//
|
||||
// 0x0 ~ 0x7FFFF
|
||||
//
|
||||
LibAmdMsrRead (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader);
|
||||
MsrData = MsrData & (~(0xFF << (8 * ((AmdHeapRamAddress >> 16) & 0x7))));
|
||||
MsrData = MsrData | (AMD_MTRR_FIX64K_UC_DRAM << (8 * ((AmdHeapRamAddress >> 16) & 0x7)));
|
||||
LibAmdMsrWrite (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader);
|
||||
}
|
||||
|
||||
// Turn on MTTR enable bit and turn off modification bit
|
||||
LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
|
||||
MsrData |= 0x40000;
|
||||
MsrData &= 0xFFFFFFFFFFF7FFFF;
|
||||
LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader);
|
||||
} else {
|
||||
// Region above 1MB
|
||||
// Variable MTTR region
|
||||
// Get family specific cache Info
|
||||
GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
|
||||
FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **) &CacheInfoPtr, &Ignored, StdHeader);
|
||||
|
||||
// Find an empty MTRRphysBase/MTRRphysMask
|
||||
for (HeapRamVariableMtrr = AMD_MTRR_VARIABLE_HEAP_BASE;
|
||||
HeapRamVariableMtrr >= AMD_MTRR_VARIABLE_BASE0;
|
||||
HeapRamVariableMtrr--) {
|
||||
LibAmdMsrRead (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader);
|
||||
LibAmdMsrRead ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader);
|
||||
if ((VariableMtrrBase == 0) && (VariableMtrrMask == 0)) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (HeapRamVariableMtrr < AMD_MTRR_VARIABLE_BASE0) {
|
||||
// All variable MTRR is used.
|
||||
ASSERT (FALSE);
|
||||
}
|
||||
|
||||
// Set variable MTRR base and mask
|
||||
// If the address ranges of two or more MTRRs overlap
|
||||
// and if at least one of the memory types is UC, the UC memory type is used.
|
||||
VariableMtrrBase = (UINT64) (AmdHeapRamAddress & CacheInfoPtr->HeapBaseMask);
|
||||
VariableMtrrMask = CacheInfoPtr->VariableMtrrHeapMask & AMD_HEAP_MTRR_MASK;
|
||||
LibAmdMsrWrite (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader);
|
||||
LibAmdMsrWrite ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader);
|
||||
}
|
||||
// Copying Heap content
|
||||
if (IsBsp (StdHeader, &IgnoredStatus)) {
|
||||
TotalSize = sizeof (HEAP_MANAGER);
|
||||
SizeOfNodeData = 0;
|
||||
AlignTo16ByteInTempMem = 0;
|
||||
BaseAddressInCache = (UINT8 *) (UINT32)StdHeader->HeapBasePtr;
|
||||
HeapManagerInCache = (HEAP_MANAGER *) BaseAddressInCache;
|
||||
HeapInCacheOffset = HeapManagerInCache->FirstActiveBufferOffset;
|
||||
HeapInCache = (BUFFER_NODE *) (BaseAddressInCache + HeapInCacheOffset);
|
||||
|
||||
BaseAddressInTempMem = (UINT8 *) (UINTN) UserOptions.CfgHeapDramAddress;
|
||||
HeapManagerInTempMem = (HEAP_MANAGER *) BaseAddressInTempMem;
|
||||
HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize);
|
||||
|
||||
// copy heap from cache to temp memory.
|
||||
// only heap with persist great than HEAP_LOCAL_CACHE will be copied.
|
||||
// Note: Only copy heap with persist greater than HEAP_LOCAL_CACHE.
|
||||
while (HeapInCacheOffset != AMD_HEAP_INVALID_HEAP_OFFSET) {
|
||||
if (HeapInCache->Persist > HEAP_LOCAL_CACHE) {
|
||||
AlignTo16ByteInCache = HeapInCache->PadSize;
|
||||
AlignTo16ByteInTempMem = (UINT8) ((0x10 - (((UINTN) (VOID *) HeapInTempMem + sizeof (BUFFER_NODE) + SIZE_OF_SENTINEL) & 0xF)) & 0xF);
|
||||
SizeOfNodeData = HeapInCache->BufferSize - AlignTo16ByteInCache;
|
||||
TotalSize = (UINT32) (TotalSize + sizeof (BUFFER_NODE) + SizeOfNodeData + AlignTo16ByteInTempMem);
|
||||
Source = (UINT8 *) HeapInCache + sizeof (BUFFER_NODE) + AlignTo16ByteInCache;
|
||||
Destination = (UINT8 *) HeapInTempMem + sizeof (BUFFER_NODE) + AlignTo16ByteInTempMem;
|
||||
LibAmdMemCopy (HeapInTempMem, HeapInCache, sizeof (BUFFER_NODE), StdHeader);
|
||||
LibAmdMemCopy (Destination, Source, SizeOfNodeData, StdHeader);
|
||||
HeapInTempMem->OffsetOfNextNode = TotalSize;
|
||||
HeapInTempMem->BufferSize = SizeOfNodeData + AlignTo16ByteInTempMem;
|
||||
HeapInTempMem->PadSize = AlignTo16ByteInTempMem;
|
||||
HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize);
|
||||
}
|
||||
HeapInCacheOffset = HeapInCache->OffsetOfNextNode;
|
||||
HeapInCache = (BUFFER_NODE *) (BaseAddressInCache + HeapInCacheOffset);
|
||||
}
|
||||
// initialize heap manager
|
||||
if (TotalSize == sizeof (HEAP_MANAGER)) {
|
||||
// heap is empty
|
||||
HeapManagerInTempMem->UsedSize = sizeof (HEAP_MANAGER);
|
||||
HeapManagerInTempMem->FirstActiveBufferOffset = AMD_HEAP_INVALID_HEAP_OFFSET;
|
||||
HeapManagerInTempMem->FirstFreeSpaceOffset = sizeof (HEAP_MANAGER);
|
||||
} else {
|
||||
// heap is NOT empty
|
||||
HeapManagerInTempMem->UsedSize = TotalSize;
|
||||
HeapManagerInTempMem->FirstActiveBufferOffset = sizeof (HEAP_MANAGER);
|
||||
HeapManagerInTempMem->FirstFreeSpaceOffset = TotalSize;
|
||||
HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize - SizeOfNodeData - AlignTo16ByteInTempMem - sizeof (BUFFER_NODE));
|
||||
HeapInTempMem->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET;
|
||||
HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize);
|
||||
}
|
||||
// heap signature
|
||||
HeapManagerInCache->Signature = 0x00000000;
|
||||
HeapManagerInTempMem->Signature = HEAP_SIGNATURE_VALID;
|
||||
// Free space node
|
||||
HeapInTempMem->BufferSize = (UINT32) (AMD_HEAP_SIZE_PER_CORE - TotalSize);
|
||||
HeapInTempMem->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET;
|
||||
}
|
||||
return AGESA_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
/* -----------------------------------------------------------------------------*/
|
||||
/**
|
||||
*
|
||||
* CopyHeapToMainRamAtPost
|
||||
*
|
||||
* This function copies Temp Ram heap content to Main Ram
|
||||
*
|
||||
* @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct.
|
||||
*
|
||||
* @retval AGESA_STATUS
|
||||
*
|
||||
*/
|
||||
AGESA_STATUS
|
||||
CopyHeapToMainRamAtPost (
|
||||
IN OUT AMD_CONFIG_PARAMS *StdHeader
|
||||
)
|
||||
{
|
||||
UINT8 *BaseAddressInTempMem;
|
||||
UINT8 *BaseAddressInMainMem;
|
||||
UINT8 *Source;
|
||||
UINT8 *Destination;
|
||||
UINT8 AlignTo16ByteInTempMem;
|
||||
UINT8 AlignTo16ByteInMainMem;
|
||||
UINT8 Ignored;
|
||||
UINT32 SizeOfNodeData;
|
||||
UINT32 TotalSize;
|
||||
UINT32 HeapInTempMemOffset;
|
||||
UINT32 HeapRamVariableMtrr;
|
||||
UINT64 VariableMtrrBase;
|
||||
UINT64 VariableMtrrMask;
|
||||
AGESA_STATUS IgnoredStatus;
|
||||
BUFFER_NODE *HeapInTempMem;
|
||||
BUFFER_NODE *HeapInMainMem;
|
||||
HEAP_MANAGER *HeapManagerInTempMem;
|
||||
HEAP_MANAGER *HeapManagerInMainMem;
|
||||
AGESA_BUFFER_PARAMS AgesaBuffer;
|
||||
CACHE_INFO *CacheInfoPtr;
|
||||
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
|
||||
|
||||
if (IsBsp (StdHeader, &IgnoredStatus)) {
|
||||
TotalSize = sizeof (HEAP_MANAGER);
|
||||
SizeOfNodeData = 0;
|
||||
AlignTo16ByteInMainMem = 0;
|
||||
BaseAddressInTempMem = (UINT8 *)(UINT32) StdHeader->HeapBasePtr;
|
||||
HeapManagerInTempMem = (HEAP_MANAGER *)(UINT32) StdHeader->HeapBasePtr;
|
||||
HeapInTempMemOffset = HeapManagerInTempMem->FirstActiveBufferOffset;
|
||||
HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + HeapInTempMemOffset);
|
||||
|
||||
AgesaBuffer.StdHeader = *StdHeader;
|
||||
AgesaBuffer.BufferHandle = AMD_HEAP_IN_MAIN_MEMORY_HANDLE;
|
||||
AgesaBuffer.BufferLength = AMD_HEAP_SIZE_PER_CORE;
|
||||
if (AgesaAllocateBuffer (0, &AgesaBuffer) != AGESA_SUCCESS) {
|
||||
return AGESA_ERROR;
|
||||
}
|
||||
BaseAddressInMainMem = (UINT8 *) AgesaBuffer.BufferPointer;
|
||||
HeapManagerInMainMem = (HEAP_MANAGER *) BaseAddressInMainMem;
|
||||
HeapInMainMem = (BUFFER_NODE *) (BaseAddressInMainMem + TotalSize);
|
||||
LibAmdMemFill (BaseAddressInMainMem, 0x00, AMD_HEAP_SIZE_PER_CORE, StdHeader);
|
||||
// copy heap from temp memory to main memory.
|
||||
// only heap with persist great than HEAP_TEMP_MEM will be copied.
|
||||
// Note: Only copy heap buffers with persist greater than HEAP_TEMP_MEM.
|
||||
while (HeapInTempMemOffset != AMD_HEAP_INVALID_HEAP_OFFSET) {
|
||||
if (HeapInTempMem->Persist > HEAP_TEMP_MEM) {
|
||||
AlignTo16ByteInTempMem = HeapInTempMem->PadSize;
|
||||
AlignTo16ByteInMainMem = (UINT8) ((0x10 - (((UINTN) (VOID *) HeapInMainMem + sizeof (BUFFER_NODE) + SIZE_OF_SENTINEL) & 0xF)) & 0xF);
|
||||
SizeOfNodeData = HeapInTempMem->BufferSize - AlignTo16ByteInTempMem;
|
||||
TotalSize = (UINT32) (TotalSize + sizeof (BUFFER_NODE) + SizeOfNodeData + AlignTo16ByteInMainMem);
|
||||
Source = (UINT8 *) HeapInTempMem + sizeof (BUFFER_NODE) + AlignTo16ByteInTempMem;
|
||||
Destination = (UINT8 *) HeapInMainMem + sizeof (BUFFER_NODE) + AlignTo16ByteInMainMem;
|
||||
LibAmdMemCopy (HeapInMainMem, HeapInTempMem, sizeof (BUFFER_NODE), StdHeader);
|
||||
LibAmdMemCopy (Destination, Source, SizeOfNodeData, StdHeader);
|
||||
HeapInMainMem->OffsetOfNextNode = TotalSize;
|
||||
HeapInMainMem->BufferSize = SizeOfNodeData + AlignTo16ByteInMainMem;
|
||||
HeapInMainMem->PadSize = AlignTo16ByteInMainMem;
|
||||
HeapInMainMem = (BUFFER_NODE *) (BaseAddressInMainMem + TotalSize);
|
||||
}
|
||||
HeapInTempMemOffset = HeapInTempMem->OffsetOfNextNode;
|
||||
HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + HeapInTempMemOffset);
|
||||
}
|
||||
// initialize heap manager
|
||||
if (TotalSize == sizeof (HEAP_MANAGER)) {
|
||||
// heap is empty
|
||||
HeapManagerInMainMem->UsedSize = sizeof (HEAP_MANAGER);
|
||||
HeapManagerInMainMem->FirstActiveBufferOffset = AMD_HEAP_INVALID_HEAP_OFFSET;
|
||||
HeapManagerInMainMem->FirstFreeSpaceOffset = sizeof (HEAP_MANAGER);
|
||||
} else {
|
||||
// heap is NOT empty
|
||||
HeapManagerInMainMem->UsedSize = TotalSize;
|
||||
HeapManagerInMainMem->FirstActiveBufferOffset = sizeof (HEAP_MANAGER);
|
||||
HeapManagerInMainMem->FirstFreeSpaceOffset = TotalSize;
|
||||
HeapInMainMem = (BUFFER_NODE *) (BaseAddressInMainMem + TotalSize - SizeOfNodeData - AlignTo16ByteInMainMem - sizeof (BUFFER_NODE));
|
||||
HeapInMainMem->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET;
|
||||
HeapInMainMem = (BUFFER_NODE *) (BaseAddressInMainMem + TotalSize);
|
||||
}
|
||||
// heap signature
|
||||
HeapManagerInTempMem->Signature = 0x00000000;
|
||||
HeapManagerInMainMem->Signature = HEAP_SIGNATURE_VALID;
|
||||
// Free space node
|
||||
HeapInMainMem->BufferSize = AMD_HEAP_SIZE_PER_CORE - TotalSize;
|
||||
HeapInMainMem->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET;
|
||||
}
|
||||
// if address of heap in temp memory is above 1M, then we must used one variable MTRR.
|
||||
if ( (UINTN) StdHeader->HeapBasePtr >= 0x100000) {
|
||||
// Find out which variable MTRR was used in CopyHeapToTempRamAtPost.
|
||||
GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
|
||||
FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **) &CacheInfoPtr, &Ignored, StdHeader);
|
||||
for (HeapRamVariableMtrr = AMD_MTRR_VARIABLE_HEAP_BASE;
|
||||
HeapRamVariableMtrr >= AMD_MTRR_VARIABLE_BASE0;
|
||||
HeapRamVariableMtrr--) {
|
||||
LibAmdMsrRead (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader);
|
||||
LibAmdMsrRead ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader);
|
||||
if ((VariableMtrrBase == (UINT64) (UINTN) (StdHeader->HeapBasePtr & CacheInfoPtr->HeapBaseMask)) &&
|
||||
(VariableMtrrMask == (UINT64) (CacheInfoPtr->VariableMtrrHeapMask & AMD_HEAP_MTRR_MASK))) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (HeapRamVariableMtrr >= AMD_MTRR_VARIABLE_BASE0) {
|
||||
// Clear variable MTRR which set in CopyHeapToTempRamAtPost.
|
||||
VariableMtrrBase = 0;
|
||||
VariableMtrrMask = 0;
|
||||
LibAmdMsrWrite (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader);
|
||||
LibAmdMsrWrite ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader);
|
||||
}
|
||||
}
|
||||
return AGESA_SUCCESS;
|
||||
}
|
||||
3116
src/vendorcode/amd/agesa/f15tn/Legacy/agesa.inc
Normal file
3116
src/vendorcode/amd/agesa/f15tn/Legacy/agesa.inc
Normal file
File diff suppressed because it is too large
Load Diff
488
src/vendorcode/amd/agesa/f15tn/Legacy/amd.inc
Normal file
488
src/vendorcode/amd/agesa/f15tn/Legacy/amd.inc
Normal file
@ -0,0 +1,488 @@
|
||||
; ****************************************************************************
|
||||
; *
|
||||
; * @file
|
||||
; *
|
||||
; * Agesa structures and definitions
|
||||
; *
|
||||
; * Contains AMD AGESA core interface
|
||||
; *
|
||||
; * @xrefitem bom "File Content Label" "Release Content"
|
||||
; * @e project: AGESA
|
||||
; * @e sub-project: Include
|
||||
; * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
;
|
||||
; ****************************************************************************
|
||||
; *
|
||||
; * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
; *
|
||||
; * AMD is granting you permission to use this software (the Materials)
|
||||
; * pursuant to the terms and conditions of your Software License Agreement
|
||||
; * with AMD. This header does *NOT* give you permission to use the Materials
|
||||
; * or any rights under AMD's intellectual property. Your use of any portion
|
||||
; * of these Materials shall constitute your acceptance of those terms and
|
||||
; * conditions. If you do not agree to the terms and conditions of the Software
|
||||
; * License Agreement, please do not use any portion of these Materials.
|
||||
; *
|
||||
; * CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
; * confidential and provided to you by AMD shall be kept confidential in
|
||||
; * accordance with the terms and conditions of the Software License Agreement.
|
||||
; *
|
||||
; * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
; * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
; * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
; * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
; * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
; * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
; * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
; * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
; * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
; * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
; * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
; * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
; * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
; *
|
||||
; * AMD does not assume any responsibility for any errors which may appear in
|
||||
; * the Materials or any other related information provided to you by AMD, or
|
||||
; * result from use of the Materials or any related information.
|
||||
; *
|
||||
; * You agree that you will not reverse engineer or decompile the Materials.
|
||||
; *
|
||||
; * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
; * further information, software, technical information, know-how, or show-how
|
||||
; * available to you. Additionally, AMD retains the right to modify the
|
||||
; * Materials at any time, without notice, and is not obligated to provide such
|
||||
; * modified Materials to you.
|
||||
; *
|
||||
; * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
; * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
; * subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
; * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
; * Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
; *
|
||||
; * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
; * direct product thereof will be exported directly or indirectly, into any
|
||||
; * country prohibited by the United States Export Administration Act and the
|
||||
; * regulations thereunder, without the required authorization from the U.S.
|
||||
; * government nor will be used for any purpose prohibited by the same.
|
||||
; *
|
||||
; **************************************************************************
|
||||
|
||||
|
||||
UINT64 TEXTEQU <QWORD>
|
||||
UINT32 TEXTEQU <DWORD>
|
||||
UINT16 TEXTEQU <WORD>
|
||||
UINT8 TEXTEQU <BYTE>
|
||||
CHAR8 TEXTEQU <BYTE>
|
||||
BOOLEAN TEXTEQU <BYTE>
|
||||
POINTER TEXTEQU <DWORD>
|
||||
|
||||
; AGESA Types and Definitions
|
||||
|
||||
AGESA_REVISION EQU "Arch2008"
|
||||
AGESA_ID EQU "AGESA"
|
||||
|
||||
LAST_ENTRY EQU 0FFFFFFFFh
|
||||
IMAGE_SIGNATURE EQU 'DMA$'
|
||||
IOCF8 EQU 0CF8h
|
||||
IOCFC EQU 0CFCh
|
||||
|
||||
; The return status for all AGESA public services.
|
||||
|
||||
; Services return the most severe status of any logged event. Status other than SUCCESS, UNSUPPORTED, and BOUNDS_CHK
|
||||
; will have log entries with more detail.
|
||||
|
||||
AGESA_SUCCESS EQU 0 ; < The service completed normally. Info may be logged.
|
||||
AGESA_UNSUPPORTED EQU 1 ; < The dispatcher or create struct had an unimplemented function requested.
|
||||
; < Not logged.
|
||||
AGESA_BOUNDS_CHK EQU 2 ; < A dynamic parameter was out of range and the service was not provided.
|
||||
; < Example, memory address not installed, heap buffer handle not found.
|
||||
; < Not Logged.
|
||||
; AGESA_STATUS of greater severity (the ones below this line), always have a log entry available.
|
||||
AGESA_ALERT EQU 3 ; < An observed condition, but no loss of function.
|
||||
; < See log. Example, HT CRC.
|
||||
AGESA_WARNING EQU 4 ; < Possible or minor loss of function. See Log.
|
||||
AGESA_ERROR EQU 5 ; < Significant loss of function, boot may be possible. See Log.
|
||||
AGESA_CRITICAL EQU 6 ; < Continue boot only to notify user. See Log.
|
||||
AGESA_FATAL EQU 7 ; < Halt booting. See Log.
|
||||
AgesaStatusMax EQU 8 ; < Not a status, use for limit checking.
|
||||
AGESA_STATUS TEXTEQU <DWORD>
|
||||
|
||||
; For checking whether a status is at or above the mandatory log level.
|
||||
AGESA_STATUS_LOG_LEVEL EQU AGESA_ALERT
|
||||
|
||||
CALLOUT_ENTRY TEXTEQU <POINTER>
|
||||
IMAGE_ENTRY TEXTEQU <POINTER>
|
||||
MODULE_ENTRY TEXTEQU <POINTER>
|
||||
|
||||
; This allocation type is used by the AmdCreateStruct entry point
|
||||
PreMemHeap EQU 0 ; < Create heap in cache.
|
||||
PostMemDram EQU 1 ; < Create heap in memory.
|
||||
ByHost EQU 2 ; < Create heap by Host.
|
||||
ALLOCATION_METHOD TEXTEQU <DWORD>
|
||||
|
||||
; These width descriptors are used by the library function, and others, to specify the data size
|
||||
AccessWidth8 EQU 1 ; < Access width is 8 bits.
|
||||
AccessWidth16 EQU 2 ; < Access width is 16 bits.
|
||||
AccessWidth32 EQU 3 ; < Access width is 32 bits.
|
||||
AccessWidth64 EQU 4 ; < Access width is 64 bits.
|
||||
|
||||
AccessS3SaveWidth8 EQU 81h ; < Save 8 bits data.
|
||||
AccessS3SaveWidth16 EQU 130 ; < Save 16 bits data.
|
||||
AccessS3SaveWidth32 EQU 131 ; < Save 32 bits data.
|
||||
AccessS3SaveWidth64 EQU 132 ; < Save 64 bits data.
|
||||
ACCESS_WIDTH TEXTEQU <DWORD>
|
||||
|
||||
; AGESA struct name
|
||||
|
||||
; AGESA BASIC FUNCTIONS
|
||||
AMD_INIT_RECOVERY EQU 00020000h
|
||||
AMD_CREATE_STRUCT EQU 00020001h
|
||||
AMD_INIT_EARLY EQU 00020002h
|
||||
AMD_INIT_ENV EQU 00020003h
|
||||
AMD_INIT_LATE EQU 00020004h
|
||||
AMD_INIT_MID EQU 00020005h
|
||||
AMD_INIT_POST EQU 00020006h
|
||||
AMD_INIT_RESET EQU 00020007h
|
||||
AMD_INIT_RESUME EQU 00020008h
|
||||
AMD_RELEASE_STRUCT EQU 00020009h
|
||||
AMD_S3LATE_RESTORE EQU 0002000Ah
|
||||
AMD_S3_SAVE EQU 0002000Bh
|
||||
AMD_GET_APIC_ID EQU 0002000Ch
|
||||
AMD_GET_PCI_ADDRESS EQU 0002000Dh
|
||||
AMD_IDENTIFY_CORE EQU 0002000Eh
|
||||
AMD_READ_EVENT_LOG EQU 0002000Fh
|
||||
AMD_GET_EXECACHE_SIZE EQU 00020010h
|
||||
AMD_LATE_RUN_AP_TASK EQU 00020011h
|
||||
AMD_IDENTIFY_DIMMS EQU 00020012h
|
||||
AGESA_STRUCT_NAME TEXTEQU <DWORD>
|
||||
|
||||
|
||||
; ResetType constant values
|
||||
WARM_RESET_WHENEVER EQU 1
|
||||
COLD_RESET_WHENEVER EQU 2
|
||||
WARM_RESET_IMMEDIATELY EQU 3
|
||||
COLD_RESET_IMMEDIATELY EQU 4
|
||||
|
||||
|
||||
; AGESA Structures
|
||||
|
||||
; The standard header for all AGESA services.
|
||||
AMD_CONFIG_PARAMS STRUCT
|
||||
ImageBasePtr UINT32 ? ; < The AGESA Image base address.
|
||||
Func UINT32 ? ; < The service desired, @sa dispatch.h.
|
||||
AltImageBasePtr UINT32 ? ; < Alternate Image location
|
||||
CalloutPtr CALLOUT_ENTRY ? ; < For Callout from AGESA
|
||||
HeapStatus UINT8 ? ; < For heap status from boot time slide.
|
||||
HeapBasePtr UINT64 ? ; < Location of the heap
|
||||
Reserved UINT8 (7) DUP (?) ; < This space is reserved for future use.
|
||||
AMD_CONFIG_PARAMS ENDS
|
||||
|
||||
|
||||
; Create Struct Interface.
|
||||
AMD_INTERFACE_PARAMS STRUCT
|
||||
StdHeader AMD_CONFIG_PARAMS {} ; < Config header
|
||||
AgesaFunctionName AGESA_STRUCT_NAME ? ; < The service to init, @sa dispatch.h
|
||||
AllocationMethod ALLOCATION_METHOD ? ; < How to handle buffer allocation
|
||||
NewStructSize UINT32 ? ; < The size of the allocated data, in for ByHost, else out only.
|
||||
NewStructPtr POINTER ? ; < The struct for the service.
|
||||
; < The struct to init for ByHost allocation,
|
||||
; < the initialized struct on return.
|
||||
AMD_INTERFACE_PARAMS ENDS
|
||||
|
||||
FUNC_0 EQU 0 ; bit-placed for PCI address creation
|
||||
FUNC_1 EQU 1
|
||||
FUNC_2 EQU 2
|
||||
FUNC_3 EQU 3
|
||||
FUNC_4 EQU 4
|
||||
FUNC_5 EQU 5
|
||||
FUNC_6 EQU 6
|
||||
FUNC_7 EQU 7
|
||||
|
||||
; AGESA Binary module header structure
|
||||
AMD_IMAGE_HEADER STRUCT
|
||||
Signature UINT32 ? ; < Binary Signature
|
||||
CreatorID CHAR8 (8) DUP (?) ; < 8 characters ID
|
||||
Version CHAR8 (12) DUP (?) ; < 12 characters version
|
||||
ModuleInfoOffset UINT32 ? ; < Offset of module
|
||||
EntryPointAddress UINT32 ? ; < Entry address
|
||||
ImageBase UINT32 ? ; < Image base
|
||||
RelocTableOffset UINT32 ? ; < Relocate Table offset
|
||||
ImageSize UINT32 ? ; < Size
|
||||
Checksum UINT16 ? ; < Checksum
|
||||
ImageType UINT8 ? ; < Type
|
||||
V_Reserved UINT8 ? ; < Reserved
|
||||
AMD_IMAGE_HEADER ENDS
|
||||
; AGESA Binary module header structure
|
||||
AMD_MODULE_HEADER STRUCT
|
||||
ModuleHeaderSignature UINT32 ? ; < Module signature
|
||||
ModuleIdentifier CHAR8 (8) DUP (?) ; < 8 characters ID
|
||||
ModuleVersion CHAR8 (12) DUP (?) ; < 12 characters version
|
||||
ModuleDispatcher POINTER ? ; < A pointer point to dispatcher
|
||||
NextBlock POINTER ? ; < Next module header link
|
||||
AMD_MODULE_HEADER ENDS
|
||||
|
||||
; AMD_CODE_HEADER Signatures.
|
||||
AGESA_CODE_SIGNATURE TEXTEQU <'!', '!', 'A', 'G', 'E', 'S', 'A', ' '>
|
||||
CIMXNB_CODE_SIGNATURE TEXTEQU <'!', '!', 'C', 'I', 'M', 'X', 'N', 'B'>
|
||||
CIMXSB_CODE_SIGNATURE TEXTEQU <'!', '!', 'C', 'I', 'M', 'X', 'S', 'B'>
|
||||
|
||||
; AGESA_CODE_SIGNATURE
|
||||
AMD_CODE_HEADER STRUCT
|
||||
Signature CHAR8 (8) DUP (?) ; < code header Signature
|
||||
ComponentName CHAR8 (8) DUP (?) ; < 8 character name of the code module
|
||||
Version CHAR8 (12) DUP (?) ; < 12 character version string
|
||||
TerminatorNull CHAR8 ? ; < null terminated string
|
||||
VerReserved CHAR8 (7) DUP (?) ; < reserved space
|
||||
AMD_CODE_HEADER ENDS
|
||||
|
||||
; Extended PCI address format
|
||||
EXT_PCI_ADDR STRUCT
|
||||
Register UINT32 ?
|
||||
; IN OUT UINT32 Register:12; ; < Register offset
|
||||
; IN OUT UINT32 Function:3; ; < Function number
|
||||
; IN OUT UINT32 Device:5; ; < Device number
|
||||
; IN OUT UINT32 Bus:8; ; < Bus number
|
||||
; IN OUT UINT32 Segment:4; ; < Segment
|
||||
EXT_PCI_ADDR ENDS
|
||||
|
||||
; Union type for PCI address
|
||||
PCI_ADDR UNION
|
||||
AddressValue UINT32 ? ; < Formal address
|
||||
Address EXT_PCI_ADDR {} ; < Extended address
|
||||
PCI_ADDR ENDS
|
||||
|
||||
; SBDFO - Segment Bus Device Function Offset
|
||||
; 31:28 Segment (4-bits)
|
||||
; 27:20 Bus (8-bits)
|
||||
; 19:15 Device (5-bits)
|
||||
; 14:12 Function(3-bits)
|
||||
; 11:00 Offset (12-bits)
|
||||
|
||||
|
||||
|
||||
ILLEGAL_SBDFO EQU 0FFFFFFFFh
|
||||
|
||||
; CPUID data received registers format
|
||||
CPUID_DATA STRUCT
|
||||
EAX_Reg UINT32 ? ; < CPUID instruction result in EAX
|
||||
EBX_Reg UINT32 ? ; < CPUID instruction result in EBX
|
||||
ECX_Reg UINT32 ? ; < CPUID instruction result in ECX
|
||||
EDX_Reg UINT32 ? ; < CPUID instruction result in EDX
|
||||
CPUID_DATA ENDS
|
||||
|
||||
; HT frequency for external callbacks
|
||||
;typedef enum {
|
||||
HT_FREQUENCY_200M EQU 0 ; < HT speed 200 for external callbacks
|
||||
HT_FREQUENCY_400M EQU 2 ; < HT speed 400 for external callbacks
|
||||
HT_FREQUENCY_600M EQU 4 ; < HT speed 600 for external callbacks
|
||||
HT_FREQUENCY_800M EQU 5 ; < HT speed 800 for external callbacks
|
||||
HT_FREQUENCY_1000M EQU 6 ; < HT speed 1000 for external callbacks
|
||||
HT_FREQUENCY_1200M EQU 7 ; < HT speed 1200 for external callbacks
|
||||
HT_FREQUENCY_1400M EQU 8 ; < HT speed 1400 for external callbacks
|
||||
HT_FREQUENCY_1600M EQU 9 ; < HT speed 1600 for external callbacks
|
||||
HT_FREQUENCY_1800M EQU 10 ; < HT speed 1800 for external callbacks
|
||||
HT_FREQUENCY_2000M EQU 11 ; < HT speed 2000 for external callbacks
|
||||
HT_FREQUENCY_2200M EQU 12 ; < HT speed 2200 for external callbacks
|
||||
HT_FREQUENCY_2400M EQU 13 ; < HT speed 2400 for external callbacks
|
||||
HT_FREQUENCY_2600M EQU 14 ; < HT speed 2600 for external callbacks
|
||||
HT_FREQUENCY_2800M EQU 17 ; < HT speed 2800 for external callbacks
|
||||
HT_FREQUENCY_3000M EQU 18 ; < HT speed 3000 for external callbacks
|
||||
HT_FREQUENCY_3200M EQU 19 ; < HT speed 3200 for external callbacks
|
||||
HT_FREQUENCY_MAX EQU 20 ; < Limit Check.
|
||||
HT_FREQUENCIES TEXTEQU <DWORD> ;} HT_FREQUENCIES;
|
||||
|
||||
HT3_FREQUENCY_MIN EQU HT_FREQUENCY_1200M
|
||||
|
||||
IFNDEF BIT0
|
||||
BIT0 EQU 0000000000000001h
|
||||
ENDIF
|
||||
IFNDEF BIT1
|
||||
BIT1 EQU 0000000000000002h
|
||||
ENDIF
|
||||
IFNDEF BIT2
|
||||
BIT2 EQU 0000000000000004h
|
||||
ENDIF
|
||||
IFNDEF BIT3
|
||||
BIT3 EQU 0000000000000008h
|
||||
ENDIF
|
||||
IFNDEF BIT4
|
||||
BIT4 EQU 0000000000000010h
|
||||
ENDIF
|
||||
IFNDEF BIT5
|
||||
BIT5 EQU 0000000000000020h
|
||||
ENDIF
|
||||
IFNDEF BIT6
|
||||
BIT6 EQU 0000000000000040h
|
||||
ENDIF
|
||||
IFNDEF BIT7
|
||||
BIT7 EQU 0000000000000080h
|
||||
ENDIF
|
||||
IFNDEF BIT8
|
||||
BIT8 EQU 0000000000000100h
|
||||
ENDIF
|
||||
IFNDEF BIT9
|
||||
BIT9 EQU 0000000000000200h
|
||||
ENDIF
|
||||
IFNDEF BIT10
|
||||
BIT10 EQU 0000000000000400h
|
||||
ENDIF
|
||||
IFNDEF BIT11
|
||||
BIT11 EQU 0000000000000800h
|
||||
ENDIF
|
||||
IFNDEF BIT12
|
||||
BIT12 EQU 0000000000001000h
|
||||
ENDIF
|
||||
IFNDEF BIT13
|
||||
BIT13 EQU 0000000000002000h
|
||||
ENDIF
|
||||
IFNDEF BIT14
|
||||
BIT14 EQU 0000000000004000h
|
||||
ENDIF
|
||||
IFNDEF BIT15
|
||||
BIT15 EQU 0000000000008000h
|
||||
ENDIF
|
||||
IFNDEF BIT16
|
||||
BIT16 EQU 0000000000010000h
|
||||
ENDIF
|
||||
IFNDEF BIT17
|
||||
BIT17 EQU 0000000000020000h
|
||||
ENDIF
|
||||
IFNDEF BIT18
|
||||
BIT18 EQU 0000000000040000h
|
||||
ENDIF
|
||||
IFNDEF BIT19
|
||||
BIT19 EQU 0000000000080000h
|
||||
ENDIF
|
||||
IFNDEF BIT20
|
||||
BIT20 EQU 0000000000100000h
|
||||
ENDIF
|
||||
IFNDEF BIT21
|
||||
BIT21 EQU 0000000000200000h
|
||||
ENDIF
|
||||
IFNDEF BIT22
|
||||
BIT22 EQU 0000000000400000h
|
||||
ENDIF
|
||||
IFNDEF BIT23
|
||||
BIT23 EQU 0000000000800000h
|
||||
ENDIF
|
||||
IFNDEF BIT24
|
||||
BIT24 EQU 0000000001000000h
|
||||
ENDIF
|
||||
IFNDEF BIT25
|
||||
BIT25 EQU 0000000002000000h
|
||||
ENDIF
|
||||
IFNDEF BIT26
|
||||
BIT26 EQU 0000000004000000h
|
||||
ENDIF
|
||||
IFNDEF BIT27
|
||||
BIT27 EQU 0000000008000000h
|
||||
ENDIF
|
||||
IFNDEF BIT28
|
||||
BIT28 EQU 0000000010000000h
|
||||
ENDIF
|
||||
IFNDEF BIT29
|
||||
BIT29 EQU 0000000020000000h
|
||||
ENDIF
|
||||
IFNDEF BIT30
|
||||
BIT30 EQU 0000000040000000h
|
||||
ENDIF
|
||||
IFNDEF BIT31
|
||||
BIT31 EQU 0000000080000000h
|
||||
ENDIF
|
||||
IFNDEF BIT32
|
||||
BIT32 EQU 0000000100000000h
|
||||
ENDIF
|
||||
IFNDEF BIT33
|
||||
BIT33 EQU 0000000200000000h
|
||||
ENDIF
|
||||
IFNDEF BIT34
|
||||
BIT34 EQU 0000000400000000h
|
||||
ENDIF
|
||||
IFNDEF BIT35
|
||||
BIT35 EQU 0000000800000000h
|
||||
ENDIF
|
||||
IFNDEF BIT36
|
||||
BIT36 EQU 0000001000000000h
|
||||
ENDIF
|
||||
IFNDEF BIT37
|
||||
BIT37 EQU 0000002000000000h
|
||||
ENDIF
|
||||
IFNDEF BIT38
|
||||
BIT38 EQU 0000004000000000h
|
||||
ENDIF
|
||||
IFNDEF BIT39
|
||||
BIT39 EQU 0000008000000000h
|
||||
ENDIF
|
||||
IFNDEF BIT40
|
||||
BIT40 EQU 0000010000000000h
|
||||
ENDIF
|
||||
IFNDEF BIT41
|
||||
BIT41 EQU 0000020000000000h
|
||||
ENDIF
|
||||
IFNDEF BIT42
|
||||
BIT42 EQU 0000040000000000h
|
||||
ENDIF
|
||||
IFNDEF BIT43
|
||||
BIT43 EQU 0000080000000000h
|
||||
ENDIF
|
||||
IFNDEF BIT44
|
||||
BIT44 EQU 0000100000000000h
|
||||
ENDIF
|
||||
IFNDEF BIT45
|
||||
BIT45 EQU 0000200000000000h
|
||||
ENDIF
|
||||
IFNDEF BIT46
|
||||
BIT46 EQU 0000400000000000h
|
||||
ENDIF
|
||||
IFNDEF BIT47
|
||||
BIT47 EQU 0000800000000000h
|
||||
ENDIF
|
||||
IFNDEF BIT48
|
||||
BIT48 EQU 0001000000000000h
|
||||
ENDIF
|
||||
IFNDEF BIT49
|
||||
BIT49 EQU 0002000000000000h
|
||||
ENDIF
|
||||
IFNDEF BIT50
|
||||
BIT50 EQU 0004000000000000h
|
||||
ENDIF
|
||||
IFNDEF BIT51
|
||||
BIT51 EQU 0008000000000000h
|
||||
ENDIF
|
||||
IFNDEF BIT52
|
||||
BIT52 EQU 0010000000000000h
|
||||
ENDIF
|
||||
IFNDEF BIT53
|
||||
BIT53 EQU 0020000000000000h
|
||||
ENDIF
|
||||
IFNDEF BIT54
|
||||
BIT54 EQU 0040000000000000h
|
||||
ENDIF
|
||||
IFNDEF BIT55
|
||||
BIT55 EQU 0080000000000000h
|
||||
ENDIF
|
||||
IFNDEF BIT56
|
||||
BIT56 EQU 0100000000000000h
|
||||
ENDIF
|
||||
IFNDEF BIT57
|
||||
BIT57 EQU 0200000000000000h
|
||||
ENDIF
|
||||
IFNDEF BIT58
|
||||
BIT58 EQU 0400000000000000h
|
||||
ENDIF
|
||||
IFNDEF BIT59
|
||||
BIT59 EQU 0800000000000000h
|
||||
ENDIF
|
||||
IFNDEF BIT60
|
||||
BIT60 EQU 1000000000000000h
|
||||
ENDIF
|
||||
IFNDEF BIT61
|
||||
BIT61 EQU 2000000000000000h
|
||||
ENDIF
|
||||
IFNDEF BIT62
|
||||
BIT62 EQU 4000000000000000h
|
||||
ENDIF
|
||||
IFNDEF BIT63
|
||||
BIT63 EQU 8000000000000000h
|
||||
ENDIF
|
||||
|
||||
603
src/vendorcode/amd/agesa/f15tn/Legacy/bridge32.inc
Normal file
603
src/vendorcode/amd/agesa/f15tn/Legacy/bridge32.inc
Normal file
@ -0,0 +1,603 @@
|
||||
; ****************************************************************************
|
||||
; *
|
||||
; * @file
|
||||
; *
|
||||
; * Agesa structures and definitions
|
||||
; *
|
||||
; * Contains AMD AGESA core interface
|
||||
; *
|
||||
; * @xrefitem bom "File Content Label" "Release Content"
|
||||
; * @e project: AGESA
|
||||
; * @e sub-project: Include
|
||||
; * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
;
|
||||
; ****************************************************************************
|
||||
;
|
||||
; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
;
|
||||
; AMD is granting you permission to use this software (the Materials)
|
||||
; pursuant to the terms and conditions of your Software License Agreement
|
||||
; with AMD. This header does *NOT* give you permission to use the Materials
|
||||
; or any rights under AMD's intellectual property. Your use of any portion
|
||||
; of these Materials shall constitute your acceptance of those terms and
|
||||
; conditions. If you do not agree to the terms and conditions of the Software
|
||||
; License Agreement, please do not use any portion of these Materials.
|
||||
;
|
||||
; CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
; confidential and provided to you by AMD shall be kept confidential in
|
||||
; accordance with the terms and conditions of the Software License Agreement.
|
||||
;
|
||||
; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
; THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
;
|
||||
; AMD does not assume any responsibility for any errors which may appear in
|
||||
; the Materials or any other related information provided to you by AMD, or
|
||||
; result from use of the Materials or any related information.
|
||||
;
|
||||
; You agree that you will not reverse engineer or decompile the Materials.
|
||||
;
|
||||
; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
; further information, software, technical information, know-how, or show-how
|
||||
; available to you. Additionally, AMD retains the right to modify the
|
||||
; Materials at any time, without notice, and is not obligated to provide such
|
||||
; modified Materials to you.
|
||||
;
|
||||
; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
; subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
; Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
;
|
||||
; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
; direct product thereof will be exported directly or indirectly, into any
|
||||
; country prohibited by the United States Export Administration Act and the
|
||||
; regulations thereunder, without the required authorization from the U.S.
|
||||
; government nor will be used for any purpose prohibited by the same.
|
||||
;*****************************************************************************
|
||||
|
||||
PARAM1 textequ <[bp+8]>
|
||||
PARAM2 textequ <[bp+12]>
|
||||
PARAM3 textequ <[bp+16]>
|
||||
RETAddress textequ <[bp+4]>
|
||||
|
||||
AMD_PRIVATE_PARAMS STRUCT
|
||||
Gate16_CS DW ? ; Segment of AMD_BRIDGE_32 and AMD_CALLOUT_16
|
||||
Gate16_SS DW ? ; RM stack segment
|
||||
Router_Seg DW ? ; Segment of oem router
|
||||
Router_Off DW ? ; Offset of oem router
|
||||
AMD_PRIVATE_PARAMS ENDS
|
||||
|
||||
; OEM may pre-define the GDT and selector offsets. If they do not, use our defaults.
|
||||
IFNDEF AGESA_SELECTOR_GDT
|
||||
AGESA_SELECTOR_GDT EQU 00h
|
||||
ENDIF
|
||||
IFNDEF AGESA_SELECTOR_CODE16
|
||||
AGESA_SELECTOR_CODE16 EQU 08h
|
||||
ENDIF
|
||||
IFNDEF AGESA_SELECTOR_DATA16
|
||||
AGESA_SELECTOR_DATA16 EQU 10h
|
||||
ENDIF
|
||||
IFNDEF AGESA_SELECTOR_CODE32
|
||||
AGESA_SELECTOR_CODE32 EQU 18h
|
||||
ENDIF
|
||||
IFNDEF AGESA_SELECTOR_DATA32
|
||||
AGESA_SELECTOR_DATA32 EQU 20h
|
||||
ENDIF
|
||||
|
||||
|
||||
AMD_BRIDGE_32_GDT MACRO GDT_Name:REQ
|
||||
|
||||
GDT_Name LABEL BYTE
|
||||
DD 000000000h, 000000000h ; NULL descriptor
|
||||
DD 00000ffffh, 000009b00h ; 16-bit code, fixed up
|
||||
DD 00000ffffh, 000009300h ; 16-bit data, fixed up
|
||||
DD 00000ffffh, 000CF9B00h ; 32-bit protected mode code
|
||||
DD 00000ffffh, 000CF9300h ; 32-bit protected mode data
|
||||
GDT_Length EQU ($-GDT_Name)
|
||||
|
||||
ENDM
|
||||
|
||||
;+-------------------------------------------------------------------------
|
||||
;
|
||||
; AMD_BRIDGE_32 - Execute Agesa through Pushhigh interface
|
||||
;
|
||||
; Processing:
|
||||
; The following steps are taken:
|
||||
; 1) Enter 32bit Protected Mode (PM32)
|
||||
; 2) Run AGESA code
|
||||
; 3) Restore Real Mode (RM)
|
||||
;
|
||||
; Entry:
|
||||
; [big real mode] : ds, es set to base 0 limit 4G segment
|
||||
; EDX - if not 0, provides a FAR PTR to oem router (Seg | Offset)
|
||||
; ESI - configuration block pointer
|
||||
;
|
||||
; Exit:
|
||||
; EAX - return value
|
||||
; ESI - configuration block pointer
|
||||
; ds, es, fs, gs - Set to 4GB segment limit for Big Real Mode
|
||||
;
|
||||
; Modified:
|
||||
; None
|
||||
;
|
||||
|
||||
AMD_BRIDGE_32 MACRO GDT_Name
|
||||
|
||||
local copyGDT
|
||||
local flushTo16PM
|
||||
local agesaReturnAddress
|
||||
local leave32bitPM
|
||||
local flush2RM
|
||||
|
||||
push gs
|
||||
push fs
|
||||
push ebx
|
||||
push ecx
|
||||
push edi
|
||||
mov eax, esp
|
||||
push eax
|
||||
movzx esp, sp
|
||||
;
|
||||
; Do not use any locals here, BP will be changed frequently during RM->PM32->RM
|
||||
;
|
||||
pushf
|
||||
cli ; Disable interrupts during AGESA
|
||||
cld ; Need known direction flag during AGESA
|
||||
|
||||
;
|
||||
; Save the FAR PTR input parameter
|
||||
;
|
||||
mov gs, dx ; Offset
|
||||
shr edx, 16
|
||||
mov fs, dx ; Segment
|
||||
;
|
||||
; Determine where our binary file is and get entry point
|
||||
;
|
||||
mov edx, (AMD_CONFIG_PARAMS PTR [esi]).ImageBasePtr
|
||||
add edx, (AMD_IMAGE_HEADER PTR [edx]).EntryPointAddress
|
||||
;
|
||||
; Figure out the return address we will use after calling AGESA
|
||||
; and store it in ebx until we have our stack set up properly
|
||||
;
|
||||
mov ebx, cs
|
||||
shl ebx, 4
|
||||
add ebx, OFFSET agesaReturnAddress
|
||||
;
|
||||
; Save our current RM stack AND entry EBP
|
||||
;
|
||||
push ebp
|
||||
; push esp
|
||||
push ss
|
||||
|
||||
;
|
||||
; BEGIN --- STACK MUST BE BALANCED AT THIS POINT --- BEGIN
|
||||
;
|
||||
; Copy the GDT onto the stack for modification
|
||||
;
|
||||
mov cx, GDT_Length
|
||||
sub sp, cx
|
||||
mov bp, sp
|
||||
lea di, GDT_Name
|
||||
copyGDT:
|
||||
mov al, cs:[di]
|
||||
mov [bp], al
|
||||
inc di
|
||||
inc bp
|
||||
loop copyGDT
|
||||
;
|
||||
; Patch 16-bit code and data descriptors on stack. We will
|
||||
; fix up CS and SS for PM16 during the callout if applicable.
|
||||
;
|
||||
mov bp, sp
|
||||
|
||||
mov eax, cs
|
||||
shl eax, 4
|
||||
mov [bp+AGESA_SELECTOR_CODE16+2], ax
|
||||
shr eax, 16
|
||||
mov [bp+AGESA_SELECTOR_CODE16+4], al
|
||||
|
||||
mov eax, ss
|
||||
shl eax, 4
|
||||
mov [bp+AGESA_SELECTOR_DATA16+2], ax
|
||||
shr eax, 16
|
||||
mov [bp+AGESA_SELECTOR_DATA16+4], al
|
||||
;
|
||||
; Need to place Length and Address on GDT
|
||||
;
|
||||
mov eax, ss
|
||||
shl eax, 4
|
||||
add eax, esp
|
||||
push eax
|
||||
push WORD PTR (GDT_Length-1)
|
||||
;
|
||||
; Load the GDT
|
||||
;
|
||||
mov bp, sp
|
||||
lgdt FWORD PTR [bp]
|
||||
;
|
||||
; TABLE 1
|
||||
;
|
||||
; Place PRIVATE DATA on stack DIRECTLY following GDT
|
||||
; During this routine, stack data is critical. If
|
||||
; order is changed or additional added, bad things
|
||||
; will happen!
|
||||
;
|
||||
; HIGHEST PHYSICAL ADDRESS
|
||||
;
|
||||
; | ... |
|
||||
; ------------------------
|
||||
; | old RM SP |
|
||||
; | old RM SS |
|
||||
; ------------------------ sp + SIZEOF AMD_PRIVATE_PARAMS + (SIZEOF GDT_LENGTH + 6 {size, address})
|
||||
; | GDT_DATA32 |
|
||||
; | ... |
|
||||
; | GDT_NULL |
|
||||
; | GDT Addr, Length |
|
||||
; ------------------------ sp + SIZEOF AMD_PRIVATE_PARAMS
|
||||
; | Priv.Gate16_SS |
|
||||
; | Priv.Gate16_CS |
|
||||
; ------------------------ sp
|
||||
; ------ THEN PUSH -------
|
||||
; | Return to 16-bit CS |
|
||||
; | Return to 16-bit Off |
|
||||
; | ... |
|
||||
;
|
||||
; LOWEST PHYSICAL ADDRESS
|
||||
;
|
||||
mov edi, esp
|
||||
sub edi, SIZEOF AMD_PRIVATE_PARAMS
|
||||
mov ax, cs
|
||||
mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_CS, ax
|
||||
mov ax, ss
|
||||
mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_SS, ax
|
||||
mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Off, gs
|
||||
mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Seg, fs
|
||||
|
||||
mov esp, edi
|
||||
;
|
||||
; Save an address for returning to 16 bit real mode on stack,
|
||||
; we'll use it in a far ret after turning off CR0.PE so that
|
||||
; we can take our address off and force a far jump. Be sure
|
||||
; no unexpected data is on the stack after this!
|
||||
;
|
||||
mov ax, cs
|
||||
push cs
|
||||
lea ax, flush2RM
|
||||
push ax
|
||||
;
|
||||
; Convert ss:esp to "flat"
|
||||
;
|
||||
|
||||
mov ax, sp
|
||||
push ax
|
||||
mov eax, ss
|
||||
shl eax, 4
|
||||
add eax, esp
|
||||
mov esp, eax ; Load the zero based ESP
|
||||
|
||||
;
|
||||
; Set CR0.PE
|
||||
;
|
||||
mov eax, CR0 ; Get CPU control word 0
|
||||
or al, 01 ; Enable CPU protected mode
|
||||
mov CR0, eax ; Write back to CPU control word 0
|
||||
jmp flushTo16PM
|
||||
|
||||
flushTo16PM:
|
||||
;
|
||||
; 16-bit protected mode
|
||||
;
|
||||
mov ax, AGESA_SELECTOR_DATA32
|
||||
mov ds, ax
|
||||
mov es, ax
|
||||
mov fs, ax
|
||||
mov gs, ax
|
||||
mov ss, ax
|
||||
;
|
||||
; Push our parameters RIGHT TO LEFT, and then return address
|
||||
;
|
||||
push esi ; AGESA configuration block pointer (data)
|
||||
push ebx ; after AGESA return offset (32PM flat) - consumed by dispatcher ret
|
||||
pushd AGESA_SELECTOR_CODE32 ; AGESA entry selector (32PM flat)
|
||||
push edx ; AGESA entry point (32PM flat)
|
||||
|
||||
DB 066h
|
||||
retf ; <><><> Enter AGESA 32-bit code!!! <><><>
|
||||
|
||||
agesaReturnAddress:
|
||||
;
|
||||
; Returns from the Agesa 32-bit code still PM32
|
||||
;
|
||||
DB 0EAh
|
||||
DD OFFSET leave32bitPM
|
||||
DW AGESA_SELECTOR_CODE16
|
||||
|
||||
leave32bitPM:
|
||||
;
|
||||
; Now in 16-bit PM
|
||||
;
|
||||
add esp, 4 ; +4 to remove our config block pointer
|
||||
;
|
||||
; Eax reserve AGESA_STATUS return code, save it
|
||||
;
|
||||
mov ebx, eax
|
||||
;
|
||||
; Turn off CR0.PE, restore 64K stack limit
|
||||
;
|
||||
pop ax
|
||||
mov sp, ax
|
||||
mov ax, AGESA_SELECTOR_DATA16
|
||||
mov ss, ax
|
||||
|
||||
mov eax, CR0
|
||||
and al, NOT 1 ; Disable protected mode
|
||||
mov CR0, eax ; Write back CR0.PE
|
||||
;
|
||||
; Jump far to enter RM, we saved this address on the stack
|
||||
; already. Hopefully stack is balanced through AGESA
|
||||
; nor were any params added by pushing them on the stack and
|
||||
; not removing them between BEGIN-END comments.
|
||||
;
|
||||
retf
|
||||
|
||||
flush2RM:
|
||||
;
|
||||
; Set segments registers for big real mode before returning
|
||||
;
|
||||
xor ax, ax
|
||||
mov ds, ax
|
||||
mov es, ax
|
||||
mov fs, ax
|
||||
mov gs, ax
|
||||
;
|
||||
; Discard GDT, +6 for GDT pointer/size, privates
|
||||
;
|
||||
add esp, GDT_Length + 6 + SIZEOF AMD_PRIVATE_PARAMS
|
||||
;
|
||||
; Restore real mode stack and entry EBP
|
||||
;
|
||||
pop cx
|
||||
; mov esp, [esp]
|
||||
mov ss, cx
|
||||
pop ebp
|
||||
;
|
||||
; Restore AGESA_STATUS return code to eax
|
||||
;
|
||||
mov eax, ebx
|
||||
;
|
||||
; END --- STACK MUST BE BALANCED TO THIS POINT --- END
|
||||
;
|
||||
|
||||
popf
|
||||
pop ebx
|
||||
mov esp, ebx
|
||||
pop edi
|
||||
pop ecx
|
||||
pop ebx
|
||||
pop fs
|
||||
pop gs
|
||||
; EXIT AMD_BRIDGE_32
|
||||
ENDM
|
||||
;+-------------------------------------------------------------------------
|
||||
;
|
||||
; AMD_CALLOUT_16 - Execute Callback from Pushhigh interface
|
||||
;
|
||||
; Processing:
|
||||
; The following steps are taken:
|
||||
; 1) Enter PM16
|
||||
; 2) Setup stack, get private params
|
||||
; 3) Enter RM
|
||||
; 4) Get 3 params
|
||||
; 5) Call oemCallout OR oem router
|
||||
; 6) Enter PM32
|
||||
; 7) Return to Agesa PH
|
||||
;
|
||||
; Entry:
|
||||
; [32-bit protected mode]
|
||||
; [esp+8] Func
|
||||
; [esp+12] Data
|
||||
; [esp+16] Configuration Block
|
||||
; [esp+4] return address to Agesa
|
||||
;
|
||||
; Exit:
|
||||
; [32-bit protected mode]
|
||||
;
|
||||
; Modified:
|
||||
; None
|
||||
;
|
||||
AMD_CALLOUT_16 MACRO LocalOemCalloutRouter
|
||||
;
|
||||
; Note that we are still PM32, so MASM may work strangely
|
||||
;
|
||||
|
||||
push bp ; Save our original SP to access params
|
||||
mov bp, sp
|
||||
push bx
|
||||
push si
|
||||
push di
|
||||
push cx
|
||||
push dx
|
||||
push di
|
||||
|
||||
DB 066h, 0EAh
|
||||
DW OFFSET PM16Entry
|
||||
DW AGESA_SELECTOR_CODE16
|
||||
|
||||
PM16Entry:
|
||||
;
|
||||
; PM16 CS, but still PM32 SS, as we need to access our private params
|
||||
; before we enter RM.
|
||||
;
|
||||
; Note: we are working below the stack temporarily, and and it will
|
||||
; not affect our ability to get entry params
|
||||
;
|
||||
xor ecx, ecx
|
||||
xor edx, edx
|
||||
;
|
||||
; SGDT will give us the original location of the GDT on our CAS stack.
|
||||
; We need this value because our private parameters are located just
|
||||
; below the GDT.
|
||||
;
|
||||
mov edi, esp
|
||||
sub edi, GDT_Length + 6
|
||||
sgdt FWORD PTR [edi] ; [edi] = word size, dword address
|
||||
mov edi, DWORD PTR [edi+2] ; Get the PM32 address only
|
||||
sub edi, SIZEOF AMD_PRIVATE_PARAMS + 6
|
||||
;
|
||||
; cx = code segment of this code in RM
|
||||
; dx = stack segment of CAS in RM
|
||||
; fs = code segment of oem router (save for later)
|
||||
; gs = offset of oem router (save for later)
|
||||
; fs and gs are loaded after switch to real mode because we can't
|
||||
; use them as scratch pad registers in protected mode
|
||||
;
|
||||
mov cx, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_CS
|
||||
mov dx, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_SS
|
||||
|
||||
mov eax, edi ; Save edi in eax for after RM switch
|
||||
mov edi, esp ; Save our current ESP for RM
|
||||
|
||||
movzx ebx, dx
|
||||
shl ebx, 4
|
||||
sub esp, ebx
|
||||
|
||||
;
|
||||
; We had been accessing the stack in PM32, we will now change to PM16 so we
|
||||
; will make the stack segment 64KB limit so SP needs to be fixed made PM16
|
||||
; compatible.
|
||||
;
|
||||
mov bx, AGESA_SELECTOR_DATA16
|
||||
mov ss, bx
|
||||
|
||||
;
|
||||
; Save the RM segment and RM offset of the jump we will need to make in
|
||||
; order to enter RM so that code in this segment is relocatable.
|
||||
;
|
||||
; BEGIN --- Don't unbalance the stack --- BEGIN
|
||||
;
|
||||
push cx
|
||||
pushw OFFSET RMEntry
|
||||
|
||||
mov ebx, CR0
|
||||
and bl, NOT 1
|
||||
mov CR0, ebx ; CR0.PE cleared
|
||||
;
|
||||
; Far jump to clear segment descriptor cache and enter RM
|
||||
;
|
||||
retf
|
||||
|
||||
RMEntry:
|
||||
;
|
||||
; We are in RM, setup RM stack
|
||||
;
|
||||
movzx ebx, dx ; Get RM SS in ebx
|
||||
shl ebx, 4 ; Get our stack top on entry in EBP to
|
||||
sub ebp, ebx ; access our entry parameters
|
||||
sub eax, ebx ; save copy of parameters address
|
||||
mov ss, dx ; Set stack segment
|
||||
;
|
||||
; We are going to figure out the address to use when we return
|
||||
; and have to go back into PM32 while we have access to it
|
||||
;
|
||||
movzx ebx, cx ; Get original CS in ebx
|
||||
shl ebx, 4
|
||||
add ebx, OFFSET PM32Entry
|
||||
;
|
||||
; Now we put our data, func, block params into calling convention
|
||||
; for our hook
|
||||
;
|
||||
; ECX = Func
|
||||
; EDX = Data
|
||||
; ESI = config pointer
|
||||
;
|
||||
mov ecx, PARAM1 ; Func
|
||||
mov edx, PARAM2 ; Data
|
||||
mov esi, PARAM3 ; pointer
|
||||
|
||||
push ebx ; Save PM32 mode switch address
|
||||
push edi ; Save PM32 stack pointer
|
||||
pushf
|
||||
;
|
||||
; Get Router Function Address
|
||||
;
|
||||
mov edi, eax
|
||||
mov ax, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Seg
|
||||
mov fs, ax
|
||||
mov ax, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Off
|
||||
mov gs, ax
|
||||
|
||||
mov eax, AGESA_UNSUPPORTED ; Default return value
|
||||
;
|
||||
; If AMD_BRIDGE_32 EDX == 0 call oemCallout
|
||||
; otherwise call FAR PTR EDX
|
||||
;
|
||||
; Critical:
|
||||
; sp+2 - EDI aka PM32 stack address
|
||||
; sp+4 - address of PM32Entry in PM32
|
||||
;
|
||||
mov bx, fs
|
||||
shl ebx, 16
|
||||
mov bx, gs
|
||||
|
||||
.if (ebx == 0)
|
||||
call LocalOemCalloutRouter
|
||||
.else
|
||||
;
|
||||
; Make far call to Router function
|
||||
;
|
||||
push cs
|
||||
push offset CalloutReturn
|
||||
push ebx
|
||||
retf
|
||||
CalloutReturn:
|
||||
.endif
|
||||
;
|
||||
; Restore PM32 esp from RM stack
|
||||
;
|
||||
popf
|
||||
pop edi ; Our PM32 stack pointer
|
||||
pop edx ; Our PM32 mode switch address
|
||||
|
||||
mov ebx, CR0
|
||||
or bl, 1 ; CR0.PE set
|
||||
mov CR0, ebx
|
||||
|
||||
mov ebx, AGESA_SELECTOR_DATA32
|
||||
pushd AGESA_SELECTOR_CODE32 ; PM32 selector
|
||||
push edx ; PM32 entry point
|
||||
|
||||
DB 066h
|
||||
retf ; Far jump to enter PM32
|
||||
|
||||
PM32Entry:
|
||||
;
|
||||
; END --- Don't unbalance the stack --- END
|
||||
; We are now PM32, so remember MASM is assembling in 16-bit again
|
||||
;
|
||||
mov ss, bx
|
||||
mov ds, bx
|
||||
mov es, bx
|
||||
mov fs, bx
|
||||
mov gs, bx
|
||||
|
||||
mov sp, di
|
||||
pop di
|
||||
pop dx
|
||||
pop cx
|
||||
pop di
|
||||
pop si
|
||||
pop bx
|
||||
pop bp
|
||||
; EXIT AMD_CALLOUT_16
|
||||
ENDM
|
||||
1387
src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c
Normal file
1387
src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c
Normal file
File diff suppressed because it is too large
Load Diff
398
src/vendorcode/amd/agesa/f15tn/Lib/amdlib.h
Normal file
398
src/vendorcode/amd/agesa/f15tn/Lib/amdlib.h
Normal file
@ -0,0 +1,398 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* AMD Library
|
||||
*
|
||||
* Contains interface to the AMD AGESA library
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: Lib
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*
|
||||
*/
|
||||
/*
|
||||
******************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
******************************************************************************
|
||||
**/
|
||||
|
||||
#ifndef _AMD_LIB_H_
|
||||
#define _AMD_LIB_H_
|
||||
|
||||
#define IOCF8 0xCF8
|
||||
#define IOCFC 0xCFC
|
||||
|
||||
// Reg Values for ReadCpuReg and WriteCpuReg
|
||||
#define CR4_REG 0x04
|
||||
#define DR0_REG 0x10
|
||||
#define DR1_REG 0x11
|
||||
#define DR2_REG 0x12
|
||||
#define DR3_REG 0x13
|
||||
#define DR7_REG 0x17
|
||||
|
||||
// PROTOTYPES FOR amdlib32.asm
|
||||
UINT8
|
||||
ReadIo8 (
|
||||
IN UINT16 Address
|
||||
);
|
||||
|
||||
UINT16
|
||||
ReadIo16 (
|
||||
IN UINT16 Address
|
||||
);
|
||||
|
||||
UINT32
|
||||
ReadIo32 (
|
||||
IN UINT16 Address
|
||||
);
|
||||
|
||||
VOID
|
||||
WriteIo8 (
|
||||
IN UINT16 Address,
|
||||
IN UINT8 Data
|
||||
);
|
||||
|
||||
VOID
|
||||
WriteIo16 (
|
||||
IN UINT16 Address,
|
||||
IN UINT16 Data
|
||||
);
|
||||
|
||||
VOID
|
||||
WriteIo32 (
|
||||
IN UINT16 Address,
|
||||
IN UINT32 Data
|
||||
);
|
||||
|
||||
UINT8
|
||||
Read64Mem8 (
|
||||
IN UINT64 Address
|
||||
);
|
||||
|
||||
UINT16
|
||||
Read64Mem16 (
|
||||
IN UINT64 Address
|
||||
);
|
||||
|
||||
UINT32
|
||||
Read64Mem32 (
|
||||
IN UINT64 Address
|
||||
);
|
||||
|
||||
VOID
|
||||
Write64Mem8 (
|
||||
IN UINT64 Address,
|
||||
IN UINT8 Data
|
||||
);
|
||||
|
||||
VOID
|
||||
Write64Mem16 (
|
||||
IN UINT64 Address,
|
||||
IN UINT16 Data
|
||||
);
|
||||
|
||||
VOID
|
||||
Write64Mem32 (
|
||||
IN UINT64 Address,
|
||||
IN UINT32 Data
|
||||
);
|
||||
|
||||
UINT64
|
||||
ReadTSC (
|
||||
VOID);
|
||||
|
||||
// MSR
|
||||
VOID
|
||||
LibAmdMsrRead (
|
||||
IN UINT32 MsrAddress,
|
||||
OUT UINT64 *Value,
|
||||
IN OUT AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
VOID
|
||||
LibAmdMsrWrite (
|
||||
IN UINT32 MsrAddress,
|
||||
IN UINT64 *Value,
|
||||
IN OUT AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
// IO
|
||||
VOID
|
||||
LibAmdIoRead (
|
||||
IN ACCESS_WIDTH AccessWidth,
|
||||
IN UINT16 IoAddress,
|
||||
OUT VOID *Value,
|
||||
IN OUT AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
VOID
|
||||
LibAmdIoWrite (
|
||||
IN ACCESS_WIDTH AccessWidth,
|
||||
IN UINT16 IoAddress,
|
||||
IN VOID *Value,
|
||||
IN OUT AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
VOID
|
||||
LibAmdIoRMW (
|
||||
IN ACCESS_WIDTH AccessWidth,
|
||||
IN UINT16 IoAddress,
|
||||
IN VOID *Data,
|
||||
IN VOID *DataMask,
|
||||
IN OUT AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
VOID
|
||||
LibAmdIoPoll (
|
||||
IN ACCESS_WIDTH AccessWidth,
|
||||
IN UINT16 IoAddress,
|
||||
IN VOID *Data,
|
||||
IN VOID *DataMask,
|
||||
IN UINT64 Delay,
|
||||
IN OUT AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
// Memory or MMIO
|
||||
VOID
|
||||
LibAmdMemRead (
|
||||
IN ACCESS_WIDTH AccessWidth,
|
||||
IN UINT64 MemAddress,
|
||||
OUT VOID *Value,
|
||||
IN OUT AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
VOID
|
||||
LibAmdMemWrite (
|
||||
IN ACCESS_WIDTH AccessWidth,
|
||||
IN UINT64 MemAddress,
|
||||
IN VOID *Value,
|
||||
IN OUT AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
VOID
|
||||
LibAmdMemRMW (
|
||||
IN ACCESS_WIDTH AccessWidth,
|
||||
IN UINT64 MemAddress,
|
||||
IN VOID *Data,
|
||||
IN VOID *DataMask,
|
||||
IN OUT AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
VOID
|
||||
LibAmdMemPoll (
|
||||
IN ACCESS_WIDTH AccessWidth,
|
||||
IN UINT64 MemAddress,
|
||||
IN VOID *Data,
|
||||
IN VOID *DataMask,
|
||||
IN UINT64 Delay,
|
||||
IN OUT AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
// PCI
|
||||
VOID
|
||||
LibAmdPciRead (
|
||||
IN ACCESS_WIDTH AccessWidth,
|
||||
IN PCI_ADDR PciAddress,
|
||||
OUT VOID *Value,
|
||||
IN OUT AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
VOID
|
||||
LibAmdPciWrite (
|
||||
IN ACCESS_WIDTH AccessWidth,
|
||||
IN PCI_ADDR PciAddress,
|
||||
IN VOID *Value,
|
||||
IN OUT AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
VOID
|
||||
LibAmdPciRMW (
|
||||
IN ACCESS_WIDTH AccessWidth,
|
||||
IN PCI_ADDR PciAddress,
|
||||
IN VOID *Data,
|
||||
IN VOID *DataMask,
|
||||
IN OUT AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
VOID
|
||||
LibAmdPciPoll (
|
||||
IN ACCESS_WIDTH AccessWidth,
|
||||
IN PCI_ADDR PciAddress,
|
||||
IN VOID *Data,
|
||||
IN VOID *DataMask,
|
||||
IN UINT64 Delay,
|
||||
IN OUT AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
VOID
|
||||
LibAmdPciReadBits (
|
||||
IN PCI_ADDR Address,
|
||||
IN UINT8 Highbit,
|
||||
IN UINT8 Lowbit,
|
||||
OUT UINT32 *Value,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
VOID
|
||||
LibAmdPciWriteBits (
|
||||
IN PCI_ADDR Address,
|
||||
IN UINT8 Highbit,
|
||||
IN UINT8 Lowbit,
|
||||
IN UINT32 *Value,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
VOID
|
||||
LibAmdPciFindNextCap (
|
||||
IN OUT PCI_ADDR *Address,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
// CPUID
|
||||
VOID
|
||||
LibAmdCpuidRead (
|
||||
IN UINT32 CpuidFcnAddress,
|
||||
OUT CPUID_DATA *Value,
|
||||
IN OUT AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
// Utility Functions
|
||||
VOID
|
||||
LibAmdMemFill (
|
||||
IN VOID *Destination,
|
||||
IN UINT8 Value,
|
||||
IN UINTN FillLength,
|
||||
IN OUT AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
VOID
|
||||
LibAmdMemCopy (
|
||||
IN VOID *Destination,
|
||||
IN VOID *Source,
|
||||
IN UINTN CopyLength,
|
||||
IN OUT AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
VOID *
|
||||
LibAmdLocateImage (
|
||||
IN VOID *StartAddress,
|
||||
IN VOID *EndAddress,
|
||||
IN UINT32 Alignment,
|
||||
IN CHAR8 ModuleSignature[8]
|
||||
);
|
||||
|
||||
UINT32
|
||||
LibAmdGetPackageType (
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
LibAmdVerifyImageChecksum (
|
||||
IN VOID *ImagePtr
|
||||
);
|
||||
|
||||
UINT8
|
||||
LibAmdBitScanReverse (
|
||||
IN UINT32 value
|
||||
);
|
||||
UINT8
|
||||
LibAmdBitScanForward (
|
||||
IN UINT32 value
|
||||
);
|
||||
|
||||
VOID
|
||||
LibAmdReadCpuReg (
|
||||
IN UINT8 RegNum,
|
||||
OUT UINT32 *Value
|
||||
);
|
||||
VOID
|
||||
LibAmdWriteCpuReg (
|
||||
IN UINT8 RegNum,
|
||||
IN UINT32 Value
|
||||
);
|
||||
|
||||
VOID
|
||||
LibAmdWriteBackInvalidateCache (
|
||||
IN VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
LibAmdSimNowEnterDebugger (VOID);
|
||||
|
||||
VOID
|
||||
LibAmdHDTBreakPoint (VOID);
|
||||
|
||||
UINT8
|
||||
LibAmdAccessWidth (
|
||||
IN ACCESS_WIDTH AccessWidth
|
||||
);
|
||||
|
||||
VOID
|
||||
LibAmdCLFlush (
|
||||
IN UINT64 Address,
|
||||
IN UINT8 Count
|
||||
);
|
||||
|
||||
VOID
|
||||
LibAmdFinit (
|
||||
VOID);
|
||||
|
||||
VOID
|
||||
StopHere (
|
||||
VOID
|
||||
);
|
||||
|
||||
#endif // _AMD_LIB_H_
|
||||
68
src/vendorcode/amd/agesa/f15tn/Lib/helper.c
Normal file
68
src/vendorcode/amd/agesa/f15tn/Lib/helper.c
Normal file
@ -0,0 +1,68 @@
|
||||
/*
|
||||
*****************************************************************************
|
||||
*
|
||||
* Copyright (c) 2011, Advanced Micro Devices, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* ***************************************************************************
|
||||
*
|
||||
*/
|
||||
|
||||
// helper.c - these functions are compiled separately because they redefine
|
||||
// functions invoked directly by the compiler code generator.
|
||||
// The Microsoft tools do not allow such functions to be compiled
|
||||
// with the "Enable link-time code generation (/GL)" option. Compile
|
||||
// this module without /GL to avoid a build failure LNK1237.
|
||||
//
|
||||
|
||||
#if defined (_MSC_VER)
|
||||
|
||||
#include "Porting.h"
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
void *memcpy (void *dest, const void *src, size_t bytes)
|
||||
{
|
||||
// Rep movsb is faster than a byte loop, but still quite slow
|
||||
// for large operations. However, it is a good choice here because
|
||||
// this function is intended for use by the compiler only. For
|
||||
// large copy operations, call LibAmdMemCopy.
|
||||
__movsb (dest, src, bytes);
|
||||
return dest;
|
||||
}
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
void *memset (void *dest, int value, size_t bytes)
|
||||
{
|
||||
// Rep stosb is faster than a byte loop, but still quite slow
|
||||
// for large operations. However, it is a good choice here because
|
||||
// this function is intended for use by the compiler only. For
|
||||
// large fill operations, call LibAmdMemFill.
|
||||
__stosb (dest, value, bytes);
|
||||
return dest;
|
||||
}
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
#endif
|
||||
629
src/vendorcode/amd/agesa/f15tn/Lib/x64/amdlib64.asm
Normal file
629
src/vendorcode/amd/agesa/f15tn/Lib/x64/amdlib64.asm
Normal file
@ -0,0 +1,629 @@
|
||||
;/**
|
||||
; * @file
|
||||
; *
|
||||
; * Agesa library 64bit
|
||||
; *
|
||||
; * Contains AMD AGESA Library
|
||||
; *
|
||||
; * @xrefitem bom "File Content Label" "Release Content"
|
||||
; * @e project: AGESA
|
||||
; * @e sub-project: Lib
|
||||
; * @e \$Revision: 17071 $ @e \$Date: 2009-07-30 10:13:11 -0700 (Thu, 30 Jul 2009) $
|
||||
; */
|
||||
;*****************************************************************************
|
||||
;
|
||||
; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
;
|
||||
; AMD is granting you permission to use this software (the Materials)
|
||||
; pursuant to the terms and conditions of your Software License Agreement
|
||||
; with AMD. This header does *NOT* give you permission to use the Materials
|
||||
; or any rights under AMD's intellectual property. Your use of any portion
|
||||
; of these Materials shall constitute your acceptance of those terms and
|
||||
; conditions. If you do not agree to the terms and conditions of the Software
|
||||
; License Agreement, please do not use any portion of these Materials.
|
||||
;
|
||||
; CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
; confidential and provided to you by AMD shall be kept confidential in
|
||||
; accordance with the terms and conditions of the Software License Agreement.
|
||||
;
|
||||
; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
; THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
;
|
||||
; AMD does not assume any responsibility for any errors which may appear in
|
||||
; the Materials or any other related information provided to you by AMD, or
|
||||
; result from use of the Materials or any related information.
|
||||
;
|
||||
; You agree that you will not reverse engineer or decompile the Materials.
|
||||
;
|
||||
; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
; further information, software, technical information, know-how, or show-how
|
||||
; available to you. Additionally, AMD retains the right to modify the
|
||||
; Materials at any time, without notice, and is not obligated to provide such
|
||||
; modified Materials to you.
|
||||
;
|
||||
; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
; subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
; Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
;
|
||||
; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
; direct product thereof will be exported directly or indirectly, into any
|
||||
; country prohibited by the United States Export Administration Act and the
|
||||
; regulations thereunder, without the required authorization from the U.S.
|
||||
; government nor will be used for any purpose prohibited by the same.
|
||||
;*****************************************************************************
|
||||
|
||||
.code
|
||||
;/*++
|
||||
|
||||
;/*---------------------------------------------------------------------------------------*/
|
||||
;/**
|
||||
; * Write IO byte
|
||||
; *
|
||||
; * @param[in] CX IO port address
|
||||
; * @param[in] DL IO port Value
|
||||
; */
|
||||
|
||||
PUBLIC WriteIo8
|
||||
WriteIo8 PROC
|
||||
mov al, dl
|
||||
mov dx, cx
|
||||
out dx, al
|
||||
ret
|
||||
WriteIo8 ENDP
|
||||
|
||||
;/*---------------------------------------------------------------------------------------*/
|
||||
;/**
|
||||
; * Write IO word
|
||||
; *
|
||||
; * @param[in] CX IO port address
|
||||
; * @param[in] DX IO port Value
|
||||
; */
|
||||
PUBLIC WriteIo16
|
||||
WriteIo16 PROC
|
||||
mov ax, dx
|
||||
mov dx, cx
|
||||
out dx, ax
|
||||
ret
|
||||
WriteIo16 ENDP
|
||||
|
||||
;/*---------------------------------------------------------------------------------------*/
|
||||
;/**
|
||||
; * Write IO dword
|
||||
; *
|
||||
; * @param[in] CX IO port address
|
||||
; * @param[in] EDX IO port Value
|
||||
; */
|
||||
|
||||
PUBLIC WriteIo32
|
||||
WriteIo32 PROC
|
||||
mov eax, edx
|
||||
mov dx, cx
|
||||
out dx, eax
|
||||
ret
|
||||
WriteIo32 ENDP
|
||||
|
||||
;/*---------------------------------------------------------------------------------------*/
|
||||
;/**
|
||||
; * Read IO byte
|
||||
; *
|
||||
; * @param[in] CX IO port address
|
||||
; * @retval AL IO port Value
|
||||
; */
|
||||
PUBLIC ReadIo8
|
||||
ReadIo8 PROC
|
||||
mov dx, cx
|
||||
in al, dx
|
||||
ret
|
||||
ReadIo8 ENDP
|
||||
|
||||
;/*---------------------------------------------------------------------------------------*/
|
||||
;/**
|
||||
; * Read IO word
|
||||
; *
|
||||
; * @param[in] CX IO port address
|
||||
; * @retval AX IO port Value
|
||||
; */
|
||||
PUBLIC ReadIo16
|
||||
ReadIo16 PROC
|
||||
mov dx, cx
|
||||
in ax, dx
|
||||
ret
|
||||
ReadIo16 ENDP
|
||||
|
||||
;/*---------------------------------------------------------------------------------------*/
|
||||
;/**
|
||||
; * Read IO dword
|
||||
; *
|
||||
; * @param[in] CX IO port address
|
||||
; * @retval EAX IO port Value
|
||||
; */
|
||||
PUBLIC ReadIo32
|
||||
ReadIo32 PROC
|
||||
mov dx, cx
|
||||
in eax, dx
|
||||
ret
|
||||
ReadIo32 ENDP
|
||||
|
||||
|
||||
;/*---------------------------------------------------------------------------------------*/
|
||||
;/**
|
||||
; * Read MSR
|
||||
; *
|
||||
; * @param[in] RCX MSR Address
|
||||
; * @param[in] RDX Pointer to data
|
||||
; * @param[in] R8D ConfigPtr (Optional)
|
||||
; */
|
||||
PUBLIC LibAmdMsrRead
|
||||
LibAmdMsrRead PROC
|
||||
push rsi
|
||||
mov rsi, rdx
|
||||
rdmsr
|
||||
mov [rsi], eax
|
||||
mov [rsi+4], edx
|
||||
pop rsi
|
||||
ret
|
||||
LibAmdMsrRead ENDP
|
||||
|
||||
;/*---------------------------------------------------------------------------------------*/
|
||||
;/**
|
||||
; * Write MSR
|
||||
; *
|
||||
; * @param[in] RCX MSR Address
|
||||
; * @param[in] RDX Pointer to data
|
||||
; * @param[in] R8D ConfigPtr (Optional)
|
||||
; */
|
||||
PUBLIC LibAmdMsrWrite
|
||||
LibAmdMsrWrite PROC
|
||||
push rsi
|
||||
mov rsi, rdx
|
||||
mov eax, [rsi]
|
||||
and rax, 0ffffffffh
|
||||
mov edx, [rsi+4]
|
||||
and rdx, 0ffffffffh
|
||||
wrmsr
|
||||
pop rsi
|
||||
ret
|
||||
LibAmdMsrWrite ENDP
|
||||
|
||||
;/*---------------------------------------------------------------------------------------*/
|
||||
;/**
|
||||
; * Read CPUID
|
||||
; *
|
||||
; * @param[in] RCX CPUID function
|
||||
; * @param[in] RDX Pointer to CPUID_DATA to save cpuid data
|
||||
; * @param[in] R8D ConfigPtr (Optional)
|
||||
; */
|
||||
PUBLIC LibAmdCpuidRead
|
||||
LibAmdCpuidRead PROC
|
||||
|
||||
push rbx
|
||||
push rsi
|
||||
mov rsi, rdx
|
||||
mov rax, rcx
|
||||
cpuid
|
||||
mov [rsi], eax
|
||||
mov [rsi+4], ebx
|
||||
mov [rsi+8], ecx
|
||||
mov [rsi+12],edx
|
||||
pop rsi
|
||||
pop rbx
|
||||
ret
|
||||
|
||||
LibAmdCpuidRead ENDP
|
||||
|
||||
;/*---------------------------------------------------------------------------------------*/
|
||||
;/**
|
||||
; * Read TSC
|
||||
; *
|
||||
; *
|
||||
; * @retval RAX Time stamp counter value
|
||||
; */
|
||||
|
||||
PUBLIC ReadTSC
|
||||
ReadTSC PROC
|
||||
rdtsc
|
||||
and rax, 0ffffffffh
|
||||
shl rdx, 32
|
||||
or rax, rdx
|
||||
ret
|
||||
ReadTSC ENDP
|
||||
|
||||
|
||||
;/*---------------------------------------------------------------------------------------*/
|
||||
;/**
|
||||
; * Read memory/MMIO byte
|
||||
; *
|
||||
; * @param[in] RCX - Memory Address
|
||||
; * @retval Memory byte at given address
|
||||
; */
|
||||
PUBLIC Read64Mem8
|
||||
Read64Mem8 PROC
|
||||
|
||||
xor rax, rax
|
||||
mov al, [rcx]
|
||||
ret
|
||||
|
||||
Read64Mem8 ENDP
|
||||
|
||||
;/*---------------------------------------------------------------------------------------*/
|
||||
;/**
|
||||
; * Read memory/MMIO word
|
||||
; *
|
||||
; * @param[in] RCX - Memory Address
|
||||
; * @retval Memory word at given address
|
||||
; */
|
||||
PUBLIC Read64Mem16
|
||||
Read64Mem16 PROC
|
||||
|
||||
xor rax, rax
|
||||
mov ax, [rcx]
|
||||
ret
|
||||
|
||||
Read64Mem16 ENDP
|
||||
|
||||
;/*---------------------------------------------------------------------------------------*/
|
||||
;/**
|
||||
; * Read memory/MMIO dword
|
||||
; *
|
||||
; * @param[in] RCX - Memory Address
|
||||
; * @retval Memory dword at given address
|
||||
; */
|
||||
PUBLIC Read64Mem32
|
||||
Read64Mem32 PROC
|
||||
|
||||
xor rax, rax
|
||||
mov eax, [rcx]
|
||||
ret
|
||||
|
||||
Read64Mem32 ENDP
|
||||
|
||||
|
||||
;/*---------------------------------------------------------------------------------------*/
|
||||
;/**
|
||||
; * Write memory/MMIO byte
|
||||
; *
|
||||
; * @param[in] RCX Memory Address
|
||||
; * @param[in] DL Value to write
|
||||
; */
|
||||
|
||||
PUBLIC Write64Mem8
|
||||
Write64Mem8 PROC
|
||||
|
||||
xor rax, rax
|
||||
mov rax, rdx
|
||||
mov [rcx], al
|
||||
ret
|
||||
|
||||
Write64Mem8 ENDP
|
||||
|
||||
;/*---------------------------------------------------------------------------------------*/
|
||||
;/**
|
||||
; * Write memory/MMIO word
|
||||
; *
|
||||
; * @param[in] RCX Memory Address
|
||||
; * @param[in] DX Value to write
|
||||
; */
|
||||
PUBLIC Write64Mem16
|
||||
Write64Mem16 PROC
|
||||
|
||||
xor rax, rax
|
||||
mov rax, rdx
|
||||
mov [rcx], ax
|
||||
ret
|
||||
|
||||
Write64Mem16 ENDP
|
||||
|
||||
;/*---------------------------------------------------------------------------------------*/
|
||||
;/**
|
||||
; * Write memory/MMIO dword
|
||||
; *
|
||||
; * @param[in] RCX Memory Address
|
||||
; * @param[in] EDX Value to write
|
||||
; */
|
||||
PUBLIC Write64Mem32
|
||||
Write64Mem32 PROC
|
||||
|
||||
xor rax, rax
|
||||
mov rax, rdx
|
||||
mov [rcx], eax
|
||||
ret
|
||||
|
||||
Write64Mem32 ENDP
|
||||
|
||||
;/*---------------------------------------------------------------------------------------*/
|
||||
;/**
|
||||
; * Read various CPU registers
|
||||
; *
|
||||
; * @param[in] CL Register ID (0/4 - CR0/CR4, 10h/11h/12h/13h/17h - DR0/DR1/DR2/DR3/DR7)
|
||||
; * @param[in] RDX Pointer to value
|
||||
; */
|
||||
|
||||
PUBLIC LibAmdReadCpuReg
|
||||
LibAmdReadCpuReg PROC
|
||||
|
||||
push rax
|
||||
xor rax, rax
|
||||
Reg00h:
|
||||
cmp cl, 00h
|
||||
jne Reg04h
|
||||
mov rax, cr0
|
||||
jmp RegRead
|
||||
Reg04h:
|
||||
cmp cl, 04h
|
||||
jne Reg10h
|
||||
mov rax, cr4
|
||||
jmp RegRead
|
||||
Reg10h:
|
||||
cmp cl, 10h
|
||||
jne Reg11h
|
||||
mov rax, dr0
|
||||
jmp RegRead
|
||||
Reg11h:
|
||||
cmp cl, 11h
|
||||
jne Reg12h
|
||||
mov rax, dr1
|
||||
jmp RegRead
|
||||
Reg12h:
|
||||
cmp cl, 12h
|
||||
jne Reg13h
|
||||
mov rax, dr2
|
||||
jmp RegRead
|
||||
Reg13h:
|
||||
cmp cl, 13h
|
||||
jne Reg17h
|
||||
mov rax, dr3
|
||||
jmp RegRead
|
||||
Reg17h:
|
||||
cmp cl, 17h
|
||||
jne RegRead
|
||||
mov rax, dr7
|
||||
RegRead:
|
||||
mov [rdx], eax
|
||||
pop rax
|
||||
ret
|
||||
LibAmdReadCpuReg ENDP
|
||||
|
||||
|
||||
|
||||
;/*---------------------------------------------------------------------------------------*/
|
||||
;/**
|
||||
; * Write various CPU registers
|
||||
; *
|
||||
; * @param[in] CL Register ID (0/4 - CR0/CR4, 10h/11h/12h/13h/17h - DR0/DR1/DR2/DR3/DR7)
|
||||
; * @param[in] RDX Value to write
|
||||
; */
|
||||
|
||||
PUBLIC LibAmdWriteCpuReg
|
||||
LibAmdWriteCpuReg PROC
|
||||
|
||||
push rax
|
||||
Reg00h:
|
||||
cmp cl, 00h
|
||||
jne Reg04h
|
||||
mov rax, cr0
|
||||
mov eax, edx
|
||||
mov cr0, rax
|
||||
jmp Done
|
||||
Reg04h:
|
||||
cmp cl, 04h
|
||||
jne Reg10h
|
||||
mov rax, cr4
|
||||
mov eax, edx
|
||||
mov cr4, rax
|
||||
jmp Done
|
||||
Reg10h:
|
||||
cmp cl, 10h
|
||||
jne Reg11h
|
||||
mov rax, dr0
|
||||
mov eax, edx
|
||||
mov dr0, rax
|
||||
jmp Done
|
||||
Reg11h:
|
||||
cmp cl, 11h
|
||||
jne Reg12h
|
||||
mov rax, dr1
|
||||
mov eax, edx
|
||||
mov dr1, rax
|
||||
jmp Done
|
||||
Reg12h:
|
||||
cmp cl, 12h
|
||||
jne Reg13h
|
||||
mov rax, dr2
|
||||
mov eax, edx
|
||||
mov dr2, rax
|
||||
jmp Done
|
||||
Reg13h:
|
||||
cmp cl, 13h
|
||||
jne Reg17h
|
||||
mov rax, dr3
|
||||
mov eax, edx
|
||||
mov dr3, rax
|
||||
jmp Done
|
||||
Reg17h:
|
||||
cmp cl, 17h
|
||||
jne Done
|
||||
mov rax, dr7
|
||||
mov eax, edx
|
||||
mov dr7, rax
|
||||
Done:
|
||||
pop rax
|
||||
ret
|
||||
LibAmdWriteCpuReg ENDP
|
||||
|
||||
;/*---------------------------------------------------------------------------------------*/
|
||||
;/**
|
||||
; * Write back invalidate caches using wbinvd.
|
||||
; *
|
||||
; *
|
||||
; *
|
||||
; */
|
||||
|
||||
PUBLIC LibAmdWriteBackInvalidateCache
|
||||
LibAmdWriteBackInvalidateCache PROC
|
||||
wbinvd
|
||||
ret
|
||||
LibAmdWriteBackInvalidateCache ENDP
|
||||
|
||||
;/*---------------------------------------------------------------------------------------*/
|
||||
;/**
|
||||
; * Stop CPU
|
||||
; *
|
||||
; *
|
||||
; *
|
||||
; */
|
||||
|
||||
PUBLIC StopHere
|
||||
StopHere PROC
|
||||
@@:
|
||||
jmp short @b
|
||||
StopHere ENDP
|
||||
|
||||
;/*---------------------------------------------------------------------------------------*/
|
||||
;/**
|
||||
; * Enter debugger on SimNow
|
||||
; *
|
||||
; *
|
||||
; *
|
||||
; */
|
||||
PUBLIC LibAmdSimNowEnterDebugger
|
||||
LibAmdSimNowEnterDebugger PROC
|
||||
pushfq
|
||||
mov rax, 0BACCD00Bh ; Backdoor in SimNow
|
||||
mov rbx, 2 ; Select breakpoint feature
|
||||
cpuid
|
||||
@@:
|
||||
jmp short @b
|
||||
popfq
|
||||
ret
|
||||
LibAmdSimNowEnterDebugger ENDP
|
||||
|
||||
;/*---------------------------------------------------------------------------------------*/
|
||||
;/**
|
||||
; * IDS IO port write
|
||||
; *
|
||||
; * @param[in] ECX IO Port Address
|
||||
; * @param[in] EDX Value to write
|
||||
; * @param[in] R8D IDS flags
|
||||
; *
|
||||
; */
|
||||
|
||||
PUBLIC IdsOutPort
|
||||
IdsOutPort PROC
|
||||
push rbx
|
||||
push rax
|
||||
|
||||
mov ebx, r8d
|
||||
mov eax, edx
|
||||
mov edx, ecx
|
||||
out dx, eax
|
||||
|
||||
pop rax
|
||||
pop rbx
|
||||
ret
|
||||
IdsOutPort ENDP
|
||||
|
||||
;/*---------------------------------------------------------------------------------------*/
|
||||
;/**
|
||||
; * Force breakpoint on HDT
|
||||
; *
|
||||
; *
|
||||
; */
|
||||
PUBLIC LibAmdHDTBreakPoint
|
||||
LibAmdHDTBreakPoint PROC
|
||||
|
||||
push rbx
|
||||
|
||||
mov rcx, 0C001100Ah ;bit 0 = HDT redirect
|
||||
mov rdi, 09C5A203Ah ;Password
|
||||
rdmsr
|
||||
and rax, 0ffffffffh
|
||||
or rax, 1
|
||||
|
||||
wrmsr
|
||||
|
||||
mov rax, 0B2h ;Marker = B2
|
||||
db 0F1h ;ICEBP
|
||||
|
||||
pop rbx
|
||||
ret
|
||||
|
||||
LibAmdHDTBreakPoint ENDP
|
||||
|
||||
;/*---------------------------------------------------------------------------------------*/
|
||||
;/**
|
||||
; * Find the most right hand side non-zero bit with
|
||||
; *
|
||||
; * @param[in] ECX Value
|
||||
; */
|
||||
PUBLIC LibAmdBitScanForward
|
||||
LibAmdBitScanForward PROC
|
||||
bsf eax, ecx
|
||||
jnz nonZeroSource
|
||||
mov al,32
|
||||
nonZeroSource:
|
||||
ret
|
||||
LibAmdBitScanForward ENDP
|
||||
|
||||
;/*---------------------------------------------------------------------------------------*/
|
||||
;/**
|
||||
; * Find the most left hand side non-zero bit.
|
||||
; *
|
||||
; * @param[in] ECX Value
|
||||
; */
|
||||
PUBLIC LibAmdBitScanReverse
|
||||
LibAmdBitScanReverse PROC
|
||||
bsr eax, ecx
|
||||
jnz nonZeroSource
|
||||
mov al,0FFh
|
||||
nonZeroSource:
|
||||
ret
|
||||
LibAmdBitScanReverse ENDP
|
||||
|
||||
;/*---------------------------------------------------------------------------------------*/
|
||||
;/**
|
||||
; * Flush specified number of cache line
|
||||
; *
|
||||
; * @param[in] RCX Physical address to be flushed
|
||||
; * @param[in] DL number of cachelines to be flushed
|
||||
; */
|
||||
PUBLIC LibAmdCLFlush
|
||||
LibAmdCLFlush PROC
|
||||
push rax
|
||||
mov rax, rcx
|
||||
movzx rcx, dl
|
||||
@@:
|
||||
mfence
|
||||
clflush [rax]
|
||||
mfence
|
||||
add rax,64
|
||||
loop @B
|
||||
pop rax
|
||||
ret
|
||||
LibAmdCLFlush ENDP
|
||||
|
||||
;/*---------------------------------------------------------------------------------------*/
|
||||
;/**
|
||||
; * FPU init
|
||||
; *
|
||||
; *
|
||||
; */
|
||||
PUBLIC LibAmdFinit
|
||||
LibAmdFinit PROC
|
||||
finit
|
||||
ret
|
||||
LibAmdFinit ENDP
|
||||
|
||||
END
|
||||
148
src/vendorcode/amd/agesa/f15tn/MainPage.h
Normal file
148
src/vendorcode/amd/agesa/f15tn/MainPage.h
Normal file
@ -0,0 +1,148 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* Create outline and references for mainpage documentation.
|
||||
*
|
||||
* Design guides, maintenance guides, and general documentation, are
|
||||
* collected using this file onto the documentation mainpage.
|
||||
* This file contains doxygen comment blocks, only.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: Documentation
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*
|
||||
*/
|
||||
/*
|
||||
******************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/**
|
||||
* @mainpage
|
||||
*
|
||||
* The design and maintenance documentation for AGESA Sample Code is organized as
|
||||
* follows. On this page, you can reference design guides, maintenance guides, and
|
||||
* general documentation. Detailed Data Structure, Function, and Interface documentation
|
||||
* may be found using the Data Structures or Files tabs. See Related Pages for a
|
||||
* Release content summary, and, if this is not a production release, lists of To Do's,
|
||||
* Deprecated items, etc.
|
||||
*
|
||||
* @subpage starthere "Start Here - Initial Porting and Integration."
|
||||
*
|
||||
* @subpage optionmain "Build Configuration and Options Guides and Documentation."
|
||||
*
|
||||
* @subpage commonmain "Processor Common Component Guides and Documentation."
|
||||
*
|
||||
* @subpage cpumain "CPU Component Guides and Documentation."
|
||||
*
|
||||
* @subpage htmain "HT Component Guides and Documentation."
|
||||
*
|
||||
* @subpage memmain "MEM Component Guides and Documentation."
|
||||
*
|
||||
* @subpage gnbmain "GNB Component Documentation."
|
||||
*
|
||||
* @subpage fchmain "FCH Component Documentation."
|
||||
*
|
||||
* @subpage idsmain "IDS Component Guides and Documentation."
|
||||
*
|
||||
* @subpage recoverymain "Recovery Component Guides and Documentation."
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
* @page starthere Initial Porting and Integration
|
||||
*
|
||||
* @par Basic Check List
|
||||
*
|
||||
* <ul>
|
||||
* <li> Copy the \<plat\>Options.c file from the Addendum directory to the platform tip build directory.
|
||||
* AMD recommends the use of a sub-directory named AGESA to contain these files and the build output files.
|
||||
* <li> Copy the OptionsIds.h content in the spec to OptionsIds.h in the platform build tip directory
|
||||
* and make changes to enable the IDS support desired. It is highly recommended to set the following for
|
||||
* initial integration and development:@n
|
||||
* @code
|
||||
* #define IDSOPT_IDS_ENABLED TRUE
|
||||
* #define IDSOPT_ERROR_TRAP_ENABLED TRUE
|
||||
* #define IDSOPT_ASSERT_ENABLED TRUE
|
||||
* @endcode
|
||||
* <li> Edit and modify the option selections in those two files to meet the needs of the specific platform.
|
||||
* <li> Set the environment variable AGESA_ROOT to the root folder of the AGESA code.
|
||||
* <li> Set the environment variable AGESA_OptsDir the platform build tip AGESA directory.
|
||||
* <li> Generate the doxygen documentation or locate the file arch2008.chm within your AGESA release package.
|
||||
* </ul>
|
||||
*
|
||||
* @par Debugging Using ASSERT and IDS_ERROR_TRAP
|
||||
*
|
||||
* While AGESA code uses ::ASSERT and ::IDS_ERROR_TRAP to check for internal errors, these macros can also
|
||||
* catch and assist debug of wrapper and platform BIOS issues.
|
||||
*
|
||||
* When an ::ASSERT fails or an ::IDS_ERROR_TRAP is executed, the AGESA code will enter a halt loop and display a
|
||||
* Stop Code. A Stop Code is eight hex digits. The first (most significant) four are the FILECODE.
|
||||
* FILECODEs can be looked up in Filecode.h to determine which file contains the stop macro. Each file has a
|
||||
* unique code value.
|
||||
* The least significant digits are the line number in that file.
|
||||
* For example, 0210 means the macro is on line two hundred ten.
|
||||
* (see ::IdsErrorStop for more details on stop code display.)
|
||||
*
|
||||
* Enabling ::ASSERT and ::IDS_ERROR_TRAP ensure errors are caught and also provide a useful debug assist.
|
||||
* Comments near each macro use will describe the nature of the error and typical wrapper errors or other
|
||||
* root causes.
|
||||
*
|
||||
* After your wrapper consistently executes ::ASSERT and ::IDS_ERROR_TRAP stop free, you can disable them in
|
||||
* OptionsIds.h, except for regression testing. IDS is not expected to be enabled in production BIOS builds.
|
||||
*
|
||||
*/
|
||||
95
src/vendorcode/amd/agesa/f15tn/Makefile.inc
Normal file
95
src/vendorcode/amd/agesa/f15tn/Makefile.inc
Normal file
@ -0,0 +1,95 @@
|
||||
#*****************************************************************************
|
||||
#
|
||||
# Copyright (c) 2012, Advanced Micro Devices, Inc.
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are met:
|
||||
# * Redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer.
|
||||
# * Redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution.
|
||||
# * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
||||
# its contributors may be used to endorse or promote products derived
|
||||
# from this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
# DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
||||
# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
#*****************************************************************************
|
||||
|
||||
# AGESA V5 Files
|
||||
AGESA_ROOT = src/vendorcode/amd/agesa/f15tn
|
||||
|
||||
AGESA_INC = -Isrc/mainboard/$(MAINBOARDDIR)
|
||||
AGESA_INC += -I$(AGESA_ROOT)
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Include
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Lib
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Legacy
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Proc/Common
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Proc/HT
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Feature
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Family
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Family/0x15
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Family/0x15/TN
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem/NB/TN
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS/Family
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS/Family/0x15
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Common
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Nb
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Nb/Family
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Nb/Family/0x15
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Nb/Feature
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/PCIe
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/PCIe/Family
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/PCIe/Family/0x15
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/PCIe/Feature
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Gfx
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Gfx/Family
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxConfig
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxInitLibV1
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbNbInitLibV1
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbSbLib
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieTrainingV1
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS/Family/0x15/TN
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Proc/HT/NbCommon
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem/Main
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS/Library
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbNbInitLibV4
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbIommuIvrs
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbIvrsLib
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbSbIommuLib
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbTable
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV4
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch/Common
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS/Debug
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieAspm
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Include/Library
|
||||
|
||||
AGESA_INC += -I$(src)/southbridge/amd/agesa/hudson
|
||||
|
||||
AGESA_CFLAGS =-march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing
|
||||
|
||||
export AGESA_ROOT := $(AGESA_ROOT)
|
||||
export AGESA_INC := $(AGESA_INC)
|
||||
export AGESA_CFLAGS := $(AGESA_CFLAGS)
|
||||
CC := $(CC) $(AGESA_INC) $(AGESA_CFLAGS)
|
||||
#######################################################################
|
||||
309
src/vendorcode/amd/agesa/f15tn/Porting.h
Normal file
309
src/vendorcode/amd/agesa/f15tn/Porting.h
Normal file
@ -0,0 +1,309 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* Describes compiler dependencies - to support several compile time environments
|
||||
*
|
||||
* Contains compiler environment porting descriptions
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: Includes
|
||||
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 03:16:51 -0600 (Wed, 22 Dec 2010) $
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2011 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef _PORTING_H_
|
||||
#define _PORTING_H_
|
||||
|
||||
#if defined (_MSC_VER)
|
||||
#include <intrin.h>
|
||||
void _disable (void);
|
||||
void _enable (void);
|
||||
#pragma warning(disable: 4103 4001 4733)
|
||||
#pragma intrinsic (_disable, _enable)
|
||||
#pragma warning(push)
|
||||
// -----------------------------------------------------------------------
|
||||
// Define a code_seg MACRO
|
||||
//
|
||||
#define MAKE_AS_A_STRING(arg) #arg
|
||||
|
||||
#define CODE_GROUP(arg) __pragma (code_seg (MAKE_AS_A_STRING (.t##arg)))
|
||||
|
||||
#define RDATA_GROUP(arg) __pragma (const_seg (MAKE_AS_A_STRING (.d##arg)))
|
||||
#define FUNC_ATTRIBUTE(arg) __declspec(arg)
|
||||
//#include <intrin.h> // MS has built-in functions
|
||||
|
||||
#if _MSC_VER < 900
|
||||
// -----------------------------------------------------------------------
|
||||
// Assume MSVC 1.52C (16-bit)
|
||||
//
|
||||
// NOTE: When using MSVC 1.52C use the following command line:
|
||||
//
|
||||
// CL.EXE /G3 /AL /O1i /Fa <FILENAME.C>
|
||||
//
|
||||
// This will produce 32-bit code in USE16 segment that is optimized for code
|
||||
// size.
|
||||
typedef void VOID;
|
||||
|
||||
// Create the universal 32, 16, and 8-bit data types
|
||||
typedef unsigned long UINTN;
|
||||
typedef long INT32;
|
||||
typedef unsigned long UINT32;
|
||||
typedef int INT16;
|
||||
typedef unsigned int UINT16;
|
||||
typedef char INT8;
|
||||
typedef unsigned char UINT8;
|
||||
typedef char CHAR8;
|
||||
typedef unsigned short CHAR16;
|
||||
|
||||
/// struct for 16-bit environment handling of 64-bit value
|
||||
typedef struct _UINT64 {
|
||||
IN OUT UINT32 lo; ///< lower 32-bits of 64-bit value
|
||||
IN OUT UINT32 hi; ///< highest 32-bits of 64-bit value
|
||||
} UINT64;
|
||||
|
||||
// Create the Boolean type
|
||||
#define TRUE 1
|
||||
#define FALSE 0
|
||||
typedef unsigned char BOOLEAN;
|
||||
|
||||
#define CONST const
|
||||
#define STATIC static
|
||||
#define VOLATILE volatile
|
||||
#define CALLCONV __pascal
|
||||
#define ROMDATA __based( __segname( "_CODE" ) )
|
||||
#define _16BYTE_ALIGN __declspec(align(16))
|
||||
|
||||
// Force tight packing of structures
|
||||
// Note: Entire AGESA (Project / Solution) will be using pragma pack 1
|
||||
#pragma warning( disable : 4103 ) // Disable '#pragma pack' in .h warning
|
||||
#pragma pack(1)
|
||||
|
||||
// Disable WORD->BYTE automatic conversion warnings. Example:
|
||||
// BYTE LocalByte;
|
||||
// void MyFunc(BYTE val);
|
||||
//
|
||||
// MyFunc(LocalByte*2+1); // Warning, automatic conversion
|
||||
//
|
||||
// The problem is any time math is performed on a BYTE, it is converted to a
|
||||
// WORD by MSVC 1.52c, and then when it is converted back to a BYTE, a warning
|
||||
// is generated. Disable warning C4761
|
||||
#pragma warning( disable : 4761 )
|
||||
|
||||
#else
|
||||
// -----------------------------------------------------------------------
|
||||
// Assume a 32-bit MSVC++
|
||||
//
|
||||
// Disable the following warnings:
|
||||
// 4100 - 'identifier' : unreferenced formal parameter
|
||||
// 4276 - 'function' : no prototype provided; assumed no parameters
|
||||
// 4214 - non standard extension used : bit field types other than int
|
||||
// 4001 - nonstandard extension 'single line comment' was used
|
||||
// 4142 - benign redefinition of type for following declaration
|
||||
// - typedef char INT8
|
||||
#if defined (_M_IX86)
|
||||
#pragma warning (disable: 4100 4276 4214 4001 4142 4305 4306)
|
||||
|
||||
#ifndef VOID
|
||||
typedef void VOID;
|
||||
#endif
|
||||
// Create the universal 32, 16, and 8-bit data types
|
||||
#ifndef UINTN
|
||||
typedef unsigned __w64 UINTN;
|
||||
#endif
|
||||
typedef __int64 INT64;
|
||||
typedef unsigned __int64 UINT64;
|
||||
typedef int INT32;
|
||||
typedef unsigned int UINT32;
|
||||
typedef short INT16;
|
||||
typedef unsigned short UINT16;
|
||||
typedef char INT8;
|
||||
typedef unsigned char UINT8;
|
||||
typedef char CHAR8;
|
||||
typedef unsigned short CHAR16;
|
||||
|
||||
// Create the Boolean type
|
||||
#ifndef TRUE
|
||||
#define TRUE 1
|
||||
#endif
|
||||
#ifndef FALSE
|
||||
#define FALSE 0
|
||||
#endif
|
||||
typedef unsigned char BOOLEAN;
|
||||
|
||||
// Force tight packing of structures
|
||||
// Note: Entire AGESA (Project / Solution) will be using pragma pack 1
|
||||
#pragma pack(1)
|
||||
|
||||
#define CONST const
|
||||
#define STATIC static
|
||||
#define VOLATILE volatile
|
||||
#define CALLCONV
|
||||
#define ROMDATA
|
||||
#define _16BYTE_ALIGN __declspec(align(64))
|
||||
// 64 bit of compiler
|
||||
#else
|
||||
#pragma warning (disable: 4100 4276 4214 4001 4142 4305 4306 4366)
|
||||
|
||||
#ifndef VOID
|
||||
typedef void VOID;
|
||||
#endif
|
||||
// Create the universal 32, 16, and 8-bit data types
|
||||
#ifndef UINTN
|
||||
typedef unsigned __int64 UINTN;
|
||||
#endif
|
||||
typedef __int64 INT64;
|
||||
typedef unsigned __int64 UINT64;
|
||||
typedef int INT32;
|
||||
typedef unsigned int UINT32;
|
||||
typedef short INT16;
|
||||
typedef unsigned short UINT16;
|
||||
typedef char INT8;
|
||||
typedef unsigned char UINT8;
|
||||
typedef char CHAR8;
|
||||
typedef unsigned short CHAR16;
|
||||
|
||||
// Create the Boolean type
|
||||
#ifndef TRUE
|
||||
#define TRUE 1
|
||||
#endif
|
||||
#ifndef FALSE
|
||||
#define FALSE 0
|
||||
#endif
|
||||
typedef unsigned char BOOLEAN;
|
||||
|
||||
// Force tight packing of structures
|
||||
// Note: Entire AGESA (Project / Solution) will be using pragma pack 1
|
||||
#pragma pack(1)
|
||||
|
||||
#define CONST const
|
||||
#define STATIC static
|
||||
#define VOLATILE volatile
|
||||
#define CALLCONV
|
||||
#define ROMDATA
|
||||
#endif
|
||||
#endif
|
||||
// -----------------------------------------------------------------------
|
||||
// End of MS compiler versions
|
||||
|
||||
#elif defined __GNUC__
|
||||
|
||||
#define IN
|
||||
#define OUT
|
||||
#define STATIC static
|
||||
#define VOLATILE volatile
|
||||
#define TRUE 1
|
||||
#define FALSE 0
|
||||
// #undef CONST
|
||||
#define CONST const
|
||||
#define ROMDATA
|
||||
#define CALLCONV
|
||||
#define _16BYTE_ALIGN __attribute__ ((aligned (16)))
|
||||
|
||||
typedef unsigned char BOOLEAN;
|
||||
typedef signed char INT8;
|
||||
typedef signed short INT16;
|
||||
typedef signed long INT32;
|
||||
typedef char CHAR8;
|
||||
typedef unsigned char UINT8;
|
||||
typedef unsigned short UINT16;
|
||||
typedef unsigned long UINT32;
|
||||
typedef unsigned long UINTN;
|
||||
typedef unsigned long long UINT64;
|
||||
typedef long long INT64;
|
||||
typedef void VOID;
|
||||
//typedef unsigned long size_t;
|
||||
|
||||
//#include <intrin.h> // MingW-w64 library header
|
||||
#pragma pack(1)
|
||||
|
||||
#define CODE_GROUP(arg)
|
||||
#define RDATA_GROUP(arg)
|
||||
|
||||
#define FUNC_ATTRIBUTE(arg) __attribute__((arg))
|
||||
#define MAKE_AS_A_STRING(arg) #arg
|
||||
#include <stddef.h>
|
||||
#include "gcc-intrin.h"
|
||||
|
||||
#include <assert.h>
|
||||
#include <console/console.h>
|
||||
#include <console/loglevel.h>
|
||||
|
||||
#ifndef NULL
|
||||
#define NULL (void *)0
|
||||
#endif
|
||||
|
||||
#else
|
||||
// -----------------------------------------------------------------------
|
||||
// Unknown or unsupported compiler
|
||||
//
|
||||
#error "Unknown compiler in use"
|
||||
#endif
|
||||
|
||||
// -----------------------------------------------------------------------
|
||||
// Common definitions for all compilers
|
||||
//
|
||||
|
||||
//Support forward reference construct
|
||||
#define AGESA_FORWARD_DECLARATION(x) typedef struct _##x x
|
||||
|
||||
// The following are use in conformance to the UEFI style guide
|
||||
#define IN
|
||||
#define OUT
|
||||
|
||||
#endif // _PORTING_H_
|
||||
@ -0,0 +1,234 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* AMD Family_15 P-state HPC mode Initialization
|
||||
*
|
||||
* Enables High performance Computing mode.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: CPU/Family/0x15
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*
|
||||
*/
|
||||
/*
|
||||
******************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* M O D U L E S U S E D
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
#include "AGESA.h"
|
||||
#include "amdlib.h"
|
||||
#include "GeneralServices.h"
|
||||
#include "cpuServices.h"
|
||||
#include "cpuRegisters.h"
|
||||
#include "cpuFamilyTranslation.h"
|
||||
#include "heapManager.h"
|
||||
#include "cpuF15PowerMgmt.h"
|
||||
#include "CommonReturns.h"
|
||||
#include "cpuPstateHpcMode.h"
|
||||
#include "cpuPstateTables.h"
|
||||
#include "Filecode.h"
|
||||
CODE_GROUP (G3_DXE)
|
||||
RDATA_GROUP (G3_DXE)
|
||||
|
||||
#define FILECODE PROC_CPU_FAMILY_0X15_F15PSTATEHPCMODE_FILECODE
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* D E F I N I T I O N S A N D M A C R O S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* T Y P E D E F S A N D S T R U C T U R E S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* E X P O R T E D F U N C T I O N S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* entry point for enabling High Performance Computing.
|
||||
*
|
||||
* This function must be run after P-states initialization and before enabling low power P-states
|
||||
*
|
||||
* @param[in] PstateHpcModeServices The current CPU's family services.
|
||||
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
|
||||
* @param[in] StdHeader Config handle for library and services.
|
||||
*
|
||||
* @retval AGESA_SUCCESS Always succeeds.
|
||||
*
|
||||
*/
|
||||
AGESA_STATUS
|
||||
STATIC
|
||||
F15InitializePstateHpcMode (
|
||||
IN PSTATE_HPC_MODE_FAMILY_SERVICES *PstateHpcModeServices,
|
||||
IN PLATFORM_CONFIGURATION *PlatformConfig,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
)
|
||||
{
|
||||
UINT8 OriginalPstate;
|
||||
UINT8 X;
|
||||
UINT32 Socket;
|
||||
UINT32 Module;
|
||||
UINT32 Core;
|
||||
UINT32 SocketCount;
|
||||
UINT32 i;
|
||||
UINT64 MsrData;
|
||||
PCI_ADDR PciAddr;
|
||||
AGESA_STATUS IgnoredSts;
|
||||
AGESA_STATUS Flag;
|
||||
F15_CPB_CTRL_REGISTER CpbCtrl;
|
||||
CLK_PWR_TIMING_CTRL2_REGISTER CPTC2;
|
||||
HTC_REGISTER Htc;
|
||||
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
|
||||
LOCATE_HEAP_PTR LocateHeapParams;
|
||||
PSTATE_LEVELING *PStateLevelingBuffer;
|
||||
PSTATE_LEVELING *PStateLevelingBufferTemp;
|
||||
|
||||
Flag = AGESA_SUCCESS;
|
||||
// Locate P-State data buffer
|
||||
LocateHeapParams.BufferHandle = AMD_PSTATE_DATA_BUFFER_HANDLE;
|
||||
if (HeapLocateBuffer (&LocateHeapParams, StdHeader) != AGESA_SUCCESS) {
|
||||
Flag = AGESA_ERROR;
|
||||
PStateLevelingBuffer = NULL;
|
||||
SocketCount = 1;
|
||||
} else {
|
||||
PStateLevelingBuffer = ((S_CPU_AMD_PSTATE *) (LocateHeapParams.BufferPtr))->PStateLevelingStruc;
|
||||
SocketCount = ((S_CPU_AMD_PSTATE *) (LocateHeapParams.BufferPtr))->TotalSocketInSystem;
|
||||
}
|
||||
|
||||
// Step1. Read MSRC001_0063[CurPstate] and store the value in OriginalPstate.
|
||||
LibAmdMsrRead (MSR_PSTATE_STS, &MsrData, StdHeader);
|
||||
OriginalPstate = (UINT8) (((PSTATE_STS_MSR *) &MsrData)->CurPstate);
|
||||
// Step2. Write 0 to MSRC001_0062[PstateCmd].
|
||||
// Step3. Wait for MSRC001_0063[CurPstate] == 0.
|
||||
GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
|
||||
FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 0, (BOOLEAN) TRUE, StdHeader);
|
||||
// Step4. If D18F4x15C[NumBoostStates] != D18F3xDC[PstateMaxVal], execute the following sequence
|
||||
// 4.A Set X = D18F4x15C[NumBoostStates].
|
||||
// 4.B If X+1 == D18F3xDC[PstateMaxVal], go to step 5.
|
||||
// 4.C Copy MSRC001_00[6B:64] indexed by P-state X to MSRC001_00[6B:64] indexed by P-state X+1.
|
||||
// 4.D Write 0b to PstateEn from MSRC001_00[6B:64] indexed by P-state X+1.
|
||||
// 4.E Set X = X+1 and go to step B.
|
||||
IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
|
||||
GetPciAddress (StdHeader, Socket, Module, &PciAddr, &IgnoredSts);
|
||||
PciAddr.Address.Function = FUNC_4;
|
||||
PciAddr.Address.Register = CPB_CTRL_REG;
|
||||
LibAmdPciRead (AccessWidth32, PciAddr, &CpbCtrl, StdHeader); // F4x15C
|
||||
|
||||
PciAddr.Address.Function = FUNC_3;
|
||||
PciAddr.Address.Register = CPTC2_REG;
|
||||
LibAmdPciRead (AccessWidth32, PciAddr, &CPTC2, StdHeader); // F3xDC
|
||||
|
||||
// In case that F3xDC[PstateMaxVal] was increased by Low Power Pstate function during the first time of running that function.
|
||||
// Get the real PstateMaxVal by checking C001_00[6B:64][PsEnable]
|
||||
while (CPTC2.PstateMaxVal != 0) {
|
||||
LibAmdMsrRead ((PS_REG_BASE + CPTC2.PstateMaxVal), &MsrData, StdHeader);
|
||||
if ((MsrData & BIT63) == BIT63) {
|
||||
break;
|
||||
}
|
||||
CPTC2.PstateMaxVal--;
|
||||
}
|
||||
|
||||
if (CpbCtrl.NumBoostStates != CPTC2.PstateMaxVal) {
|
||||
X = (UINT8) CpbCtrl.NumBoostStates;
|
||||
while ((X + 1) < (UINT8) CPTC2.PstateMaxVal) {
|
||||
LibAmdMsrRead ((PS_REG_BASE + X), &MsrData, StdHeader);
|
||||
MsrData &= ~BIT63;
|
||||
LibAmdMsrWrite ((PS_REG_BASE + X + 1), &MsrData, StdHeader);
|
||||
// Make sure Agesa doesn't declared the P-states modified by these algorithms to the OS
|
||||
if (PStateLevelingBuffer != NULL) {
|
||||
PStateLevelingBufferTemp = PStateLevelingBuffer;
|
||||
for (i = 0; i < SocketCount; i++) {
|
||||
PStateLevelingBufferTemp->PStateCoreStruct[0].PStateStruct[X + 1].PStateEnable = 0;
|
||||
//Calculate next node buffer address
|
||||
PStateLevelingBufferTemp = (PSTATE_LEVELING *) ((UINT8 *) PStateLevelingBufferTemp + (UINTN) sizeof (PSTATE_LEVELING) + (UINTN) (PStateLevelingBufferTemp->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES)));
|
||||
}
|
||||
}
|
||||
X++;
|
||||
}
|
||||
}
|
||||
// Step5. Write OriginalPstate to MSRC001_0062[PstateCmd].
|
||||
// Step6. Wait for MSRC001_0063[CurPstate] == OriginalPstate.
|
||||
FamilySpecificServices->TransitionPstate (FamilySpecificServices, OriginalPstate, (BOOLEAN) TRUE, StdHeader);
|
||||
// Step7. Write D18F3x64[HtcPstateLimit] with the value from D18F3xDC[PstateMaxVal]
|
||||
PciAddr.Address.Register = HTC_REG;
|
||||
LibAmdPciRead (AccessWidth32, PciAddr, &Htc, StdHeader); // F3x64
|
||||
Htc.HtcPstateLimit = CPTC2.PstateMaxVal;
|
||||
LibAmdPciWrite (AccessWidth32, PciAddr, &Htc, StdHeader); // F3x64
|
||||
|
||||
return Flag;
|
||||
}
|
||||
|
||||
|
||||
|
||||
CONST PSTATE_HPC_MODE_FAMILY_SERVICES ROMDATA F15PstateHpcSupport =
|
||||
{
|
||||
0,
|
||||
F15InitializePstateHpcMode
|
||||
};
|
||||
@ -0,0 +1,224 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* AMD Family_15 Trinity C6 C-state feature support functions.
|
||||
*
|
||||
* Provides the functions necessary to initialize the C6 feature.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: CPU/F15/TN
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*
|
||||
*/
|
||||
/*
|
||||
******************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* M O D U L E S U S E D
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
#include "AGESA.h"
|
||||
#include "amdlib.h"
|
||||
#include "Ids.h"
|
||||
#include "cpuRegisters.h"
|
||||
#include "cpuFeatures.h"
|
||||
#include "cpuC6State.h"
|
||||
#include "cpuApicUtilities.h"
|
||||
#include "cpuF15PowerMgmt.h"
|
||||
#include "cpuF15TnPowerMgmt.h"
|
||||
#include "cpuEarlyInit.h"
|
||||
#include "cpuServices.h"
|
||||
#include "cpuFamilyTranslation.h"
|
||||
#include "Filecode.h"
|
||||
CODE_GROUP (G3_DXE)
|
||||
RDATA_GROUP (G3_DXE)
|
||||
|
||||
#define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNC6STATE_FILECODE
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* D E F I N I T I O N S A N D M A C R O S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* T Y P E D E F S A N D S T R U C T U R E S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
VOID
|
||||
F15TnReloadMicrocodePatchAfterMemInit (
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* E X P O R T E D F U N C T I O N S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Is C6 supported on this CPU
|
||||
*
|
||||
* @param[in] C6Services Pointer to this CPU's C6 family services.
|
||||
* @param[in] Socket This core's zero-based socket number.
|
||||
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
|
||||
* @param[in] StdHeader Config Handle for library, services.
|
||||
*
|
||||
* @retval TRUE C6 state is supported.
|
||||
* @retval FALSE C6 state is not supported.
|
||||
*
|
||||
*/
|
||||
BOOLEAN
|
||||
STATIC
|
||||
F15TnIsC6Supported (
|
||||
IN C6_FAMILY_SERVICES *C6Services,
|
||||
IN UINT32 Socket,
|
||||
IN PLATFORM_CONFIGURATION *PlatformConfig,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
)
|
||||
{
|
||||
ASSERT (IsFeatureEnabled (CacheFlushOnHalt, PlatformConfig, StdHeader) == TRUE);
|
||||
// Assuming CFOH is always enabled.
|
||||
return (IsFeatureEnabled (IoCstate, PlatformConfig, StdHeader));
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Enable C6 on a family 15h CPU.
|
||||
*
|
||||
* @param[in] C6Services Pointer to this CPU's C6 family services.
|
||||
* @param[in] EntryPoint Timepoint designator.
|
||||
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
|
||||
* @param[in] StdHeader Config Handle for library, services.
|
||||
*
|
||||
* @return AGESA_SUCCESS Always succeeds.
|
||||
*
|
||||
*/
|
||||
AGESA_STATUS
|
||||
STATIC
|
||||
F15TnInitializeC6 (
|
||||
IN C6_FAMILY_SERVICES *C6Services,
|
||||
IN UINT64 EntryPoint,
|
||||
IN PLATFORM_CONFIGURATION *PlatformConfig,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
)
|
||||
{
|
||||
PCI_ADDR PciAddress;
|
||||
CSTATE_CTRL1_REGISTER CstateCtrl1;
|
||||
POPUP_PSTATE_REGISTER PopDownPstate;
|
||||
CLK_PWR_TIMING_CTRL2_REGISTER ClkPwrTimingCtrl2;
|
||||
|
||||
if ((EntryPoint & CPU_FEAT_AFTER_PM_INIT) != 0) {
|
||||
// Initialize F4x118
|
||||
PciAddress.AddressValue = CSTATE_CTRL1_PCI_ADDR;
|
||||
LibAmdPciRead (AccessWidth32, PciAddress, &CstateCtrl1, StdHeader);
|
||||
// Set C-state Action Field 0
|
||||
CstateCtrl1.PwrGateEnCstAct0 = 1;
|
||||
CstateCtrl1.PwrOffEnCstAct0 = 1;
|
||||
CstateCtrl1.NbPwrGate0 = 1;
|
||||
CstateCtrl1.NbClkGate0 = 1;
|
||||
CstateCtrl1.SelfRefr0 = 1;
|
||||
CstateCtrl1.CpuPrbEnCstAct0 = 1;
|
||||
// Set C-state Action Field 1
|
||||
CstateCtrl1.PwrGateEnCstAct1 = 1;
|
||||
CstateCtrl1.PwrOffEnCstAct1 = 1;
|
||||
CstateCtrl1.NbPwrGate1 = 1;
|
||||
CstateCtrl1.NbClkGate1 = 1;
|
||||
CstateCtrl1.SelfRefr1 = 1;
|
||||
CstateCtrl1.CpuPrbEnCstAct1 = 1;
|
||||
LibAmdPciWrite (AccessWidth32, PciAddress, &CstateCtrl1, StdHeader);
|
||||
|
||||
// Initialize F3xA8[PopDownPstate] = F3xDC[PstateMaxVal]
|
||||
PciAddress.AddressValue = CPTC2_PCI_ADDR;
|
||||
LibAmdPciRead (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader);
|
||||
PciAddress.AddressValue = POPUP_PSTATE_PCI_ADDR;
|
||||
LibAmdPciRead (AccessWidth32, PciAddress, &PopDownPstate, StdHeader);
|
||||
PopDownPstate.PopDownPstate = ClkPwrTimingCtrl2.PstateMaxVal;
|
||||
LibAmdPciWrite (AccessWidth32, PciAddress, &PopDownPstate, StdHeader);
|
||||
}
|
||||
|
||||
return AGESA_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* Reload microcode patch after memory is initialized.
|
||||
*
|
||||
* @param[in] StdHeader Config Handle for library, services.
|
||||
*
|
||||
*/
|
||||
VOID
|
||||
F15TnReloadMicrocodePatchAfterMemInit (
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
)
|
||||
{
|
||||
LoadMicrocodePatch (StdHeader);
|
||||
}
|
||||
|
||||
CONST C6_FAMILY_SERVICES ROMDATA F15TnC6Support =
|
||||
{
|
||||
0,
|
||||
F15TnIsC6Supported,
|
||||
F15TnInitializeC6,
|
||||
F15TnReloadMicrocodePatchAfterMemInit
|
||||
};
|
||||
@ -0,0 +1,204 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* AMD Family_15 CPB Initialization
|
||||
*
|
||||
* Enables core performance boost.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: CPU/F15/TN
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*
|
||||
*/
|
||||
/*
|
||||
******************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* M O D U L E S U S E D
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
#include "AGESA.h"
|
||||
#include "amdlib.h"
|
||||
#include "GeneralServices.h"
|
||||
#include "cpuFamilyTranslation.h"
|
||||
#include "cpuF15PowerMgmt.h"
|
||||
#include "cpuF15TnPowerMgmt.h"
|
||||
#include "cpuFeatures.h"
|
||||
#include "cpuCpb.h"
|
||||
#include "Filecode.h"
|
||||
CODE_GROUP (G3_DXE)
|
||||
RDATA_GROUP (G3_DXE)
|
||||
|
||||
#define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNCPB_FILECODE
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* D E F I N I T I O N S A N D M A C R O S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* T Y P E D E F S A N D S T R U C T U R E S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* E X P O R T E D F U N C T I O N S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* BSC entry point for checking whether or not CPB is supported.
|
||||
*
|
||||
* @param[in] CpbServices The current CPU's family services.
|
||||
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
|
||||
* @param[in] Socket Zero based socket number to check.
|
||||
* @param[in] StdHeader Config handle for library and services.
|
||||
*
|
||||
* @retval TRUE CPB is supported.
|
||||
* @retval FALSE CPB is not supported.
|
||||
*
|
||||
*/
|
||||
BOOLEAN
|
||||
STATIC
|
||||
F15TnIsCpbSupported (
|
||||
IN CPB_FAMILY_SERVICES *CpbServices,
|
||||
IN PLATFORM_CONFIGURATION *PlatformConfig,
|
||||
IN UINT32 Socket,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
)
|
||||
{
|
||||
CPB_CTRL_REGISTER CpbControl;
|
||||
PCI_ADDR PciAddress;
|
||||
|
||||
PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
|
||||
LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader);
|
||||
return (BOOLEAN) (CpbControl.NumBoostStates != 0);
|
||||
}
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* BSC entry point for for enabling Core Performance Boost.
|
||||
*
|
||||
* Set up D18F4x15C[BoostSrc] and start the PDMs according to the BKDG.
|
||||
*
|
||||
* @param[in] CpbServices The current CPU's family services.
|
||||
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
|
||||
* @param[in] EntryPoint Current CPU feature dispatch point.
|
||||
* @param[in] Socket Zero based socket number to check.
|
||||
* @param[in] StdHeader Config handle for library and services.
|
||||
*
|
||||
* @retval AGESA_SUCCESS Always succeeds.
|
||||
*
|
||||
*/
|
||||
AGESA_STATUS
|
||||
STATIC
|
||||
F15TnInitializeCpb (
|
||||
IN CPB_FAMILY_SERVICES *CpbServices,
|
||||
IN PLATFORM_CONFIGURATION *PlatformConfig,
|
||||
IN UINT64 EntryPoint,
|
||||
IN UINT32 Socket,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
)
|
||||
{
|
||||
CPB_CTRL_REGISTER CpbControl;
|
||||
PCI_ADDR PciAddress;
|
||||
F15_PSTATE_MSR PstateMsrData;
|
||||
UINT32 Pbx;
|
||||
|
||||
if ((EntryPoint & CPU_FEAT_AFTER_PM_INIT) != 0) {
|
||||
PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
|
||||
LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader);
|
||||
if (CpbControl.NumBoostStates == 0) {
|
||||
CpbControl.ApmMasterEn = 0;
|
||||
} else {
|
||||
CpbControl.ApmMasterEn = 1;
|
||||
}
|
||||
LibAmdPciWrite (AccessWidth32, PciAddress, &CpbControl, StdHeader);
|
||||
|
||||
} else if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) {
|
||||
PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
|
||||
LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader);
|
||||
if ((CpbControl.BoostSrc == 0) && (CpbControl.NumBoostStates != 0)) {
|
||||
// If any boosted P-state is still enabled, set BoostSrc = 1.
|
||||
for (Pbx = 0; Pbx < CpbControl.NumBoostStates; Pbx++) {
|
||||
LibAmdMsrRead (PS_REG_BASE + Pbx, (UINT64 *)&PstateMsrData, StdHeader);
|
||||
if (PstateMsrData.PsEnable == 1) {
|
||||
CpbControl.BoostSrc = 1;
|
||||
LibAmdPciWrite (AccessWidth32, PciAddress, &CpbControl, StdHeader);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
return AGESA_SUCCESS;
|
||||
}
|
||||
|
||||
CONST CPB_FAMILY_SERVICES ROMDATA F15TnCpbSupport =
|
||||
{
|
||||
0,
|
||||
F15TnIsCpbSupported,
|
||||
F15TnInitializeCpb
|
||||
};
|
||||
@ -0,0 +1,155 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* AMD Family_15 Trinity Equivalence Table related data
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: CPU/Family/0x15/TN
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*
|
||||
*/
|
||||
/*
|
||||
******************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* M O D U L E S U S E D
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
#include "AGESA.h"
|
||||
#include "cpuFamilyTranslation.h"
|
||||
#include "Filecode.h"
|
||||
#include "amdlib.h"
|
||||
#include "cpuRegisters.h"
|
||||
CODE_GROUP (G2_PEI)
|
||||
RDATA_GROUP (G2_PEI)
|
||||
|
||||
#define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNEQUIVALENCETABLE_FILECODE
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* D E F I N I T I O N S A N D M A C R O S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* T Y P E D E F S A N D S T R U C T U R E S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
VOID
|
||||
GetF15TnMicrocodeEquivalenceTable (
|
||||
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
|
||||
OUT CONST VOID **TnEquivalenceTablePtr,
|
||||
OUT UINT8 *NumberOfElements,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* E X P O R T E D F U N C T I O N S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
STATIC CONST UINT16 ROMDATA CpuF15TnMicrocodeEquivalenceTable[] =
|
||||
{
|
||||
0x6101, 0x6101,
|
||||
0x6100, 0x6100
|
||||
};
|
||||
|
||||
// Unencrypted equivalent
|
||||
STATIC CONST UINT16 ROMDATA CpuF15TnUnEncryptedMicrocodeEquivalenceTable[] =
|
||||
{
|
||||
0x6101, 0x6901,
|
||||
0x6100, 0x6900
|
||||
};
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Returns the appropriate microcode patch equivalent ID table.
|
||||
*
|
||||
* @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
|
||||
*
|
||||
* @param[in] FamilySpecificServices The current Family Specific Services.
|
||||
* @param[out] TnEquivalenceTablePtr Points to the first entry in the table.
|
||||
* @param[out] NumberOfElements Number of valid entries in the table.
|
||||
* @param[in] StdHeader Header for library and services.
|
||||
*
|
||||
*/
|
||||
VOID
|
||||
GetF15TnMicrocodeEquivalenceTable (
|
||||
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
|
||||
OUT CONST VOID **TnEquivalenceTablePtr,
|
||||
OUT UINT8 *NumberOfElements,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
)
|
||||
{
|
||||
UINT64 MsrDeCfg;
|
||||
|
||||
LibAmdMsrRead (MSR_DE_CFG, &MsrDeCfg, StdHeader);
|
||||
if ((MsrDeCfg & 0x80000) == 0) {
|
||||
*NumberOfElements = ((sizeof (CpuF15TnUnEncryptedMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
|
||||
*TnEquivalenceTablePtr = CpuF15TnUnEncryptedMicrocodeEquivalenceTable;
|
||||
} else {
|
||||
*NumberOfElements = ((sizeof (CpuF15TnMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
|
||||
*TnEquivalenceTablePtr = CpuF15TnMicrocodeEquivalenceTable;
|
||||
}
|
||||
}
|
||||
|
||||
@ -0,0 +1,315 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* Initialize the Family 15h Trinity specific way of running early initialization.
|
||||
*
|
||||
* Returns the table of initialization steps to perform at
|
||||
* AmdInitEarly.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: CPU/FAMILY/0x15/TN
|
||||
* @e \$Revision: 64491 $ @e \$Date: 2012-01-23 12:37:30 -0600 (Mon, 23 Jan 2012) $
|
||||
*
|
||||
*/
|
||||
/*
|
||||
******************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* M O D U L E S U S E D
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
#include "AGESA.h"
|
||||
#include "amdlib.h"
|
||||
#include "cpuFamilyTranslation.h"
|
||||
#include "Filecode.h"
|
||||
#include "GeneralServices.h"
|
||||
#include "heapManager.h"
|
||||
#include "Fch.h"
|
||||
#include "Gnb.h"
|
||||
#include "GnbLib.h"
|
||||
#include "cpuEarlyInit.h"
|
||||
#include "cpuF15TnPowerMgmt.h"
|
||||
CODE_GROUP (G2_PEI)
|
||||
RDATA_GROUP (G2_PEI)
|
||||
#define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNINITEARLYTABLE_FILECODE
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* D E F I N I T I O N S A N D M A C R O S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* T Y P E D E F S A N D S T R U C T U R E S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
VOID
|
||||
F15TnLoadMicrocodePatchAtEarly (
|
||||
IN CPU_SPECIFIC_SERVICES *FamilyServices,
|
||||
IN AMD_CPU_EARLY_PARAMS *EarlyParams,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
VOID
|
||||
GetF15TnEarlyInitOnCoreTable (
|
||||
IN CPU_SPECIFIC_SERVICES *FamilyServices,
|
||||
OUT CONST S_PERFORM_EARLY_INIT_ON_CORE **Table,
|
||||
IN AMD_CPU_EARLY_PARAMS *EarlyParams,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
VOID
|
||||
ApplyWorkaroundForFchErratum39 (
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
VOID
|
||||
F15TnNbPstateForceBeforeApLaunchAtEarly (
|
||||
IN CPU_SPECIFIC_SERVICES *FamilyServices,
|
||||
IN AMD_CPU_EARLY_PARAMS *EarlyParams,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* E X P O R T E D F U N C T I O N S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
extern F_PERFORM_EARLY_INIT_ON_CORE SetRegistersFromTablesAtEarly;
|
||||
extern F_PERFORM_EARLY_INIT_ON_CORE F15SetBrandIdRegistersAtEarly;
|
||||
extern F_PERFORM_EARLY_INIT_ON_CORE LocalApicInitializationAtEarly;
|
||||
|
||||
CONST S_PERFORM_EARLY_INIT_ON_CORE ROMDATA F15TnEarlyInitOnCoreTable[] =
|
||||
{
|
||||
{SetRegistersFromTablesAtEarly, PERFORM_EARLY_ANY_CONDITION},
|
||||
{F15SetBrandIdRegistersAtEarly, PERFORM_EARLY_ANY_CONDITION},
|
||||
{LocalApicInitializationAtEarly, PERFORM_EARLY_ANY_CONDITION},
|
||||
{F15TnLoadMicrocodePatchAtEarly, PERFORM_EARLY_ANY_CONDITION},
|
||||
{F15TnNbPstateForceBeforeApLaunchAtEarly, PERFORM_EARLY_WARM_RESET},
|
||||
{NULL, 0}
|
||||
};
|
||||
|
||||
/*------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Initializer routine that may be invoked at AmdCpuEarly to return the steps that a
|
||||
* processor that uses the standard initialization steps should take.
|
||||
*
|
||||
* @CpuServiceMethod{::F_GET_EARLY_INIT_TABLE}.
|
||||
*
|
||||
* @param[in] FamilyServices The current Family Specific Services.
|
||||
* @param[out] Table Table of appropriate init steps for the executing core.
|
||||
* @param[in] EarlyParams Service Interface structure to initialize.
|
||||
* @param[in] StdHeader Opaque handle to standard config header.
|
||||
*
|
||||
*/
|
||||
VOID
|
||||
GetF15TnEarlyInitOnCoreTable (
|
||||
IN CPU_SPECIFIC_SERVICES *FamilyServices,
|
||||
OUT CONST S_PERFORM_EARLY_INIT_ON_CORE **Table,
|
||||
IN AMD_CPU_EARLY_PARAMS *EarlyParams,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
)
|
||||
{
|
||||
*Table = F15TnEarlyInitOnCoreTable;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Update microcode patch in current processor for Family15h TN.
|
||||
*
|
||||
* This function acts as a wrapper for calling the LoadMicrocodePatch
|
||||
* routine at AmdInitEarly.
|
||||
*
|
||||
* @param[in] FamilyServices The current Family Specific Services.
|
||||
* @param[in] EarlyParams Service parameters.
|
||||
* @param[in] StdHeader Config handle for library and services.
|
||||
*
|
||||
*/
|
||||
VOID
|
||||
F15TnLoadMicrocodePatchAtEarly (
|
||||
IN CPU_SPECIFIC_SERVICES *FamilyServices,
|
||||
IN AMD_CPU_EARLY_PARAMS *EarlyParams,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
)
|
||||
{
|
||||
BOOLEAN IsPatchLoaded;
|
||||
|
||||
AGESA_TESTPOINT (TpProcCpuLoadUcode, StdHeader);
|
||||
|
||||
if (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, StdHeader)) {
|
||||
IsPatchLoaded = LoadMicrocodePatch (StdHeader);
|
||||
}
|
||||
|
||||
// After microcode patch has been loaded, apply the workaround for FCH erratum 39
|
||||
ApplyWorkaroundForFchErratum39 (StdHeader);
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Apply the workaround for FCH H2/H3 erratum #39.
|
||||
*
|
||||
* This function detects the FCH version and applies the appropriate workaround, if
|
||||
* required.
|
||||
*
|
||||
* @param[in] StdHeader Config handle for library and services.
|
||||
*
|
||||
*/
|
||||
VOID
|
||||
ApplyWorkaroundForFchErratum39 (
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
)
|
||||
{
|
||||
UINT8 MiscReg51;
|
||||
UINT8 RevisionId;
|
||||
UINT16 AcpiPmTmrBlk;
|
||||
UINT32 VendorIdDeviceId;
|
||||
UINT64 MsrValue;
|
||||
PCI_ADDR PciAddress;
|
||||
AGESA_STATUS IgnoredSts;
|
||||
CPU_LOGICAL_ID LogicalId;
|
||||
|
||||
// Read Vendor ID / Device ID
|
||||
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0, 0);
|
||||
LibAmdPciRead (AccessWidth32, PciAddress, &VendorIdDeviceId, StdHeader);
|
||||
|
||||
// For Hudson based system, perform workaround
|
||||
if (VendorIdDeviceId == 0x780B1022) {
|
||||
PciAddress.Address.Register = 0x8;
|
||||
LibAmdPciRead (AccessWidth8, PciAddress, &RevisionId, StdHeader);
|
||||
if ((RevisionId == 0x14) && IsBsp (StdHeader, &IgnoredSts)) {
|
||||
// Enable hardware workaround by setting Misc_reg x51[0]
|
||||
LibAmdMemRead (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + MISC_BASE + 0x51), &MiscReg51, StdHeader);
|
||||
MiscReg51 |= BIT0;
|
||||
LibAmdMemWrite (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + MISC_BASE + 0x51), &MiscReg51, StdHeader);
|
||||
} else if (RevisionId == 0x13) {
|
||||
GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
|
||||
if ((LogicalId.Revision & AMD_F15_TN_GT_A0) != 0) {
|
||||
// For revs A1+, set up the C0010055 MSR
|
||||
GnbLibIndirectIoBlockRead (0xCD6, 0xCD7, AccessWidth8, 0x64, 2, &AcpiPmTmrBlk, StdHeader);
|
||||
LibAmdMsrRead (0xC0010055, &MsrValue, StdHeader);
|
||||
MsrValue |= BIT30;
|
||||
MsrValue |= AcpiPmTmrBlk;
|
||||
LibAmdMsrWrite (0xC0010055, &MsrValue, StdHeader);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Prevent NB P-state transitions prior to AP launch on Family 15h TN.
|
||||
*
|
||||
* This function determines the current NB P-state and forces the NB to remain
|
||||
* in that P-state.
|
||||
*
|
||||
* @param[in] FamilyServices The current Family Specific Services.
|
||||
* @param[in] EarlyParams Service parameters.
|
||||
* @param[in] StdHeader Config handle for library and services.
|
||||
*
|
||||
*/
|
||||
VOID
|
||||
F15TnNbPstateForceBeforeApLaunchAtEarly (
|
||||
IN CPU_SPECIFIC_SERVICES *FamilyServices,
|
||||
IN AMD_CPU_EARLY_PARAMS *EarlyParams,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
)
|
||||
{
|
||||
UINT64 MsrValue;
|
||||
UINT64 PerfCtrlSave;
|
||||
UINT64 PerfStsSave;
|
||||
PCI_ADDR PciAddress;
|
||||
AGESA_STATUS IgnoredSts;
|
||||
ALLOCATE_HEAP_PARAMS Alloc;
|
||||
NB_PSTATE_CTRL_REGISTER NbPsCtrl;
|
||||
|
||||
if (IsBsp (StdHeader, &IgnoredSts) && FamilyServices->IsNbPstateEnabled (FamilyServices, &EarlyParams->PlatformConfig, StdHeader)) {
|
||||
LibAmdMsrRead (MSR_NB_PERF_CTL3, &PerfCtrlSave, StdHeader);
|
||||
MsrValue = 0x00000006004004E9;
|
||||
LibAmdMsrRead (MSR_NB_PERF_CTR3, &PerfStsSave, StdHeader);
|
||||
LibAmdMsrWrite (MSR_NB_PERF_CTL3, &MsrValue, StdHeader);
|
||||
MsrValue = 0;
|
||||
LibAmdMsrWrite (MSR_NB_PERF_CTR3, &MsrValue, StdHeader);
|
||||
PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR;
|
||||
LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader);
|
||||
Alloc.RequestedBufferSize = sizeof (NB_PSTATE_CTRL_REGISTER);
|
||||
Alloc.BufferHandle = AMD_CPU_NB_PSTATE_FIXUP_HANDLE;
|
||||
Alloc.Persist = 0;
|
||||
if (HeapAllocateBuffer (&Alloc, StdHeader) == AGESA_SUCCESS) {
|
||||
*((NB_PSTATE_CTRL_REGISTER *) Alloc.BufferPtr) = NbPsCtrl;
|
||||
} else {
|
||||
ASSERT (FALSE);
|
||||
}
|
||||
LibAmdMsrRead (MSR_NB_PERF_CTR3, &MsrValue, StdHeader);
|
||||
if (MsrValue == 0) {
|
||||
NbPsCtrl.SwNbPstateLoDis = 1;
|
||||
} else {
|
||||
NbPsCtrl.SwNbPstateLoDis = 0;
|
||||
NbPsCtrl.NbPstateDisOnP0 = 0;
|
||||
NbPsCtrl.NbPstateThreshold = 0;
|
||||
}
|
||||
LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader);
|
||||
LibAmdMsrWrite (MSR_NB_PERF_CTL3, &PerfCtrlSave, StdHeader);
|
||||
LibAmdMsrWrite (MSR_NB_PERF_CTR3, &PerfStsSave, StdHeader);
|
||||
}
|
||||
}
|
||||
|
||||
@ -0,0 +1,402 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* AMD Family_15 Trinity IO C-state feature support functions.
|
||||
*
|
||||
* Provides the functions necessary to initialize the IO C-state feature.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: CPU/Family/0x15/TN
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*
|
||||
*/
|
||||
/*
|
||||
******************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
******************************************************************************
|
||||
*/
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* M O D U L E S U S E D
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#include "AGESA.h"
|
||||
#include "amdlib.h"
|
||||
#include "Ids.h"
|
||||
#include "cpuFeatures.h"
|
||||
#include "cpuIoCstate.h"
|
||||
#include "cpuF15PowerMgmt.h"
|
||||
#include "cpuF15TnPowerMgmt.h"
|
||||
#include "cpuLateInit.h"
|
||||
#include "cpuRegisters.h"
|
||||
#include "cpuServices.h"
|
||||
#include "cpuApicUtilities.h"
|
||||
#include "cpuFamilyTranslation.h"
|
||||
#include "CommonReturns.h"
|
||||
#include "Filecode.h"
|
||||
CODE_GROUP (G3_DXE)
|
||||
RDATA_GROUP (G3_DXE)
|
||||
#define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNIOCSTATE_FILECODE
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
VOID
|
||||
STATIC
|
||||
F15TnInitializeIoCstateOnCore (
|
||||
IN VOID *CstateBaseMsr,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
F15TnIsCsdObjGenerated (
|
||||
IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* D E F I N I T I O N S A N D M A C R O S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
extern CPU_FAMILY_SUPPORT_TABLE IoCstateFamilyServiceTable;
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* E X P O R T E D F U N C T I O N S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Enable IO Cstate on a family 15h Trinity CPU.
|
||||
* Implement BIOS Requirements for Initialization of C-states
|
||||
*
|
||||
* @param[in] IoCstateServices Pointer to this CPU's IO Cstate family services.
|
||||
* @param[in] EntryPoint Timepoint designator.
|
||||
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
|
||||
* @param[in] StdHeader Config Handle for library, services.
|
||||
*
|
||||
* @return AGESA_SUCCESS Always succeeds.
|
||||
*
|
||||
*/
|
||||
AGESA_STATUS
|
||||
STATIC
|
||||
F15TnInitializeIoCstate (
|
||||
IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
|
||||
IN UINT64 EntryPoint,
|
||||
IN PLATFORM_CONFIGURATION *PlatformConfig,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
)
|
||||
{
|
||||
UINT64 LocalMsrRegister;
|
||||
AP_TASK TaskPtr;
|
||||
PCI_ADDR PciAddress;
|
||||
CSTATE_POLICY_CTRL1_REGISTER CstatePolicyCtrl1;
|
||||
|
||||
if ((EntryPoint & CPU_FEAT_AFTER_PM_INIT) != 0) {
|
||||
// Initialize F4x128
|
||||
// bit[1] CoreCstatePolicy = 0
|
||||
// bit[4:2] HaltCstateIndex = 0
|
||||
// bit[31] CstateMsgDis = 1
|
||||
PciAddress.AddressValue = CSTATE_POLICY_CTRL1_PCI_ADDR;
|
||||
LibAmdPciRead (AccessWidth32, PciAddress, &CstatePolicyCtrl1, StdHeader);
|
||||
CstatePolicyCtrl1.CoreCstatePolicy = 0;
|
||||
CstatePolicyCtrl1.HaltCstateIndex = 0;
|
||||
CstatePolicyCtrl1.CstateMsgDis = 1;
|
||||
LibAmdPciWrite (AccessWidth32, PciAddress, &CstatePolicyCtrl1, StdHeader);
|
||||
|
||||
// Initialize MSRC001_0073[CstateAddr] on each core to a region of
|
||||
// the IO address map with 8 consecutive available addresses.
|
||||
LocalMsrRegister = 0;
|
||||
|
||||
IDS_HDT_CONSOLE (CPU_TRACE, " Init IO C-state Base at 0x%x\n", PlatformConfig->CStateIoBaseAddress);
|
||||
((CSTATE_ADDRESS_MSR *) &LocalMsrRegister)->CstateAddr = PlatformConfig->CStateIoBaseAddress;
|
||||
|
||||
TaskPtr.FuncAddress.PfApTaskI = F15TnInitializeIoCstateOnCore;
|
||||
TaskPtr.DataTransfer.DataSizeInDwords = 2;
|
||||
TaskPtr.DataTransfer.DataPtr = &LocalMsrRegister;
|
||||
TaskPtr.DataTransfer.DataTransferFlags = 0;
|
||||
TaskPtr.ExeFlags = WAIT_FOR_CORE;
|
||||
ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL);
|
||||
}
|
||||
return AGESA_SUCCESS;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Enable CState on a family 15h Trinity core.
|
||||
*
|
||||
* @param[in] CstateBaseMsr MSR value to write to C001_0073 as determined by core 0.
|
||||
* @param[in] StdHeader Config Handle for library, services.
|
||||
*
|
||||
*/
|
||||
VOID
|
||||
STATIC
|
||||
F15TnInitializeIoCstateOnCore (
|
||||
IN VOID *CstateBaseMsr,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
)
|
||||
{
|
||||
// Initialize MSRC001_0073[CstateAddr] on each core
|
||||
LibAmdMsrWrite (MSR_CSTATE_ADDRESS, (UINT64 *) CstateBaseMsr, StdHeader);
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Returns the size of CST object
|
||||
*
|
||||
* @param[in] IoCstateServices IO Cstate services.
|
||||
* @param[in] PlatformConfig Contains the runtime modifiable feature input data
|
||||
* @param[in] StdHeader Config Handle for library, services.
|
||||
*
|
||||
* @retval CstObjSize Size of CST Object
|
||||
*
|
||||
*/
|
||||
UINT32
|
||||
STATIC
|
||||
F15TnGetAcpiCstObj (
|
||||
IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
|
||||
IN PLATFORM_CONFIGURATION *PlatformConfig,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
)
|
||||
{
|
||||
BOOLEAN GenerateCsdObj;
|
||||
UINT32 CStateAcpiObjSize;
|
||||
IO_CSTATE_FAMILY_SERVICES *FamilyServices;
|
||||
ACPI_CST_GET_INPUT CstGetInput;
|
||||
|
||||
CstGetInput.IoCstateServices = IoCstateServices;
|
||||
CstGetInput.PlatformConfig = PlatformConfig;
|
||||
CstGetInput.CStateAcpiObjSizePtr = &CStateAcpiObjSize;
|
||||
|
||||
IDS_SKIP_HOOK (IDS_CST_SIZE, &CstGetInput, StdHeader) {
|
||||
CStateAcpiObjSize = CST_HEADER_SIZE + CST_BODY_SIZE;
|
||||
|
||||
// If CSD Object is generated, add the size of CSD Object to the total size of
|
||||
// CState ACPI Object size
|
||||
GetFeatureServicesOfCurrentCore (&IoCstateFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader);
|
||||
ASSERT (FamilyServices != NULL);
|
||||
GenerateCsdObj = FamilyServices->IsCsdObjGenerated (FamilyServices, StdHeader);
|
||||
|
||||
if (GenerateCsdObj) {
|
||||
CStateAcpiObjSize += CSD_HEADER_SIZE + CSD_BODY_SIZE;
|
||||
}
|
||||
}
|
||||
return CStateAcpiObjSize;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Routine to generate the C-State ACPI objects
|
||||
*
|
||||
* @param[in] IoCstateServices IO Cstate services.
|
||||
* @param[in] LocalApicId Local Apic Id for each core.
|
||||
* @param[in, out] **PstateAcpiBufferPtr Pointer to the Acpi Buffer Pointer.
|
||||
* @param[in] StdHeader Config Handle for library, services.
|
||||
*
|
||||
*/
|
||||
VOID
|
||||
STATIC
|
||||
F15TnCreateAcpiCstObj (
|
||||
IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
|
||||
IN UINT8 LocalApicId,
|
||||
IN OUT VOID **PstateAcpiBufferPtr,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
)
|
||||
{
|
||||
UINT64 MsrData;
|
||||
BOOLEAN GenerateCsdObj;
|
||||
CST_HEADER_STRUCT *CstHeaderPtr;
|
||||
CST_BODY_STRUCT *CstBodyPtr;
|
||||
CSD_HEADER_STRUCT *CsdHeaderPtr;
|
||||
CSD_BODY_STRUCT *CsdBodyPtr;
|
||||
IO_CSTATE_FAMILY_SERVICES *FamilyServices;
|
||||
ACPI_CST_CREATE_INPUT CstInput;
|
||||
|
||||
CstInput.IoCstateServices = IoCstateServices;
|
||||
CstInput.LocalApicId = LocalApicId;
|
||||
CstInput.PstateAcpiBufferPtr = PstateAcpiBufferPtr;
|
||||
|
||||
IDS_SKIP_HOOK (IDS_CST_CREATE, &CstInput, StdHeader) {
|
||||
// Read from MSR C0010073 to obtain CstateAddr
|
||||
LibAmdMsrRead (MSR_CSTATE_ADDRESS, &MsrData, StdHeader);
|
||||
|
||||
// Typecast the pointer
|
||||
CstHeaderPtr = (CST_HEADER_STRUCT *) *PstateAcpiBufferPtr;
|
||||
|
||||
// Set CST Header
|
||||
CstHeaderPtr->NameOpcode = NAME_OPCODE;
|
||||
CstHeaderPtr->CstName_a__ = CST_NAME__;
|
||||
CstHeaderPtr->CstName_a_C = CST_NAME_C;
|
||||
CstHeaderPtr->CstName_a_S = CST_NAME_S;
|
||||
CstHeaderPtr->CstName_a_T = CST_NAME_T;
|
||||
|
||||
// Typecast the pointer
|
||||
CstHeaderPtr++;
|
||||
CstBodyPtr = (CST_BODY_STRUCT *) CstHeaderPtr;
|
||||
|
||||
// Set CST Body
|
||||
CstBodyPtr->PkgOpcode = PACKAGE_OPCODE;
|
||||
CstBodyPtr->PkgLength = CST_LENGTH;
|
||||
CstBodyPtr->PkgElements = CST_NUM_OF_ELEMENTS;
|
||||
CstBodyPtr->BytePrefix = BYTE_PREFIX_OPCODE;
|
||||
CstBodyPtr->Count = CST_COUNT;
|
||||
CstBodyPtr->PkgOpcode2 = PACKAGE_OPCODE;
|
||||
CstBodyPtr->PkgLength2 = CST_PKG_LENGTH;
|
||||
CstBodyPtr->PkgElements2 = CST_PKG_ELEMENTS;
|
||||
CstBodyPtr->BufferOpcode = BUFFER_OPCODE;
|
||||
CstBodyPtr->BufferLength = CST_SUBPKG_LENGTH;
|
||||
CstBodyPtr->BufferElements = CST_SUBPKG_ELEMENTS;
|
||||
CstBodyPtr->BufferOpcode2 = BUFFER_OPCODE;
|
||||
CstBodyPtr->GdrOpcode = GENERIC_REG_DESCRIPTION;
|
||||
CstBodyPtr->GdrLength = CST_GDR_LENGTH;
|
||||
CstBodyPtr->AddrSpaceId = GDR_ASI_SYSTEM_IO;
|
||||
CstBodyPtr->RegBitWidth = 0x08;
|
||||
CstBodyPtr->RegBitOffset = 0x00;
|
||||
CstBodyPtr->AddressSize = GDR_ASZ_BYTE_ACCESS;
|
||||
CstBodyPtr->RegisterAddr = ((CSTATE_ADDRESS_MSR *) &MsrData)->CstateAddr + 1;
|
||||
CstBodyPtr->EndTag = 0x0079;
|
||||
CstBodyPtr->BytePrefix2 = BYTE_PREFIX_OPCODE;
|
||||
CstBodyPtr->Type = CST_C2_TYPE;
|
||||
CstBodyPtr->WordPrefix = WORD_PREFIX_OPCODE;
|
||||
CstBodyPtr->Latency = 100;
|
||||
CstBodyPtr->DWordPrefix = DWORD_PREFIX_OPCODE;
|
||||
CstBodyPtr->Power = 0;
|
||||
|
||||
CstBodyPtr++;
|
||||
//Update the pointer
|
||||
*PstateAcpiBufferPtr = CstBodyPtr;
|
||||
|
||||
|
||||
// Check whether CSD object should be generated
|
||||
GetFeatureServicesOfCurrentCore (&IoCstateFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader);
|
||||
ASSERT (FamilyServices != NULL);
|
||||
GenerateCsdObj = FamilyServices->IsCsdObjGenerated (FamilyServices, StdHeader);
|
||||
|
||||
if (GenerateCsdObj) {
|
||||
CsdHeaderPtr = (CSD_HEADER_STRUCT *) *PstateAcpiBufferPtr;
|
||||
|
||||
// Set CSD Header
|
||||
CsdHeaderPtr->NameOpcode = NAME_OPCODE;
|
||||
CsdHeaderPtr->CsdName_a__ = CST_NAME__;
|
||||
CsdHeaderPtr->CsdName_a_C = CST_NAME_C;
|
||||
CsdHeaderPtr->CsdName_a_S = CST_NAME_S;
|
||||
CsdHeaderPtr->CsdName_a_D = CSD_NAME_D;
|
||||
|
||||
CsdHeaderPtr++;
|
||||
CsdBodyPtr = (CSD_BODY_STRUCT *) CsdHeaderPtr;
|
||||
|
||||
// Set CSD Body
|
||||
CsdBodyPtr->PkgOpcode = PACKAGE_OPCODE;
|
||||
CsdBodyPtr->PkgLength = CSD_BODY_SIZE - 1;
|
||||
CsdBodyPtr->PkgElements = 1;
|
||||
CsdBodyPtr->PkgOpcode2 = PACKAGE_OPCODE;
|
||||
CsdBodyPtr->PkgLength2 = CSD_BODY_SIZE - 4; // CSD_BODY_SIZE - Package() - Package Opcode
|
||||
CsdBodyPtr->PkgElements2 = 6;
|
||||
CsdBodyPtr->BytePrefix = BYTE_PREFIX_OPCODE;
|
||||
CsdBodyPtr->NumEntries = 6;
|
||||
CsdBodyPtr->BytePrefix2 = BYTE_PREFIX_OPCODE;
|
||||
CsdBodyPtr->Revision = 0;
|
||||
CsdBodyPtr->DWordPrefix = DWORD_PREFIX_OPCODE;
|
||||
CsdBodyPtr->Domain = (LocalApicId & 0xFE) >> 1;
|
||||
CsdBodyPtr->DWordPrefix2 = DWORD_PREFIX_OPCODE;
|
||||
CsdBodyPtr->CoordType = CSD_COORD_TYPE_HW_ALL;
|
||||
CsdBodyPtr->DWordPrefix3 = DWORD_PREFIX_OPCODE;
|
||||
CsdBodyPtr->NumProcessors = 0x2;
|
||||
CsdBodyPtr->DWordPrefix4 = DWORD_PREFIX_OPCODE;
|
||||
CsdBodyPtr->Index = 0x0;
|
||||
|
||||
CsdBodyPtr++;
|
||||
|
||||
// Update the pointer
|
||||
*PstateAcpiBufferPtr = CsdBodyPtr;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Routine to check whether CSD object should be created.
|
||||
*
|
||||
* @param[in] IoCstateServices IO Cstate services.
|
||||
* @param[in] StdHeader Config Handle for library, services.
|
||||
*
|
||||
* @retval TRUE CSD Object should be created.
|
||||
* @retval FALSE CSD Object should not be created.
|
||||
*
|
||||
*/
|
||||
BOOLEAN
|
||||
F15TnIsCsdObjGenerated (
|
||||
IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
)
|
||||
{
|
||||
// CSD Object should only be created when there are two cores per compute unit
|
||||
if (GetComputeUnitMapping (StdHeader) == EvenCoresMapping) {
|
||||
return TRUE;
|
||||
}
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F15TnIoCstateSupport =
|
||||
{
|
||||
0,
|
||||
(PF_IO_CSTATE_IS_SUPPORTED) CommonReturnTrue,
|
||||
F15TnInitializeIoCstate,
|
||||
F15TnGetAcpiCstObj,
|
||||
F15TnCreateAcpiCstObj,
|
||||
F15TnIsCsdObjGenerated
|
||||
};
|
||||
@ -0,0 +1,134 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* AMD Family_15 Trinity Logical ID Table
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: CPU/Family/0x15/TN
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*
|
||||
*/
|
||||
/*
|
||||
******************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* M O D U L E S U S E D
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
#include "AGESA.h"
|
||||
#include "cpuRegisters.h"
|
||||
#include "Filecode.h"
|
||||
CODE_GROUP (G3_DXE)
|
||||
RDATA_GROUP (G3_DXE)
|
||||
|
||||
#define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNLOGICALIDTABLES_FILECODE
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* D E F I N I T I O N S A N D M A C R O S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* T Y P E D E F S A N D S T R U C T U R E S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
VOID
|
||||
GetF15TnLogicalIdAndRev (
|
||||
OUT CONST CPU_LOGICAL_ID_XLAT **TnIdPtr,
|
||||
OUT UINT8 *NumberOfElements,
|
||||
OUT UINT64 *LogicalFamily,
|
||||
IN OUT AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* E X P O R T E D F U N C T I O N S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
STATIC CONST CPU_LOGICAL_ID_XLAT ROMDATA CpuF15TnLogicalIdAndRevArray[] =
|
||||
{
|
||||
{
|
||||
0x6101,
|
||||
AMD_F15_TN_A1
|
||||
},
|
||||
{
|
||||
0x6100,
|
||||
0x0000000000000100ull
|
||||
}
|
||||
};
|
||||
|
||||
VOID
|
||||
GetF15TnLogicalIdAndRev (
|
||||
OUT CONST CPU_LOGICAL_ID_XLAT **TnIdPtr,
|
||||
OUT UINT8 *NumberOfElements,
|
||||
OUT UINT64 *LogicalFamily,
|
||||
IN OUT AMD_CONFIG_PARAMS *StdHeader
|
||||
)
|
||||
{
|
||||
*NumberOfElements = (sizeof (CpuF15TnLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT));
|
||||
*TnIdPtr = CpuF15TnLogicalIdAndRevArray;
|
||||
*LogicalFamily = AMD_FAMILY_15_TN;
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,138 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* AMD Family_15 Trinity microcode patches
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: CPU/Family/0x15/TN
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*
|
||||
*/
|
||||
/*
|
||||
******************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* M O D U L E S U S E D
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
#include "AGESA.h"
|
||||
#include "cpuRegisters.h"
|
||||
#include "cpuEarlyInit.h"
|
||||
#include "cpuFamilyTranslation.h"
|
||||
#include "Filecode.h"
|
||||
CODE_GROUP (G3_DXE)
|
||||
RDATA_GROUP (G3_DXE)
|
||||
|
||||
|
||||
#define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNMICROCODEPATCHTABLES_FILECODE
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* D E F I N I T I O N S A N D M A C R O S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* T Y P E D E F S A N D S T R U C T U R E S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
extern CONST MICROCODE_PATCHES_4K ROMDATA *CpuF15TnMicroCodePatchArray[];
|
||||
extern CONST UINT8 ROMDATA CpuF15TnNumberOfMicrocodePatches;
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
VOID
|
||||
GetF15TnMicroCodePatchesStruct (
|
||||
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
|
||||
OUT CONST VOID **TnUcodePtr,
|
||||
OUT UINT8 *NumberOfElements,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* E X P O R T E D F U N C T I O N S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Returns a table containing the appropriate microcode patches.
|
||||
*
|
||||
* @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
|
||||
*
|
||||
* @param[in] FamilySpecificServices The current Family Specific Services.
|
||||
* @param[out] TnUcodePtr Points to the first entry in the table.
|
||||
* @param[out] NumberOfElements Number of valid entries in the table.
|
||||
* @param[in] StdHeader Header for library and services.
|
||||
*
|
||||
*/
|
||||
VOID
|
||||
GetF15TnMicroCodePatchesStruct (
|
||||
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
|
||||
OUT CONST VOID **TnUcodePtr,
|
||||
OUT UINT8 *NumberOfElements,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
)
|
||||
{
|
||||
*NumberOfElements = CpuF15TnNumberOfMicrocodePatches;
|
||||
*TnUcodePtr = &CpuF15TnMicroCodePatchArray[0];
|
||||
}
|
||||
|
||||
@ -0,0 +1,324 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* AMD Family_15 Trinity MSR tables with values as defined in BKDG
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: CPU/Family/0x15/TN
|
||||
* @e \$Revision: 63495 $ @e \$Date: 2011-12-23 01:30:59 -0600 (Fri, 23 Dec 2011) $
|
||||
*
|
||||
*/
|
||||
/*
|
||||
******************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* M O D U L E S U S E D
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
#include "AGESA.h"
|
||||
#include "amdlib.h"
|
||||
#include "cpuRegisters.h"
|
||||
#include "cpuF15TnPowerMgmt.h"
|
||||
#include "F15TnPackageType.h"
|
||||
#include "Table.h"
|
||||
#include "Filecode.h"
|
||||
CODE_GROUP (G3_DXE)
|
||||
RDATA_GROUP (G3_DXE)
|
||||
|
||||
#define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNMSRTABLES_FILECODE
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* D E F I N I T I O N S A N D M A C R O S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* T Y P E D E F S A N D S T R U C T U R E S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
VOID
|
||||
STATIC
|
||||
SetTopologyExtensions (
|
||||
IN UINT32 Data,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
VOID
|
||||
STATIC
|
||||
SetForceSmcCheckFlwStDis (
|
||||
IN UINT32 Data,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* E X P O R T E D F U N C T I O N S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F15TnMsrRegisters[] =
|
||||
{
|
||||
// M S R T a b l e s
|
||||
// ----------------------
|
||||
|
||||
// MSR_NB_CFG (0xC001001F)
|
||||
// bit[23] = 1, erratum #663
|
||||
{
|
||||
MsrRegister,
|
||||
{
|
||||
(AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily
|
||||
AMD_F15_TN_ALL // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MSR_NB_CFG, // MSR Address
|
||||
0x0000000000800000, // OR Mask
|
||||
0x0000000000800000, // NAND Mask
|
||||
}}
|
||||
},
|
||||
|
||||
// MSR_LS_CFG2 (0xC001102D)
|
||||
// bit[23] DisScbThreshold = 1
|
||||
{
|
||||
MsrRegister,
|
||||
{
|
||||
(AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily
|
||||
AMD_F15_TN_ALL // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MSR_LS_CFG2, // MSR Address
|
||||
0x0000000000800000, // OR Mask
|
||||
0x0000000000800000, // NAND Mask
|
||||
}}
|
||||
},
|
||||
// MSR_HWCR (0xC0010015)
|
||||
// bit[27] EffFreqReadOnlyLock = 1
|
||||
// bit[12] HltXSpCycEn = 1
|
||||
{
|
||||
MsrRegister,
|
||||
{
|
||||
(AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily
|
||||
AMD_F15_TN_ALL // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MSR_HWCR, // MSR Address
|
||||
0x0000000008001000, // OR Mask
|
||||
0x0000000008001000, // NAND Mask
|
||||
}}
|
||||
},
|
||||
// MSR_OSVW_ID_Length (0xC0010140)
|
||||
// bit[15:0] = 4
|
||||
{
|
||||
MsrRegister,
|
||||
{
|
||||
(AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily
|
||||
AMD_F15_TN_ALL // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MSR_OSVW_ID_Length, // MSR Address
|
||||
0x0000000000000004, // OR Mask
|
||||
0x000000000000FFFF, // NAND Mask
|
||||
}}
|
||||
},
|
||||
// MSR 0xC0011000
|
||||
// bit[17] = 1, Disable Erratum #671
|
||||
// bit[16] = 1, Erratum #608 for all TN revisions
|
||||
{
|
||||
MsrRegister,
|
||||
{
|
||||
(AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily
|
||||
AMD_F15_TN_ALL // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
0xC0011000, // MSR Address
|
||||
0x0000000000030000, // OR Mask
|
||||
0x0000000000030000, // NAND Mask
|
||||
}}
|
||||
},
|
||||
// MSR_CPUID_EXT_FEATS (0xC0011005)
|
||||
// bit[51] NodeId = 1
|
||||
{
|
||||
MsrRegister,
|
||||
{
|
||||
(AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily
|
||||
AMD_F15_TN_ALL // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MSR_CPUID_EXT_FEATS, // MSR Address
|
||||
0x0008000000000000, // OR Mask
|
||||
0x0008000000000000, // NAND Mask
|
||||
}}
|
||||
},
|
||||
};
|
||||
|
||||
CONST REGISTER_TABLE ROMDATA F15TnMsrRegisterTable = {
|
||||
AllCores,
|
||||
(sizeof (F15TnMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
|
||||
(TABLE_ENTRY_FIELDS *) &F15TnMsrRegisters,
|
||||
};
|
||||
|
||||
// MSR with Special Programming Requirements Table
|
||||
|
||||
STATIC CONST FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_INITIALIZER ROMDATA F15TnMsrWorkarounds[] =
|
||||
{
|
||||
// MSR_C001_1005
|
||||
{
|
||||
FamSpecificWorkaround,
|
||||
{
|
||||
(AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily
|
||||
AMD_F15_TN_ALL // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
SetTopologyExtensions, // function call
|
||||
0x00000000, // data
|
||||
}}
|
||||
},
|
||||
// MSR_C001_102D
|
||||
{
|
||||
FamSpecificWorkaround,
|
||||
{
|
||||
(AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily
|
||||
AMD_F15_TN_ALL // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
SetForceSmcCheckFlwStDis, // function call
|
||||
0x00000000, // data
|
||||
}}
|
||||
},
|
||||
};
|
||||
|
||||
CONST REGISTER_TABLE ROMDATA F15TnMsrWorkaroundTable = {
|
||||
AllCores,
|
||||
(sizeof (F15TnMsrWorkarounds) / sizeof (TABLE_ENTRY_FIELDS)),
|
||||
(TABLE_ENTRY_FIELDS *) F15TnMsrWorkarounds,
|
||||
};
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* MSR special programming requirements for MSR_C001_1005
|
||||
*
|
||||
* AGESA should program MSR_C001_1005[54, TopologyExtensions] as follows:
|
||||
* IF (CPUID Fn8000_0001_EBX[PkgType]==0010b) THEN 0 ELSE 1 ENDIF.
|
||||
*
|
||||
* @param[in] Data The table data value, for example to indicate which CPU and Platform types matched.
|
||||
* @param[in] StdHeader Config handle for library and services.
|
||||
*
|
||||
*/
|
||||
VOID
|
||||
STATIC
|
||||
SetTopologyExtensions (
|
||||
IN UINT32 Data,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
)
|
||||
{
|
||||
UINT32 PkgType;
|
||||
UINT64 CpuMsrData;
|
||||
|
||||
PkgType = LibAmdGetPackageType (StdHeader);
|
||||
LibAmdMsrRead (MSR_CPUID_EXT_FEATS, &CpuMsrData, StdHeader);
|
||||
CpuMsrData &= ~(BIT54);
|
||||
if (PkgType == PACKAGE_TYPE_FM2) {
|
||||
CpuMsrData |= BIT54;
|
||||
}
|
||||
LibAmdMsrWrite (MSR_CPUID_EXT_FEATS, &CpuMsrData, StdHeader);
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* MSR special programming requirements for MSR_C001_102D
|
||||
*
|
||||
* AGESA should program MSR_C001_102D[14] with the fused value from F3x1FC[23]
|
||||
*
|
||||
* @param[in] Data The table data value, for example to indicate which CPU and Platform types matched.
|
||||
* @param[in] StdHeader Config handle for library and services.
|
||||
*
|
||||
*/
|
||||
VOID
|
||||
STATIC
|
||||
SetForceSmcCheckFlwStDis (
|
||||
IN UINT32 Data,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
)
|
||||
{
|
||||
PCI_ADDR PciAddress;
|
||||
PRODUCT_INFO_REGISTER ProductInfo;
|
||||
LS_CFG2_MSR LsCfg2;
|
||||
|
||||
PciAddress.AddressValue = PRCT_INFO_PCI_ADDR;
|
||||
LibAmdPciRead (AccessWidth32, PciAddress, (VOID *) &ProductInfo, StdHeader);
|
||||
|
||||
LibAmdMsrRead (MSR_LS_CFG2, (UINT64 *) &LsCfg2, StdHeader);
|
||||
|
||||
LsCfg2.ForceSmcCheckFlwStDis = ProductInfo.ForceSmcCheckFlwStDis;
|
||||
LibAmdMsrWrite (MSR_LS_CFG2, (UINT64 *) &LsCfg2, StdHeader);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
@ -0,0 +1,102 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* AMD Family_15 Trinity Package Type Definitions
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: CPU/Family/0x15/TN
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*
|
||||
*/
|
||||
/*
|
||||
******************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef _F15_TN_PACKAGE_TYPE_H_
|
||||
#define _F15_TN_PACKAGE_TYPE_H_
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------
|
||||
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
|
||||
*---------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------
|
||||
* D E F I N I T I O N S A N D M A C R O S
|
||||
*---------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
// Below equates are defined to cooperate with LibAmdGetPackageType.
|
||||
#define PACKAGE_TYPE_FP2 (1 << 0)
|
||||
#define PACKAGE_TYPE_FS1r2 (1 << 1)
|
||||
#define PACKAGE_TYPE_FM2 (1 << 2)
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------
|
||||
* T Y P E D E F S, S T R U C T U R E S, E N U M S
|
||||
*---------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------
|
||||
* F U N C T I O N P R O T O T Y P E
|
||||
*---------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#endif // _F15_TN_PACKAGE_TYPE_H_
|
||||
@ -0,0 +1,849 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* AMD Family_15 Trinity PCI tables with values as defined in BKDG
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: CPU/Family/0x15/TN
|
||||
* @e \$Revision: 64462 $ @e \$Date: 2012-01-21 10:59:15 -0600 (Sat, 21 Jan 2012) $
|
||||
*
|
||||
*/
|
||||
/*
|
||||
******************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* M O D U L E S U S E D
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
#include "AGESA.h"
|
||||
#include "amdlib.h"
|
||||
#include "cpuRegisters.h"
|
||||
#include "cpuF15TnPowerMgmt.h"
|
||||
#include "Table.h"
|
||||
#include "Filecode.h"
|
||||
CODE_GROUP (G3_DXE)
|
||||
RDATA_GROUP (G3_DXE)
|
||||
|
||||
#define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNPCITABLES_FILECODE
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* D E F I N I T I O N S A N D M A C R O S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* T Y P E D E F S A N D S T R U C T U R E S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
VOID
|
||||
STATIC
|
||||
SetEnCstateBoostBlockCC6Exit (
|
||||
IN UINT32 Data,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
VOID
|
||||
STATIC
|
||||
Erratum687Workaround (
|
||||
IN UINT32 Data,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* E X P O R T E D F U N C T I O N S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
// P C I T a b l e s
|
||||
// ----------------------
|
||||
|
||||
STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F15TnPciRegisters[] =
|
||||
{
|
||||
// F0x68 - Link Transaction Control
|
||||
// bits[22:21] DsNpReqLmt = 01b
|
||||
// bit [19] ApicExtSpur = 1
|
||||
// bit [18] ApicExtId = 1
|
||||
// bit [17] ApicExtBrdCst = 1
|
||||
// bit [15] LimitCldtCfg = 1
|
||||
// bit [10] DisFillP = 0
|
||||
{
|
||||
PciRegister,
|
||||
{
|
||||
AMD_FAMILY_15_TN, // CpuFamily
|
||||
AMD_F15_TN_ALL // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68), // Address
|
||||
0x002E8000, // regData
|
||||
0x006E8400, // regMask
|
||||
}}
|
||||
},
|
||||
// F0x6C - Link Initialization Control
|
||||
// bit[0] RouteTblDis = 0
|
||||
{
|
||||
PciRegister,
|
||||
{
|
||||
AMD_FAMILY_15_TN, // CpuFamily
|
||||
AMD_F15_TN_ALL // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MAKE_SBDFO (0, 0, 24, FUNC_0, 0x6C), // Address
|
||||
0x00000000, // regData
|
||||
0x00000001, // regMask
|
||||
}}
|
||||
},
|
||||
// F0x84 - Link Control
|
||||
// bit [12] IsocEn = 1
|
||||
{
|
||||
PciRegister,
|
||||
{
|
||||
AMD_FAMILY_15_TN, // CpuFamily
|
||||
AMD_F15_TN_ALL // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MAKE_SBDFO (0, 0, 24, FUNC_0, 0x84), // Address
|
||||
0x00001000, // regData
|
||||
0x00001000, // regMask
|
||||
}}
|
||||
},
|
||||
// F0x90 - Upstream Base Channel Buffer Count
|
||||
// bits[27:25] FreeData = 0
|
||||
// bits[24:20] FreeCmd = 0
|
||||
// bits[19:18] RspData = 1
|
||||
// bits[17:16] NpReqData = 1
|
||||
// bits[15:12] ProbeCmd = 0
|
||||
// bits[11:8] RspCmd = 2
|
||||
// bits[7:5] PReq = 5
|
||||
// bits[4:0] NpReqCmd = 8
|
||||
{
|
||||
PciRegister,
|
||||
{
|
||||
AMD_FAMILY_15_TN, // CpuFamily
|
||||
AMD_F15_TN_ALL // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MAKE_SBDFO (0, 0, 24, FUNC_0, 0x90), // Address
|
||||
0x000502A8, // regData
|
||||
0x0FFFFFFF, // regMask
|
||||
}}
|
||||
},
|
||||
// F0x94 - Link Isochronous Channel Buffer Count
|
||||
// bits[28:27] IsocRspData = 0
|
||||
// bits[26:25] IsocNpReqData = 1
|
||||
// bits[24:22] IsocRspCmd = 0
|
||||
// bits[21:19] IsocpReq = 0
|
||||
// bits[18:16] IsocNpReqCmd = 1
|
||||
// bits[15:8] SecBusNum = 0 (F1XE0 [BaseBusNum])
|
||||
{
|
||||
PciRegister,
|
||||
{
|
||||
AMD_FAMILY_15_TN, // CpuFamily
|
||||
AMD_F15_TN_ALL // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MAKE_SBDFO (0, 0, 24, FUNC_0, 0x94), // Address
|
||||
0x02010000, // regData
|
||||
0x1FFFFF00, // regMask
|
||||
}}
|
||||
},
|
||||
// F1xE0 - Configuration Map
|
||||
// bits[31:24] BusNumLimit = F8
|
||||
// bits[23:16] BaseBusNum = 0
|
||||
// bit [1] WE = 1
|
||||
// bit [0] RE = 1
|
||||
{
|
||||
PciRegister,
|
||||
{
|
||||
AMD_FAMILY_15_TN, // CpuFamily
|
||||
AMD_F15_TN_ALL // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MAKE_SBDFO (0, 0, 24, FUNC_1, 0xE0),// Address
|
||||
0xF8000003, // regData
|
||||
0xFFFF0003, // regMask
|
||||
}}
|
||||
},
|
||||
// F3x44 - MCA NB Configuration
|
||||
//
|
||||
// bit[30] SyncFloodOnDramAdrParErr = 1
|
||||
// bit[27] NbMcaToMstCpuEn = 1
|
||||
// bit[21] SyncFloodOnAnyUcErr = 1
|
||||
// bit[20] SyncFloodOnWDT = 1
|
||||
|
||||
{
|
||||
PciRegister,
|
||||
{
|
||||
AMD_FAMILY_15_TN, // CpuFamily
|
||||
AMD_F15_TN_ALL // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x44), // Address
|
||||
0x48300000, // regData
|
||||
0x48300000, // regMask
|
||||
}}
|
||||
},
|
||||
// F3x70 - SRI_to_XBAR Command Buffer Count
|
||||
// bits[30:28] IsocRspCBC = 1
|
||||
// bits[26:24] IsocPreqCBC = 0
|
||||
// bits[22:20] IsocReqCBC = 1
|
||||
// bits[18:16] UpRspCBC = 7
|
||||
// bits[14:12] DnPreqCBC = 1
|
||||
// bits[10:8] UpPreqCBC = 1
|
||||
// bits[7:6] DnRspCBC = 1
|
||||
// bits[5:4] DnReqCBC = 1
|
||||
// bits[2:0] UpReqCBC = 7
|
||||
{
|
||||
PciRegister,
|
||||
{
|
||||
AMD_FAMILY_15_TN, // CpuFamily
|
||||
AMD_F15_TN_ALL // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70), // Address
|
||||
0x10171157, // regData
|
||||
0x777777F7, // regMask
|
||||
}}
|
||||
},
|
||||
// F3x74 - XBAR_to_SRI Command Buffer Count
|
||||
// bits[31:28] DRReqCBC = 0
|
||||
// bits[26:24] IsocPreqCBC = 1
|
||||
// bits[23:20] IsocReqCBC = 1
|
||||
// bits[19:16] ProbeCBC = 8
|
||||
// bits[14:12] DnPreqCBC = 0
|
||||
// bits[10:8] UpPreqCBC = 1
|
||||
// bits[6:4] DnReqCBC = 0
|
||||
// bits[2:0] UpReqCBC = 1
|
||||
{
|
||||
PciRegister,
|
||||
{
|
||||
AMD_FAMILY_15_TN, // CpuFamily
|
||||
AMD_F15_TN_ALL // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address
|
||||
0x01180101, // regData
|
||||
0xF7FF7777, // regMask
|
||||
}}
|
||||
},
|
||||
// F3x7C - Free List Buffer Count
|
||||
// bits[26:23] ExtSrqFreeList = 8
|
||||
// bits[22:20] Sri2XbarFreeRspDBC = 0
|
||||
// bits[19:16] Sri2XbarFreeXreqDBC = 5
|
||||
// bits[15:12] Sri2XbarFreeRspCBC = 0
|
||||
// bits[11:8] Sri2XbarFreeXreqCBC = 0xE
|
||||
// bits[4:0] Xbar2SriFreeListCBC = 18h
|
||||
{
|
||||
PciRegister,
|
||||
{
|
||||
AMD_FAMILY_15_TN, // CpuFamily
|
||||
AMD_F15_TN_ALL // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address
|
||||
0x04050E18, // regData
|
||||
0x07FFFF1F, // regMask
|
||||
}}
|
||||
},
|
||||
// F3x84 - ACPI Power State Control High
|
||||
// ACPI State S3
|
||||
// bit[1] NbLowPwrEnSmafAct4 = 1
|
||||
// bit[7:5] ClkDivisorSmafAct4 = 7
|
||||
{
|
||||
PciRegister,
|
||||
{
|
||||
AMD_FAMILY_15_TN, // CpuFamily
|
||||
AMD_F15_TN_ALL // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x84), // Address
|
||||
0x000000E2, // regData
|
||||
0x000000E2, // regMask
|
||||
}}
|
||||
},
|
||||
// F3xA0 - Power Control Miscellaneous
|
||||
// bit[14] Svi2HighFreqSel = 1, if PERFORMANCE_VRM_HIGH_SPEED_ENABLE == TRUE
|
||||
{
|
||||
ProfileFixup,
|
||||
{
|
||||
AMD_FAMILY_15_TN, // CpuFamily
|
||||
AMD_F15_TN_ALL // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
PERFORMANCE_VRM_HIGH_SPEED_ENABLE, // PerformanceFeatures
|
||||
MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0), // Address
|
||||
0x00004000, // regData
|
||||
0x00004000, // regMask
|
||||
}}
|
||||
},
|
||||
// F3xD4 - Clock Power Timing Control 0
|
||||
// bit [31] NbClkDivApplyAll = 1
|
||||
// bits[30:28] NbClkDiv = 4
|
||||
// bits[27:24] PowerStepUp = 8
|
||||
// bits[23:20] PowerStepDown = 8
|
||||
// bit [14] CacheFlushImmOnAllHalt = 0
|
||||
// bit [12] ClkRampHystCtl = 0
|
||||
// bits[11:8] ClkRampHystSel = 0xF
|
||||
{
|
||||
PciRegister,
|
||||
{
|
||||
AMD_FAMILY_15_TN, // CpuFamily
|
||||
AMD_F15_TN_ALL // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MAKE_SBDFO (0, 0, 24, FUNC_3, 0xD4), // Address
|
||||
0xC8800F00, // regData
|
||||
0xFFF05F00, // regMask
|
||||
}}
|
||||
},
|
||||
// F3xD8 - Clock Power Timing Control 1
|
||||
// bits[6:4] VSRampSlamTime = 100b
|
||||
{
|
||||
PciRegister,
|
||||
{
|
||||
AMD_FAMILY_15_TN, // CpuFamily
|
||||
AMD_F15_TN_ALL // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MAKE_SBDFO (0, 0, 24, FUNC_3, 0xD8), // Address
|
||||
0x00000040, // regData
|
||||
0x00000070, // regMask
|
||||
}}
|
||||
},
|
||||
// F3xDC - Clock Power Timing Control 2
|
||||
// bits[14:12] NbsynPtrAdj = 5
|
||||
{
|
||||
PciRegister,
|
||||
{
|
||||
(AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily
|
||||
AMD_F15_TN_ALL // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC), // Address
|
||||
0x00005000, // regData
|
||||
0x00007000, // regMask
|
||||
}}
|
||||
},
|
||||
// F3x140 - SRI_to_XCS Token Count
|
||||
// bits[23:20] FreeTok = 0xA
|
||||
// bits[17:16] IsocRspTok = 1
|
||||
// bits[15:14] IsocPreqTok = 0
|
||||
// bits[13:12] IsocReqTok = 1
|
||||
// bits[11:10] DnRspTok = 1
|
||||
// bits[9:8] UpRspTok = 1
|
||||
// bits[7:6] DnPreqTok = 1
|
||||
// bits[5:4] UpPreqTok = 1
|
||||
// bits[3:2] DnReqTok = 1
|
||||
// bits[1:0] UpReqTok = 1
|
||||
{
|
||||
PciRegister,
|
||||
{
|
||||
AMD_FAMILY_15_TN, // CpuFamily
|
||||
AMD_F15_TN_ALL // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platform Features
|
||||
{{
|
||||
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
|
||||
0x00A11555, // regData
|
||||
0x00F3FFFF, // regMask
|
||||
}}
|
||||
},
|
||||
// F3x144 - MCT_to_XCS Token Count
|
||||
// bits[7:4] ProbeTok = 7
|
||||
// bits[3:0] RspTok = 7
|
||||
{
|
||||
PciRegister,
|
||||
{
|
||||
AMD_FAMILY_15_TN, // CpuFamily
|
||||
AMD_F15_TN_ALL // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platform Features
|
||||
{{
|
||||
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
|
||||
0x00000077, // regData
|
||||
0x000000FF, // regMask
|
||||
}}
|
||||
},
|
||||
// F3x148 - Link_to_XCS Token Count
|
||||
// bits[31:30] FreeTok[3:2] = FreeTok[1:0] = 0
|
||||
// bit [28] IsocRspTok1 = 0
|
||||
// bit [26] IsocPreqTok1 = 0
|
||||
// bit [24] IsocReqTok1 = 0
|
||||
// bits[23:22] ProbeTok1 = 0
|
||||
// bits[21:20] RspTok1 = 0
|
||||
// bits[19:18] PReqTok1 = 0
|
||||
// bits[17:16] ReqTok1 = 0
|
||||
// bits[15:14] FreeTok[1:0] = 0
|
||||
// bits[13:12] IsocRspTok0 = 0
|
||||
// bits[11:10] IsocPreqTok0 = 1
|
||||
// bits[9:8] IsocReqTok0 = 1
|
||||
// bits[7:6] ProbeTok0 = 0
|
||||
// bits[5:4] RspTok0 = 2
|
||||
// bits[3:2] PReqTok0 = 2
|
||||
// bits[1:0] ReqTok0 = 2
|
||||
{
|
||||
PciRegister,
|
||||
{
|
||||
AMD_FAMILY_15_TN, // CpuFamily
|
||||
AMD_F15_TN_ALL // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platform Features
|
||||
{{
|
||||
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
|
||||
0x0000052A, // regData
|
||||
0xD5FFFFFF // regMask
|
||||
}}
|
||||
},
|
||||
// F3x17C - Extended Freelist Buffer Count
|
||||
// bits[3:0] SPQPrbFreeCBC = 4
|
||||
{
|
||||
PciRegister,
|
||||
{
|
||||
AMD_FAMILY_15_TN, // CpuFamily
|
||||
AMD_F15_TN_ALL // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platform Features
|
||||
{{
|
||||
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x17C), // Address
|
||||
0x00000004, // regData
|
||||
0x0000000F // regMask
|
||||
}}
|
||||
},
|
||||
// F3x180 - NB Extended Configuration
|
||||
// bit[24] McaLogErrAddrWdtErr = 1
|
||||
// bit[22] SyncFloodOnTblWalkErr = 1
|
||||
// bit[21] SyncFloodOnCpuLeakErr = 1
|
||||
// bit[20] SyncFloodOnL3LeakErr = 1
|
||||
// bit[9] SyncFloodOnUCNbAry = 1
|
||||
// bit[8] SyncFloodOnHtProt = 1
|
||||
// bit[7] SyncFloodOnTgtAbortErr = 1
|
||||
// bit[6] SyncFloodOnDatErr = 1
|
||||
// bit[5] DisPciCfgCpuMstAbortRsp = 1
|
||||
{
|
||||
PciRegister,
|
||||
{
|
||||
AMD_FAMILY_15_TN, // CpuFamily
|
||||
AMD_F15_TN_ALL // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x180), // Address
|
||||
0x017003E0, // regData
|
||||
0x017003E0, // regMask
|
||||
}}
|
||||
},
|
||||
// F3x1A0 - Core to NB Buffer Count
|
||||
// bit[17:16] CpuToNbFreeBufCnt = 3
|
||||
{
|
||||
PciRegister,
|
||||
{
|
||||
AMD_FAMILY_15_TN, // CpuFamily
|
||||
AMD_F15_TN_ALL // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1A0), // Address
|
||||
0x00030000, // regData
|
||||
0x00030000, // regMask
|
||||
}}
|
||||
},
|
||||
// F4x110 - Sample and Residency Timer
|
||||
// bits[11:0] CSampleTimer = 2
|
||||
{
|
||||
PciRegister,
|
||||
{
|
||||
AMD_FAMILY_15_TN, // CpuFamily
|
||||
AMD_F15_TN_ALL // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MAKE_SBDFO (0, 0, 24, FUNC_4, 0x110), // Address
|
||||
0x00000002, // regData
|
||||
0x00000FFF, // regMask
|
||||
}}
|
||||
},
|
||||
// F4x124 - C-state Interrupt Control
|
||||
// bits[26:23] IntMonPC6Limit = 0
|
||||
// bit [22] IntMonPC6En = 1
|
||||
{
|
||||
PciRegister,
|
||||
{
|
||||
AMD_FAMILY_15_TN, // CpuFamily
|
||||
AMD_F15_TN_ALL // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MAKE_SBDFO (0, 0, 24, FUNC_4, 0x124), // Address
|
||||
0x00400000, // regData
|
||||
0x07C00000, // regMask
|
||||
}}
|
||||
},
|
||||
// F4x16C - Erratum #667
|
||||
// bit [1] = 1
|
||||
// bit [4] = 1
|
||||
{
|
||||
PciRegister,
|
||||
{
|
||||
AMD_FAMILY_15_TN, // CpuFamily
|
||||
AMD_F15_TN_ALL // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MAKE_SBDFO (0, 0, 24, FUNC_4, 0x16C), // Address
|
||||
0x00000012, // regData
|
||||
0x00000012, // regMask
|
||||
}}
|
||||
},
|
||||
// F5xAC - Erratum #667
|
||||
// bit [3] = 1
|
||||
{
|
||||
PciRegister,
|
||||
{
|
||||
AMD_FAMILY_15_TN, // CpuFamily
|
||||
AMD_F15_TN_ALL // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MAKE_SBDFO (0, 0, 24, FUNC_5, 0xAC), // Address
|
||||
0x00000008, // regData
|
||||
0x00000008, // regMask
|
||||
}}
|
||||
},
|
||||
// F5x88 - Northbridge Configuration 4
|
||||
// bit[24] DisHbNpReqBusLock = 1
|
||||
// bit[2] IntStpClkHaltExitEn = 1
|
||||
{
|
||||
PciRegister,
|
||||
{
|
||||
AMD_FAMILY_15_TN, // CpuFamily
|
||||
AMD_F15_TN_ALL // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MAKE_SBDFO (0, 0, 24, FUNC_5, 0x88), // Address
|
||||
0x01000004, // regData
|
||||
0x01000004, // regMask
|
||||
}}
|
||||
},
|
||||
// F5xE0 - Processor TDP Running Average
|
||||
// bits[3:0] RunAvgRange = 0x2
|
||||
{
|
||||
PciRegister,
|
||||
{
|
||||
AMD_FAMILY_15_TN, // CpuFamily
|
||||
AMD_F15_TN_ALL // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MAKE_SBDFO (0, 0, 24, FUNC_5, 0xE0), // Address
|
||||
0x00000002, // regData
|
||||
0x0000000F, // regMask
|
||||
}}
|
||||
},
|
||||
// F5x128 - Clock Power/Timing Control 3
|
||||
// bits[13:12] PwrGateTmr = 1
|
||||
// bits[11:10] PllVddOutUpTime = 3
|
||||
// bit [9] FastSlamTimeDown = 1
|
||||
{
|
||||
PciRegister,
|
||||
{
|
||||
AMD_FAMILY_15_TN, // CpuFamily
|
||||
AMD_F15_TN_ALL // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MAKE_SBDFO (0, 0, 24, FUNC_5, 0x128), // Address
|
||||
0x00001E00, // regData
|
||||
0x00003E00, // regMask
|
||||
}}
|
||||
},
|
||||
// F5x12C - Clock Power/Timing Control 4
|
||||
// bit [5] CorePsi1En = 1
|
||||
{
|
||||
PciRegister,
|
||||
{
|
||||
AMD_FAMILY_15_TN, // CpuFamily
|
||||
AMD_F15_TN_ALL // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MAKE_SBDFO (0, 0, 24, FUNC_5, 0x12C), // Address
|
||||
0x00000020, // regData
|
||||
0x00000020, // regMask
|
||||
}}
|
||||
},
|
||||
// F5x178 - Northbridge Fusion Configuration
|
||||
// bit [18] CstateFusionHsDis = 1
|
||||
// bit [17] Dis2ndGnbAllowPsWait = 1
|
||||
// bit [11] AllowSelfRefrS3Dis = 1
|
||||
// bit [10] InbWakeS3Dis = 1
|
||||
// bit [2] CstateFusionDis = 1
|
||||
{
|
||||
PciRegister,
|
||||
{
|
||||
AMD_FAMILY_15_TN, // CpuFamily
|
||||
AMD_F15_TN_ALL // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MAKE_SBDFO (0, 0, 24, FUNC_5, 0x178), // Address
|
||||
0x00060C04, // regData
|
||||
0x00060C04, // regMask
|
||||
}}
|
||||
},
|
||||
// F0x90 - Upstream Base Channel Buffer Count
|
||||
// bit [31] LockBc = 1
|
||||
//
|
||||
// NOTE: The entry is intended to be programmed after other bits of D18F0x[90, 94] is programmed and before D18F0x6C[30] is programmed.
|
||||
{
|
||||
PciRegister,
|
||||
{
|
||||
AMD_FAMILY_15_TN, // CpuFamily
|
||||
AMD_F15_TN_ALL // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MAKE_SBDFO (0, 0, 24, FUNC_0, 0x90), // Address
|
||||
0x80000000, // regData
|
||||
0x80000000, // regMask
|
||||
}}
|
||||
},
|
||||
// F0x6C - Link Initialization Control
|
||||
// bit [30] RlsLnkFullTokCntImm = 1
|
||||
// bit [28] RlsIntFullTokCntImm = 1
|
||||
//
|
||||
// NOTE: The entry is intended to be after D18F0x[90, 94] and D18F0x[70, 74, 78, 7C, 140, 144, 148, 17C, 1A0] are programmed.
|
||||
{
|
||||
PciRegister,
|
||||
{
|
||||
AMD_FAMILY_15_TN, // CpuFamily
|
||||
AMD_F15_TN_ALL // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MAKE_SBDFO (0, 0, 24, FUNC_0, 0x6C), // Address
|
||||
0x50000000, // regData
|
||||
0x50000000, // regMask
|
||||
}}
|
||||
},
|
||||
// F0x6C - Link Initialization Control
|
||||
// bit [27] ApplyIsocModeEnNow = 1
|
||||
//
|
||||
// NOTE: The entry is intended to be after D18F0x6C[30, 28] are programmed.
|
||||
{
|
||||
PciRegister,
|
||||
{
|
||||
AMD_FAMILY_15_TN, // CpuFamily
|
||||
AMD_F15_TN_ALL // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MAKE_SBDFO (0, 0, 24, FUNC_0, 0x6C), // Address
|
||||
0x08000000, // regData
|
||||
0x08000000, // regMask
|
||||
}}
|
||||
},
|
||||
};
|
||||
|
||||
|
||||
// PCI with Special Programming Requirements Table
|
||||
|
||||
STATIC CONST FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_INITIALIZER ROMDATA F15TnPciWorkarounds[] =
|
||||
{
|
||||
// D18F5x88
|
||||
{
|
||||
FamSpecificWorkaround,
|
||||
{
|
||||
(AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily
|
||||
AMD_F15_TN_GT_A0 // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
SetEnCstateBoostBlockCC6Exit, // function call
|
||||
0x00000000, // data
|
||||
}}
|
||||
},
|
||||
// D18F5x88 and D18F2x408
|
||||
{
|
||||
FamSpecificWorkaround,
|
||||
{
|
||||
(AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily
|
||||
AMD_F15_TN_ALL // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
Erratum687Workaround, // function call
|
||||
0x00000000, // data
|
||||
}}
|
||||
},
|
||||
};
|
||||
|
||||
|
||||
CONST REGISTER_TABLE ROMDATA F15TnPciRegisterTable = {
|
||||
PrimaryCores,
|
||||
(sizeof (F15TnPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
|
||||
F15TnPciRegisters,
|
||||
};
|
||||
|
||||
|
||||
CONST REGISTER_TABLE ROMDATA F15TnPciWorkaroundTable = {
|
||||
PrimaryCores,
|
||||
(sizeof (F15TnPciWorkarounds) / sizeof (TABLE_ENTRY_FIELDS)),
|
||||
(TABLE_ENTRY_FIELDS *) F15TnPciWorkarounds,
|
||||
};
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Workaround for Non-A0 TN processors.
|
||||
*
|
||||
* AGESA should program F5x88[18] with the fused value from F3x1FC[20] for non-RevA0 parts.
|
||||
*
|
||||
* @param[in] Data The table data value, for example to indicate which CPU and Platform types matched.
|
||||
* @param[in] StdHeader Config handle for library and services.
|
||||
*
|
||||
*/
|
||||
VOID
|
||||
STATIC
|
||||
SetEnCstateBoostBlockCC6Exit (
|
||||
IN UINT32 Data,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
)
|
||||
{
|
||||
PCI_ADDR PciAddress;
|
||||
PRODUCT_INFO_REGISTER ProductInfo;
|
||||
NB_CFG_4_REGISTER NbCfg4;
|
||||
|
||||
PciAddress.AddressValue = PRCT_INFO_PCI_ADDR;
|
||||
LibAmdPciRead (AccessWidth32, PciAddress, (VOID *)&ProductInfo, StdHeader);
|
||||
|
||||
PciAddress.AddressValue = NB_CFG_REG4_PCI_ADDR;
|
||||
LibAmdPciRead (AccessWidth32, PciAddress, (VOID *)&NbCfg4, StdHeader);
|
||||
|
||||
NbCfg4.EnCstateBoostBlockCC6Exit = ProductInfo.EnCstateBoostBlockCC6Exit;
|
||||
LibAmdPciWrite (AccessWidth32, PciAddress, (VOID *)&NbCfg4, StdHeader);
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Workaround for Erratum #687 for TN processors.
|
||||
*
|
||||
* AGESA should program F5x88[14] with the fused value from F3x1FC[29] and
|
||||
* program F2x408[CpuElevPrioDis] with inversed fuse value from F3x1FC[29] for all TN parts.
|
||||
*
|
||||
* @param[in] Data The table data value, for example to indicate which CPU and Platform types matched.
|
||||
* @param[in] StdHeader Config handle for library and services.
|
||||
*
|
||||
*/
|
||||
VOID
|
||||
STATIC
|
||||
Erratum687Workaround (
|
||||
IN UINT32 Data,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
)
|
||||
{
|
||||
PCI_ADDR PciAddress;
|
||||
PRODUCT_INFO_REGISTER ProductInfo;
|
||||
NB_CFG_4_REGISTER NbCfg4;
|
||||
GMC_TO_DCT_CTL_2_REGISTER GmcToDctCtrl2;
|
||||
UINT32 DctSelCnt;
|
||||
DCT_CFG_SEL_REGISTER DctCfgSel;
|
||||
|
||||
PciAddress.AddressValue = PRCT_INFO_PCI_ADDR;
|
||||
LibAmdPciRead (AccessWidth32, PciAddress, (VOID *)&ProductInfo, StdHeader);
|
||||
|
||||
PciAddress.AddressValue = NB_CFG_REG4_PCI_ADDR;
|
||||
LibAmdPciRead (AccessWidth32, PciAddress, (VOID *)&NbCfg4, StdHeader);
|
||||
NbCfg4.Bit14 = ProductInfo.EnDcqChgPriToHigh;
|
||||
LibAmdPciWrite (AccessWidth32, PciAddress, (VOID *)&NbCfg4, StdHeader);
|
||||
|
||||
for (DctSelCnt = 0; DctSelCnt <= 1; DctSelCnt++) {
|
||||
PciAddress.AddressValue = GMC_TO_DCT_CTL_2_PCI_ADDR;
|
||||
LibAmdPciRead (AccessWidth32, PciAddress, (VOID *)&GmcToDctCtrl2, StdHeader);
|
||||
GmcToDctCtrl2.CpuElevPrioDis = ~ProductInfo.EnDcqChgPriToHigh;
|
||||
LibAmdPciWrite (AccessWidth32, PciAddress, (VOID *)&GmcToDctCtrl2, StdHeader);
|
||||
|
||||
PciAddress.AddressValue = DCT_CFG_SEL_REG_PCI_ADDR;
|
||||
LibAmdPciRead (AccessWidth32, PciAddress, (VOID *)&DctCfgSel, StdHeader);
|
||||
DctCfgSel.DctCfgSel = ~DctCfgSel.DctCfgSel;
|
||||
LibAmdPciWrite (AccessWidth32, PciAddress, (VOID *)&DctCfgSel, StdHeader);
|
||||
}
|
||||
}
|
||||
|
||||
@ -0,0 +1,195 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* AMD Family_15 Models 0x10 - 0x1F Power Management related initialization table
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: CPU/Family/0x15/TN
|
||||
* @e \$Revision: 63692 $ @e \$Date: 2012-01-03 22:13:28 -0600 (Tue, 03 Jan 2012) $
|
||||
*
|
||||
*/
|
||||
/*
|
||||
******************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* M O D U L E S U S E D
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
#include "AGESA.h"
|
||||
#include "Ids.h"
|
||||
#include "cpuRegisters.h"
|
||||
#include "cpuApicUtilities.h"
|
||||
#include "cpuFamilyTranslation.h"
|
||||
#include "cpuPowerMgmtSystemTables.h"
|
||||
#include "cpuF15TnCoreAfterReset.h"
|
||||
#include "cpuF15TnNbAfterReset.h"
|
||||
#include "F15TnPowerPlane.h"
|
||||
#include "cpuF15TnPowerCheck.h"
|
||||
#include "F15TnUtilities.h"
|
||||
#include "IdsF15TnAllService.h"
|
||||
#include "Filecode.h"
|
||||
CODE_GROUP (G2_PEI)
|
||||
RDATA_GROUP (G2_PEI)
|
||||
|
||||
#define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNPOWERMGMTSYSTEMTABLES_FILECODE
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* D E F I N I T I O N S A N D M A C R O S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* T Y P E D E F S A N D S T R U C T U R E S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
VOID
|
||||
GetF15TnSysPmTable (
|
||||
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
|
||||
OUT CONST VOID **SysPmTblPtr,
|
||||
OUT UINT8 *NumberOfElements,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* E X P O R T E D F U N C T I O N S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/* Family 15h Only Table */
|
||||
/* ---------------------- */
|
||||
CONST SYS_PM_TBL_STEP ROMDATA CpuF15TnSysPmTableArray[] =
|
||||
{
|
||||
IDS_INITIAL_F15_TN_PM_STEP
|
||||
|
||||
// Step 1 - Configure F3x[84:80]. Handled by PCI register table.
|
||||
// Step 2 - Power Plane Initialization
|
||||
// Execute both cold & warm
|
||||
{
|
||||
0, // ExeFlags
|
||||
F15TnPmPwrPlaneInit // Function Pointer
|
||||
},
|
||||
|
||||
// Step 3 - Adjust NB VID
|
||||
// Execute only after cold reset
|
||||
{
|
||||
PM_EXEFLAGS_COLD_ONLY, // ExeFlags
|
||||
F15TnNbPstateVidAdjustAfterReset // Function Pointer
|
||||
},
|
||||
|
||||
// Step 4 - Disable NB Pstate, if required
|
||||
// Execute both cold & warm
|
||||
{
|
||||
0, // ExeFlags
|
||||
F15TnNbPstateDis // Function Pointer
|
||||
},
|
||||
|
||||
// Step 5 - Core Minimum P-state Transition Sequence After Warm Reset
|
||||
// Execute only after warm reset
|
||||
{
|
||||
PM_EXEFLAGS_WARM_ONLY, // ExeFlags
|
||||
F15TnPmCoreAfterReset // Function Pointer
|
||||
},
|
||||
|
||||
// Step 6 - NB P-state COF and VID Synchronization After Warm Reset
|
||||
// Execute only after warm reset
|
||||
{
|
||||
PM_EXEFLAGS_WARM_ONLY, // ExeFlags
|
||||
F15TnPmNbAfterReset // Function Pointer
|
||||
},
|
||||
|
||||
// Step 7 - Power Check
|
||||
// Execute both cold & warm
|
||||
{
|
||||
0, // ExeFlags
|
||||
F15TnPmPwrCheck // Function Pointer
|
||||
},
|
||||
|
||||
IDS_F15_TN_PM_CUSTOM_STEP
|
||||
|
||||
};
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Returns the appropriate table of steps to perform to initialize the power management
|
||||
* subsystem.
|
||||
*
|
||||
* @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
|
||||
*
|
||||
* @param[in] FamilySpecificServices The current Family Specific Services.
|
||||
* @param[out] SysPmTblPtr Points to the first entry in the table.
|
||||
* @param[out] NumberOfElements Number of valid entries in the table.
|
||||
* @param[in] StdHeader Header for library and services.
|
||||
*
|
||||
*/
|
||||
VOID
|
||||
GetF15TnSysPmTable (
|
||||
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
|
||||
OUT CONST VOID **SysPmTblPtr,
|
||||
OUT UINT8 *NumberOfElements,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
)
|
||||
{
|
||||
*NumberOfElements = (sizeof (CpuF15TnSysPmTableArray) / sizeof (SYS_PM_TBL_STEP));
|
||||
*SysPmTblPtr = CpuF15TnSysPmTableArray;
|
||||
}
|
||||
@ -0,0 +1,207 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* AMD Family_15 Models 0x10 - 0x1F Power Plane Initialization
|
||||
*
|
||||
* Performs the "BIOS Requirements for Power Plane Initialization" as described
|
||||
* in the BKDG.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: CPU/Family/0x15/TN
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*
|
||||
*/
|
||||
/*
|
||||
******************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* M O D U L E S U S E D
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
#include "AGESA.h"
|
||||
#include "amdlib.h"
|
||||
#include "Ids.h"
|
||||
#include "cpuRegisters.h"
|
||||
#include "cpuF15PowerMgmt.h"
|
||||
#include "cpuF15TnPowerMgmt.h"
|
||||
#include "cpuApicUtilities.h"
|
||||
#include "cpuServices.h"
|
||||
#include "GeneralServices.h"
|
||||
#include "cpuFamilyTranslation.h"
|
||||
#include "Table.h"
|
||||
#include "F15TnPowerPlane.h"
|
||||
#include "Filecode.h"
|
||||
CODE_GROUP (G2_PEI)
|
||||
RDATA_GROUP (G2_PEI)
|
||||
|
||||
#define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNPOWERPLANE_FILECODE
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* D E F I N I T I O N S A N D M A C R O S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
// Register encodings for D18F3xD8[VSRampSlamTime]
|
||||
STATIC CONST UINT32 ROMDATA F15TnVSRampSlamWaitTimes[8] =
|
||||
{
|
||||
500, // 000b: 5.00us
|
||||
375, // 001b: 3.75us
|
||||
300, // 010b: 3.00us
|
||||
240, // 011b: 2.40us
|
||||
200, // 100b: 2.00us
|
||||
150, // 101b: 1.50us
|
||||
120, // 110b: 1.20us
|
||||
100 // 111b: 1.00us
|
||||
};
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* T Y P E D E F S A N D S T R U C T U R E S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* E X P O R T E D F U N C T I O N S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Family 15h core 0 entry point for performing power plane initialization.
|
||||
*
|
||||
* The steps are as follows:
|
||||
* 1. Configure D18F3xD8[VSRampSlamTime] based on platform
|
||||
* requirements.
|
||||
* 2. Configure F3xD4[PowerStepUp & PowerStepDown]
|
||||
* 3. Optionally configure F3xA0[PsiVidEn & PsiVid]
|
||||
*
|
||||
* @param[in] FamilySpecificServices The current Family Specific Services.
|
||||
* @param[in] CpuEarlyParams Service parameters
|
||||
* @param[in] StdHeader Config handle for library and services.
|
||||
*
|
||||
*/
|
||||
VOID
|
||||
F15TnPmPwrPlaneInit (
|
||||
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
|
||||
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
)
|
||||
{
|
||||
PCI_ADDR PciAddress;
|
||||
UINT32 SystemSlewRate;
|
||||
UINT32 WaitTime;
|
||||
UINT32 VSRampSlamTime;
|
||||
UINT32 LocalPciRegister;
|
||||
CLK_PWR_TIMING_CTRL1_REGISTER ClkPwrTimingCtrl1;
|
||||
BOOLEAN SkipPowerPlan;
|
||||
|
||||
|
||||
SkipPowerPlan = FALSE;
|
||||
IDS_OPTION_CALLOUT (IDS_CALLOUT_POWER_PLAN_INIT, &SkipPowerPlan, StdHeader);
|
||||
if (!SkipPowerPlan) {
|
||||
// Step 1 - Configure D18F3xD8[VSRampSlamTime] based on platform requirements.
|
||||
// Voltage Ramp Time = maximum time to change voltage by 15mV rounded to the next higher encoding.
|
||||
SystemSlewRate = (CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].SlewRate <=
|
||||
CpuEarlyParams->PlatformConfig.VrmProperties[NbVrm].SlewRate) ?
|
||||
CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].SlewRate :
|
||||
CpuEarlyParams->PlatformConfig.VrmProperties[NbVrm].SlewRate;
|
||||
|
||||
ASSERT (SystemSlewRate != 0);
|
||||
|
||||
// First, calculate the time it takes to change 15mV using the VRM slew rate.
|
||||
WaitTime = (15000 * 100) / SystemSlewRate;
|
||||
if (((15000 * 100) % SystemSlewRate) != 0) {
|
||||
WaitTime++;
|
||||
}
|
||||
|
||||
// Next, round it to the appropriate encoded value. We will start from encoding 111b which corresponds
|
||||
// to the fastest slew rate, and work our way down to 000b, which represents the slowest an acceptable
|
||||
// VRM can be.
|
||||
for (VSRampSlamTime = ((sizeof (F15TnVSRampSlamWaitTimes) / sizeof (F15TnVSRampSlamWaitTimes[0])) - 1); VSRampSlamTime > 0; VSRampSlamTime--) {
|
||||
if (WaitTime <= F15TnVSRampSlamWaitTimes[VSRampSlamTime]) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (WaitTime > F15TnVSRampSlamWaitTimes[0]) {
|
||||
// The VRMs on this motherboard are too slow for this CPU.
|
||||
IDS_ERROR_TRAP;
|
||||
}
|
||||
|
||||
// Lastly, program D18F3xD8[VSRampSlamTime] with the appropriate encoded value.
|
||||
PciAddress.AddressValue = CPTC1_PCI_ADDR;
|
||||
LibAmdPciRead (AccessWidth32, PciAddress, &ClkPwrTimingCtrl1, StdHeader);
|
||||
ClkPwrTimingCtrl1.VSRampSlamTime = VSRampSlamTime;
|
||||
LibAmdPciWrite (AccessWidth32, PciAddress, &ClkPwrTimingCtrl1, StdHeader);
|
||||
|
||||
// Configure PowerStepUp/PowerStepDown
|
||||
PciAddress.AddressValue = CPTC0_PCI_ADDR;
|
||||
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
|
||||
((CLK_PWR_TIMING_CTRL_REGISTER *) &LocalPciRegister)->PowerStepUp = 8;
|
||||
((CLK_PWR_TIMING_CTRL_REGISTER *) &LocalPciRegister)->PowerStepDown = 8;
|
||||
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
@ -0,0 +1,103 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* AMD Family_15 Models 0x10 - 0x1F Power Plane related functions and structures
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: CPU/Family/0x15/TN
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*
|
||||
*/
|
||||
/*
|
||||
******************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef _F15_TN_POWER_PLANE_H_
|
||||
#define _F15_TN_POWER_PLANE_H_
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------
|
||||
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
|
||||
*---------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------
|
||||
* D E F I N I T I O N S A N D M A C R O S
|
||||
*---------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------
|
||||
* T Y P E D E F S, S T R U C T U R E S, E N U M S
|
||||
*---------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------
|
||||
* F U N C T I O N P R O T O T Y P E
|
||||
*---------------------------------------------------------------------------------------
|
||||
*/
|
||||
VOID
|
||||
F15TnPmPwrPlaneInit (
|
||||
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
|
||||
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
#endif // _F15_TN_POWER_PLANE_H_
|
||||
@ -0,0 +1,415 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* AMD Family_15 Trinity Shared MSR table with values as defined in BKDG
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: CPU/Family/0x15/TN
|
||||
* @e \$Revision: 64491 $ @e \$Date: 2012-01-23 12:37:30 -0600 (Mon, 23 Jan 2012) $
|
||||
*
|
||||
*/
|
||||
/*
|
||||
******************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* M O D U L E S U S E D
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
#include "AGESA.h"
|
||||
#include "amdlib.h"
|
||||
#include "cpuRegisters.h"
|
||||
#include "Table.h"
|
||||
#include "cpuF15PowerMgmt.h"
|
||||
#include "cpuF15TnPowerMgmt.h"
|
||||
#include "Filecode.h"
|
||||
CODE_GROUP (G3_DXE)
|
||||
RDATA_GROUP (G3_DXE)
|
||||
|
||||
#define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNSHAREDMSRTABLE_FILECODE
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* D E F I N I T I O N S A N D M A C R O S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* T Y P E D E F S A N D S T R U C T U R E S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
VOID
|
||||
F15TnFpCfgInit (
|
||||
IN UINT32 Data,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
VOID
|
||||
STATIC
|
||||
Update800MHzHtcPstateTo900MHz (
|
||||
IN UINT32 Data,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* E X P O R T E D F U N C T I O N S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F15TnSharedMsrRegisters[] =
|
||||
{
|
||||
// M S R T a b l e s
|
||||
// ----------------------
|
||||
|
||||
// MSR_TOM2 (0xC001001D)
|
||||
// bits[63:0] TOP_MEM2 = 0
|
||||
{
|
||||
MsrRegister,
|
||||
{
|
||||
AMD_FAMILY_15_TN, // CpuFamily
|
||||
AMD_F15_TN_ALL // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MSR_TOM2, // MSR Address - Shared
|
||||
0x0000000000000000, // OR Mask
|
||||
0xFFFFFFFFFFFFFFFF, // NAND Mask
|
||||
}}
|
||||
},
|
||||
|
||||
// MSR_SYS_CFG (0xC0010010)
|
||||
// bit[21] MtrrTom2En = 1
|
||||
{
|
||||
MsrRegister,
|
||||
{
|
||||
AMD_FAMILY_15_TN, // CpuFamily
|
||||
AMD_F15_TN_ALL // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MSR_SYS_CFG, // MSR Address - Shared
|
||||
(1 << 21), // OR Mask
|
||||
(1 << 21), // NAND Mask
|
||||
}}
|
||||
},
|
||||
|
||||
// MSR_IC_CFG (0xC0011021)
|
||||
// bit[39] DisLoopPredictor = 1
|
||||
{
|
||||
MsrRegister,
|
||||
{
|
||||
AMD_FAMILY_15_TN, // CpuFamily
|
||||
AMD_F15_TN_ALL // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MSR_IC_CFG, // MSR Address - Shared
|
||||
(1ull << 39), // OR Mask
|
||||
(1ull << 39), // NAND Mask
|
||||
}}
|
||||
},
|
||||
|
||||
// MSR_CU_CFG (0xC0011023)
|
||||
{
|
||||
MsrRegister,
|
||||
{
|
||||
AMD_FAMILY_15_TN, // CpuFamily
|
||||
AMD_F15_TN_ALL // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MSR_CU_CFG, // MSR Address - Shared
|
||||
0, // OR Mask
|
||||
0x00000400, // NAND Mask
|
||||
}}
|
||||
},
|
||||
|
||||
// MSR_CU_CFG2 (0xC001102A)
|
||||
// bit[50] RdMmExtCfgQwEn = 1
|
||||
// bit[10] VicResyncChkEn = 1
|
||||
|
||||
{
|
||||
MsrRegister,
|
||||
{
|
||||
AMD_FAMILY_15_TN, // CpuFamily
|
||||
AMD_F15_TN_ALL // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MSR_CU_CFG2, // MSR Address - Shared
|
||||
0x0004000000000400, // OR Mask
|
||||
0x0004000000000400, // NAND Mask
|
||||
}}
|
||||
},
|
||||
// MSR_CU_CFG3 (0xC001102B)
|
||||
// bit[42] PwcDisableWalkerSharing = 0
|
||||
// bit[22] PfcDoubleStride = 1
|
||||
{
|
||||
MsrRegister,
|
||||
{
|
||||
AMD_FAMILY_15_TN, // CpuFamily
|
||||
AMD_F15_TN_ALL // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MSR_CU_CFG3, // MSR Address
|
||||
0x0000000000400000, // OR Mask
|
||||
0x0000040000400000, // NAND Mask
|
||||
}}
|
||||
},
|
||||
};
|
||||
|
||||
|
||||
// Compute Unit Count Dependent MSR Table
|
||||
|
||||
STATIC CONST MSR_CU_TYPE_ENTRY_INITIALIZER ROMDATA F15TnSharedMsrCuRegisters[] =
|
||||
{
|
||||
// M S R T a b l e s
|
||||
// ----------------------
|
||||
|
||||
// MSR_CU_CFG2 (0xC001102A)
|
||||
// bits[37:36] - ThrottleNbInterface[3:2] = 0
|
||||
// bits[7:6] - ThrottleNbInterface[1:0] = 0
|
||||
{
|
||||
CompUnitCountsMsr,
|
||||
{
|
||||
AMD_FAMILY_15_TN, // CpuFamily
|
||||
AMD_F15_TN_ALL // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
{(COMPUTE_UNIT_RANGE_0 (1, 1) | COUNT_RANGE_NONE)}, // 1 compute unit
|
||||
{
|
||||
MSR_CU_CFG2, // MSR Address - Shared
|
||||
0x0000000000000000, // OR Mask
|
||||
0x00000030000000C0, // NAND Mask
|
||||
}
|
||||
}}
|
||||
},
|
||||
|
||||
// MSR_CU_CFG2 (0xC001102A)
|
||||
// bits[37:36] - ThrottleNbInterface[3:2] = 0
|
||||
// bits[7:6] - ThrottleNbInterface[1:0] = 1
|
||||
{
|
||||
CompUnitCountsMsr,
|
||||
{
|
||||
AMD_FAMILY_15_TN, // CpuFamily
|
||||
AMD_F15_TN_ALL // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
{(COMPUTE_UNIT_RANGE_0 (2, 2) | COUNT_RANGE_NONE)}, // 2 compute units
|
||||
{
|
||||
MSR_CU_CFG2, // MSR Address - Shared
|
||||
0x0000000000000040, // OR Mask
|
||||
0x00000030000000C0, // NAND Mask
|
||||
}
|
||||
}}
|
||||
}
|
||||
|
||||
};
|
||||
|
||||
|
||||
// Shared MSRs with Special Programming Requirements Table
|
||||
|
||||
STATIC CONST FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_INITIALIZER ROMDATA F15TnSharedMsrWorkarounds[] =
|
||||
{
|
||||
// MSR_FP_CFG (0xC0011028)
|
||||
// bit[16] - DiDtMode = F3x1FC[0]
|
||||
// bits[22:18] - DiDtCfg0 = F3x1FC[5:1]
|
||||
// bits[34:27] - DiDtCfg1 = F3x1FC[13:6]
|
||||
// bits[26:25] - DiDtCfg2 = F3x1FC[15:14]
|
||||
// bits[44:42] - DiDtCfg4 = F3x1FC[19:17]
|
||||
{
|
||||
FamSpecificWorkaround,
|
||||
{
|
||||
AMD_FAMILY_15_TN,
|
||||
AMD_F15_TN_ALL
|
||||
},
|
||||
{AMD_PF_ALL},
|
||||
{{
|
||||
F15TnFpCfgInit,
|
||||
0x00000000
|
||||
}}
|
||||
},
|
||||
};
|
||||
|
||||
|
||||
CONST REGISTER_TABLE ROMDATA F15TnSharedMsrRegisterTable = {
|
||||
CorePairPrimary,
|
||||
(sizeof (F15TnSharedMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
|
||||
(TABLE_ENTRY_FIELDS *) &F15TnSharedMsrRegisters,
|
||||
};
|
||||
|
||||
|
||||
CONST REGISTER_TABLE ROMDATA F15TnSharedMsrCuRegisterTable = {
|
||||
CorePairPrimary,
|
||||
(sizeof (F15TnSharedMsrCuRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
|
||||
(TABLE_ENTRY_FIELDS *) &F15TnSharedMsrCuRegisters,
|
||||
};
|
||||
|
||||
CONST REGISTER_TABLE ROMDATA F15TnSharedMsrWorkaroundTable = {
|
||||
CorePairPrimary,
|
||||
(sizeof (F15TnSharedMsrWorkarounds) / sizeof (TABLE_ENTRY_FIELDS)),
|
||||
(TABLE_ENTRY_FIELDS *) &F15TnSharedMsrWorkarounds,
|
||||
};
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Update the FP_CFG MSR in current processor for Family15h TN.
|
||||
*
|
||||
* This function satisfies the programming requirements for the FP_CFG MSR.
|
||||
*
|
||||
* @param[in] Data The table data value, for example to indicate which CPU and Platform types matched.
|
||||
* @param[in] StdHeader Config handle for library and services.
|
||||
*
|
||||
*/
|
||||
VOID
|
||||
F15TnFpCfgInit (
|
||||
IN UINT32 Data,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
)
|
||||
{
|
||||
UINT32 ProductInfo;
|
||||
UINT64 FpCfg;
|
||||
PCI_ADDR PciAddress;
|
||||
|
||||
PciAddress.AddressValue = PRCT_INFO_PCI_ADDR;
|
||||
LibAmdPciRead (AccessWidth32, PciAddress, &ProductInfo, StdHeader);
|
||||
|
||||
LibAmdMsrRead (MSR_FP_CFG, &FpCfg, StdHeader);
|
||||
((FP_CFG_MSR *) &FpCfg)->DiDtMode = ((PRODUCT_INFO_REGISTER *) &ProductInfo)->DiDtMode;
|
||||
((FP_CFG_MSR *) &FpCfg)->DiDtCfg0 = ((PRODUCT_INFO_REGISTER *) &ProductInfo)->DiDtCfg0;
|
||||
((FP_CFG_MSR *) &FpCfg)->DiDtCfg1 = ((PRODUCT_INFO_REGISTER *) &ProductInfo)->DiDtCfg1;
|
||||
((FP_CFG_MSR *) &FpCfg)->DiDtCfg2 = ((PRODUCT_INFO_REGISTER *) &ProductInfo)->DiDtCfg2;
|
||||
((FP_CFG_MSR *) &FpCfg)->DiDtCfg4 = ((PRODUCT_INFO_REGISTER *) &ProductInfo)->DiDtCfg4;
|
||||
((FP_CFG_MSR *) &FpCfg)->DiDtCfg5 = ((PRODUCT_INFO_REGISTER *) &ProductInfo)->DiDtCfg5;
|
||||
LibAmdMsrWrite (MSR_FP_CFG, &FpCfg, StdHeader);
|
||||
}
|
||||
|
||||
|
||||
// Per-Node MSR with Special Programming Requirements Table
|
||||
STATIC CONST FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_INITIALIZER ROMDATA F15TnPerNodeMsrWorkarounds[] =
|
||||
{
|
||||
// MSR C001_00[6B:64]
|
||||
{
|
||||
FamSpecificWorkaround,
|
||||
{
|
||||
(AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily
|
||||
AMD_F15_TN_ALL // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
Update800MHzHtcPstateTo900MHz, // function call
|
||||
0x00000000, // data
|
||||
}}
|
||||
}
|
||||
};
|
||||
|
||||
|
||||
CONST REGISTER_TABLE ROMDATA F15TnPerNodeMsrWorkaroundTable = {
|
||||
PrimaryCores,
|
||||
(sizeof (F15TnPerNodeMsrWorkarounds) / sizeof (TABLE_ENTRY_FIELDS)),
|
||||
(TABLE_ENTRY_FIELDS *) F15TnPerNodeMsrWorkarounds,
|
||||
};
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Workaround for CPUs with a minimum P-state = 800MHz.
|
||||
*
|
||||
* AGESA should change the frequency of 800MHz P-states to 900MHz.
|
||||
*
|
||||
* @param[in] Data The table data value, for example to indicate which CPU and Platform types matched.
|
||||
* @param[in] StdHeader Config handle for library and services.
|
||||
*
|
||||
*/
|
||||
VOID
|
||||
STATIC
|
||||
Update800MHzHtcPstateTo900MHz (
|
||||
IN UINT32 Data,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
)
|
||||
{
|
||||
PCI_ADDR PciAddress;
|
||||
PSTATE_MSR HtcPstate;
|
||||
PSTATE_MSR HtcPstateMinus1;
|
||||
HTC_REGISTER HtcRegister;
|
||||
|
||||
PciAddress.AddressValue = HTC_PCI_ADDR;
|
||||
LibAmdPciRead (AccessWidth32, PciAddress, (VOID *) &HtcRegister, StdHeader);
|
||||
|
||||
LibAmdMsrRead ((HtcRegister.HtcPstateLimit + MSR_PSTATE_0), (UINT64 *) &HtcPstate, StdHeader);
|
||||
|
||||
if (HtcPstate.CpuFid == 0 && HtcPstate.CpuDid == 1) {
|
||||
if (HtcRegister.HtcPstateLimit == 0) {
|
||||
HtcPstateMinus1 = HtcPstate;
|
||||
} else {
|
||||
LibAmdMsrRead ((HtcRegister.HtcPstateLimit + MSR_PSTATE_0 - 1), (UINT64 *) &HtcPstateMinus1, StdHeader);
|
||||
}
|
||||
HtcPstate.CpuVid = HtcPstateMinus1.CpuVid;
|
||||
HtcPstate.CpuFid = 2;
|
||||
LibAmdMsrWrite ((HtcRegister.HtcPstateLimit + MSR_PSTATE_0), (UINT64 *) &HtcPstate, StdHeader);
|
||||
}
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,177 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* AMD Family_15 Trinity specific utility functions.
|
||||
*
|
||||
* Provides numerous utility functions specific to family 15h.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: CPU/Family/0x15/TN
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*
|
||||
*/
|
||||
/*
|
||||
******************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef _F15_TN_UTILITES_H_
|
||||
#define _F15_TN_UTILITES_H_
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------
|
||||
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
|
||||
*---------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------
|
||||
* D E F I N I T I O N S A N D M A C R O S
|
||||
*---------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------
|
||||
* T Y P E D E F S, S T R U C T U R E S, E N U M S
|
||||
*---------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------
|
||||
* F U N C T I O N P R O T O T Y P E
|
||||
*---------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
UINT8
|
||||
F15TnGetNumberOfPhysicalCores (
|
||||
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
VOID
|
||||
F15TnGetApMailboxFromHardware (
|
||||
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
|
||||
OUT AP_MAILBOXES *ApMailboxInfo,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
F15TnIsNbPstateEnabled (
|
||||
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
|
||||
IN PLATFORM_CONFIGURATION *PlatformConfig,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
VOID
|
||||
F15TnNbPstateDis (
|
||||
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
|
||||
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
F15TnGetProcIddMax (
|
||||
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
|
||||
IN UINT8 Pstate,
|
||||
OUT UINT32 *ProcIddMax,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
F15TnGetNbIddMax (
|
||||
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
|
||||
IN UINT8 NbPstate,
|
||||
OUT UINT32 *NbIddMax,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
AGESA_STATUS
|
||||
F15TnGetCurrentNbFrequency (
|
||||
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
|
||||
OUT UINT32 *FrequencyInMHz,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
AGESA_STATUS
|
||||
F15TnGetMinMaxNbFrequency (
|
||||
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
|
||||
IN PLATFORM_CONFIGURATION *PlatformConfig,
|
||||
IN PCI_ADDR *PciAddress,
|
||||
OUT UINT32 *MinFreqInMHz,
|
||||
OUT UINT32 *MaxFreqInMHz,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
F15TnGetNbPstateInfo (
|
||||
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
|
||||
IN PLATFORM_CONFIGURATION *PlatformConfig,
|
||||
IN PCI_ADDR *PciAddress,
|
||||
IN UINT32 NbPstate,
|
||||
OUT UINT32 *FreqNumeratorInMHz,
|
||||
OUT UINT32 *FreqDivisor,
|
||||
OUT UINT32 *VoltageInuV,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
UINT32
|
||||
F15TnGetApCoreNumber (
|
||||
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,191 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* AMD CPU Cache Flush On Halt Function for Family 15h Trinity.
|
||||
*
|
||||
* Contains code to initialize Cache Flush On Halt feature for Family 15h Trinity.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: CPU/Family/0x15/TN
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*
|
||||
*/
|
||||
/*
|
||||
******************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
******************************************************************************
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
*----------------------------------------------------------------------------
|
||||
* MODULES USED
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
#include "AGESA.h"
|
||||
#include "amdlib.h"
|
||||
#include "cpuRegisters.h"
|
||||
#include "cpuServices.h"
|
||||
#include "cpuFamilyTranslation.h"
|
||||
#include "cpuPostInit.h"
|
||||
#include "cpuF15PowerMgmt.h"
|
||||
#include "cpuF15TnPowerMgmt.h"
|
||||
#include "cpuFeatures.h"
|
||||
#include "Filecode.h"
|
||||
CODE_GROUP (G3_DXE)
|
||||
RDATA_GROUP (G3_DXE)
|
||||
|
||||
#define FILECODE PROC_CPU_FAMILY_0X15_TN_CPUF15TNCACHEFLUSHONHALT_FILECODE
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* DEFINITIONS AND MACROS
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* TYPEDEFS AND STRUCTURES
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* E X P O R T E D F U N C T I O N S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* PROTOTYPES OF LOCAL FUNCTIONS
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
VOID
|
||||
SetF15TnCacheFlushOnHaltRegister (
|
||||
IN CPU_CFOH_FAMILY_SERVICES *FamilySpecificServices,
|
||||
IN UINT64 EntryPoint,
|
||||
IN PLATFORM_CONFIGURATION *PlatformConfig,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* P U B L I C F U N C T I O N S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/* -----------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Enable Cpu Cache Flush On Halt Function
|
||||
*
|
||||
* @param[in] FamilySpecificServices The current Family Specific Services.
|
||||
* @param[in] EntryPoint Timepoint designator.
|
||||
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
|
||||
* @param[in] StdHeader Config Handle for library, services.
|
||||
*/
|
||||
VOID
|
||||
SetF15TnCacheFlushOnHaltRegister (
|
||||
IN CPU_CFOH_FAMILY_SERVICES *FamilySpecificServices,
|
||||
IN UINT64 EntryPoint,
|
||||
IN PLATFORM_CONFIGURATION *PlatformConfig,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
)
|
||||
{
|
||||
PCI_ADDR PciAddress;
|
||||
CLK_PWR_TIMING_CTRL2_REGISTER ClkPwrTimingCtrl2;
|
||||
CSTATE_POLICY_CTRL1_REGISTER CstatePolicyCtrl1;
|
||||
CSTATE_CTRL1_REGISTER CstateCtrl1;
|
||||
|
||||
if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) {
|
||||
// Set D18F3xDC[CacheFlushOnHaltCtl] != 0
|
||||
// Set D18F3xDC[CacheFlushOnHaltTmr]
|
||||
PciAddress.AddressValue = CPTC2_PCI_ADDR;
|
||||
LibAmdPciRead (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader);
|
||||
ClkPwrTimingCtrl2.CacheFlushOnHaltCtl = 7;
|
||||
ClkPwrTimingCtrl2.CacheFlushOnHaltTmr = 0x14;
|
||||
LibAmdPciWrite (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader);
|
||||
|
||||
// Set D18F4x128[CacheFlushTmr, CacheFlushSucMonThreshold]
|
||||
PciAddress.AddressValue = CSTATE_POLICY_CTRL1_PCI_ADDR;
|
||||
LibAmdPciRead (AccessWidth32, PciAddress, &CstatePolicyCtrl1, StdHeader);
|
||||
CstatePolicyCtrl1.CacheFlushTmr = 0x14;
|
||||
CstatePolicyCtrl1.CacheFlushSucMonThreshold = 7;
|
||||
LibAmdPciWrite (AccessWidth32, PciAddress, &CstatePolicyCtrl1, StdHeader);
|
||||
|
||||
// Set cache flush bits in D18F4x118
|
||||
PciAddress.AddressValue = CSTATE_CTRL1_PCI_ADDR;
|
||||
LibAmdPciRead (AccessWidth32, PciAddress, &CstateCtrl1, StdHeader);
|
||||
// Set C-state Action Field 0
|
||||
CstateCtrl1.CacheFlushEnCstAct0 = 1;
|
||||
CstateCtrl1.CacheFlushTmrSelCstAct0 = 2;
|
||||
CstateCtrl1.ClkDivisorCstAct0 = 0;
|
||||
// Set C-state Action Field 1
|
||||
CstateCtrl1.CacheFlushEnCstAct1 = 1;
|
||||
CstateCtrl1.CacheFlushTmrSelCstAct1 = 1;
|
||||
CstateCtrl1.ClkDivisorCstAct1 = 0;
|
||||
LibAmdPciWrite (AccessWidth32, PciAddress, &CstateCtrl1, StdHeader);
|
||||
|
||||
//Override the default setting
|
||||
IDS_OPTION_HOOK (IDS_CACHE_FLUSH_HLT, NULL, StdHeader);
|
||||
}
|
||||
}
|
||||
|
||||
CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F15TnCacheFlushOnHalt =
|
||||
{
|
||||
0,
|
||||
SetF15TnCacheFlushOnHaltRegister
|
||||
};
|
||||
@ -0,0 +1,280 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* AMD Family_15 Trinity after warm reset sequence for core P-states
|
||||
*
|
||||
* Performs the "Core Minimum P-State Transition Sequence After Warm Reset"
|
||||
* as described in the BKDG.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: CPU/Family/0x15/TN
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*
|
||||
*/
|
||||
/*
|
||||
******************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* M O D U L E S U S E D
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
#include "AGESA.h"
|
||||
#include "amdlib.h"
|
||||
#include "cpuF15PowerMgmt.h"
|
||||
#include "cpuF15TnPowerMgmt.h"
|
||||
#include "cpuRegisters.h"
|
||||
#include "GeneralServices.h"
|
||||
#include "cpuApicUtilities.h"
|
||||
#include "cpuFamilyTranslation.h"
|
||||
#include "OptionMultiSocket.h"
|
||||
#include "cpuF15TnCoreAfterReset.h"
|
||||
#include "Filecode.h"
|
||||
CODE_GROUP (G3_DXE)
|
||||
RDATA_GROUP (G3_DXE)
|
||||
|
||||
|
||||
#define FILECODE PROC_CPU_FAMILY_0X15_TN_CPUF15TNCOREAFTERRESET_FILECODE
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* D E F I N I T I O N S A N D M A C R O S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* T Y P E D E F S A N D S T R U C T U R E S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
VOID
|
||||
STATIC
|
||||
F15TnPmCoreAfterResetPhase1OnCore (
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
VOID
|
||||
STATIC
|
||||
F15TnPmCoreAfterResetPhase2OnCore (
|
||||
IN VOID *HwPsMaxVal,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* E X P O R T E D F U N C T I O N S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Family 15h Trinity core 0 entry point for performing the necessary steps for core
|
||||
* P-states after a warm reset has occurred.
|
||||
*
|
||||
* The steps are as follows:
|
||||
* 1. Write 0 to MSRC001_0062[PstateCmd] on all cores in the processor.
|
||||
* 2. Wait for MSRC001_0071[CurCpuFid, CurCpuDid] = [CpuFid, CpuDid] from
|
||||
* MSRC001_00[6B:64] indexed by MSRC001_0071[CurPstateLimit].
|
||||
* 3. Write MSRC001_0061[PstateMaxVal] to MSRC001_0062[PstateCmd] on all
|
||||
* cores in the processor.
|
||||
* 4. Wait for MSRC001_0071[CurCpuFid, CurCpuDid] = [CpuFid, CpuDid] from
|
||||
* MSRC001_00[6B:64] indexed by MSRC001_0061[PstateMaxVal].
|
||||
* 5. If MSRC001_0071[CurPstateLimit] != MSRC001_0071[CurPstate], wait for
|
||||
* MSRC001_0071[CurCpuVid] = [CpuVid] from MSRC001_00[6B:64] indexed by
|
||||
* MSRC001_0061[PstateMaxVal].
|
||||
* 6. Wait for MSRC001_0063[CurPstate] = MSRC001_0062[PstateCmd].
|
||||
*
|
||||
* @param[in] FamilySpecificServices The current Family Specific Services.
|
||||
* @param[in] CpuEarlyParamsPtr Service parameters
|
||||
* @param[in] StdHeader Config handle for library and services.
|
||||
*
|
||||
*/
|
||||
VOID
|
||||
F15TnPmCoreAfterReset (
|
||||
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
|
||||
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
)
|
||||
{
|
||||
UINT32 Core;
|
||||
UINT32 HwPsMaxVal;
|
||||
PCI_ADDR PciAddress;
|
||||
AP_TASK TaskPtr;
|
||||
|
||||
IDS_HDT_CONSOLE (CPU_TRACE, " F15TnPmCoreAfterReset\n");
|
||||
|
||||
GetCurrentCore (&Core, StdHeader);
|
||||
ASSERT (Core == 0);
|
||||
|
||||
OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader);
|
||||
PciAddress.Address.Function = FUNC_3;
|
||||
PciAddress.Address.Register = CPTC2_REG;
|
||||
LibAmdPciRead (AccessWidth32, PciAddress, &HwPsMaxVal, StdHeader);
|
||||
HwPsMaxVal = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &HwPsMaxVal)->PstateMaxVal;
|
||||
|
||||
// Launch each local core to perform steps 1 through 3.
|
||||
TaskPtr.FuncAddress.PfApTask = F15TnPmCoreAfterResetPhase1OnCore;
|
||||
TaskPtr.DataTransfer.DataSizeInDwords = 0;
|
||||
TaskPtr.ExeFlags = WAIT_FOR_CORE;
|
||||
ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);
|
||||
|
||||
// Launch each local core to perform steps 4 through 6.
|
||||
TaskPtr.FuncAddress.PfApTaskI = F15TnPmCoreAfterResetPhase2OnCore;
|
||||
TaskPtr.DataTransfer.DataSizeInDwords = 1;
|
||||
TaskPtr.DataTransfer.DataPtr = &HwPsMaxVal;
|
||||
TaskPtr.DataTransfer.DataTransferFlags = 0;
|
||||
TaskPtr.ExeFlags = WAIT_FOR_CORE;
|
||||
ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);
|
||||
}
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------
|
||||
* L O C A L F U N C T I O N S
|
||||
*---------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Support routine for F15TnPmCoreAfterReset to perform MSR initialization on all
|
||||
* cores of a family 15h socket.
|
||||
*
|
||||
* This function implements steps 1 - 3 on each core.
|
||||
*
|
||||
* @param[in] StdHeader Config handle for library and services.
|
||||
*
|
||||
*/
|
||||
VOID
|
||||
STATIC
|
||||
F15TnPmCoreAfterResetPhase1OnCore (
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
)
|
||||
{
|
||||
UINT64 CofvidSts;
|
||||
UINT64 LocalMsrRegister;
|
||||
UINT64 PstateCtrl;
|
||||
|
||||
IDS_HDT_CONSOLE (CPU_TRACE, " F15TnPmCoreAfterResetPhase1OnCore\n");
|
||||
|
||||
// 1. Write 0 to MSRC001_0062[PstateCmd] on all cores in the processor.
|
||||
PstateCtrl = 0;
|
||||
LibAmdMsrWrite (MSR_PSTATE_CTL, &PstateCtrl, StdHeader);
|
||||
|
||||
// 2. Wait for MSRC001_0071[CurCpuFid, CurCpuDid] = [CpuFid, CpuDid] from
|
||||
// MSRC001_00[6B:64] indexed by MSRC001_0071[CurPstateLimit].
|
||||
do {
|
||||
LibAmdMsrRead (MSR_COFVID_STS, &CofvidSts, StdHeader);
|
||||
LibAmdMsrRead ((UINT32) (MSR_PSTATE_0 + (UINT32) (((COFVID_STS_MSR *) &CofvidSts)->CurPstateLimit)), &LocalMsrRegister, StdHeader);
|
||||
} while ((((COFVID_STS_MSR *) &CofvidSts)->CurCpuFid != ((PSTATE_MSR *) &LocalMsrRegister)->CpuFid) ||
|
||||
(((COFVID_STS_MSR *) &CofvidSts)->CurCpuDid != ((PSTATE_MSR *) &LocalMsrRegister)->CpuDid));
|
||||
|
||||
// 3. Write MSRC001_0061[PstateMaxVal] to MSRC001_0062[PstateCmd] on all
|
||||
// cores in the processor.
|
||||
LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &LocalMsrRegister, StdHeader);
|
||||
((PSTATE_CTRL_MSR *) &PstateCtrl)->PstateCmd = ((PSTATE_CURLIM_MSR *) &LocalMsrRegister)->PstateMaxVal;
|
||||
LibAmdMsrWrite (MSR_PSTATE_CTL, &PstateCtrl, StdHeader);
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Support routine for F15TnPmCoreAfterReset to perform MSR initialization on all
|
||||
* cores of a family 15h socket.
|
||||
*
|
||||
* This function implements steps 4 - 6 on each core.
|
||||
*
|
||||
* @param[in] HwPsMaxVal Index of the highest enabled HW P-state.
|
||||
* @param[in] StdHeader Config handle for library and services.
|
||||
*
|
||||
*/
|
||||
VOID
|
||||
STATIC
|
||||
F15TnPmCoreAfterResetPhase2OnCore (
|
||||
IN VOID *HwPsMaxVal,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
)
|
||||
{
|
||||
UINT64 TargetPsMsr;
|
||||
UINT64 LocalMsrRegister;
|
||||
UINT64 PstateCtrl;
|
||||
|
||||
IDS_HDT_CONSOLE (CPU_TRACE, " F15TnPmCoreAfterResetPhase2OnCore\n");
|
||||
|
||||
// 4. Wait for MSRC001_0071[CurCpuFid, CurCpuDid] = [CpuFid, CpuDid] from
|
||||
// MSRC001_00[6B:64] indexed by D18F3xDC[PstateMaxVal].
|
||||
LibAmdMsrRead ((*(UINT32 *) HwPsMaxVal) + MSR_PSTATE_0, &TargetPsMsr, StdHeader);
|
||||
do {
|
||||
LibAmdMsrRead (MSR_COFVID_STS, &LocalMsrRegister, StdHeader);
|
||||
} while ((((COFVID_STS_MSR *) &LocalMsrRegister)->CurCpuFid != ((PSTATE_MSR *) &TargetPsMsr)->CpuFid) ||
|
||||
(((COFVID_STS_MSR *) &LocalMsrRegister)->CurCpuDid != ((PSTATE_MSR *) &TargetPsMsr)->CpuDid));
|
||||
|
||||
// 5. If MSRC001_0071[CurPstateLimit] != MSRC001_0071[CurPstate], wait for
|
||||
// MSRC001_0071[CurCpuVid] = [CpuVid] from MSRC001_00[6B:64] indexed by
|
||||
// MSRC001_0061[PstateMaxVal].
|
||||
if (((COFVID_STS_MSR *) &LocalMsrRegister)->CurPstateLimit != ((COFVID_STS_MSR *) &LocalMsrRegister)->CurPstate) {
|
||||
do {
|
||||
LibAmdMsrRead (MSR_COFVID_STS, &LocalMsrRegister, StdHeader);
|
||||
} while (GetF15TnCurCpuVid (&LocalMsrRegister) != GetF15TnCpuVid (&TargetPsMsr));
|
||||
}
|
||||
|
||||
// 6. Wait for MSRC001_0063[CurPstate] = MSRC001_0062[PstateCmd].
|
||||
LibAmdMsrRead (MSR_PSTATE_CTL, &PstateCtrl, StdHeader);
|
||||
do {
|
||||
LibAmdMsrRead (MSR_PSTATE_STS, &LocalMsrRegister, StdHeader);
|
||||
} while (((PSTATE_STS_MSR *) &LocalMsrRegister)->CurPstate != ((PSTATE_CTRL_MSR *) &PstateCtrl)->PstateCmd);
|
||||
}
|
||||
@ -0,0 +1,105 @@
|
||||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* AMD Family_15 Trinity after warm reset sequence for core P-states
|
||||
*
|
||||
* Contains code that provide power management functionality
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: CPU/Family/0x15/TN
|
||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
|
||||
*
|
||||
*/
|
||||
/*
|
||||
******************************************************************************
|
||||
*
|
||||
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
|
||||
*
|
||||
* AMD is granting you permission to use this software (the Materials)
|
||||
* pursuant to the terms and conditions of your Software License Agreement
|
||||
* with AMD. This header does *NOT* give you permission to use the Materials
|
||||
* or any rights under AMD's intellectual property. Your use of any portion
|
||||
* of these Materials shall constitute your acceptance of those terms and
|
||||
* conditions. If you do not agree to the terms and conditions of the Software
|
||||
* License Agreement, please do not use any portion of these Materials.
|
||||
*
|
||||
* CONFIDENTIALITY: The Materials and all other information, identified as
|
||||
* confidential and provided to you by AMD shall be kept confidential in
|
||||
* accordance with the terms and conditions of the Software License Agreement.
|
||||
*
|
||||
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
|
||||
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
|
||||
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
|
||||
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
|
||||
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
|
||||
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
|
||||
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
|
||||
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
|
||||
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
|
||||
*
|
||||
* AMD does not assume any responsibility for any errors which may appear in
|
||||
* the Materials or any other related information provided to you by AMD, or
|
||||
* result from use of the Materials or any related information.
|
||||
*
|
||||
* You agree that you will not reverse engineer or decompile the Materials.
|
||||
*
|
||||
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
|
||||
* further information, software, technical information, know-how, or show-how
|
||||
* available to you. Additionally, AMD retains the right to modify the
|
||||
* Materials at any time, without notice, and is not obligated to provide such
|
||||
* modified Materials to you.
|
||||
*
|
||||
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
|
||||
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
|
||||
* subject to the restrictions as set forth in FAR 52.227-14 and
|
||||
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
|
||||
* Government constitutes acknowledgement of AMD's proprietary rights in them.
|
||||
*
|
||||
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
|
||||
* direct product thereof will be exported directly or indirectly, into any
|
||||
* country prohibited by the United States Export Administration Act and the
|
||||
* regulations thereunder, without the required authorization from the U.S.
|
||||
* government nor will be used for any purpose prohibited by the same.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef _CPU_F15_TN_CORE_AFTER_RESET_H_
|
||||
#define _CPU_F15_TN_CORE_AFTER_RESET_H_
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------
|
||||
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
|
||||
*---------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------
|
||||
* D E F I N I T I O N S A N D M A C R O S
|
||||
*---------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------
|
||||
* T Y P E D E F S, S T R U C T U R E S, E N U M S
|
||||
*---------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------
|
||||
* F U N C T I O N P R O T O T Y P E
|
||||
*---------------------------------------------------------------------------------------
|
||||
*/
|
||||
VOID
|
||||
F15TnPmCoreAfterReset (
|
||||
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
|
||||
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
#endif // _CPU_F15_TN_CORE_AFTER_RESET_H_
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
x
Reference in New Issue
Block a user