soc/amd/common/smi_util: add PSP SMI helper functions

The PSP can send SMIs to the x86 side of the system. Add helper
functions to configure and to reset the PSP SMI generation. Since
Stoneyridge also selects SOC_AMD_COMMON_BLOCK_SMI, add the SMITRIG0_PSP
define and rename SMITYPE_FCH_FAKE0 to SMITYPE_PSP in its SoC-specific
smi.h to bring it in line with the newer SoCs.

This patch is split out from CB:65523.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Change-Id: I525a447c9a75fdb95b9750e85a02896056315edf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83702
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/amd/common/block/include/amdblocks/smi.h

@@ -48,5 +48,7 @@ void disable_gevent_smi(uint8_t gevent);
 void gpe_configure_sci(const struct sci_source *scis, size_t num_gpes);
 void clear_all_smi_status(void);
 void clear_smi_sci_status(void);
+void reset_psp_smi(void);
+void configure_psp_smi(void);
 
 #endif /* AMD_BLOCK_SMI_H */

src/soc/amd/common/block/smi/smi_util.c

@@ -154,3 +154,27 @@ void clear_smi_sci_status(void)
 {
 	smi_write32(SMI_SCI_STATUS, smi_read32(SMI_SCI_STATUS));
 }
+
+static void clear_psp_smi(void)
+{
+	uint32_t reg32;
+	/* SMITYPE_PSP is 33, so it's bit 33 % 32 in the second 32 bit SMI status register */
+	reg32 = smi_read32(SMI_REG_SMISTS1);
+	reg32 |= 1 << (SMITYPE_PSP % 32);
+	smi_write32(SMI_REG_SMISTS1, reg32);
+}
+
+void reset_psp_smi(void)
+{
+	uint32_t reg32;
+	reg32 = smi_read32(SMI_REG_SMITRIG0);
+	reg32 &= ~SMITRIG0_PSP;
+	smi_write32(SMI_REG_SMITRIG0, reg32);
+}
+
+void configure_psp_smi(void)
+{
+	clear_psp_smi();
+	reset_psp_smi();
+	configure_smi(SMITYPE_PSP, SMI_MODE_SMI);
+}

src/soc/amd/stoneyridge/include/soc/smi.h

@@ -71,7 +71,7 @@
 #define SMITYPE_ESPI_SYS			26
 #define SMITYPE_ESPI_WAKE_PME			27
 /* 28-32 Reserved */
-#define SMITYPE_FCH_FAKE0			33
+#define SMITYPE_PSP				33
 #define SMITYPE_FCH_FAKE1			34
 #define SMITYPE_FCH_FAKE2			35
 /* 36 Reserved */
@@ -163,6 +163,7 @@
 #define SMI_TIMER_EN				(1 << 15)
 
 #define SMI_REG_SMITRIG0		0x98
+# define SMITRIG0_PSP				BIT(25)
 # define SMITRG0_EOS				BIT(28)
 # define SMI_TIMER_SEL				BIT(29)
 # define SMITRG0_SMIENB				BIT(31)