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mb/google/brya/var/xol: Tune I2C5 timing parameters

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Update I2C5 timing parameter values to meet I2C bus spec.
- fall_time_ns: 400 -> 200

BUG=None
BRANCH=brya
TEST=built and measure I2C5 timing parameters

Before:
tLOW : 1.88 us (spec >= 1.30)
tHIGH: 0.57 us (spec >= 0.60)
fSCL : 399.80 KHz

After:
tLOW : 1.60 us (spec >= 1.30)
tHIGH: 0.97 us (spec >= 0.60)
fSCL : 392.1 KHz

Change-Id: I386b2765410fd10b8cd711f54478fb52428de5a3
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
This commit is contained in:
Seunghwan Kim
2024-04-29 15:14:31 +09:00
committed by Felix Held
parent d145a840bf
commit 7f0a7f65e6
1 changed files with 1 additions and 1 deletions
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2
src/mainboard/google/brya/variants/xol/overridetree.cb
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@@ -132,7 +132,7 @@ chip soc/intel/alderlake
.i2c[5] = { .i2c[5] = {
.speed = I2C_SPEED_FAST, .speed = I2C_SPEED_FAST,
.rise_time_ns = 650, .rise_time_ns = 650,
.fall_time_ns = 400, .fall_time_ns = 200,
.data_hold_time_ns = 50, .data_hold_time_ns = 50,
}, },
}" }"