sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/google/hatch: Create kindred variant

Browse Source 
Create the Kindred variant of Hatch by taking a copy of the Hatch files
as placeholders. Kindred-specific changes will happen in future CLs.

BUG=b:133181366
BRANCH=NONE
TEST=util/abuild/abuild -p none -t google/hatch -x -a
make sure the build includes GOOGLE_KINDRED

Change-Id: I09ad3da0505d599fc3797d7fa24b4dc170dcd18b
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32936
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Paul Fagerburg
2019-05-21 14:54:26 -06:00
committed by Aaron Durbin
parent a1d0928b00
commit 7fa3d5673c
7 changed files with 245 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
src/mainboard/google/hatch/Kconfig
View File

@@ -65,6 +65,7 @@ config GBB_HWID
default "HATCH TEST 1823" if BOARD_GOOGLE_HATCH
default "HATCH_WHL TEST 2374" if BOARD_GOOGLE_HATCH_WHL
default "KOHAKU TEST 1953" if BOARD_GOOGLE_KOHAKU
default "KINDRED TEST 2636" if BOARD_GOOGLE_KINDRED
config MAINBOARD_DIR
string
@@ -79,6 +80,7 @@ config MAINBOARD_PART_NUMBER
default "Hatch" if BOARD_GOOGLE_HATCH
default "Hatch_whl" if BOARD_GOOGLE_HATCH_WHL
default "Kohaku" if BOARD_GOOGLE_KOHAKU
default "Kindred" if BOARD_GOOGLE_KINDRED
config MAINBOARD_VENDOR
string
@@ -101,6 +103,7 @@ config VARIANT_DIR
default "hatch" if BOARD_GOOGLE_HATCH
default "hatch_whl" if BOARD_GOOGLE_HATCH_WHL
default "kohaku" if BOARD_GOOGLE_KOHAKU
default "kindred" if BOARD_GOOGLE_KINDRED
config VBOOT
select HAS_RECOVERY_MRC_CACHE

6
src/mainboard/google/hatch/Kconfig.name
View File

@@ -17,3 +17,9 @@ config BOARD_GOOGLE_KOHAKU
select BOARD_GOOGLE_BASEBOARD_HATCH
select BOARD_ROMSIZE_KB_16384
select SOC_INTEL_COMETLAKE
config BOARD_GOOGLE_KINDRED
bool "-> Kindred"
select BOARD_GOOGLE_BASEBOARD_HATCH
select BOARD_ROMSIZE_KB_16384
select SOC_INTEL_COMETLAKE

20
src/mainboard/google/hatch/variants/kindred/Makefile.inc Normal file
View File

@@ -0,0 +1,20 @@
## This file is part of the coreboot project.
##
## Copyright 2019 Google LLC
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
SPD_SOURCES = 4G_2400 # 0b000
SPD_SOURCES += empty_ddr4 # 0b001
SPD_SOURCES += 8G_2400 # 0b010
SPD_SOURCES += 8G_2666 # 0b011
SPD_SOURCES += 16G_2400 # 0b100
SPD_SOURCES += 16G_2666 # 0b101

16
src/mainboard/google/hatch/variants/kindred/include/variant/acpi/dptf.asl Normal file
View File

@@ -0,0 +1,16 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2019 Google LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <baseboard/acpi/dptf.asl>

21
src/mainboard/google/hatch/variants/kindred/include/variant/ec.h Normal file
View File

@@ -0,0 +1,21 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2019 Google LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef VARIANT_EC_H
#define VARIANT_EC_H
#include <baseboard/ec.h>
#endif

21
src/mainboard/google/hatch/variants/kindred/include/variant/gpio.h Normal file
View File

@@ -0,0 +1,21 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2019 Google LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
* GNU General Public License for more details.
*/
#ifndef VARIANT_GPIO_H
#define VARIANT_GPIO_H
#include <baseboard/gpio.h>
#endif

158
src/mainboard/google/hatch/variants/kindred/overridetree.cb Normal file
View File

@@ -0,0 +1,158 @@
chip soc/intel/cannonlake
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C1] = PchSerialIoPci,
[PchSerialIoIndexI2C2] = PchSerialIoPci,
[PchSerialIoIndexI2C3] = PchSerialIoPci,
[PchSerialIoIndexI2C4] = PchSerialIoPci,
[PchSerialIoIndexI2C5] = PchSerialIoPci,
[PchSerialIoIndexSPI0] = PchSerialIoPci,
[PchSerialIoIndexSPI1] = PchSerialIoPci,
[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
[PchSerialIoIndexUART1] = PchSerialIoDisabled,
[PchSerialIoIndexUART2] = PchSerialIoDisabled,
}"
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| GSPI0 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
#| | before memory is up |
#| GSPI1 | FP MCU |
#| I2C0 | Touchpad |
#| I2C1 | Touch screen |
#| I2C4 | Audio |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.gspi[0] = {
.speed_mhz = 1,
.early_init = 1,
},
.i2c[0] = {
.speed = I2C_SPEED_FAST,
},
.i2c[1] = {
.speed = I2C_SPEED_FAST,
},
.i2c[4] = {
.speed = I2C_SPEED_FAST,
},
}"
# GPIO for SD card detect
register "sdcard_cd_gpio" = "vSD3_CD_B"
device domain 0 on
device pci 15.0 on
chip drivers/i2c/generic
register "hid" = ""ELAN0000""
register "desc" = ""ELAN Touchpad""
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D21_IRQ)"
register "wake" = "GPE0_DW0_21"
device i2c 15 on end
end
end # I2C #0
device pci 15.1 on
chip drivers/i2c/generic
register "hid" = ""ELAN0001""
register "desc" = ""ELAN Touchscreen""
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)"
register "probed" = "1"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
register "reset_delay_ms" = "100"
register "reset_off_delay_ms" = "5"
register "has_power_resource" = "1"
register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)"
register "stop_off_delay_ms" = "5"
device i2c 49 on end
end
chip drivers/i2c/hid
register "generic.hid" = ""GDIX0000""
register "generic.desc" = ""Goodix Touchscreen""
register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)"
register "generic.probed" = "1"
register "generic.reset_gpio" =
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
register "generic.reset_delay_ms" = "10"
register "generic.reset_off_delay_ms" = "1"
register "generic.has_power_resource" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 5d on end
end
chip drivers/generic/gpio_keys
register "name" = ""PENH""
register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A8)"
register "key.wake" = "GPE0_DW0_08"
register "key.wakeup_event_action" = "EV_ACT_ASSERTED"
register "key.dev_name" = ""EJCT""
register "key.linux_code" = "SW_PEN_INSERTED"
register "key.linux_input_type" = "EV_SW"
register "key.label" = ""pen_eject""
device generic 0 on end
end
end # I2C #1
device pci 15.2 off end # I2C #2
device pci 15.3 on
chip drivers/i2c/sx9310
register "desc" = ""SAR Proximity Sensor""
register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A0)"
register "speed" = "I2C_SPEED_FAST"
register "uid" = "1"
register "reg_prox_ctrl0" = "0x10"
register "reg_prox_ctrl1" = "0x00"
register "reg_prox_ctrl2" = "0x84"
register "reg_prox_ctrl3" = "0x0e"
register "reg_prox_ctrl4" = "0x07"
register "reg_prox_ctrl5" = "0xc6"
register "reg_prox_ctrl6" = "0x20"
register "reg_prox_ctrl7" = "0x0d"
register "reg_prox_ctrl8" = "0x8d"
register "reg_prox_ctrl9" = "0x43"
register "reg_prox_ctrl10" = "0x1f"
register "reg_prox_ctrl11" = "0x00"
register "reg_prox_ctrl12" = "0x00"
register "reg_prox_ctrl13" = "0x00"
register "reg_prox_ctrl14" = "0x00"
register "reg_prox_ctrl15" = "0x00"
register "reg_prox_ctrl16" = "0x00"
register "reg_prox_ctrl17" = "0x00"
register "reg_prox_ctrl18" = "0x00"
register "reg_prox_ctrl19" = "0x00"
register "reg_sar_ctrl0" = "0x50"
register "reg_sar_ctrl1" = "0x8a"
register "reg_sar_ctrl2" = "0x3c"
device i2c 28 on end
end
end # I2C #3
device pci 19.0 on
chip drivers/i2c/generic
register "hid" = ""10EC5682""
register "name" = ""RT58""
register "desc" = ""Realtek RT5682""
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)"
register "property_count" = "1"
# Set the jd_src to RT5668_JD1 for jack detection
register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
register "property_list[0].name" = ""realtek,jd-src""
register "property_list[0].integer" = "1"
device i2c 1a on end
end
end #I2C #4
device pci 1e.3 on
chip drivers/spi/acpi
register "name" = ""CRFP""
register "hid" = "ACPI_DT_NAMESPACE_HID"
register "uid" = "1"
register "compat_string" = ""google,cros-ec-spi""
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A23_IRQ)"
device spi 1 on end
end # FPMCU
end # GSPI #1
end
end