mb/system76/*: Enable dGPUs
Change-Id: Ib5bab02801407c8bf05e6028bf8f9fa7ccc5ecd0 Signed-off-by: Tim Crawford <tcrawford@system76.com>
This commit is contained in:
		@@ -3,6 +3,7 @@ if BOARD_SYSTEM76_ADDW1 || BOARD_SYSTEM76_ADDW2
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config BOARD_SPECIFIC_OPTIONS
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					config BOARD_SPECIFIC_OPTIONS
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	def_bool y
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						def_bool y
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	select BOARD_ROMSIZE_KB_16384
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						select BOARD_ROMSIZE_KB_16384
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						select DRIVERS_GFX_NVIDIA
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	select DRIVERS_I2C_HID
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						select DRIVERS_I2C_HID
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	select DRIVERS_I2C_TAS5825M
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						select DRIVERS_I2C_TAS5825M
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	select EC_SYSTEM76_EC
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						select EC_SYSTEM76_EC
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@@ -1,4 +1,5 @@
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
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					CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
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					CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
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bootblock-y += bootblock.c
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					bootblock-y += bootblock.c
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bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c
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					bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c
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@@ -1,5 +1,8 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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					/* SPDX-License-Identifier: GPL-2.0-only */
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					#include <variant/dgpu.h>
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					#include <drivers/gfx/nvidia/acpi/gpu.asl>
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#define EC_GPE_SCI 0x03 /* GPP_K3 */
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					#define EC_GPE_SCI 0x03 /* GPP_K3 */
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#define EC_GPE_SWI 0x06 /* GPP_K6 */
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					#define EC_GPE_SWI 0x06 /* GPP_K6 */
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#include <ec/system76/ec/acpi/ec.asl>
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					#include <ec/system76/ec/acpi/ec.asl>
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@@ -58,6 +58,13 @@ chip soc/intel/cannonlake
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			# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
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								# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
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			register "PcieClkSrcUsage[8]" = "0x40"
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								register "PcieClkSrcUsage[8]" = "0x40"
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			register "PcieClkSrcClkReq[8]" = "8"
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								register "PcieClkSrcClkReq[8]" = "8"
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								chip drivers/gfx/nvidia
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									device pci 00.0 on end # VGA controller
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									device pci 00.1 on end # Audio device
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									device pci 00.2 on end # USB xHCI Host controller
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									device pci 00.3 on end # USB Type-C UCSI controller
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								end
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		end
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							end
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		device pci 02.0 on  end # Integrated Graphics Device
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							device pci 02.0 on  end # Integrated Graphics Device
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		device pci 04.0 on      # SA Thermal device
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							device pci 04.0 on      # SA Thermal device
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@@ -1,7 +1,9 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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					/* SPDX-License-Identifier: GPL-2.0-only */
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					#include <drivers/gfx/nvidia/gpu.h>
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#include <soc/cnl_memcfg_init.h>
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					#include <soc/cnl_memcfg_init.h>
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#include <soc/romstage.h>
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					#include <soc/romstage.h>
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					#include <variant/dgpu.h>
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static const struct cnl_mb_cfg memcfg = {
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					static const struct cnl_mb_cfg memcfg = {
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	.spd[0] = {
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						.spd[0] = {
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@@ -20,6 +22,18 @@ static const struct cnl_mb_cfg memcfg = {
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void mainboard_memory_init_params(FSPM_UPD *memupd)
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					void mainboard_memory_init_params(FSPM_UPD *memupd)
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{
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					{
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						const struct nvidia_gpu_config config = {
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							.power_gpio = DGPU_PWR_EN,
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							.reset_gpio = DGPU_RST_N,
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							.enable = true,
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						};
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						// Enable dGPU power
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						nvidia_set_power(&config);
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						// Set primary display to internal graphics
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						memupd->FspmConfig.PrimaryDisplay = 0;
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	// Allow higher memory speeds
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						// Allow higher memory speeds
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	memupd->FspmConfig.SaOcSupport = 1;
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						memupd->FspmConfig.SaOcSupport = 1;
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@@ -0,0 +1,12 @@
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					/* SPDX-License-Identifier: GPL-2.0-only */
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					#ifndef VARIANT_DGPU_H
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					#define VARIANT_DGPU_H
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					#include <soc/gpio.h>
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					#define DGPU_RST_N	GPP_F22
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					#define DGPU_PWR_EN	GPP_F23
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					#define DGPU_GC6	GPP_C12
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					#endif
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@@ -0,0 +1,12 @@
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					/* SPDX-License-Identifier: GPL-2.0-only */
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					#ifndef VARIANT_DGPU_H
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					#define VARIANT_DGPU_H
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					#include <soc/gpio.h>
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					#define DGPU_RST_N	GPP_F22
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					#define DGPU_PWR_EN	GPP_F23
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					#define DGPU_GC6	GPP_K21
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					#endif
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@@ -3,6 +3,7 @@ if BOARD_SYSTEM76_BONW14
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config BOARD_SPECIFIC_OPTIONS
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					config BOARD_SPECIFIC_OPTIONS
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	def_bool y
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						def_bool y
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	select BOARD_ROMSIZE_KB_16384
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						select BOARD_ROMSIZE_KB_16384
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						select DRIVERS_GFX_NVIDIA
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	select DRIVERS_I2C_HID
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						select DRIVERS_I2C_HID
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	select EC_SYSTEM76_EC
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						select EC_SYSTEM76_EC
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	select EC_SYSTEM76_EC_BAT_THRESHOLDS
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						select EC_SYSTEM76_EC_BAT_THRESHOLDS
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@@ -62,10 +62,12 @@ chip soc/intel/cannonlake
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			register "PcieClkSrcUsage[7]" = "0x40"
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								register "PcieClkSrcUsage[7]" = "0x40"
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			register "PcieClkSrcClkReq[7]" = "7"
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								register "PcieClkSrcClkReq[7]" = "7"
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			device pci 00.0 on end # VGA controller
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								chip drivers/gfx/nvidia
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			device pci 00.1 on end # Audio device
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									device pci 00.0 on end # VGA controller
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			device pci 00.2 on end # USB xHCI Host controller
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									device pci 00.1 on end # Audio device
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			device pci 00.3 on end # USB Type-C UCSI controller
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									device pci 00.2 on end # USB xHCI Host controller
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									device pci 00.3 on end # USB Type-C UCSI controller
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								end
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		end
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							end
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		# TODO: is this enough to disable iGPU?
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							# TODO: is this enough to disable iGPU?
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		device pci 02.0 off end # Integrated Graphics Device
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							device pci 02.0 off end # Integrated Graphics Device
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@@ -3,6 +3,7 @@ if BOARD_SYSTEM76_GALP5
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config BOARD_SPECIFIC_OPTIONS
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					config BOARD_SPECIFIC_OPTIONS
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	def_bool y
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						def_bool y
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	select BOARD_ROMSIZE_KB_16384
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						select BOARD_ROMSIZE_KB_16384
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						select DRIVERS_GFX_NVIDIA
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	select DRIVERS_I2C_HID
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						select DRIVERS_I2C_HID
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	select DRIVERS_INTEL_PMC
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						select DRIVERS_INTEL_PMC
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	select DRIVERS_INTEL_USB4_RETIMER
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						select DRIVERS_INTEL_USB4_RETIMER
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@@ -57,4 +58,7 @@ config UART_FOR_CONSOLE
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config USE_PM_ACPI_TIMER
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					config USE_PM_ACPI_TIMER
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	default n
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						default n
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					config DRIVERS_GFX_NVIDIA_BRIDGE
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						default 0x1c
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endif
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					endif
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										36
									
								
								src/mainboard/system76/galp5/acpi/dgpu.asl
									
									
									
									
									
										Normal file
									
								
							
							
						
						
									
										36
									
								
								src/mainboard/system76/galp5/acpi/dgpu.asl
									
									
									
									
									
										Normal file
									
								
							@@ -0,0 +1,36 @@
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					/* SPDX-License-Identifier: GPL-2.0-only */
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					Scope (\_SB.PCI0.RP05)
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					{
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						Device (DEV0)
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						{
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							Name(_ADR, 0x00000000)
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							OperationRegion (PCIC, PCI_Config, 0x00, 0x50)
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							Field (PCIC, DwordAcc, NoLock, Preserve)
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							{
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								Offset (0x40),
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								SSID, 32
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							}
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							Name (_PR0, Package () { PWRR })
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							Name (_PR3, Package () { PWRR })
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							PowerResource (PWRR, 0, 0)
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							{
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								Name (_STA, 1)
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								Method (_ON)
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								{
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									^^SSID = 0x40181558
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									Printf("GPU _ON %o", ToHexString(^^SSID))
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									_STA = 1
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								}
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								Method (_OFF)
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								{
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									Printf("GPU _OFF %o", ToHexString(^^SSID))
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									_STA = 0
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								}
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							}
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						}
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					}
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@@ -1,5 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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					/* SPDX-License-Identifier: GPL-2.0-only */
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					#include "dgpu.asl"
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#define EC_GPE_SCI 0x6E
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					#define EC_GPE_SCI 0x6E
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#define EC_GPE_SWI 0x6B
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					#define EC_GPE_SWI 0x6B
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#include <ec/system76/ec/acpi/ec.asl>
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					#include <ec/system76/ec/acpi/ec.asl>
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@@ -279,6 +279,13 @@ chip soc/intel/tigerlake
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				register "srcclk_pin" = "2" # PEG_CLKREQ#
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									register "srcclk_pin" = "2" # PEG_CLKREQ#
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				device generic 0 on end
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									device generic 0 on end
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			end
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								end
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								chip drivers/gfx/nvidia
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									device pci 00.0 on end # VGA controller
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									device pci 00.1 on end # Audio device
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									device pci 00.2 on end # USB xHCI Host controller
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									device pci 00.3 on end # USB Type-C UCSI controller
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								end
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		end
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							end
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		device ref pcie_rp9 on
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							device ref pcie_rp9 on
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			# PCIe root port #9 x1, Clock 3 (CARD)
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								# PCIe root port #9 x1, Clock 3 (CARD)
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@@ -5,6 +5,12 @@
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#include <soc/gpio.h>
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					#include <soc/gpio.h>
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					#define DGPU_RST_N	GPP_U4
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					#define DGPU_PWR_EN	GPP_U5
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					#define DGPU_GC6	GPP_D2
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					#ifndef __ACPI__
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static const struct pad_config early_gpio_table[] = {
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					static const struct pad_config early_gpio_table[] = {
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	PAD_CFG_NF(GPP_C20, UP_20K, DEEP, NF1), // UART2_RXD
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						PAD_CFG_NF(GPP_C20, UP_20K, DEEP, NF1), // UART2_RXD
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	PAD_CFG_NF(GPP_C21, UP_20K, DEEP, NF1), // UART2_TXD
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						PAD_CFG_NF(GPP_C21, UP_20K, DEEP, NF1), // UART2_TXD
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@@ -222,4 +228,6 @@ static const struct pad_config gpio_table[] = {
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	//PAD_CFG_GPO(GPP_U5, 0, DEEP), // DGPU_PWR_EN
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						//PAD_CFG_GPO(GPP_U5, 0, DEEP), // DGPU_PWR_EN
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};
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					};
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					#endif /* __ACPI__ */
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#endif /* MAINBOARD_GPIO_H */
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					#endif /* MAINBOARD_GPIO_H */
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@@ -1,5 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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					/* SPDX-License-Identifier: GPL-2.0-only */
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					#include "gpio.h"
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					#include <drivers/gfx/nvidia/gpu.h>
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#include <fsp/util.h>
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					#include <fsp/util.h>
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#include <soc/meminit.h>
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					#include <soc/meminit.h>
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#include <soc/romstage.h>
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					#include <soc/romstage.h>
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@@ -18,5 +20,20 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
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	};
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						};
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	const bool half_populated = false;
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						const bool half_populated = false;
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						const struct nvidia_gpu_config config = {
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							.power_gpio = DGPU_PWR_EN,
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							.reset_gpio = DGPU_RST_N,
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							.enable = true,
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						};
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						// Enable dGPU power
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						nvidia_set_power(&config);
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						// Set primary display to internal graphics
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						mupd->FspmConfig.PrimaryDisplay = 0;
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						// Allow memory clocks higher than 2933 MHz
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						mupd->FspmConfig.SaOcSupport = 1;
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	memcfg_init(&mupd->FspmConfig, &board_cfg, &spd_info, half_populated);
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						memcfg_init(&mupd->FspmConfig, &board_cfg, &spd_info, half_populated);
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}
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					}
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@@ -3,6 +3,7 @@ if BOARD_SYSTEM76_GAZE14 || BOARD_SYSTEM76_GAZE15
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config BOARD_SPECIFIC_OPTIONS
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					config BOARD_SPECIFIC_OPTIONS
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	def_bool y
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						def_bool y
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	select BOARD_ROMSIZE_KB_16384
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						select BOARD_ROMSIZE_KB_16384
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						select DRIVERS_GFX_NVIDIA
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			||||||
	select DRIVERS_I2C_HID
 | 
						select DRIVERS_I2C_HID
 | 
				
			||||||
	select EC_SYSTEM76_EC
 | 
						select EC_SYSTEM76_EC
 | 
				
			||||||
	select EC_SYSTEM76_EC_BAT_THRESHOLDS
 | 
						select EC_SYSTEM76_EC_BAT_THRESHOLDS
 | 
				
			||||||
 
 | 
				
			|||||||
@@ -1,5 +1,8 @@
 | 
				
			|||||||
/* SPDX-License-Identifier: GPL-2.0-only */
 | 
					/* SPDX-License-Identifier: GPL-2.0-only */
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					#include <variant/gpio.h>
 | 
				
			||||||
 | 
					#include <drivers/gfx/nvidia/acpi/gpu.asl>
 | 
				
			||||||
 | 
					
 | 
				
			||||||
#define EC_GPE_SCI 0x03 /* GPP_K3 */
 | 
					#define EC_GPE_SCI 0x03 /* GPP_K3 */
 | 
				
			||||||
#define EC_GPE_SWI 0x06 /* GPP_K6 */
 | 
					#define EC_GPE_SWI 0x06 /* GPP_K6 */
 | 
				
			||||||
#include <ec/system76/ec/acpi/ec.asl>
 | 
					#include <ec/system76/ec/acpi/ec.asl>
 | 
				
			||||||
 
 | 
				
			|||||||
@@ -57,6 +57,13 @@ chip soc/intel/cannonlake
 | 
				
			|||||||
			# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
 | 
								# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
 | 
				
			||||||
			register "PcieClkSrcUsage[8]" = "0x40"
 | 
								register "PcieClkSrcUsage[8]" = "0x40"
 | 
				
			||||||
			register "PcieClkSrcClkReq[8]" = "8"
 | 
								register "PcieClkSrcClkReq[8]" = "8"
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
								chip drivers/gfx/nvidia
 | 
				
			||||||
 | 
									device pci 00.0 on end # VGA controller
 | 
				
			||||||
 | 
									device pci 00.1 on end # Audio device
 | 
				
			||||||
 | 
									device pci 00.2 on end # USB xHCI Host controller
 | 
				
			||||||
 | 
									device pci 00.3 on end # USB Type-C UCSI controller
 | 
				
			||||||
 | 
								end
 | 
				
			||||||
		end
 | 
							end
 | 
				
			||||||
		device pci 02.0 on      # Integrated Graphics Device
 | 
							device pci 02.0 on      # Integrated Graphics Device
 | 
				
			||||||
			register "gfx" = "GMA_DEFAULT_PANEL(0)"
 | 
								register "gfx" = "GMA_DEFAULT_PANEL(0)"
 | 
				
			||||||
 
 | 
				
			|||||||
@@ -3,7 +3,15 @@
 | 
				
			|||||||
#ifndef VARIANT_GPIO_H
 | 
					#ifndef VARIANT_GPIO_H
 | 
				
			||||||
#define VARIANT_GPIO_H
 | 
					#define VARIANT_GPIO_H
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					#include <soc/gpio.h>
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					#define DGPU_RST_N	GPP_F22
 | 
				
			||||||
 | 
					#define DGPU_PWR_EN	GPP_F23
 | 
				
			||||||
 | 
					#define DGPU_GC6	GPP_K21
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					#ifndef __ACPI__
 | 
				
			||||||
void variant_configure_early_gpios(void);
 | 
					void variant_configure_early_gpios(void);
 | 
				
			||||||
void variant_configure_gpios(void);
 | 
					void variant_configure_gpios(void);
 | 
				
			||||||
 | 
					#endif
 | 
				
			||||||
 | 
					
 | 
				
			||||||
#endif
 | 
					#endif
 | 
				
			||||||
 
 | 
				
			|||||||
@@ -1,7 +1,9 @@
 | 
				
			|||||||
/* SPDX-License-Identifier: GPL-2.0-only */
 | 
					/* SPDX-License-Identifier: GPL-2.0-only */
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					#include <drivers/gfx/nvidia/gpu.h>
 | 
				
			||||||
#include <soc/cnl_memcfg_init.h>
 | 
					#include <soc/cnl_memcfg_init.h>
 | 
				
			||||||
#include <soc/romstage.h>
 | 
					#include <soc/romstage.h>
 | 
				
			||||||
 | 
					#include <variant/gpio.h>
 | 
				
			||||||
 | 
					
 | 
				
			||||||
static const struct cnl_mb_cfg memcfg = {
 | 
					static const struct cnl_mb_cfg memcfg = {
 | 
				
			||||||
	.spd[0] = {
 | 
						.spd[0] = {
 | 
				
			||||||
@@ -20,5 +22,17 @@ static const struct cnl_mb_cfg memcfg = {
 | 
				
			|||||||
 | 
					
 | 
				
			||||||
void mainboard_memory_init_params(FSPM_UPD *memupd)
 | 
					void mainboard_memory_init_params(FSPM_UPD *memupd)
 | 
				
			||||||
{
 | 
					{
 | 
				
			||||||
 | 
						const struct nvidia_gpu_config config = {
 | 
				
			||||||
 | 
							.power_gpio = DGPU_PWR_EN,
 | 
				
			||||||
 | 
							.reset_gpio = DGPU_RST_N,
 | 
				
			||||||
 | 
							.enable = true,
 | 
				
			||||||
 | 
						};
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
						// Enable dGPU power
 | 
				
			||||||
 | 
						nvidia_set_power(&config);
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
						// Set primary display to internal graphics
 | 
				
			||||||
 | 
						memupd->FspmConfig.PrimaryDisplay = 0;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
	cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
 | 
						cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
 | 
				
			||||||
}
 | 
					}
 | 
				
			||||||
 
 | 
				
			|||||||
@@ -3,6 +3,7 @@ if BOARD_SYSTEM76_GAZE16_3050 || BOARD_SYSTEM76_GAZE16_3060 || BOARD_SYSTEM76_GA
 | 
				
			|||||||
config BOARD_SPECIFIC_OPTIONS
 | 
					config BOARD_SPECIFIC_OPTIONS
 | 
				
			||||||
	def_bool y
 | 
						def_bool y
 | 
				
			||||||
	select BOARD_ROMSIZE_KB_16384
 | 
						select BOARD_ROMSIZE_KB_16384
 | 
				
			||||||
 | 
						select DRIVERS_GFX_NVIDIA
 | 
				
			||||||
	select DRIVERS_I2C_HID
 | 
						select DRIVERS_I2C_HID
 | 
				
			||||||
	select EC_SYSTEM76_EC
 | 
						select EC_SYSTEM76_EC
 | 
				
			||||||
	select EC_SYSTEM76_EC_BAT_THRESHOLDS
 | 
						select EC_SYSTEM76_EC_BAT_THRESHOLDS
 | 
				
			||||||
 
 | 
				
			|||||||
							
								
								
									
										36
									
								
								src/mainboard/system76/gaze16/acpi/dgpu.asl
									
									
									
									
									
										Normal file
									
								
							
							
						
						
									
										36
									
								
								src/mainboard/system76/gaze16/acpi/dgpu.asl
									
									
									
									
									
										Normal file
									
								
							@@ -0,0 +1,36 @@
 | 
				
			|||||||
 | 
					/* SPDX-License-Identifier: GPL-2.0-only */
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					Scope (\_SB.PCI0.PEG1)
 | 
				
			||||||
 | 
					{
 | 
				
			||||||
 | 
						Device (DEV0)
 | 
				
			||||||
 | 
						{
 | 
				
			||||||
 | 
							Name(_ADR, 0x00000000)
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
							OperationRegion (PCIC, PCI_Config, 0x00, 0x50)
 | 
				
			||||||
 | 
							Field (PCIC, DwordAcc, NoLock, Preserve)
 | 
				
			||||||
 | 
							{
 | 
				
			||||||
 | 
								Offset (0x40),
 | 
				
			||||||
 | 
								SSID, 32
 | 
				
			||||||
 | 
							}
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
							Name (_PR0, Package () { PWRR })
 | 
				
			||||||
 | 
							Name (_PR3, Package () { PWRR })
 | 
				
			||||||
 | 
							PowerResource (PWRR, 0, 0)
 | 
				
			||||||
 | 
							{
 | 
				
			||||||
 | 
								Name (_STA, 1)
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
								Method (_ON)
 | 
				
			||||||
 | 
								{
 | 
				
			||||||
 | 
									^^SSID = 0x40181558
 | 
				
			||||||
 | 
									Printf("GPU _ON %o", ToHexString(^^SSID))
 | 
				
			||||||
 | 
									_STA = 1
 | 
				
			||||||
 | 
								}
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
								Method (_OFF)
 | 
				
			||||||
 | 
								{
 | 
				
			||||||
 | 
									Printf("GPU _OFF %o", ToHexString(^^SSID))
 | 
				
			||||||
 | 
									_STA = 0
 | 
				
			||||||
 | 
								}
 | 
				
			||||||
 | 
							}
 | 
				
			||||||
 | 
						}
 | 
				
			||||||
 | 
					}
 | 
				
			||||||
@@ -1,5 +1,7 @@
 | 
				
			|||||||
/* SPDX-License-Identifier: GPL-2.0-only */
 | 
					/* SPDX-License-Identifier: GPL-2.0-only */
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					#include "dgpu.asl"
 | 
				
			||||||
 | 
					
 | 
				
			||||||
#define EC_GPE_SCI 0x6E
 | 
					#define EC_GPE_SCI 0x6E
 | 
				
			||||||
#define EC_GPE_SWI 0x6B
 | 
					#define EC_GPE_SWI 0x6B
 | 
				
			||||||
#include <ec/system76/ec/acpi/ec.asl>
 | 
					#include <ec/system76/ec/acpi/ec.asl>
 | 
				
			||||||
 
 | 
				
			|||||||
@@ -1,8 +1,10 @@
 | 
				
			|||||||
/* SPDX-License-Identifier: GPL-2.0-only */
 | 
					/* SPDX-License-Identifier: GPL-2.0-only */
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					#include <drivers/gfx/nvidia/gpu.h>
 | 
				
			||||||
#include <fsp/util.h>
 | 
					#include <fsp/util.h>
 | 
				
			||||||
#include <soc/meminit.h>
 | 
					#include <soc/meminit.h>
 | 
				
			||||||
#include <soc/romstage.h>
 | 
					#include <soc/romstage.h>
 | 
				
			||||||
 | 
					#include <variant/gpio.h>
 | 
				
			||||||
#include "variant.h"
 | 
					#include "variant.h"
 | 
				
			||||||
 | 
					
 | 
				
			||||||
static const struct mb_cfg board_cfg = {
 | 
					static const struct mb_cfg board_cfg = {
 | 
				
			||||||
@@ -22,9 +24,21 @@ static const struct mem_spd spd_info = {
 | 
				
			|||||||
 | 
					
 | 
				
			||||||
void mainboard_memory_init_params(FSPM_UPD *mupd)
 | 
					void mainboard_memory_init_params(FSPM_UPD *mupd)
 | 
				
			||||||
{
 | 
					{
 | 
				
			||||||
 | 
						const bool half_populated = false;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
						const struct nvidia_gpu_config config = {
 | 
				
			||||||
 | 
							.power_gpio = DGPU_PWR_EN,
 | 
				
			||||||
 | 
							.reset_gpio = DGPU_RST_N,
 | 
				
			||||||
 | 
							.enable = true,
 | 
				
			||||||
 | 
						};
 | 
				
			||||||
 | 
					
 | 
				
			||||||
	variant_memory_init_params(mupd);
 | 
						variant_memory_init_params(mupd);
 | 
				
			||||||
 | 
					
 | 
				
			||||||
	const bool half_populated = false;
 | 
						// Enable dGPU power
 | 
				
			||||||
 | 
						nvidia_set_power(&config);
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
						// Set primary display to internal graphics
 | 
				
			||||||
 | 
						mupd->FspmConfig.PrimaryDisplay = 0;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
	memcfg_init(&mupd->FspmConfig, &board_cfg, &spd_info, half_populated);
 | 
						memcfg_init(&mupd->FspmConfig, &board_cfg, &spd_info, half_populated);
 | 
				
			||||||
}
 | 
					}
 | 
				
			||||||
 
 | 
				
			|||||||
@@ -5,6 +5,12 @@
 | 
				
			|||||||
 | 
					
 | 
				
			||||||
#include <soc/gpio.h>
 | 
					#include <soc/gpio.h>
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					#define DGPU_RST_N	GPP_F8
 | 
				
			||||||
 | 
					#define DGPU_PWR_EN	GPP_F9
 | 
				
			||||||
 | 
					#define DGPU_GC6	GPP_K11
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					#ifndef __ACPI__
 | 
				
			||||||
 | 
					
 | 
				
			||||||
static const struct pad_config early_gpio_table[] = {
 | 
					static const struct pad_config early_gpio_table[] = {
 | 
				
			||||||
	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
 | 
						PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
 | 
				
			||||||
	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
 | 
						PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
 | 
				
			||||||
@@ -285,4 +291,6 @@ static const struct pad_config gpio_table[] = {
 | 
				
			|||||||
	PAD_CFG_GPI(GPP_S7, NONE, DEEP), // DMIC_DAT_PCH
 | 
						PAD_CFG_GPI(GPP_S7, NONE, DEEP), // DMIC_DAT_PCH
 | 
				
			||||||
};
 | 
					};
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					#endif /* __ACPI__ */
 | 
				
			||||||
 | 
					
 | 
				
			||||||
#endif /* VARIANT_GPIO_H */
 | 
					#endif /* VARIANT_GPIO_H */
 | 
				
			||||||
 
 | 
				
			|||||||
@@ -17,6 +17,13 @@ chip soc/intel/tigerlake
 | 
				
			|||||||
				register "srcclk_pin" = "-1" # GFX_CLKREQ0#
 | 
									register "srcclk_pin" = "-1" # GFX_CLKREQ0#
 | 
				
			||||||
				device generic 0 on end
 | 
									device generic 0 on end
 | 
				
			||||||
			end
 | 
								end
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
								chip drivers/gfx/nvidia
 | 
				
			||||||
 | 
									device pci 00.0 on end # VGA controller
 | 
				
			||||||
 | 
									device pci 00.1 on end # Audio device
 | 
				
			||||||
 | 
									device pci 00.2 on end # USB xHCI Host controller
 | 
				
			||||||
 | 
									device pci 00.3 on end # USB Type-C UCSI controller
 | 
				
			||||||
 | 
								end
 | 
				
			||||||
		end
 | 
							end
 | 
				
			||||||
		device ref peg0 on
 | 
							device ref peg0 on
 | 
				
			||||||
			# PCIe PEG0 x4, Clock 4 (SSD2)
 | 
								# PCIe PEG0 x4, Clock 4 (SSD2)
 | 
				
			||||||
 
 | 
				
			|||||||
@@ -5,6 +5,12 @@
 | 
				
			|||||||
 | 
					
 | 
				
			||||||
#include <soc/gpio.h>
 | 
					#include <soc/gpio.h>
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					#define DGPU_RST_N	GPP_F8
 | 
				
			||||||
 | 
					#define DGPU_PWR_EN	GPP_F9
 | 
				
			||||||
 | 
					#define DGPU_GC6	GPP_K11
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					#ifndef __ACPI__
 | 
				
			||||||
 | 
					
 | 
				
			||||||
static const struct pad_config early_gpio_table[] = {
 | 
					static const struct pad_config early_gpio_table[] = {
 | 
				
			||||||
	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
 | 
						PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
 | 
				
			||||||
	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
 | 
						PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
 | 
				
			||||||
@@ -285,4 +291,6 @@ static const struct pad_config gpio_table[] = {
 | 
				
			|||||||
	PAD_CFG_GPI(GPP_S7, NONE, DEEP), // MIC_DATA_PCH
 | 
						PAD_CFG_GPI(GPP_S7, NONE, DEEP), // MIC_DATA_PCH
 | 
				
			||||||
};
 | 
					};
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					#endif /* __ACPI__ */
 | 
				
			||||||
 | 
					
 | 
				
			||||||
#endif /* VARIANT_GPIO_H */
 | 
					#endif /* VARIANT_GPIO_H */
 | 
				
			||||||
 
 | 
				
			|||||||
@@ -17,6 +17,13 @@ chip soc/intel/tigerlake
 | 
				
			|||||||
				register "srcclk_pin" = "-1" # PEG_CLKREQ#
 | 
									register "srcclk_pin" = "-1" # PEG_CLKREQ#
 | 
				
			||||||
				device generic 0 on end
 | 
									device generic 0 on end
 | 
				
			||||||
			end
 | 
								end
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
								chip drivers/gfx/nvidia
 | 
				
			||||||
 | 
									device pci 00.0 on end # VGA controller
 | 
				
			||||||
 | 
									device pci 00.1 on end # Audio device
 | 
				
			||||||
 | 
									device pci 00.2 on end # USB xHCI Host controller
 | 
				
			||||||
 | 
									device pci 00.3 on end # USB Type-C UCSI controller
 | 
				
			||||||
 | 
								end
 | 
				
			||||||
		end
 | 
							end
 | 
				
			||||||
		device ref peg0 on
 | 
							device ref peg0 on
 | 
				
			||||||
			# PCIe PEG0 x4, Clock 7 (SSD1)
 | 
								# PCIe PEG0 x4, Clock 7 (SSD1)
 | 
				
			||||||
 
 | 
				
			|||||||
@@ -3,6 +3,7 @@ if BOARD_SYSTEM76_ORYP5
 | 
				
			|||||||
config BOARD_SPECIFIC_OPTIONS
 | 
					config BOARD_SPECIFIC_OPTIONS
 | 
				
			||||||
	def_bool y
 | 
						def_bool y
 | 
				
			||||||
	select BOARD_ROMSIZE_KB_16384
 | 
						select BOARD_ROMSIZE_KB_16384
 | 
				
			||||||
 | 
						select DRIVERS_GFX_NVIDIA
 | 
				
			||||||
	select DRIVERS_I2C_HID
 | 
						select DRIVERS_I2C_HID
 | 
				
			||||||
	select DRIVERS_I2C_TAS5825M
 | 
						select DRIVERS_I2C_TAS5825M
 | 
				
			||||||
	select EC_SYSTEM76_EC
 | 
						select EC_SYSTEM76_EC
 | 
				
			||||||
 
 | 
				
			|||||||
@@ -1,5 +1,8 @@
 | 
				
			|||||||
/* SPDX-License-Identifier: GPL-2.0-only */
 | 
					/* SPDX-License-Identifier: GPL-2.0-only */
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					#include <mainboard/gpio.h>
 | 
				
			||||||
 | 
					#include <drivers/gfx/nvidia/acpi/gpu.asl>
 | 
				
			||||||
 | 
					
 | 
				
			||||||
#define EC_GPE_SCI 0x17 /* GPP_B23 */
 | 
					#define EC_GPE_SCI 0x17 /* GPP_B23 */
 | 
				
			||||||
#define EC_GPE_SWI 0x26 /* GPP_G6 */
 | 
					#define EC_GPE_SWI 0x26 /* GPP_G6 */
 | 
				
			||||||
#include <ec/system76/ec/acpi/ec.asl>
 | 
					#include <ec/system76/ec/acpi/ec.asl>
 | 
				
			||||||
 
 | 
				
			|||||||
@@ -65,6 +65,13 @@ chip soc/intel/cannonlake
 | 
				
			|||||||
			# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
 | 
								# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
 | 
				
			||||||
			register "PcieClkSrcUsage[8]" = "0x40"
 | 
								register "PcieClkSrcUsage[8]" = "0x40"
 | 
				
			||||||
			register "PcieClkSrcClkReq[8]" = "8"
 | 
								register "PcieClkSrcClkReq[8]" = "8"
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
								chip drivers/gfx/nvidia
 | 
				
			||||||
 | 
									device pci 00.0 on end # VGA controller
 | 
				
			||||||
 | 
									device pci 00.1 on end # Audio device
 | 
				
			||||||
 | 
									device pci 00.2 on end # USB xHCI Host controller
 | 
				
			||||||
 | 
									device pci 00.3 on end # USB Type-C UCSI controller
 | 
				
			||||||
 | 
								end
 | 
				
			||||||
		end
 | 
							end
 | 
				
			||||||
		device pci 02.0 on      # Integrated Graphics Device
 | 
							device pci 02.0 on      # Integrated Graphics Device
 | 
				
			||||||
			register "gfx" = "GMA_DEFAULT_PANEL(0)"
 | 
								register "gfx" = "GMA_DEFAULT_PANEL(0)"
 | 
				
			||||||
 
 | 
				
			|||||||
@@ -3,7 +3,15 @@
 | 
				
			|||||||
#ifndef MAINBOARD_GPIO_H
 | 
					#ifndef MAINBOARD_GPIO_H
 | 
				
			||||||
#define MAINBOARD_GPIO_H
 | 
					#define MAINBOARD_GPIO_H
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					#include <soc/gpio.h>
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					#define DGPU_RST_N	GPP_F22
 | 
				
			||||||
 | 
					#define DGPU_PWR_EN	GPP_F23
 | 
				
			||||||
 | 
					#define DGPU_GC6	GPP_C12
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					#ifndef __ACPI__
 | 
				
			||||||
void mainboard_configure_early_gpios(void);
 | 
					void mainboard_configure_early_gpios(void);
 | 
				
			||||||
void mainboard_configure_gpios(void);
 | 
					void mainboard_configure_gpios(void);
 | 
				
			||||||
 | 
					#endif
 | 
				
			||||||
 | 
					
 | 
				
			||||||
#endif
 | 
					#endif
 | 
				
			||||||
 
 | 
				
			|||||||
@@ -1,5 +1,7 @@
 | 
				
			|||||||
/* SPDX-License-Identifier: GPL-2.0-only */
 | 
					/* SPDX-License-Identifier: GPL-2.0-only */
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					#include <drivers/gfx/nvidia/gpu.h>
 | 
				
			||||||
 | 
					#include <mainboard/gpio.h>
 | 
				
			||||||
#include <soc/cnl_memcfg_init.h>
 | 
					#include <soc/cnl_memcfg_init.h>
 | 
				
			||||||
#include <soc/romstage.h>
 | 
					#include <soc/romstage.h>
 | 
				
			||||||
 | 
					
 | 
				
			||||||
@@ -20,6 +22,18 @@ static const struct cnl_mb_cfg memcfg = {
 | 
				
			|||||||
 | 
					
 | 
				
			||||||
void mainboard_memory_init_params(FSPM_UPD *memupd)
 | 
					void mainboard_memory_init_params(FSPM_UPD *memupd)
 | 
				
			||||||
{
 | 
					{
 | 
				
			||||||
 | 
						const struct nvidia_gpu_config config = {
 | 
				
			||||||
 | 
							.power_gpio = DGPU_PWR_EN,
 | 
				
			||||||
 | 
							.reset_gpio = DGPU_RST_N,
 | 
				
			||||||
 | 
							.enable = true,
 | 
				
			||||||
 | 
						};
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
						// Enable dGPU power
 | 
				
			||||||
 | 
						nvidia_set_power(&config);
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
						// Set primary display to internal graphics
 | 
				
			||||||
 | 
						memupd->FspmConfig.PrimaryDisplay = 0;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
	// Allow memory speeds higher than 2666 MT/s
 | 
						// Allow memory speeds higher than 2666 MT/s
 | 
				
			||||||
	memupd->FspmConfig.SaOcSupport = 1;
 | 
						memupd->FspmConfig.SaOcSupport = 1;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 
 | 
				
			|||||||
@@ -3,6 +3,7 @@ if BOARD_SYSTEM76_ORYP6 || BOARD_SYSTEM76_ORYP7
 | 
				
			|||||||
config BOARD_SPECIFIC_OPTIONS
 | 
					config BOARD_SPECIFIC_OPTIONS
 | 
				
			||||||
	def_bool y
 | 
						def_bool y
 | 
				
			||||||
	select BOARD_ROMSIZE_KB_16384
 | 
						select BOARD_ROMSIZE_KB_16384
 | 
				
			||||||
 | 
						select DRIVERS_GFX_NVIDIA
 | 
				
			||||||
	select DRIVERS_I2C_HID
 | 
						select DRIVERS_I2C_HID
 | 
				
			||||||
	select DRIVERS_I2C_TAS5825M
 | 
						select DRIVERS_I2C_TAS5825M
 | 
				
			||||||
	select EC_SYSTEM76_EC
 | 
						select EC_SYSTEM76_EC
 | 
				
			||||||
 
 | 
				
			|||||||
@@ -1,4 +1,5 @@
 | 
				
			|||||||
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
 | 
					CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
 | 
				
			||||||
 | 
					CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
 | 
				
			||||||
 | 
					
 | 
				
			||||||
bootblock-y += bootblock.c
 | 
					bootblock-y += bootblock.c
 | 
				
			||||||
bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c
 | 
					bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c
 | 
				
			||||||
 
 | 
				
			|||||||
@@ -1,5 +1,8 @@
 | 
				
			|||||||
/* SPDX-License-Identifier: GPL-2.0-only */
 | 
					/* SPDX-License-Identifier: GPL-2.0-only */
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					#include <variant/dgpu.h>
 | 
				
			||||||
 | 
					#include <drivers/gfx/nvidia/acpi/gpu.asl>
 | 
				
			||||||
 | 
					
 | 
				
			||||||
#define EC_GPE_SCI 0x03 /* GPP_K3 */
 | 
					#define EC_GPE_SCI 0x03 /* GPP_K3 */
 | 
				
			||||||
#define EC_GPE_SWI 0x06 /* GPP_K6 */
 | 
					#define EC_GPE_SWI 0x06 /* GPP_K6 */
 | 
				
			||||||
#include <ec/system76/ec/acpi/ec.asl>
 | 
					#include <ec/system76/ec/acpi/ec.asl>
 | 
				
			||||||
 
 | 
				
			|||||||
@@ -62,6 +62,13 @@ chip soc/intel/cannonlake
 | 
				
			|||||||
			# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
 | 
								# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
 | 
				
			||||||
			register "PcieClkSrcUsage[8]" = "0x40"
 | 
								register "PcieClkSrcUsage[8]" = "0x40"
 | 
				
			||||||
			register "PcieClkSrcClkReq[8]" = "8"
 | 
								register "PcieClkSrcClkReq[8]" = "8"
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
								chip drivers/gfx/nvidia
 | 
				
			||||||
 | 
									device pci 00.0 on end # VGA controller
 | 
				
			||||||
 | 
									device pci 00.1 on end # Audio device
 | 
				
			||||||
 | 
									device pci 00.2 on end # USB xHCI Host controller
 | 
				
			||||||
 | 
									device pci 00.3 on end # USB Type-C UCSI controller
 | 
				
			||||||
 | 
								end
 | 
				
			||||||
		end
 | 
							end
 | 
				
			||||||
		device pci 02.0 on      # Integrated Graphics Device
 | 
							device pci 02.0 on      # Integrated Graphics Device
 | 
				
			||||||
			register "gfx" = "GMA_DEFAULT_PANEL(0)"
 | 
								register "gfx" = "GMA_DEFAULT_PANEL(0)"
 | 
				
			||||||
 
 | 
				
			|||||||
@@ -1,7 +1,9 @@
 | 
				
			|||||||
/* SPDX-License-Identifier: GPL-2.0-only */
 | 
					/* SPDX-License-Identifier: GPL-2.0-only */
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					#include <drivers/gfx/nvidia/gpu.h>
 | 
				
			||||||
#include <soc/cnl_memcfg_init.h>
 | 
					#include <soc/cnl_memcfg_init.h>
 | 
				
			||||||
#include <soc/romstage.h>
 | 
					#include <soc/romstage.h>
 | 
				
			||||||
 | 
					#include <variant/dgpu.h>
 | 
				
			||||||
#include <variant/romstage.h>
 | 
					#include <variant/romstage.h>
 | 
				
			||||||
 | 
					
 | 
				
			||||||
static const struct cnl_mb_cfg memcfg = {
 | 
					static const struct cnl_mb_cfg memcfg = {
 | 
				
			||||||
@@ -21,6 +23,18 @@ static const struct cnl_mb_cfg memcfg = {
 | 
				
			|||||||
 | 
					
 | 
				
			||||||
void mainboard_memory_init_params(FSPM_UPD *memupd)
 | 
					void mainboard_memory_init_params(FSPM_UPD *memupd)
 | 
				
			||||||
{
 | 
					{
 | 
				
			||||||
 | 
						const struct nvidia_gpu_config config = {
 | 
				
			||||||
 | 
							.power_gpio = DGPU_PWR_EN,
 | 
				
			||||||
 | 
							.reset_gpio = DGPU_RST_N,
 | 
				
			||||||
 | 
							.enable = true,
 | 
				
			||||||
 | 
						};
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
						// Enable dGPU power
 | 
				
			||||||
 | 
						nvidia_set_power(&config);
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
						// Set primary display to internal graphics
 | 
				
			||||||
 | 
						memupd->FspmConfig.PrimaryDisplay = 0;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
	variant_configure_fspm(memupd);
 | 
						variant_configure_fspm(memupd);
 | 
				
			||||||
 | 
					
 | 
				
			||||||
	cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
 | 
						cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
 | 
				
			||||||
 
 | 
				
			|||||||
@@ -0,0 +1,12 @@
 | 
				
			|||||||
 | 
					/* SPDX-License-Identifier: GPL-2.0-only */
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					#ifndef VARIANT_DGPU_H
 | 
				
			||||||
 | 
					#define VARIANT_DGPU_H
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					#include <soc/gpio.h>
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					#define DGPU_RST_N	GPP_F22
 | 
				
			||||||
 | 
					#define DGPU_PWR_EN	GPP_F23
 | 
				
			||||||
 | 
					#define DGPU_GC6	GPP_K21
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					#endif
 | 
				
			||||||
@@ -0,0 +1,12 @@
 | 
				
			|||||||
 | 
					/* SPDX-License-Identifier: GPL-2.0-only */
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					#ifndef VARIANT_DGPU_H
 | 
				
			||||||
 | 
					#define VARIANT_DGPU_H
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					#include <soc/gpio.h>
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					#define DGPU_RST_N	GPP_F22
 | 
				
			||||||
 | 
					#define DGPU_PWR_EN	GPP_F23
 | 
				
			||||||
 | 
					#define DGPU_GC6	GPP_K21
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					#endif
 | 
				
			||||||
@@ -3,6 +3,7 @@ if BOARD_SYSTEM76_ORYP8
 | 
				
			|||||||
config BOARD_SPECIFIC_OPTIONS
 | 
					config BOARD_SPECIFIC_OPTIONS
 | 
				
			||||||
	def_bool y
 | 
						def_bool y
 | 
				
			||||||
	select BOARD_ROMSIZE_KB_16384
 | 
						select BOARD_ROMSIZE_KB_16384
 | 
				
			||||||
 | 
						select DRIVERS_GFX_NVIDIA
 | 
				
			||||||
	select DRIVERS_I2C_HID
 | 
						select DRIVERS_I2C_HID
 | 
				
			||||||
	select DRIVERS_I2C_TAS5825M
 | 
						select DRIVERS_I2C_TAS5825M
 | 
				
			||||||
	select EC_SYSTEM76_EC
 | 
						select EC_SYSTEM76_EC
 | 
				
			||||||
 
 | 
				
			|||||||
							
								
								
									
										36
									
								
								src/mainboard/system76/oryp8/acpi/dgpu.asl
									
									
									
									
									
										Normal file
									
								
							
							
						
						
									
										36
									
								
								src/mainboard/system76/oryp8/acpi/dgpu.asl
									
									
									
									
									
										Normal file
									
								
							@@ -0,0 +1,36 @@
 | 
				
			|||||||
 | 
					/* SPDX-License-Identifier: GPL-2.0-only */
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					Scope (\_SB.PCI0.PEG1)
 | 
				
			||||||
 | 
					{
 | 
				
			||||||
 | 
						Device (DEV0)
 | 
				
			||||||
 | 
						{
 | 
				
			||||||
 | 
							Name(_ADR, 0x00000000)
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
							OperationRegion (PCIC, PCI_Config, 0x00, 0x50)
 | 
				
			||||||
 | 
							Field (PCIC, DwordAcc, NoLock, Preserve)
 | 
				
			||||||
 | 
							{
 | 
				
			||||||
 | 
								Offset (0x40),
 | 
				
			||||||
 | 
								SSID, 32
 | 
				
			||||||
 | 
							}
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
							Name (_PR0, Package () { PWRR })
 | 
				
			||||||
 | 
							Name (_PR3, Package () { PWRR })
 | 
				
			||||||
 | 
							PowerResource (PWRR, 0, 0)
 | 
				
			||||||
 | 
							{
 | 
				
			||||||
 | 
								Name (_STA, 1)
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
								Method (_ON)
 | 
				
			||||||
 | 
								{
 | 
				
			||||||
 | 
									^^SSID = 0x40181558
 | 
				
			||||||
 | 
									Printf("GPU _ON %o", ToHexString(^^SSID))
 | 
				
			||||||
 | 
									_STA = 1
 | 
				
			||||||
 | 
								}
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
								Method (_OFF)
 | 
				
			||||||
 | 
								{
 | 
				
			||||||
 | 
									Printf("GPU _OFF %o", ToHexString(^^SSID))
 | 
				
			||||||
 | 
									_STA = 0
 | 
				
			||||||
 | 
								}
 | 
				
			||||||
 | 
							}
 | 
				
			||||||
 | 
						}
 | 
				
			||||||
 | 
					}
 | 
				
			||||||
@@ -1,5 +1,7 @@
 | 
				
			|||||||
/* SPDX-License-Identifier: GPL-2.0-only */
 | 
					/* SPDX-License-Identifier: GPL-2.0-only */
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					#include "dgpu.asl"
 | 
				
			||||||
 | 
					
 | 
				
			||||||
#define EC_GPE_SCI 0x6E
 | 
					#define EC_GPE_SCI 0x6E
 | 
				
			||||||
#define EC_GPE_SWI 0x6B
 | 
					#define EC_GPE_SWI 0x6B
 | 
				
			||||||
#include <ec/system76/ec/acpi/ec.asl>
 | 
					#include <ec/system76/ec/acpi/ec.asl>
 | 
				
			||||||
 
 | 
				
			|||||||
@@ -103,6 +103,13 @@ chip soc/intel/tigerlake
 | 
				
			|||||||
				register "srcclk_pin" = "-1" # PEG_CLKREQ#
 | 
									register "srcclk_pin" = "-1" # PEG_CLKREQ#
 | 
				
			||||||
				device generic 0 on end
 | 
									device generic 0 on end
 | 
				
			||||||
			end
 | 
								end
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
								chip drivers/gfx/nvidia
 | 
				
			||||||
 | 
									device pci 00.0 on end # VGA controller
 | 
				
			||||||
 | 
									device pci 00.1 on end # Audio device
 | 
				
			||||||
 | 
									device pci 00.2 on end # USB xHCI Host controller
 | 
				
			||||||
 | 
									device pci 00.3 on end # USB Type-C UCSI controller
 | 
				
			||||||
 | 
								end
 | 
				
			||||||
		end
 | 
							end
 | 
				
			||||||
		device ref igpu on
 | 
							device ref igpu on
 | 
				
			||||||
			# DDIA is eDP
 | 
								# DDIA is eDP
 | 
				
			||||||
 
 | 
				
			|||||||
@@ -3,7 +3,15 @@
 | 
				
			|||||||
#ifndef MAINBOARD_GPIO_H
 | 
					#ifndef MAINBOARD_GPIO_H
 | 
				
			||||||
#define MAINBOARD_GPIO_H
 | 
					#define MAINBOARD_GPIO_H
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					#include <soc/gpio.h>
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					#define DGPU_RST_N	GPP_F8
 | 
				
			||||||
 | 
					#define DGPU_PWR_EN	GPP_F9
 | 
				
			||||||
 | 
					#define DGPU_GC6	GPP_K11
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					#ifndef __ACPI__
 | 
				
			||||||
void mainboard_configure_early_gpios(void);
 | 
					void mainboard_configure_early_gpios(void);
 | 
				
			||||||
void mainboard_configure_gpios(void);
 | 
					void mainboard_configure_gpios(void);
 | 
				
			||||||
 | 
					#endif
 | 
				
			||||||
 | 
					
 | 
				
			||||||
#endif
 | 
					#endif
 | 
				
			||||||
 
 | 
				
			|||||||
@@ -1,5 +1,7 @@
 | 
				
			|||||||
/* SPDX-License-Identifier: GPL-2.0-only */
 | 
					/* SPDX-License-Identifier: GPL-2.0-only */
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					#include <drivers/gfx/nvidia/gpu.h>
 | 
				
			||||||
 | 
					#include <mainboard/gpio.h>
 | 
				
			||||||
#include <fsp/util.h>
 | 
					#include <fsp/util.h>
 | 
				
			||||||
#include <soc/meminit.h>
 | 
					#include <soc/meminit.h>
 | 
				
			||||||
#include <soc/romstage.h>
 | 
					#include <soc/romstage.h>
 | 
				
			||||||
@@ -23,6 +25,18 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 | 
				
			|||||||
{
 | 
					{
 | 
				
			||||||
	const bool half_populated = false;
 | 
						const bool half_populated = false;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
						const struct nvidia_gpu_config config = {
 | 
				
			||||||
 | 
							.power_gpio = DGPU_PWR_EN,
 | 
				
			||||||
 | 
							.reset_gpio = DGPU_RST_N,
 | 
				
			||||||
 | 
							.enable = true,
 | 
				
			||||||
 | 
						};
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
						// Enable dGPU power
 | 
				
			||||||
 | 
						nvidia_set_power(&config);
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
						// Set primary display to internal graphics
 | 
				
			||||||
 | 
						mupd->FspmConfig.PrimaryDisplay = 0;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
	// Enable M.2 PCIE 4.0 and PEG1
 | 
						// Enable M.2 PCIE 4.0 and PEG1
 | 
				
			||||||
	mupd->FspmConfig.CpuPcieRpEnableMask = 0x3;
 | 
						mupd->FspmConfig.CpuPcieRpEnableMask = 0x3;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 
 | 
				
			|||||||
		Reference in New Issue
	
	Block a user