mainboard/google/reef: handle eMMC power signal polarity change
The EVT board uses an active high power control signal while the previous board used an active low signal. Update the tables to reflect the differences. BUG=chrome-os-partner:55470 Change-Id: I198c0e4e019fcffe2cf748d382351ac965a81077 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15763 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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@@ -156,7 +156,6 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_NF(PMU_SLP_S3_B, NONE, DEEP, NF1), /* PMU_SLP_S3_N */
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PAD_CFG_NF(PMU_SLP_S4_B, NONE, DEEP, NF1), /* PMU_SLP_S4_N */
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PAD_CFG_NF(PMU_SUSCLK, NONE, DEEP, NF1), /* PMU_SUSCLK */
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PAD_CFG_GPO(PMU_WAKE_B, 0, DEEP), /* EMMC_PWR_EN_N */
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PAD_CFG_NF(SUS_STAT_B, NONE, DEEP, NF1), /* SUS_STAT_N */
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PAD_CFG_NF(SUSPWRDNACK, NONE, DEEP, NF1), /* SUSPWRDNACK */
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@@ -357,6 +356,7 @@ static const struct pad_config proto_diff_table[] = {
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PAD_CFG_GPI(GPIO_3, UP_20K, DEEP), /* unused */
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PAD_CFG_GPI(GPIO_15, UP_20K, DEEP), /* unused */
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PAD_CFG_NF(GPIO_44, NATIVE, DEEP, NF1), /* LPSS_UART1_RTS */
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PAD_CFG_GPO(PMU_WAKE_B, 0, DEEP), /* EN_PP3300_EMMC_ODL */
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};
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/* Wake peripheral signals post proto. */
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@@ -364,6 +364,7 @@ static const struct pad_config nonproto_diff_table[] = {
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PAD_CFG_GPI_SCI_LOW(GPIO_3, UP_20K, DEEP, LEVEL), /* FP_INT_L */
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PAD_CFG_GPI_SCI_LOW(GPIO_15, NONE, DEEP, EDGE_SINGLE), /* TRACKPAD_INT_1V8_ODL */
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PAD_CFG_GPO(GPIO_44, 1, DEEP), /* GPS_RST_ODL */
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PAD_CFG_GPO(PMU_WAKE_B, 1, DEEP), /* EN_PP3300_EMMC */
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};
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#endif /* __ACPI__ */
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