fmap: Make FMAP_CACHE mandatory if it is configured in

Now that we have a CONFIG_NO_FMAP_CACHE to completely configure out the
pre-RAM FMAP cache code, there's no point in allowing the region to be
optional anymore. This patch makes the section required by the linker.
If a board doesn't want to provide it, it has to select NO_FMAP_CACHE.

Adding FMAP_CACHE regions to a couple more targets that I think can use
them but I don't know anything about... please yell if one of these is
a bad idea and I should mark them NO_FMAP_CACHE instead.

Change-Id: Ic7d47772ab3abfa7e3a66815c3739d0af071abc2
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/cpu/ti/am335x/memlayout.ld

@@ -19,7 +19,8 @@ SECTIONS
 {
 	DRAM_START(0x40000000)
 	BOOTBLOCK(0x402f0400, 20K)
-	ROMSTAGE(0x402f5400, 90K)
+	ROMSTAGE(0x402f5400, 88K)
+	FMAP_CACHE(0x4030b400, 2K)
 	STACK(0x4030be00, 4K)
 	RAMSTAGE(0x80200000, 192K)
 

src/include/memlayout.h

@@ -78,7 +78,7 @@
 
 #define FMAP_CACHE(addr, sz) \
 	REGION(fmap_cache, addr, sz, 4) \
-	_ = ASSERT(sz == 0 || sz >= FMAP_SIZE, \
+	_ = ASSERT(sz >= FMAP_SIZE, \
 		   STR(FMAP does not fit in FMAP_CACHE! (sz < FMAP_SIZE)));
 
 #if ENV_ROMSTAGE_OR_BEFORE

src/lib/fmap.c

@@ -36,8 +36,6 @@ static struct mem_region_device fmap_cache;
 			printk(__VA_ARGS__); \
 	} while (0)
 
-DECLARE_OPTIONAL_REGION(fmap_cache);
-
 uint64_t get_fmap_flash_offset(void)
 {
 	return FMAP_OFFSET;
@@ -71,14 +69,6 @@ static void setup_preram_cache(struct mem_region_device *cache_mrdev)
 		return;
 	}
 
-	if (REGION_SIZE(fmap_cache) == 0) {
-		/* If you see this you should add FMAP_CACHE() to your memlayout
-		   (or select NO_FMAP_CACHE if you can't afford the 2K). */
-		print_once(BIOS_ERR,
-			"ERROR: FMAP_CACHE enabled but no region provided!\n");
-		return;
-	}
-
 	struct fmap *fmap = (struct fmap *)_fmap_cache;
 	if (!ENV_BOOTBLOCK) {
 		/* NOTE: This assumes that for all platforms running this code,

src/mainboard/emulation/qemu-aarch64/memlayout.ld

@@ -24,7 +24,8 @@ SECTIONS
 
 	DRAM_START(0x40000000)
 	BOOTBLOCK(0x60010000, 64K)
-	STACK(0x60020000, 64K)
+	STACK(0x60020000, 62K)
+	FMAP_CACHE(0x6002F800, 2K)
 	ROMSTAGE(0x60030000, 128K)
 	RAMSTAGE(0x60070000, 16M)
 

src/mainboard/emulation/qemu-armv7/memlayout.ld

@@ -42,6 +42,7 @@ SECTIONS
 	/* TODO: does this thing emulate SRAM? */
 
 	BOOTBLOCK(0x00000, 64K)
+	FMAP_CACHE(0x10000, 2K)
 
 	DRAM_START(0x60000000)
 	STACK(0x60000000, 64K)

src/mainboard/emulation/qemu-power8/memlayout.ld

@@ -26,5 +26,6 @@ SECTIONS
 	ROMSTAGE(0x20000, 128K)
 	STACK(0x40000, 0x3ff00)
 	PRERAM_CBMEM_CONSOLE(0x80000, 8K)
+	FMAP_CACHE(0x82000, 2K)
 	RAMSTAGE(0x100000, 16M)
 }

src/mainboard/emulation/qemu-riscv/memlayout.ld

@@ -37,6 +37,7 @@ SECTIONS
 	REGION(opensbi, STAGES_START, 128K, 4K)
 #endif
 	PRERAM_CBMEM_CONSOLE(STAGES_START + 128K, 8K)
+	FMAP_CACHE(STAGES_START + 136K, 2K)
 	RAMSTAGE(STAGES_START + 200K, 16M)
 	STACK(STAGES_START + 200K + 16M, 4K)
 }

src/mainboard/emulation/spike-riscv/memlayout.ld

@@ -24,7 +24,8 @@ SECTIONS
 	DRAM_START(START)
 	BOOTBLOCK(START, 64K)
 	STACK(START + 8M, 4K)
-	/* hole at (START + 8M + 4K, 60K) */
+	FMAP_CACHE(START + 8M + 4K, 2K)
+	/* hole at (START + 8M + 6K, 58K) */
 	ROMSTAGE(START + 8M + 64K, 128K)
 	PRERAM_CBMEM_CONSOLE(START + 8M + 192k, 8K)
 	RAMSTAGE(START + 8M + 200K, 256K)

src/soc/cavium/cn81xx/include/soc/memlayout.ld

@@ -31,7 +31,8 @@ SECTIONS
 
 	STACK(BOOTROM_OFFSET, 16K)
 	TIMESTAMP(BOOTROM_OFFSET + 0x4000, 4K)
-	PRERAM_CBFS_CACHE(BOOTROM_OFFSET + 0x6000, 8K)
+	PRERAM_CBFS_CACHE(BOOTROM_OFFSET + 0x6000, 6K)
+	FMAP_CACHE(BOOTROM_OFFSET + 0x7800, 2K)
 	PRERAM_CBMEM_CONSOLE(BOOTROM_OFFSET + 0x8000, 8K)
 	BOOTBLOCK(BOOTROM_OFFSET + 0x20000, 64K)
 	VBOOT2_WORK(BOOTROM_OFFSET + 0x30000, 12K)

src/soc/qualcomm/sdm845/include/soc/memlayout.ld

@@ -57,7 +57,8 @@ SECTIONS
 	TIMESTAMP(0x14836000, 1K)
 	PRERAM_CBMEM_CONSOLE(0x14836400, 32K)
 	PRERAM_CBFS_CACHE(0x1483E400, 70K)
-	REGION(bsram_unused, 0x1484FC00, 0x9E300, 0x100)
+	FMAP_CACHE(0x1484FC00, 2K)
+	REGION(bsram_unused, 0x14850400, 0x9DB00, 0x100)
 	REGION(ddr_information, 0x148EDF00, 256, 256)
 	REGION(limits_cfg, 0x148EE000, 4K, 4K)
 	REGION(qclib_serial_log, 0x148EF000, 4K, 4K)

src/soc/sifive/fu540/include/soc/memlayout.ld

@@ -27,6 +27,7 @@ SECTIONS
 	BOOTBLOCK(FU540_L2LIM, 64K)
 	CAR_STACK(FU540_L2LIM + 64K, 20K)
 	PRERAM_CBMEM_CONSOLE(FU540_L2LIM + 84K, 8K)
+	FMAP_CACHE(FU540_L2LIM + 92K, 2K)
 	ROMSTAGE(FU540_L2LIM + 128K, 128K)
 	PRERAM_CBFS_CACHE(FU540_L2LIM + 256K, 128K)
 	L2LIM_END(FU540_L2LIM + 2M)