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superio/ite: Fix incorrect warnings

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Fix warning for disabled thermal inputs.

Fix warning for PECI thermal inputs if one was set up previously.
Depending on the mb, the superio will not go through power-on reset and
retain its registers. Do not trigger a warning if the current register
value aligns with the desired value. Don't return early if some input is
already configured for PECI, simply overwrite the configuration.

Both warnings were observed while porting the "HP Pro 3500 Series" mb.

Change-Id: Ibabe1b1ef55f2acb2074eceb535ec684bffc8155
Signed-off-by: Joel Linn <jl@conductive.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Joel Linn
2024-03-26 18:19:15 +01:00
committed by Nico Huber
parent cccada28f7
commit 82ff48c1b1
1 changed files with 9 additions and 4 deletions
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13
src/superio/ite/common/env_ctrl.c
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@@ -67,6 +67,8 @@ static void enable_tmpin(const u16 base, const u8 tmpin,
reg_extra = pnp_read_hwm5_index(base, ITE_EC_ADC_TEMP_EXTRA_CHANNEL_ENABLE);
switch (conf->mode) {
case THERMAL_MODE_DISABLED:
return;
case THERMAL_PECI:
/* Some chips can set any TMPIN as the target for PECI readings
while others can only read to TMPIN3. In the latter case a
@@ -78,12 +80,15 @@ static void enable_tmpin(const u16 base, const u8 tmpin,
"PECI to TMPIN2 not supported on IT8721F\n");
return;
}
if (reg & ITE_EC_ADC_TEMP_EXT_REPORTS_TO_MASK) {
u8 reg_new = (reg & ~ITE_EC_ADC_TEMP_EXT_REPORTS_TO_MASK)
| ITE_EC_ADC_TEMP_EXT_REPORTS_TO(tmpin);
/* Registers stick on reboot and resume,
don't warn for correct reg values */
if (reg & ITE_EC_ADC_TEMP_EXT_REPORTS_TO_MASK && reg != reg_new) {
printk(BIOS_WARNING,
"PECI specified for multiple TMPIN\n");
return;
"PECI specified for another TMPIN, overwriting\n");
}
reg |= ITE_EC_ADC_TEMP_EXT_REPORTS_TO(tmpin);
reg = reg_new;
} else if (tmpin == 3) {
reg_extra |= ITE_EC_ADC_TEMP_EXTRA_TMPIN3_EXT;
pnp_write_hwm5_index(base, ITE_EC_ADC_TEMP_EXTRA_CHANNEL_ENABLE,