mb/system76/tgl-u: darp7: Re-add CPU PCIe RTD3
Change-Id: I2df115c323a4fa50ffac191461060df9059381f7 Signed-off-by: Tim Crawford <tcrawford@system76.com>
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Tim Crawford
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49c455b353
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83083250f9
@@ -21,6 +21,12 @@ chip soc/intel/tigerlake
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# PCIe PEG0 x4, Clock 0 (SSD1)
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register "PcieClkSrcUsage[0]" = "0x40"
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register "PcieClkSrcClkReq[0]" = "0"
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chip soc/intel/common/block/pcie/rtd3
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B16)" # SSD1_PWR_EN
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D13)" # GPP_D13_SSD1_PLT_RST#
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register "srcclk_pin" = "0" # SSD1_CLKREQ#
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device generic 0 on end
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end
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end
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device ref north_xhci on # J_TYPEC2
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register "UsbTcPortEn" = "1"
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