sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/system76/tgl-u: darp7: Re-add CPU PCIe RTD3

Browse Source 
Change-Id: I2df115c323a4fa50ffac191461060df9059381f7
Signed-off-by: Tim Crawford <tcrawford@system76.com>
This commit is contained in:
Tim Crawford
2022-12-30 12:59:02 -07:00
committed by Tim Crawford
parent 49c455b353
commit 83083250f9
1 changed files with 6 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb
View File

@@ -21,6 +21,12 @@ chip soc/intel/tigerlake
# PCIe PEG0 x4, Clock 0 (SSD1)
register "PcieClkSrcUsage[0]" = "0x40"
register "PcieClkSrcClkReq[0]" = "0"
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B16)" # SSD1_PWR_EN
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D13)" # GPP_D13_SSD1_PLT_RST#
register "srcclk_pin" = "0" # SSD1_CLKREQ#
device generic 0 on end
end
end
device ref north_xhci on # J_TYPEC2
register "UsbTcPortEn" = "1"