mb/msi/ms7d25,ms7e06: Enable discrete TPM module support
Now that multiple TPM drivers may be compiled in, it is possible to support switching between fTPM and dTPM. The patch adds: - Device tree entry for PC80 discrete TPM - TPM PIRQ# GPIO active low routed to IOAPIC for TPM interrupt - MEMORY_MAPPED_TPM option to board's Kconfig to enable PC80 TPM driver When the ME is disabled, e.g. via HECI command, chipset will route the TPM traffic to SPI automatically. When a SPI TPM is connected to the JTPM1 on the board, it will be probed successfully and initialized in place of inactive PTT/fTPM. Change-Id: Ie6e7026b6f1cec842bce4ef40b6db7feb75200e3 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80456 Reviewed-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
committed by
Felix Held
parent
0c6d48f3ee
commit
84101434c0
@@ -16,6 +16,7 @@ config BOARD_MSI_MS7D25
|
||||
select HAVE_ACPI_RESUME
|
||||
select HAVE_ACPI_TABLES
|
||||
select INTEL_GMA_HAVE_VBT
|
||||
select MEMORY_MAPPED_TPM
|
||||
select CRB_TPM
|
||||
select HAVE_INTEL_PTT
|
||||
select USE_LEGACY_8254_TIMER
|
||||
@@ -53,6 +54,9 @@ config CBFS_SIZE
|
||||
hex
|
||||
default 0x1000000
|
||||
|
||||
config TPM_PIRQ
|
||||
default 0x3f # GPP_E7_IRQ
|
||||
|
||||
config VBOOT
|
||||
select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
|
||||
select GBB_FLAG_DISABLE_FWMP
|
||||
|
@@ -241,6 +241,9 @@ chip soc/intel/alderlake
|
||||
device pnp 4e.e off end # TACH/PWM assignment
|
||||
device pnp 4e.f off end # Function register
|
||||
end
|
||||
chip drivers/pc80/tpm
|
||||
device pnp 0.0 on end # TPM
|
||||
end
|
||||
end
|
||||
device ref p2sb on end
|
||||
device ref hda on
|
||||
|
@@ -536,8 +536,8 @@ static const struct pad_config gpio_table[] = {
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_E5, NONE, PLTRST, OFF, ACPI),
|
||||
/* GPP_E6 - GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_E6, NONE, PLTRST, OFF, ACPI),
|
||||
/* GPP_E7 - GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, PLTRST, OFF, ACPI),
|
||||
/* GPP_E7 - TPM_PIRQ# */
|
||||
PAD_CFG_GPI_APIC_LOW(GPP_E7, NONE, PLTRST),
|
||||
/* GPP_E8 - SATALED# */
|
||||
PAD_CFG_NF(GPP_E8, NONE, PLTRST, NF1),
|
||||
/* GPP_E9 - USB_OC0# */
|
||||
|
@@ -16,6 +16,7 @@ config BOARD_MSI_MS7E06
|
||||
select HAVE_ACPI_RESUME
|
||||
select HAVE_ACPI_TABLES
|
||||
select INTEL_GMA_HAVE_VBT
|
||||
select MEMORY_MAPPED_TPM
|
||||
select CRB_TPM
|
||||
select HAVE_INTEL_PTT
|
||||
|
||||
@@ -46,6 +47,9 @@ config USE_LEGACY_8254_TIMER
|
||||
config CBFS_SIZE
|
||||
default 0x1000000
|
||||
|
||||
config TPM_PIRQ
|
||||
default 0x3f # GPP_E7_IRQ
|
||||
|
||||
config VBOOT
|
||||
select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
|
||||
select GBB_FLAG_DISABLE_FWMP
|
||||
|
@@ -231,6 +231,9 @@ chip soc/intel/alderlake
|
||||
device pnp 4e.e off end # TACH/PWM assignment
|
||||
device pnp 4e.f off end # Function register
|
||||
end
|
||||
chip drivers/pc80/tpm
|
||||
device pnp 0.0 on end # TPM
|
||||
end
|
||||
end
|
||||
device ref hda on
|
||||
subsystemid 0x1462 0x9e06
|
||||
|
@@ -536,8 +536,8 @@ static const struct pad_config gpio_table[] = {
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_E5, NONE, PLTRST, OFF, ACPI),
|
||||
/* GPP_E6 - GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_E6, NONE, PLTRST, OFF, ACPI),
|
||||
/* GPP_E7 - GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, PLTRST, OFF, ACPI),
|
||||
/* GPP_E7 - TPM_PIRQ# */
|
||||
PAD_CFG_GPI_APIC_LOW(GPP_E7, NONE, PLTRST),
|
||||
/* GPP_E8 - SATALED# */
|
||||
PAD_CFG_NF(GPP_E8, NONE, PLTRST, NF1),
|
||||
/* GPP_E9 - USB_OC0# */
|
||||
|
Reference in New Issue
Block a user