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soc/intel/alderlake/{chipset.cb,chipset_pch_s.cb}: Set P2SB as hidden

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Set the P2SB device as hidden as FSP-S is hiding the PCI configuration
space from coreboot on Alder Lake systems.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I5cfde7c1f6791578a03d73e89bcde31af608f12d
This commit is contained in:
Michał Żygowski
2022-11-23 14:48:17 +01:00
committed by Jeremy Soller
parent 09f9c48146
commit 84937d76fb
2 changed files with 2 additions and 2 deletions
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2
src/soc/intel/alderlake/chipset.cb
View File

@@ -278,7 +278,7 @@ chip soc/intel/alderlake
device pci 1e.2 alias gspi0 off end
device pci 1e.3 alias gspi1 off end
device pci 1f.0 alias pch_espi on end
device pci 1f.1 alias p2sb off end
device pci 1f.1 alias p2sb hidden end
device pci 1f.2 alias pmc hidden end
device pci 1f.3 alias hda off end
device pci 1f.4 alias smbus off end

2
src/soc/intel/alderlake/chipset_pch_s.cb
View File

@@ -242,7 +242,7 @@ chip soc/intel/alderlake
device pci 1e.2 alias gspi0 off end
device pci 1e.3 alias gspi1 off end
device pci 1f.0 alias pch_espi on end
device pci 1f.1 alias p2sb off end
device pci 1f.1 alias p2sb hidden end
device pci 1f.2 alias pmc hidden end
device pci 1f.3 alias hda off end
device pci 1f.4 alias smbus off end