addw1
Change-Id: Iae42a750dce4d93d1dea75eef6c47f08160f3fe1
This commit is contained in:
Jeremy Soller
Jeremy Soller
parent
caf3ce984c
commit
84bb9befff
87
src/mainboard/system76/addw1/Kconfig
Normal file
87
src/mainboard/system76/addw1/Kconfig
Normal file
@ -0,0 +1,87 @@
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if BOARD_SYSTEM76_ADDW1
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_16384
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select DRIVERS_I2C_HID
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select DRIVERS_I2C_TAS5825M
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select DRIVERS_SYSTEM76_DGPU
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select EC_SYSTEM76_EC
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select EC_SYSTEM76_EC_COLOR_KEYBOARD
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select EC_SYSTEM76_EC_DGPU
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select EC_SYSTEM76_EC_OLED
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select HAVE_SMI_HANDLER
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select INTEL_GMA_HAVE_VBT
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select INTEL_LPSS_UART_FOR_CONSOLE
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select MAINBOARD_HAS_LPC_TPM
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select MAINBOARD_HAS_TPM2
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select NO_UART_ON_SUPERIO
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select PCIEXP_HOTPLUG
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select SOC_INTEL_CANNONLAKE_PCH_H
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select SOC_INTEL_COFFEELAKE
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select SOC_INTEL_COMMON_BLOCK_HDA
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select SOC_INTEL_COMMON_BLOCK_HDA_VERB
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select SPD_READ_BY_WORD
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select SYSTEM_TYPE_LAPTOP
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select TPM_RDRESP_NEED_DELAY
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select USE_LEGACY_8254_TIMER # Fix failure to boot GRUB
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config MAINBOARD_DIR
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string
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default "system76/addw1"
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config MAINBOARD_PART_NUMBER
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string
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default "addw1"
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config MAINBOARD_SMBIOS_PRODUCT_NAME
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string
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default "Adder WS"
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config MAINBOARD_VERSION
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string
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default "addw1"
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config CBFS_SIZE
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hex
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default 0xA00000
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config SUBSYSTEM_VENDOR_ID
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hex
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default 0x1558
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config SUBSYSTEM_DEVICE_ID
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hex
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default 0x65d1
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config CONSOLE_POST
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bool
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default y
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config ONBOARD_VGA_IS_PRIMARY
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bool
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default y
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config UART_FOR_CONSOLE
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int
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default 2
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config MAX_CPUS
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int
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default 16
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config DIMM_MAX
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int
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default 2
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config DIMM_SPD_SIZE
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int
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default 512
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config POST_DEVICE
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bool
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default n
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endif
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2
src/mainboard/system76/addw1/Kconfig.name
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2
src/mainboard/system76/addw1/Kconfig.name
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@ -0,0 +1,2 @@
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config BOARD_SYSTEM76_ADDW1
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bool "addw1"
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4
src/mainboard/system76/addw1/Makefile.inc
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4
src/mainboard/system76/addw1/Makefile.inc
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@ -0,0 +1,4 @@
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bootblock-y += bootblock.c
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ramstage-y += ramstage.c
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ramstage-y += hda_verb.c
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ramstage-y += tas5825m.c
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11
src/mainboard/system76/addw1/acpi/gpe.asl
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11
src/mainboard/system76/addw1/acpi/gpe.asl
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@ -0,0 +1,11 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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// GPP_K6 SCI
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Method (_L06, 0, Serialized) {
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Debug = Concatenate("GPE _L06: ", ToHexString(\_SB.PCI0.LPCB.EC0.WFNO))
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If (\_SB.PCI0.LPCB.EC0.ECOK) {
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If (\_SB.PCI0.LPCB.EC0.WFNO == One) {
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Notify(\_SB.LID0, 0x80)
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}
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}
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}
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17
src/mainboard/system76/addw1/acpi/mainboard.asl
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17
src/mainboard/system76/addw1/acpi/mainboard.asl
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@ -0,0 +1,17 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include "../gpio.h"
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#include <drivers/system76/dgpu/acpi/dgpu.asl>
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#define EC_GPE_SCI 0x03 /* GPP_K3 */
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#define EC_GPE_SWI 0x06 /* GPP_K6 */
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#define EC_COLOR_KEYBOARD 1
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#include <ec/system76/ec/acpi/ec.asl>
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Scope (\_SB) {
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#include "sleep.asl"
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}
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Scope (\_GPE) {
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#include "gpe.asl"
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}
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14
src/mainboard/system76/addw1/acpi/sleep.asl
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14
src/mainboard/system76/addw1/acpi/sleep.asl
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@ -0,0 +1,14 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* Method called from _PTS prior to enter sleep state */
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Method (MPTS, 1) {
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\_SB.PCI0.LPCB.EC0.PTS (Arg0)
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// Turn DGPU on before sleeping
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\_SB.PCI0.PEGP.DEV0._ON()
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}
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/* Method called from _WAK prior to wakeup */
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Method (MWAK, 1) {
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\_SB.PCI0.LPCB.EC0.WAK (Arg0)
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}
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8
src/mainboard/system76/addw1/board_info.txt
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8
src/mainboard/system76/addw1/board_info.txt
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@ -0,0 +1,8 @@
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Vendor name: System76
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Board name: addw1
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Category: laptop
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Release year: 2019
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ROM package: SOIC-8
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: y
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11
src/mainboard/system76/addw1/bootblock.c
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11
src/mainboard/system76/addw1/bootblock.c
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@ -0,0 +1,11 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootblock_common.h>
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#include <gpio.h>
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#include "gpio.h"
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#include <drivers/system76/dgpu/bootblock.c>
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void bootblock_mainboard_init(void) {
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gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
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dgpu_power_enable(1);
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}
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BIN
src/mainboard/system76/addw1/data.vbt
Normal file
BIN
src/mainboard/system76/addw1/data.vbt
Normal file
Binary file not shown.
331
src/mainboard/system76/addw1/devicetree.cb
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331
src/mainboard/system76/addw1/devicetree.cb
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@ -0,0 +1,331 @@
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chip soc/intel/cannonlake
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# Lock Down
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register "common_soc_config" = "{
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.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
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// Touchpad I2C bus
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.i2c[0] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 80,
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.fall_time_ns = 110,
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},
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}"
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# Send an extra VR mailbox command for the PS4 exit issue
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register "SendVrMbxCmd" = "2"
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# ACPI (soc/intel/cannonlake/acpi.c)
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# Disable s0ix
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register "s0ix_enable" = "0"
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# PM Timer Enabled
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register "PmTimerDisabled" = "0"
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# Disable DPTF
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register "dptf_enable" = "0"
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# CPU (soc/intel/cannonlake/cpu.c)
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# Power limit
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register "power_limits_config" = "{
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// /sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw
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.tdp_pl1_override = 45,
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// /sys/class/powercap/intel-rapl:0/constraint_1_power_limit_uw
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.tdp_pl2_override = 90,
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}"
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# Enable "Intel Speed Shift Technology"
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register "speed_shift_enable" = "1"
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# Enable Enhanced Intel SpeedStep
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register "eist_enable" = "1"
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# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
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register "SaGv" = "SaGv_Enabled"
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register "enable_c6dram" = "1"
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# FSP Silicon (soc/intel/cannonlake/fsp_params.c)
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# Serial I/O
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register "SerialIoDevMode" = "{
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[PchSerialIoIndexI2C0] = PchSerialIoPci, // Touchpad I2C bus
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[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
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[PchSerialIoIndexSPI0] = PchSerialIoDisabled,
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[PchSerialIoIndexSPI1] = PchSerialIoDisabled,
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[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
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[PchSerialIoIndexUART0] = PchSerialIoDisabled,
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[PchSerialIoIndexUART1] = PchSerialIoDisabled,
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[PchSerialIoIndexUART2] = PchSerialIoPci, // Debug console
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}"
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# SATA
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register "SataMode" = "Sata_AHCI"
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register "SataSalpSupport" = "0"
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register "SataPortsEnable[0]" = "1" # HDD (SATA0B)
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register "SataPortsEnable[1]" = "1" # SSD1 (SATA1A)
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register "SataPortsEnable[2]" = "0"
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register "SataPortsEnable[3]" = "0"
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register "SataPortsEnable[4]" = "0"
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register "SataPortsEnable[5]" = "0"
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register "SataPortsEnable[6]" = "0"
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register "SataPortsEnable[7]" = "0"
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register "SataPortsDevSlp[0]" = "0"
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register "SataPortsDevSlp[1]" = "0"
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register "SataPortsDevSlp[2]" = "0"
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register "SataPortsDevSlp[3]" = "0"
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register "SataPortsDevSlp[4]" = "0"
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register "SataPortsDevSlp[5]" = "0"
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register "SataPortsDevSlp[6]" = "0"
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register "SataPortsDevSlp[7]" = "0"
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# Audio
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register "PchHdaDspEnable" = "0"
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register "PchHdaAudioLinkHda" = "1"
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register "PchHdaAudioLinkDmic0" = "0"
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register "PchHdaAudioLinkDmic1" = "0"
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register "PchHdaAudioLinkSsp0" = "0"
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register "PchHdaAudioLinkSsp1" = "0"
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register "PchHdaAudioLinkSsp2" = "0"
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register "PchHdaAudioLinkSndw1" = "0"
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register "PchHdaAudioLinkSndw2" = "0"
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register "PchHdaAudioLinkSndw3" = "0"
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register "PchHdaAudioLinkSndw4" = "0"
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# USB
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register "SsicPortEnable" = "0"
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# USB2
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register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C and DisplayPort
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register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C
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register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 Gen 2
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register "usb2_ports[3]" = "USB2_PORT_EMPTY"
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register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 Gen 1 audio
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register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 Gen 1 back
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register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
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register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Per-Key RGB keyboard
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register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Camera
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register "usb2_ports[9]" = "USB2_PORT_EMPTY"
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register "usb2_ports[10]" = "USB2_PORT_EMPTY"
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register "usb2_ports[11]" = "USB2_PORT_EMPTY"
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register "usb2_ports[12]" = "USB2_PORT_EMPTY"
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register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
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register "usb2_ports[14]" = "USB2_PORT_EMPTY"
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register "usb2_ports[15]" = "USB2_PORT_EMPTY"
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# USB3
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C and DisplayPort
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 2 right
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C (without TBT)
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C (without TBT)
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register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 1 audio
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register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 1 back
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register "usb3_ports[6]" = "USB3_PORT_EMPTY"
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register "usb3_ports[7]" = "USB3_PORT_EMPTY"
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register "usb3_ports[8]" = "USB3_PORT_EMPTY"
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register "usb3_ports[9]" = "USB3_PORT_EMPTY"
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# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
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register "PcieClkSrcUsage[8]" = "0x40"
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# PCI Express root port #9 x4, Clock 9 (SSD1)
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register "PcieRpEnable[8]" = "1"
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register "PcieRpLtrEnable[8]" = "1"
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register "PcieClkSrcUsage[9]" = "8"
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# PCI Express root port #14 x1, Clock 5 (GLAN)
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register "PcieRpEnable[13]" = "1"
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register "PcieRpLtrEnable[13]" = "1"
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register "PcieClkSrcUsage[5]" = "13"
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# PCI Express root port #15 x1, Clock 7 (Card Reader)
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register "PcieRpEnable[14]" = "1"
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register "PcieRpLtrEnable[14]" = "1"
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register "PcieClkSrcUsage[7]" = "14"
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# PCI Express root port #16 x1, Clock 6 (WLAN)
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register "PcieRpEnable[15]" = "1"
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register "PcieRpLtrEnable[15]" = "1"
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register "PcieClkSrcUsage[6]" = "15"
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# PCI Express root port #17 x4, Clock 0 (Thunderbolt)
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register "PcieRpEnable[16]" = "1"
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register "PcieRpLtrEnable[16]" = "1"
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register "PcieRpHotPlug[16]" = "1"
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register "PcieClkSrcUsage[0]" = "16"
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# PCI Express root port #21 x4, Clock 10 (SSD2)
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register "PcieRpEnable[20]" = "1"
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register "PcieRpLtrEnable[20]" = "1"
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register "PcieClkSrcUsage[10]" = "20"
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# Set all clocks sources to the same clock request
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register "PcieClkSrcClkReq[0]" = "0"
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register "PcieClkSrcClkReq[1]" = "1"
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register "PcieClkSrcClkReq[2]" = "2"
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register "PcieClkSrcClkReq[3]" = "3"
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register "PcieClkSrcClkReq[4]" = "4"
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register "PcieClkSrcClkReq[5]" = "5"
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register "PcieClkSrcClkReq[6]" = "6"
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register "PcieClkSrcClkReq[7]" = "7"
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register "PcieClkSrcClkReq[8]" = "8"
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register "PcieClkSrcClkReq[9]" = "9"
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register "PcieClkSrcClkReq[10]" = "10"
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register "PcieClkSrcClkReq[11]" = "11"
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register "PcieClkSrcClkReq[12]" = "12"
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register "PcieClkSrcClkReq[13]" = "13"
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register "PcieClkSrcClkReq[14]" = "14"
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register "PcieClkSrcClkReq[15]" = "15"
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# Misc
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register "Device4Enable" = "1"
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register "HeciEnabled" = "0"
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register "Heci3Enabled" = "0"
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register "AcousticNoiseMitigation" = "1"
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#register "dmipwroptimize" = "1"
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#register "satapwroptimize" = "1"
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# Power
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# sudo devmem2 0xfe001020 (pmc_bar + GEN_PMCON_A), bits 11:10
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# WARNING: must then be mapped from FSP value to PCH value
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register "PchPmSlpS3MinAssert" = "3" # 50ms
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# sudo devmem2 0xfe001020 (pmc_bar + GEN_PMCON_A), bits 5:4
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# WARNING: must then be mapped from FSP value to PCH value
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register "PchPmSlpS4MinAssert" = "1" # 1s
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# sudo devmem2 0xfe001818 (pmc_bar + PM_CFG), bits 19:18
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# WARNING: must then be mapped from FSP value to PCH value
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register "PchPmSlpSusMinAssert" = "4" # 4s
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# sudo devmem2 0xfe001818 (pmc_bar + PM_CFG), bits 17:16
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# WARNING: must then be mapped from FSP value to PCH value
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register "PchPmSlpAMinAssert" = "4" # 2s
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# Thermal
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# rdmsr --bitfield 31:24 --decimal 0x1A2
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register "tcc_offset" = "8"
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# Serial IRQ Continuous
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register "serirq_mode" = "SERIRQ_CONTINUOUS"
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# LPC (soc/intel/cannonlake/lpc.c)
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# LPC configuration from lspci -s 1f.0 -xxx
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# Address 0x84: Decode 0x80 - 0x8F (Port 80)
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register "gen1_dec" = "0x000c0081"
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# Address 0x88: Decode 0x68 - 0x6F (PMC)
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register "gen2_dec" = "0x00040069"
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# Address 0x8C: Decode 0xE00 - 0xEFF (AP/EC command)
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register "gen3_dec" = "0x00fc0E01"
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# Address 0x90: Decode 0xF00 - 0xFFF (AP/EC debug)
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register "gen4_dec" = "0x00fc0F01"
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|
||||
# PMC (soc/intel/cannonlake/pmc.c)
|
||||
# Disable deep Sx states
|
||||
register "deep_s3_enable_ac" = "0"
|
||||
register "deep_s3_enable_dc" = "0"
|
||||
register "deep_s5_enable_ac" = "0"
|
||||
register "deep_s5_enable_dc" = "0"
|
||||
register "deep_sx_config" = "0"
|
||||
|
||||
# PM Util (soc/intel/cannonlake/pmutil.c)
|
||||
# GPE configuration
|
||||
# Note that GPE events called out in ASL code rely on this
|
||||
# route. i.e. If this route changes then the affected GPE
|
||||
# offset bits also need to be changed.
|
||||
# sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
|
||||
register "gpe0_dw0" = "PMC_GPP_K"
|
||||
register "gpe0_dw1" = "PMC_GPP_G"
|
||||
register "gpe0_dw2" = "PMC_GPP_E"
|
||||
|
||||
# Actual device tree
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # Host Bridge
|
||||
device pci 01.0 on end # GPU Port
|
||||
device pci 02.0 on end # Integrated Graphics Device
|
||||
device pci 04.0 on end # SA Thermal device
|
||||
device pci 12.0 on end # Thermal Subsystem
|
||||
device pci 12.5 off end # UFS SCS
|
||||
device pci 12.6 off end # GSPI #2
|
||||
device pci 13.0 off end # Integrated Sensor Hub
|
||||
device pci 14.0 on end # USB xHCI
|
||||
device pci 14.1 off end # USB xDCI (OTG)
|
||||
device pci 14.2 on end # Shared SRAM
|
||||
#chip drivers/intel/wifi
|
||||
# register "wake" = "PME_B0_EN_BIT"
|
||||
device pci 14.3 on end # CNVi wifi
|
||||
#end
|
||||
device pci 14.5 off end # SDCard
|
||||
device pci 15.0 on
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""PNP0C50""
|
||||
register "generic.desc" = ""Synaptics Touchpad""
|
||||
register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)"
|
||||
register "generic.probed" = "1"
|
||||
register "hid_desc_reg_offset" = "0x20"
|
||||
device i2c 2c on end
|
||||
end
|
||||
end # I2C #0
|
||||
device pci 15.1 off end # I2C #1
|
||||
device pci 15.2 off end # I2C #2
|
||||
device pci 15.3 off end # I2C #3
|
||||
device pci 16.0 off end # Management Engine Interface 1
|
||||
device pci 16.1 off end # Management Engine Interface 2
|
||||
device pci 16.2 off end # Management Engine IDE-R
|
||||
device pci 16.3 off end # Management Engine KT Redirection
|
||||
device pci 16.4 off end # Management Engine Interface 3
|
||||
device pci 16.5 off end # Management Engine Interface 4
|
||||
device pci 17.0 on end # SATA
|
||||
device pci 19.0 off end # I2C #4
|
||||
device pci 19.1 off end # I2C #5
|
||||
device pci 19.2 on end # UART #2
|
||||
device pci 1a.0 off end # eMMC
|
||||
device pci 1b.0 on end # PCI Express Port 17
|
||||
device pci 1b.1 off end # PCI Express Port 18
|
||||
device pci 1b.2 off end # PCI Express Port 19
|
||||
device pci 1b.3 off end # PCI Express Port 20
|
||||
device pci 1b.4 on end # PCI Express Port 21
|
||||
device pci 1b.5 off end # PCI Express Port 22
|
||||
device pci 1b.6 off end # PCI Express Port 23
|
||||
device pci 1b.7 off end # PCI Express Port 24
|
||||
device pci 1c.0 off end # PCI Express Port 1
|
||||
device pci 1c.1 off end # PCI Express Port 2
|
||||
device pci 1c.2 off end # PCI Express Port 3
|
||||
device pci 1c.3 off end # PCI Express Port 4
|
||||
device pci 1c.4 off end # PCI Express Port 5
|
||||
device pci 1c.5 off end # PCI Express Port 6
|
||||
device pci 1c.6 off end # PCI Express Port 7
|
||||
device pci 1c.7 off end # PCI Express Port 8
|
||||
device pci 1d.0 on end # PCI Express Port 9
|
||||
device pci 1d.1 off end # PCI Express Port 10
|
||||
device pci 1d.2 off end # PCI Express Port 11
|
||||
device pci 1d.3 off end # PCI Express Port 12
|
||||
device pci 1d.4 off end # PCI Express Port 13
|
||||
device pci 1d.5 on end # PCI Express Port 14
|
||||
device pci 1d.6 on end # PCI Express Port 15
|
||||
device pci 1d.7 on end # PCI Express Port 16
|
||||
device pci 1e.0 off end # UART #0
|
||||
device pci 1e.1 off end # UART #1
|
||||
device pci 1e.2 off end # GSPI #0
|
||||
device pci 1e.3 off end # GSPI #1
|
||||
device pci 1f.0 on # LPC Interface
|
||||
chip drivers/pc80/tpm
|
||||
device pnp 0c31.0 on end
|
||||
end
|
||||
end
|
||||
device pci 1f.1 off end # P2SB
|
||||
device pci 1f.2 off end # Power Management Controller
|
||||
device pci 1f.3 on end # Intel HDA
|
||||
device pci 1f.4 on
|
||||
chip drivers/i2c/tas5825m
|
||||
register "id" = "0"
|
||||
device i2c 4e on end # (8bit address: 0x9c)
|
||||
end # tas5825m
|
||||
end # SMBus
|
||||
device pci 1f.5 on end # PCH SPI
|
||||
device pci 1f.6 off end # GbE
|
||||
end
|
||||
end
|
||||
29
src/mainboard/system76/addw1/dsdt.asl
Normal file
29
src/mainboard/system76/addw1/dsdt.asl
Normal file
@ -0,0 +1,29 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <acpi/acpi.h>
|
||||
DefinitionBlock(
|
||||
"dsdt.aml",
|
||||
"DSDT",
|
||||
0x02, // DSDT revision: ACPI v2.0 and up
|
||||
OEM_ID,
|
||||
ACPI_TABLE_CREATOR,
|
||||
0x20110725 // OEM revision
|
||||
)
|
||||
{
|
||||
#include <soc/intel/cannonlake/acpi/platform.asl>
|
||||
#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
|
||||
#include <cpu/intel/common/acpi/cpu.asl>
|
||||
|
||||
Device (\_SB.PCI0) {
|
||||
#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
|
||||
#include <soc/intel/cannonlake/acpi/southbridge.asl>
|
||||
}
|
||||
|
||||
#include <southbridge/intel/common/acpi/sleepstates.asl>
|
||||
|
||||
Scope (\_SB.PCI0.LPCB) {
|
||||
#include <drivers/pc80/pc/ps2_controller.asl>
|
||||
}
|
||||
|
||||
#include "acpi/mainboard.asl"
|
||||
}
|
||||
255
src/mainboard/system76/addw1/gpio.h
Normal file
255
src/mainboard/system76/addw1/gpio.h
Normal file
@ -0,0 +1,255 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#define DGPU_RST_N GPP_F22
|
||||
#define DGPU_PWR_EN GPP_F23
|
||||
#define DGPU_GC6 GPP_C12
|
||||
|
||||
#ifndef __ACPI__
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
/* Pad configuration in romstage. */
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
PAD_CFG_TERM_GPO(GPP_F22, 0, NONE, DEEP), // DGPU_RST_N
|
||||
PAD_CFG_TERM_GPO(GPP_F23, 0, NONE, DEEP), // DGPU_PWR_EN
|
||||
};
|
||||
|
||||
/* Pad configuration in ramstage. */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
PAD_CFG_NF(GPD0, NONE, DEEP, NF1), // PM_BATLOW#
|
||||
PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), // AC_PRESENT
|
||||
PAD_CFG_GPI(GPD2, NATIVE, PWROK), // NC
|
||||
PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWR_BTN#
|
||||
PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SUSB#_PCH
|
||||
PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SUSC#_PCH
|
||||
PAD_CFG_NF(GPD6, NONE, DEEP, NF1), // NC
|
||||
PAD_CFG_GPI(GPD7, NONE, PWROK), // NC
|
||||
PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // SUS_CLK
|
||||
PAD_CFG_NF(GPD9, NONE, PWROK, NF1), // NC
|
||||
_PAD_CFG_STRUCT(GPD10, 0x04000601, 0x0000), // NC
|
||||
PAD_CFG_NF(GPD11, NONE, DEEP, NF1), // NC
|
||||
PAD_CFG_TERM_GPO(GPP_A0, 0, NONE, DEEP), // SB_KBCRST#
|
||||
PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), // LPC_AD0
|
||||
PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), // LPC_AD1
|
||||
PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), // LPC_AD2
|
||||
PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), // LPC_AD3
|
||||
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), // LPC_FRAME#
|
||||
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // SERIRQ
|
||||
PAD_CFG_GPI(GPP_A7, NONE, DEEP), // SCI#_GPP_A7
|
||||
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), // ECCLKRUN#
|
||||
PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // PCLK_KBC
|
||||
PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), // NC
|
||||
PAD_CFG_GPI(GPP_A11, UP_20K, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_A12, NONE, DEEP), // NC
|
||||
PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), // SUSWARN#
|
||||
PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), // NC
|
||||
PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), // SUS_PWR_ACK#
|
||||
PAD_CFG_GPI(GPP_A16, DN_20K, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_A17, NONE, DEEP), // AMP_TYPE_DET
|
||||
PAD_CFG_TERM_GPO(GPP_A18, 1, NONE, DEEP), // SB_BLON
|
||||
PAD_CFG_GPI(GPP_A19, NONE, DEEP), // NC
|
||||
PAD_CFG_TERM_GPO(GPP_A20, 1, NONE, DEEP), // PEX_WAKE#
|
||||
PAD_CFG_GPI(GPP_A21, NONE, DEEP), // NC
|
||||
PAD_CFG_TERM_GPO(GPP_A22, 1, NONE, DEEP), // SMARTAMP_SW
|
||||
PAD_CFG_GPI(GPP_A23, NONE, DEEP), // SMART AMP PWR (L:3.3VS H:3.3V)
|
||||
PAD_CFG_GPI(GPP_B0, NONE, DEEP), // TPM_PIRQ#
|
||||
PAD_CFG_GPI(GPP_B1, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_B2, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST, EDGE_SINGLE, INVERT), // PCH_GPP_B3 (touchpad interrupt)
|
||||
PAD_CFG_GPI(GPP_B4, NONE, DEEP), // NC
|
||||
PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), // TBT_CLKREQ#
|
||||
PAD_CFG_GPI(GPP_B6, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_B7, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_B8, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_B9, NONE, DEEP), // NC
|
||||
PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), // GLAN_CLKREQ#
|
||||
PAD_CFG_GPI(GPP_B11, NONE, DEEP), // NC
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
|
||||
_PAD_CFG_STRUCT(GPP_B13, 0x44000601, 0x0000), // PLT_RST#
|
||||
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // PCH_SPKR
|
||||
PAD_CFG_GPI(GPP_B15, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_B16, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_B17, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_B18, NONE, DEEP), // NO REBOOT STRAP
|
||||
PAD_CFG_GPI(GPP_B19, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_B20, NONE, DEEP), // SMI#_GPP_B20
|
||||
PAD_CFG_GPI(GPP_B21, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_B22, NONE, DEEP), // BOOT BIOS STRAP
|
||||
PAD_CFG_GPI(GPP_B23, NONE, DEEP), // DCI-OOB STRAP
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
|
||||
_PAD_CFG_STRUCT(GPP_C2, 0x40880100, 0x0000), // CNVI_WAKE#
|
||||
PAD_CFG_GPI(GPP_C3, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_C4, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_C5, NONE, DEEP), // WLAN_WAKEUP#
|
||||
PAD_CFG_GPI(GPP_C6, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_C7, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_C8, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_C9, NONE, DEEP), // BOARD_ID2
|
||||
PAD_CFG_GPI(GPP_C10, NONE, DEEP), // BOARD_ID1
|
||||
PAD_CFG_GPI(GPP_C11, NONE, DEEP), // TBT_DET#
|
||||
PAD_CFG_GPI(GPP_C12, NONE, DEEP), // GC6_FB_EN_PCH
|
||||
PAD_CFG_GPI(GPP_C13, NONE, DEEP), // TPM_DET
|
||||
PAD_CFG_TERM_GPO(GPP_C14, 1, NONE, DEEP), // GPU_EVENT#
|
||||
PAD_CFG_GPI(GPP_C15, NONE, DEEP), // 100K pull-down
|
||||
PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), // TP_DAT_PCH_I2C0
|
||||
PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), // TP_CLK_PCH_I2C0
|
||||
PAD_CFG_NF(GPP_C18, NONE, PLTRST, NF1), // I2C1_SDA
|
||||
PAD_CFG_NF(GPP_C19, NONE, PLTRST, NF1), // I2C1_SCL
|
||||
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
|
||||
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
|
||||
PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), // UART2_RTS#
|
||||
PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), // UART2_CTS#
|
||||
PAD_CFG_GPI(GPP_D0, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_D1, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_D2, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_D3, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_D4, NONE, DEEP), // NC
|
||||
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3), // CNVI_RST#
|
||||
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), // CNVI_CLKREQ
|
||||
PAD_CFG_GPI(GPP_D7, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_D8, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_D9, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_D10, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_D11, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_D12, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_D13, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_D14, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_D15, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_D16, NONE, DEEP), // NC
|
||||
PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), // NC
|
||||
PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), // NC
|
||||
PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), // NC
|
||||
PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), // NC
|
||||
PAD_CFG_GPI(GPP_D21, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_D22, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_D23, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_E0, NONE, DEEP), // NC
|
||||
PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1), // SATAGP1
|
||||
PAD_CFG_GPI(GPP_E2, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_E3, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_E4, NONE, DEEP), // NC
|
||||
PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), // SATA_DEVSLP1
|
||||
PAD_CFG_TERM_GPO(GPP_E6, 1, NONE, DEEP), // PCH_MUTE#
|
||||
PAD_CFG_GPI(GPP_E7, NONE, DEEP), // NC
|
||||
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // SATAHDD_LED#
|
||||
PAD_CFG_GPI(GPP_E9, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_E10, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_E11, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_E12, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_F0, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_F1, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_F2, NONE, DEEP), // NC
|
||||
PAD_CFG_TERM_GPO(GPP_F3, 1, NONE, DEEP), // GPP_F3_LAN_RST#
|
||||
PAD_CFG_TERM_GPO(GPP_F4, 1, NONE, DEEP), // GPP_F4_TBT_RST#
|
||||
PAD_CFG_GPI(GPP_F5, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_F6, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_F7, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_F8, NONE, DEEP), // NC
|
||||
PAD_CFG_TERM_GPO(GPP_F9, 0, NONE, DEEP), // PS8331_SW
|
||||
PAD_CFG_GPI(GPP_F10, NONE, DEEP), // BIOS RECOVERY ENABLE STRAP
|
||||
PAD_CFG_GPI(GPP_F11, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_F12, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_F13, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_F14, NONE, DEEP), // H_SKTOCC_N
|
||||
PAD_CFG_GPI(GPP_F15, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_F16, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_F17, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_F18, NONE, DEEP), // NC
|
||||
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
|
||||
PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON
|
||||
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS
|
||||
PAD_CFG_TERM_GPO(GPP_F22, 1, NONE, DEEP), // DGPU_RST#_PCH
|
||||
PAD_CFG_TERM_GPO(GPP_F23, 1, NONE, DEEP), // DGPU_PWR_EN
|
||||
PAD_CFG_GPI(GPP_G0, NONE, DEEP), // GSYNC_DET
|
||||
PAD_CFG_GPI(GPP_G1, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_G2, NONE, DEEP), // NVSR_DET#
|
||||
PAD_CFG_GPI(GPP_G3, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_G4, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_G5, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_G6, NONE, DEEP), // SWI#_GPP_G6
|
||||
PAD_CFG_GPI(GPP_G7, NONE, DEEP), // NC
|
||||
PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), // WLAN_CLKREQ#
|
||||
PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1), // SD4.0_CLKREQ#
|
||||
PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), // PEG_CLKREQ#
|
||||
PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), // SSD1_CLKREQ#
|
||||
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // SSD2_CLKREQ#
|
||||
PAD_CFG_GPI(GPP_H5, NONE, DEEP), // NC
|
||||
PAD_CFG_TERM_GPO(GPP_H6, 1, NONE, DEEP), // PCIE_SSD1_RST#
|
||||
PAD_CFG_TERM_GPO(GPP_H7, 1, NONE, DEEP), // PCIE_SSD2_RST#
|
||||
PAD_CFG_GPI(GPP_H8, NONE, DEEP), // GPP_H8_LAN_RST#
|
||||
PAD_CFG_GPI(GPP_H9, NONE, DEEP), // TBT_GPIO_WAKE#
|
||||
PAD_CFG_GPI(GPP_H10, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_H11, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_H12, NONE, DEEP), // ESPI FLASH SHARING STRAP
|
||||
PAD_CFG_GPI(GPP_H13, NONE, DEEP), // TBTA_HRESET
|
||||
PAD_CFG_GPI(GPP_H14, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_H15, NONE, DEEP), // RESERVED STRAP
|
||||
_PAD_CFG_STRUCT(GPP_H16, 0x44000101, 0x0000), // TBT_RTD3_PWR_EN
|
||||
PAD_CFG_TERM_GPO(GPP_H17, 0, NONE, PLTRST), // TBT_FORCE_PWR
|
||||
PAD_CFG_TERM_GPO(GPP_H18, 1, NONE, DEEP), // NC
|
||||
PAD_CFG_TERM_GPO(GPP_H19, 1, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_H20, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_H21, NONE, DEEP), // XTAL FREQUENCY SELECT STRAP
|
||||
PAD_CFG_GPI(GPP_H22, NONE, DEEP), // NC
|
||||
_PAD_CFG_STRUCT(GPP_H23, 0x82880100, 0x0000), // TBCIO_PLUG_EVENT#
|
||||
PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), // ANX7411_HPD
|
||||
PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), // HDMI_HPD
|
||||
PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), // MDP_E_HPD
|
||||
PAD_CFG_NF(GPP_I3, NONE, DEEP, NF1), // MDP_A_TBT_HPD
|
||||
PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), // SB_IEDP_HPD
|
||||
PAD_CFG_TERM_GPO(GPP_I5, 1, NONE, DEEP), // TBT_GPIO_RST#
|
||||
PAD_CFG_GPI(GPP_I6, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_I7, NONE, DEEP), // NC
|
||||
PAD_CFG_TERM_GPO(GPP_I8, 1, NONE, DEEP), // SSD1_PWR_EN
|
||||
PAD_CFG_TERM_GPO(GPP_I9, 1, NONE, DEEP), // SSD2_PWR_EN
|
||||
PAD_CFG_GPI(GPP_I10, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_I11, NONE, DEEP), // NC
|
||||
PAD_CFG_TERM_GPO(GPP_I12, 1, NONE, DEEP), // SATA_PWR_EN
|
||||
PAD_CFG_GPI(GPP_I13, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_I14, NONE, DEEP), // NC
|
||||
PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
|
||||
PAD_CFG_TERM_GPO(GPP_J1, 1, NONE, DEEP), // GPP_J1
|
||||
PAD_CFG_GPI(GPP_J2, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_J3, NONE, DEEP), // NC
|
||||
PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // CNVI_BRI_DT
|
||||
PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
|
||||
PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // CNVI_RGI_DT
|
||||
PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
|
||||
PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1), // CNVI_MFUART2_RXD
|
||||
PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1), // CNVI_MFUART2_TXD
|
||||
PAD_CFG_GPI(GPP_J10, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_J11, DN_20K, DEEP), // NC
|
||||
PAD_CFG_TERM_GPO(GPP_K0, 0, NONE, DEEP), // GPP_K0_SPK_MUTE
|
||||
PAD_CFG_TERM_GPO(GPP_K1, 0, NONE, DEEP), // GPP_K1_WOOFER_MUTE
|
||||
PAD_CFG_GPI(GPP_K2, NONE, DEEP), // NC
|
||||
_PAD_CFG_STRUCT(GPP_K3, 0x40880100, 0x0000), // SCI#_GPP_K3
|
||||
PAD_CFG_GPI(GPP_K4, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_K5, NONE, DEEP), // NC
|
||||
_PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x0000), // SWI#_GPP_K6
|
||||
PAD_CFG_GPI(GPP_K7, NONE, DEEP), // GPP_K7_LAN_WAKEUP#
|
||||
PAD_CFG_TERM_GPO(GPP_K8, 1, NONE, DEEP), // GPP_K8_LAN_RTD3
|
||||
PAD_CFG_GPI(GPP_K9, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_K10, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_K11, NONE, DEEP), // NC
|
||||
PAD_CFG_TERM_GPO(GPP_K12, 1, NONE, DEEP), // PCH_GPP_K12
|
||||
PAD_CFG_GPI(GPP_K13, NONE, DEEP), // NC
|
||||
PAD_CFG_TERM_GPO(GPP_K14, 0, NONE, DEEP), // GPP_K14_TEST_R
|
||||
_PAD_CFG_STRUCT(GPP_K15, 0x80100100, 0x0000), // GPP_K15_INTP_OUT
|
||||
PAD_CFG_GPI(GPP_K16, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_K17, NONE, DEEP), // NC
|
||||
PAD_CFG_TERM_GPO(GPP_K18, 1, NONE, DEEP), // GPP_K18_TBT_WAKE#
|
||||
_PAD_CFG_STRUCT(GPP_K19, 0x42800101, 0x0000), // SMI#_GPP_K19
|
||||
PAD_CFG_GPI(GPP_K20, NONE, DEEP), // NC
|
||||
PAD_CFG_GPI(GPP_K21, NONE, DEEP), // NC
|
||||
_PAD_CFG_STRUCT(GPP_K22, 0x44000101, 0x0000), // NC
|
||||
PAD_CFG_GPI(GPP_K23, NONE, DEEP), // NC
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
30
src/mainboard/system76/addw1/hda_verb.c
Normal file
30
src/mainboard/system76/addw1/hda_verb.c
Normal file
@ -0,0 +1,30 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek, ALC1220 */
|
||||
0x10ec1220, /* Vendor ID */
|
||||
0x155865d1, /* Subsystem ID */
|
||||
12, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x155865d1),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x0421101f),
|
||||
AZALIA_PIN_CFG(0, 0x15, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x04a11040),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x04451150),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {
|
||||
// Enable DMIC microphone on ALC1220
|
||||
0x02050036,
|
||||
0x02042a6a,
|
||||
};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
10
src/mainboard/system76/addw1/ramstage.c
Normal file
10
src/mainboard/system76/addw1/ramstage.c
Normal file
@ -0,0 +1,10 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <soc/ramstage.h>
|
||||
#include "gpio.h"
|
||||
|
||||
void mainboard_silicon_init_params(FSP_S_CONFIG *params) {
|
||||
/* Configure pads prior to SiliconInit() in case there's any
|
||||
* dependencies during hardware initialization. */
|
||||
cnl_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
|
||||
}
|
||||
87
src/mainboard/system76/addw1/romstage.c
Normal file
87
src/mainboard/system76/addw1/romstage.c
Normal file
@ -0,0 +1,87 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <soc/cnl_memcfg_init.h>
|
||||
#include <soc/romstage.h>
|
||||
|
||||
static const struct cnl_mb_cfg memcfg = {
|
||||
/* Parameters required to access SPD for CH0D0/CH0D1/CH1D0/CH1D1. */
|
||||
.spd[0] = {
|
||||
.read_type = READ_SMBUS,
|
||||
.spd_spec = {.spd_smbus_address = 0xa0},
|
||||
},
|
||||
.spd[1] = {.read_type = NOT_EXISTING},
|
||||
.spd[2] = {
|
||||
.read_type = READ_SMBUS,
|
||||
.spd_spec = {.spd_smbus_address = 0xa4},
|
||||
},
|
||||
.spd[3] = {.read_type = NOT_EXISTING},
|
||||
|
||||
/*
|
||||
* For each channel, there are 3 sets of DQ byte mappings,
|
||||
* where each set has a package 0 and a package 1 value (package 0
|
||||
* represents the first 64-bit lpddr4 chip combination, and package 1
|
||||
* represents the second 64-bit lpddr4 chip combination).
|
||||
* The first three sets are for CLK, CMD, and CTL.
|
||||
* The fsp package actually expects 6 sets, but the last 3 sets are
|
||||
* not used in CNL, so we only define the three sets that are used
|
||||
* and let the meminit_lpddr4() routine take care of clearing the
|
||||
* unused fields for the caller.
|
||||
*/
|
||||
.dq_map[DDR_CH0] = {
|
||||
{0x0F, 0xF0}, {0x00, 0xF0}, {0x0F, 0xF0},
|
||||
//{0x0F, 0x00}, {0xFF, 0x00}, {0xFF, 0x00}
|
||||
},
|
||||
.dq_map[DDR_CH1] = {
|
||||
{0x33, 0xCC}, {0x00, 0xCC}, {0x33, 0xCC},
|
||||
//{0x33, 0x00}, {0xFF, 0x00}, {0xFF, 0x00}
|
||||
},
|
||||
|
||||
/*
|
||||
* DQS CPU<>DRAM map Ch0 and Ch1. Each array entry represents a
|
||||
* mapping of a dq bit on the CPU to the bit it's connected to on
|
||||
* the memory part. The array index represents the dqs bit number
|
||||
* on the memory part, and the values in the array represent which
|
||||
* pin on the CPU that DRAM pin connects to.
|
||||
*/
|
||||
.dqs_map[DDR_CH0] = {0, 1, 2, 3, 4, 5, 6, 7},
|
||||
.dqs_map[DDR_CH1] = {0, 1, 2, 3, 4, 5, 6, 7},
|
||||
|
||||
/*
|
||||
* Rcomp resistor values. These values represent the resistance in
|
||||
* ohms of the three rcomp resistors attached to the DDR_COMP_0,
|
||||
* DDR_COMP_1, and DDR_COMP_2 pins on the DRAM.
|
||||
*/
|
||||
.rcomp_resistor = { 121, 75, 100 },
|
||||
|
||||
/*
|
||||
* Rcomp target values. These will typically be the following
|
||||
* values for Cannon Lake : { 80, 40, 40, 40, 30 }
|
||||
*/
|
||||
.rcomp_targets = { 50, 25, 20, 20, 26 },
|
||||
|
||||
/*
|
||||
* Indicates whether memory is interleaved.
|
||||
* Set to 1 for an interleaved design,
|
||||
* set to 0 for non-interleaved design.
|
||||
*/
|
||||
.dq_pins_interleaved = 1,
|
||||
|
||||
/*
|
||||
* VREF_CA configuration.
|
||||
* Set to 0 VREF_CA goes to both CH_A and CH_B,
|
||||
* set to 1 VREF_CA goes to CH_A and VREF_DQ_A goes to CH_B,
|
||||
* set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B.
|
||||
*/
|
||||
.vref_ca_config = 2,
|
||||
|
||||
/* Early Command Training */
|
||||
.ect = 0,
|
||||
};
|
||||
|
||||
void mainboard_memory_init_params(FSPM_UPD *memupd) {
|
||||
// Allow memory clocks higher than 2933 MHz
|
||||
memupd->FspmConfig.SaOcSupport = 1;
|
||||
// Set primary display to internal graphics
|
||||
memupd->FspmConfig.PrimaryDisplay = 0;
|
||||
cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
|
||||
}
|
||||
4367
src/mainboard/system76/addw1/tas5825m.c
Normal file
4367
src/mainboard/system76/addw1/tas5825m.c
Normal file
File diff suppressed because it is too large
Load Diff
Loading…
x
Reference in New Issue
Block a user