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mb/google/cyan: Fix variant GPIOs

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- set GPSE-77 (Maxim jack detect) to NC for variants using Realtek audio
- set GPSW-37 to NC for all variants (not used for LPE audio)
- set GPSW-95 (Realtek jack detect) to NC for variant using Maxim audio
- set GPSE-77 as maskable on variant using Maxim audio, to match mask setting
  for jack detect GPIO on other variants
- set GPSE-81 as maskable on CELES to prevent interrupt storm (likely due to
  change in cherryview pinctrl driver circa kernel v3.18  which no longer masks
  all interrupts at init)

Change-Id: I50d4b3516eba8906042bb8dea768b229afcf11ea
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: CoolStar Organization <coolstarorganization@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Matt DeVillier
2021-12-22 10:00:57 -06:00
committed by Felix Held
parent 2aef22f6fb
commit 84d4ccde79
11 changed files with 20 additions and 37 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
src/mainboard/google/cyan/variants/banon/gpio.c
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@@ -51,8 +51,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = {
GPIO_NC, /* 69 MMC1_RCLK */
Native_M1, /* 75 GPO USB_OC1_B */
Native_M1, /* 76 PMU_RESETBUTTON_B */
GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA),
/* GPIO_ALERT 77 */
GPIO_NC, /* GPIO_ALERT 77 */
GPIO_NC, /* 78 SDMMC3_PWR_EN_B */
GPIO_NC, /* 79 GPI ILB_SERIRQ */
Native_M1, /* 80 USB_OC0_B */

8
src/mainboard/google/cyan/variants/celes/gpio.c
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@@ -51,12 +51,11 @@ static const struct soc_gpio_map gpse_gpio_map[] = {
GPIO_NC, /* 69 MMC1_RCLK */
Native_M1, /* 75 GPO USB_OC1_B */
Native_M1, /* 76 PMU_RESETBUTTON_B */
GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA),
/* GPIO_ALERT 77 */
GPIO_NC, /* GPIO_ALERT 77 */
Native_M1, /* 78 SDMMC3_PWR_EN_B */
GPIO_NC, /* 79 GPI ILB_SERIRQ */
Native_M1, /* 80 USB_OC0_B */
GPI(trig_edge_both, L1, P_20K_H, non_maskable,
GPI(trig_edge_both, L1, P_20K_H, maskable,
en_edge_detect, NA, NA),
/* 81 SDMMC3_CD_B */
GPIO_NC, /* 82 spkr assumed gpio number */
@@ -92,8 +91,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = {
/* 34 MF_HDA_DOCKRSTB */
GPIO_NC, /* 35 MF_HDA_SYNC */
GPIO_NC, /* 36 GPIO_SW36 MF_HDA_SDI1 */
GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA),
/* 37 MF_HDA_DOCKENB */
GPIO_NC, /* 37 MF_HDA_DOCKENB */
NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */
NATIVE_PU1K_CSEN_INVTX(1), /* 46 I2C4_SDA */
NATIVE_PU1K_CSEN_INVTX(1), /* 47 I2C6_SDA */

10
src/mainboard/google/cyan/variants/cyan/gpio.c
View File

@@ -51,8 +51,8 @@ static const struct soc_gpio_map gpse_gpio_map[] = {
GPIO_NC, /* 69 MMC1_RCLK */
Native_M1, /* 75 GPO USB_OC1_B */
Native_M1, /* 76 PMU_RESETBUTTON_B */
GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA),
/* GPIO_ALERT 77 */
GPI(trig_edge_both, L0, NA, 0, en_edge_detect, NA, NA),
/* GPIO_ALERT 77 */
Native_M1, /* 78 SDMMC3_PWR_EN_B */
GPIO_NC, /* 79 GPI ILB_SERIRQ */
Native_M1, /* 80 USB_OC0_B */
@@ -90,8 +90,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = {
/* 34 MF_HDA_DOCKRSTB */
GPIO_NC, /* 35 MF_HDA_SYNC */
GPIO_NC, /* 36 GPIO_SW36 MF_HDA_SDI1 */
GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA),
/* 37 MF_HDA_DOCKENB */
GPIO_NC, /* 37 MF_HDA_DOCKENB */
NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */
GPIO_NC, /* 46 I2C4_SDA */
NATIVE_PU20K(2), /* 47 I2C6_SDA */
@@ -124,8 +123,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = {
assert it low. */
GPIO_OUT_LOW, /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */
Native_M1, /* 94 GP_SSP_2_RXD */
GPI(trig_edge_both, L1, P_5K_H, 0, en_edge_detect, NA, NA),
/* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */
GPIO_NC, /* 95 RTK_AUDIO_CODEC_IRQ */
Native_M1, /* 96 GP_SSP_2_FS */
NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */
GPIO_END

3
src/mainboard/google/cyan/variants/edgar/gpio.c
View File

@@ -51,8 +51,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = {
GPIO_NC, /* 69 MMC1_RCLK */
Native_M1, /* 75 GPO USB_OC1_B */
Native_M1, /* 76 PMU_RESETBUTTON_B */
GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA),
/* GPIO_ALERT 77 */
GPIO_NC, /* GPIO_ALERT 77 */
Native_M1, /* 78 SDMMC3_PWR_EN_B */
GPIO_NC, /* 79 GPI ILB_SERIRQ */
Native_M1, /* 80 USB_OC0_B */

3
src/mainboard/google/cyan/variants/kefka/gpio.c
View File

@@ -51,8 +51,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = {
GPIO_NC, /* 69 MMC1_RCLK */
Native_M1, /* 75 GPO USB_OC1_B */
Native_M1, /* 76 PMU_RESETBUTTON_B */
GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA),
/* GPIO_ALERT 77 */
GPIO_NC, /* GPIO_ALERT 77 */
Native_M1, /* 78 SDMMC3_PWR_EN_B */
GPIO_NC, /* 79 GPI ILB_SERIRQ */
Native_M1, /* 80 USB_OC0_B */

6
src/mainboard/google/cyan/variants/reks/gpio.c
View File

@@ -51,8 +51,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = {
GPIO_NC, /* 69 MMC1_RCLK */
Native_M1, /* 75 GPO USB_OC1_B */
Native_M1, /* 76 PMU_RESETBUTTON_B */
GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA),
/* GPIO_ALERT 77 */
GPIO_NC, /* GPIO_ALERT 77 */
Native_M1, /* 78 SDMMC3_PWR_EN_B */
GPIO_NC, /* 79 GPI ILB_SERIRQ */
Native_M1, /* 80 USB_OC0_B */
@@ -90,8 +89,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = {
/* 34 MF_HDA_DOCKRSTB */
GPIO_NC, /* 35 MF_HDA_SYNC */
GPIO_NC, /* 36 GPIO_SW36 MF_HDA_SDI1 */
GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA),
/* 37 MF_HDA_DOCKENB */
GPIO_NC, /* 37 MF_HDA_DOCKENB */
NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */
NATIVE_PU1K_CSEN_INVTX(1), /* 46 I2C4_SDA */
NATIVE_PU20K(2), /* 47 I2C6_SDA */

6
src/mainboard/google/cyan/variants/relm/gpio.c
View File

@@ -51,8 +51,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = {
GPIO_NC, /* 69 MMC1_RCLK */
Native_M1, /* 75 GPO USB_OC1_B */
Native_M1, /* 76 PMU_RESETBUTTON_B */
GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA),
/* GPIO_ALERT 77 */
GPIO_NC, /* GPIO_ALERT 77 */
Native_M1, /* 78 SDMMC3_PWR_EN_B */
GPIO_NC, /* 79 GPI ILB_SERIRQ */
Native_M1, /* 80 USB_OC0_B */
@@ -90,8 +89,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = {
/* 34 MF_HDA_DOCKRSTB */
GPIO_NC, /* 35 MF_HDA_SYNC */
GPIO_NC, /* 36 GPIO_SW36 MF_HDA_SDI1 */
GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA),
/* 37 MF_HDA_DOCKENB */
GPIO_NC, /* 37 MF_HDA_DOCKENB */
NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */
NATIVE_PU1K_CSEN_INVTX(1), /* 46 I2C4_SDA */
NATIVE_PU20K(2), /* 47 I2C6_SDA */

3
src/mainboard/google/cyan/variants/setzer/gpio.c
View File

@@ -51,8 +51,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = {
GPIO_NC, /* 69 MMC1_RCLK */
Native_M1, /* 75 GPO USB_OC1_B */
Native_M1, /* 76 PMU_RESETBUTTON_B */
GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA),
/* GPIO_ALERT 77 */
GPIO_NC, /* GPIO_ALERT 77 */
Native_M1, /* 78 SDMMC3_PWR_EN_B */
GPIO_NC, /* 79 GPI ILB_SERIRQ */
Native_M1, /* 80 USB_OC0_B */

3
src/mainboard/google/cyan/variants/terra/gpio.c
View File

@@ -51,8 +51,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = {
GPIO_NC, /* 69 MMC1_RCLK */
Native_M1, /* 75 GPO USB_OC1_B */
Native_M1, /* 76 PMU_RESETBUTTON_B */
GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA),
/* GPIO_ALERT 77 */
GPIO_NC, /* GPIO_ALERT 77 */
Native_M1, /* 78 SDMMC3_PWR_EN_B */
GPIO_NC, /* 79 GPI ILB_SERIRQ */
Native_M1, /* 80 USB_OC0_B */

6
src/mainboard/google/cyan/variants/ultima/gpio.c
View File

@@ -51,8 +51,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = {
GPIO_NC, /* 69 MMC1_RCLK */
Native_M1, /* 75 GPO USB_OC1_B */
Native_M1, /* 76 PMU_RESETBUTTON_B */
GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA),
/* GPIO_ALERT 77 */
GPIO_NC, /* GPIO_ALERT 77 */
Native_M1, /* 78 SDMMC3_PWR_EN_B */
GPIO_NC, /* 79 GPI ILB_SERIRQ */
Native_M1, /* 80 USB_OC0_B */
@@ -90,8 +89,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = {
/* 34 MF_HDA_DOCKRSTB */
GPIO_NC, /* 35 MF_HDA_SYNC */
GPIO_NC, /* 36 GPIO_SW36 MF_HDA_SDI1 */
GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA),
/* 37 MF_HDA_DOCKENB */
GPIO_NC, /* 37 MF_HDA_DOCKENB */
NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */
NATIVE_PU1K_CSEN_INVTX(1), /* 46 I2C4_SDA */
NATIVE_PU20K(2), /* 47 I2C6_SDA */

6
src/mainboard/google/cyan/variants/wizpig/gpio.c
View File

@@ -51,8 +51,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = {
GPIO_NC, /* 69 MMC1_RCLK */
Native_M1, /* 75 GPO USB_OC1_B */
Native_M1, /* 76 PMU_RESETBUTTON_B */
GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA),
/* GPIO_ALERT 77 */
GPIO_NC, /* GPIO_ALERT 77 */
Native_M1, /* 78 SDMMC3_PWR_EN_B */
GPIO_NC, /* 79 GPI ILB_SERIRQ */
Native_M1, /* 80 USB_OC0_B */
@@ -90,8 +89,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = {
/* 34 MF_HDA_DOCKRSTB */
GPIO_NC, /* 35 MF_HDA_SYNC */
GPIO_NC, /* 36 GPIO_SW36 MF_HDA_SDI1 */
GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA),
/* 37 MF_HDA_DOCKENB */
GPIO_NC, /* 37 MF_HDA_DOCKENB */
NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */
NATIVE_PU1K_CSEN_INVTX(1), /* 46 I2C4_SDA */
NATIVE_PU1K_CSEN_INVTX(1), /* 47 I2C6_SDA */