src: Remove unused 'include <stdint.h>

Found using:
diff <(git grep -l '#include <stdint.h>' -- src/) <(git grep -l 'int8_t\|int16_t\|int32_t\|int64_t\|intptr_t\|intmax_t\|s8\|u8\|s16\|u16\|s32\|u32\|s64\|u64\|INT8_MIN\|INT8_MAX\|INT16_MIN\|INT16_MAX\|INT32_MIN\|INT32_MAX\|INT64_MIN\|INT64_MAX\|INTMAX_MIN\|INTMAX_MAX' -- src/) |grep -v vendorcode |grep '<'

Change-Id: I5e14bf4887c7d2644a64f4d58c6d8763eb74d2ed
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41827
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/arch/arm/include/armv4/arch/cache.h

@@ -7,7 +7,6 @@
 #define ARM_CACHE_H
 
 #include <stddef.h>
-#include <stdint.h>
 
 /*
  * Cache maintenance API

src/arch/arm64/include/armv8/arch/cache.h

@@ -11,7 +11,6 @@
 #ifndef __ASSEMBLER__
 
 #include <stddef.h>
-#include <stdint.h>
 #include <arch/barrier.h>
 
 /* dcache clean by virtual address to PoC */

src/arch/x86/include/arch/ebda.h

@@ -3,7 +3,6 @@
 #ifndef __ARCH_EBDA_H
 #define __ARCH_EBDA_H
 
-#include <stdint.h>
 #include <stddef.h>
 
 #define X86_BDA_SIZE		0x200

src/commonlib/include/commonlib/region.h

@@ -4,7 +4,6 @@
 #define _REGION_H_
 
 #include <sys/types.h>
-#include <stdint.h>
 #include <stddef.h>
 #include <stdbool.h>
 #include <commonlib/mem_pool.h>

src/drivers/i2c/rt1011/chip.h

@@ -4,7 +4,6 @@
  * Realtek RT1011 audio codec devicetree bindings
  */
 
-#include <stdint.h>
 
 struct drivers_i2c_rt1011_config {
 	const char *name; /* ACPI Device Name */

src/drivers/intel/fsp1_1/include/fsp/car.h

@@ -4,7 +4,6 @@
 #define FSP1_1_CAR_H
 
 #include <fsp/api.h>
-#include <stdint.h>
 
 /* Per stage calls from the above two functions. The void * return from
  * cache_as_ram_stage_main() is the stack pointer to use in RAM after

src/drivers/intel/ptt/ptt.h

@@ -8,7 +8,6 @@
  * is still in the preboot phase.
  *
  */
-#include <stdint.h>
 /*
  * ptt_active
  *

src/drivers/intel/soundwire/soundwire.c

@@ -8,7 +8,6 @@
 #include <device/path.h>
 #include <device/soundwire.h>
 #include <stdbool.h>
-#include <stdint.h>
 
 #include "soundwire.h"
 #include "chip.h"

src/mainboard/google/slippy/variants/falco/romstage.c

@@ -1,7 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <stddef.h>
-#include <stdint.h>
 #include <string.h>
 #include <cbfs.h>
 #include <console/console.h>

src/mainboard/google/slippy/variants/leon/romstage.c

@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <stdint.h>
 #include <string.h>
 #include <cbfs.h>
 #include <console/console.h>

src/mainboard/google/slippy/variants/wolf/romstage.c

@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <stdint.h>
 #include <string.h>
 #include <cbfs.h>
 #include <console/console.h>

src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/variants.h

@@ -4,7 +4,6 @@
 #define __BASEBOARD_VARIANTS_H__
 
 #include <soc/gpio.h>
-#include <stdint.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
 /* The next set of functions return the gpio table and fill in the number of

src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/variants.h

@@ -5,7 +5,6 @@
 
 #include <soc/cnl_memcfg_init.h>
 #include <soc/gpio.h>
-#include <stdint.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
 /* The next set of functions return the gpio table and fill in the number of

src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/variants.h

@@ -5,7 +5,6 @@
 
 #include <soc/gpio.h>
 #include <soc/meminit.h>
-#include <stdint.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
 /**

src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h

@@ -4,7 +4,6 @@
 #define __BASEBOARD_VARIANTS_H__
 
 #include <soc/gpio.h>
-#include <stdint.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
 /* The next set of functions return the gpio table and fill in the number of

src/mainboard/intel/jasperlake_rvp/board_id.h

@@ -3,7 +3,6 @@
 #ifndef _MAINBOARD_COMMON_BOARD_ID_H_
 #define _MAINBOARD_COMMON_BOARD_ID_H_
 
-#include <stdint.h>
 
 /* Board/FAB ID Command */
 #define EC_FAB_ID_CMD	0x0D

src/mainboard/intel/tglrvp/board_id.h

@@ -3,7 +3,6 @@
 #ifndef _MAINBOARD_COMMON_BOARD_ID_H_
 #define _MAINBOARD_COMMON_BOARD_ID_H_
 
-#include <stdint.h>
 
 /* Board/FAB ID Command */
 #define EC_FAB_ID_CMD	0x0D

src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h

@@ -5,7 +5,6 @@
 
 #include <soc/gpio.h>
 #include <soc/meminit.h>
-#include <stdint.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
 /* The next set of functions return the gpio table and fill in the number of

src/northbridge/intel/sandybridge/romstage.c

@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <stdint.h>
 #include <console/console.h>
 #include <cf9_reset.h>
 #include <device/pci_ops.h>

src/security/memory/memory.h

@@ -1,5 +1,4 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <stdint.h>
 
 bool security_clear_dram_request(void);

src/security/vboot/vboot_common.h

@@ -3,7 +3,6 @@
 #define __VBOOT_VBOOT_COMMON_H__
 
 #include <commonlib/region.h>
-#include <stdint.h>
 #include <vb2_api.h>
 
 /*

src/soc/amd/common/block/include/amdblocks/agesawrapper.h

@@ -3,7 +3,6 @@
 #ifndef __AGESAWRAPPER_H__
 #define __AGESAWRAPPER_H__
 
-#include <stdint.h>
 #include <agesa_headers.h>
 
 enum {

src/soc/amd/common/block/include/amdblocks/s3_resume.h

@@ -3,7 +3,6 @@
 #ifndef __AMD_S3_RESUME_H__
 #define __AMD_S3_RESUME_H__
 
-#include <stdint.h>
 #include <agesa_headers.h>
 
 AGESA_STATUS OemInitResume(S3_DATA_BLOCK *dataBlock);

src/soc/amd/picasso/psp_verstage/printk.c

@@ -4,7 +4,6 @@
 #include <console/console.h>
 #include <console/streams.h>
 #include <stdarg.h>
-#include <stdint.h>
 
 void console_hw_init(void)
 {

src/soc/amd/picasso/psp_verstage/reset.c

@@ -3,8 +3,6 @@
 #include <bl_uapp/bl_syscall_public.h>
 #include <console/console.h>
 #include <reset.h>
-#include <stdint.h>
-
 
 void do_board_reset(void)
 {

src/soc/intel/baytrail/include/soc/romstage.h

@@ -3,7 +3,6 @@
 #ifndef _BAYTRAIL_ROMSTAGE_H_
 #define _BAYTRAIL_ROMSTAGE_H_
 
-#include <stdint.h>
 #include <soc/mrc_wrapper.h>
 
 void mainboard_fill_mrc_params(struct mrc_params *mp);

src/soc/intel/braswell/include/soc/romstage.h

@@ -3,7 +3,6 @@
 #ifndef _SOC_ROMSTAGE_H_
 #define _SOC_ROMSTAGE_H_
 
-#include <stdint.h>
 #include <fsp/romstage.h>
 #include <fsp/util.h>
 #include <soc/pm.h>

src/soc/intel/broadwell/include/soc/romstage.h

@@ -3,7 +3,6 @@
 #ifndef _BROADWELL_ROMSTAGE_H_
 #define _BROADWELL_ROMSTAGE_H_
 
-#include <stdint.h>
 #include <soc/pei_data.h>
 
 struct chipset_power_state;

src/soc/intel/cannonlake/include/soc/pch.h

@@ -3,7 +3,6 @@
 #ifndef _SOC_CANNONLAKE_PCH_H_
 #define _SOC_CANNONLAKE_PCH_H_
 
-#include <stdint.h>
 
 #define PCH_H				1
 #define PCH_LP				2

src/soc/intel/common/block/include/intelblocks/pcie_rp.h

@@ -3,7 +3,6 @@
 #ifndef SOC_INTEL_COMMON_BLOCK_PCIE_RP_H
 #define SOC_INTEL_COMMON_BLOCK_PCIE_RP_H
 
-#include <stdint.h>
 
 /*
  * The PCIe Root Ports usually come in groups of up to 8 PCI-device

src/soc/intel/common/block/smbus/smbuslib.h

@@ -3,7 +3,6 @@
 #ifndef SOC_INTEL_COMMON_BLOCK_SMBUS__LIB_H
 #define SOC_INTEL_COMMON_BLOCK_SMBUS__LIB_H
 
-#include <stdint.h>
 
 /* SMBus IO Base Address */
 #define SMBUS_IO_BASE	0xefa0

src/soc/intel/common/mma.h

@@ -3,7 +3,6 @@
 #ifndef _SOC_MMA_H_
 #define _SOC_MMA_H_
 
-#include <stdint.h>
 #include <commonlib/region.h>
 
 struct mma_config_param {

src/soc/intel/common/pch/include/intelpch/lockdown.h

@@ -3,7 +3,6 @@
 #ifndef SOC_INTEL_COMMON_PCH_LOCKDOWN_H
 #define SOC_INTEL_COMMON_PCH_LOCKDOWN_H
 
-#include <stdint.h>
 
 /*
  * This function will get lockdown config specific to soc.

src/soc/intel/icelake/include/soc/pch.h

@@ -3,7 +3,6 @@
 #ifndef _SOC_ICELAKE_PCH_H_
 #define _SOC_ICELAKE_PCH_H_
 
-#include <stdint.h>
 
 #define PCH_H				1
 #define PCH_LP				2

src/soc/intel/jasperlake/include/soc/espi.h

@@ -3,7 +3,6 @@
 #ifndef _SOC_JASPERLAKE_ESPI_H_
 #define _SOC_JASPERLAKE_ESPI_H_
 
-#include <stdint.h>
 
 /* PCI Configuration Space (D31:F0): ESPI */
 #define SCI_IRQ_SEL		(7 << 0)

src/soc/intel/jasperlake/include/soc/pch.h

@@ -3,7 +3,6 @@
 #ifndef _SOC_JASPERLAKE_PCH_H_
 #define _SOC_JASPERLAKE_PCH_H_
 
-#include <stdint.h>
 
 #define PCIE_CLK_NOTUSED		0xFF
 #define PCIE_CLK_LAN			0x70

src/soc/intel/jasperlake/me.c

@@ -4,7 +4,6 @@
 #include <intelblocks/cse.h>
 #include <console/console.h>
 #include <soc/me.h>
-#include <stdint.h>
 
 static void dump_me_status(void *unused)
 {

src/soc/intel/tigerlake/include/soc/espi.h

@@ -9,7 +9,6 @@
 #ifndef _SOC_TIGERLAKE_ESPI_H_
 #define _SOC_TIGERLAKE_ESPI_H_
 
-#include <stdint.h>
 
 /* PCI Configuration Space (D31:F0): ESPI */
 #define SCI_IRQ_SEL		(7 << 0)

src/soc/intel/tigerlake/include/soc/pch.h

@@ -3,7 +3,6 @@
 #ifndef _SOC_TIGERLAKE_PCH_H_
 #define _SOC_TIGERLAKE_PCH_H_
 
-#include <stdint.h>
 
 #define PCIE_CLK_NOTUSED		0xFF
 #define PCIE_CLK_LAN			0x70

src/soc/mediatek/mt8173/include/soc/addressmap.h

@@ -4,7 +4,6 @@
 #define __SOC_MEDIATEK_MT8173_INCLUDE_SOC_ADDRESS_MAP_H__
 
 #include <stddef.h>
-#include <stdint.h>
 
 enum {
 	VER_BASE	= 0x08000000,

src/soc/nvidia/tegra/usb.h

@@ -3,7 +3,6 @@
 #ifndef __SOC_NVIDIA_TEGRA_USB_H__
 #define __SOC_NVIDIA_TEGRA_USB_H__
 
-#include <stdint.h>
 
 enum usb_phy_type {		/* For use in lpm_ctrl[31:29] */
 	USB_PHY_UTMIP = 0,

src/soc/nvidia/tegra124/include/soc/gpio.h

@@ -5,7 +5,6 @@
 
 #include <soc/nvidia/tegra/gpio.h>
 #include <soc/pinmux.h>	/* for pinmux constants in GPIO macro */
-#include <stdint.h>
 
 /* GPIO index constants. */
 

src/soc/nvidia/tegra124/include/soc/pingroup.h

@@ -4,7 +4,6 @@
 #define __SOC_NVIDIA_TEGRA124_PINGROUP_H__
 
 #include <soc/nvidia/tegra/pingroup.h>
-#include <stdint.h>
 
 enum {
 	PINGROUP_AO1_INDEX = 0,		/* offset 0x868 */

src/soc/nvidia/tegra124/include/soc/pinmux.h

@@ -4,7 +4,6 @@
 #define __SOC_NVIDIA_TEGRA124_PINMUX_H__
 
 #include <soc/nvidia/tegra/pinmux.h>
-#include <stdint.h>
 
 enum {
 	PINMUX_FUNC_MASK = 3 << 0,

src/soc/nvidia/tegra210/include/soc/ccplex.h

@@ -3,7 +3,6 @@
 #ifndef __SOC_NVIDIA_TEGRA210_CCPLEX_H__
 #define __SOC_NVIDIA_TEGRA210_CCPLEX_H__
 
-#include <stdint.h>
 
 #define MTS_LOAD_ADDRESS 0x82000000
 

src/soc/nvidia/tegra210/include/soc/pinmux.h

@@ -3,7 +3,6 @@
 #ifndef __SOC_NVIDIA_TEGRA210_PINMUX_H__
 #define __SOC_NVIDIA_TEGRA210_PINMUX_H__
 
-#include <stdint.h>
 #include <soc/nvidia/tegra/gpio.h>
 #include <soc/nvidia/tegra/pinmux.h>
 

src/soc/qualcomm/qcs405/include/soc/addressmap.h

@@ -3,7 +3,6 @@
 #ifndef __SOC_QUALCOMM_QCS405_ADDRESS_MAP_H__
 #define __SOC_QUALCOMM_QCS405_ADDRESS_MAP_H__
 
-#include <stdint.h>
 
 #define QSPI_BASE			0x88DF000
 #define TLMM_EAST_TILE_BASE		0x7B00000

src/soc/qualcomm/sc7180/include/soc/addressmap.h

@@ -3,7 +3,6 @@
 #ifndef _SOC_QUALCOMM_SC7180_ADDRESS_MAP_H_
 #define _SOC_QUALCOMM_SC7180_ADDRESS_MAP_H_
 
-#include <stdint.h>
 
 #define AOSS_CC_BASE			0x0C2A0000
 #define GCC_BASE			0x00100000

src/soc/qualcomm/sdm845/include/soc/addressmap.h

@@ -3,7 +3,6 @@
 #ifndef __SOC_QUALCOMM_SDM845_ADDRESS_MAP_H__
 #define __SOC_QUALCOMM_SDM845_ADDRESS_MAP_H__
 
-#include <stdint.h>
 
 #define QSPI_BASE			0x88DF000
 #define TLMM_EAST_TILE_BASE             0x03500000

src/southbridge/amd/cimx/sb800/cfg.h

@@ -1,11 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-
 #ifndef _SB800_CFG_H_
 #define _SB800_CFG_H_
 
-#include <stdint.h>
-
 /**
  * @brief South Bridge CIMx configuration
  *