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mb/amd: Drop unneeded empty lines

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Change-Id: Ib82689150689716bc9afdf8d4527a1dcd5deae56
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Elyes HAOUAS 2020-08-19 21:52:49 +02:00 committed by Patrick Georgi
parent d429c1a842
commit 85c681e279
26 changed files with 0 additions and 33 deletions
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2
src/mainboard/amd/gardenia/acpi/routing.asl
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@ -10,7 +10,6 @@ Name(PR0, Package(){
Package(){0x0001FFFF, 0, INTB, 0 }, Package(){0x0001FFFF, 0, INTB, 0 },
Package(){0x0001FFFF, 1, INTC, 0 }, Package(){0x0001FFFF, 1, INTC, 0 },
/* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */ /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */
Package(){0x0002FFFF, 0, INTC, 0 }, Package(){0x0002FFFF, 0, INTC, 0 },
Package(){0x0002FFFF, 1, INTD, 0 }, Package(){0x0002FFFF, 1, INTD, 0 },
@ -70,7 +69,6 @@ Name(APR0, Package(){
Package(){0x0011FFFF, 0, 0, 19 }, Package(){0x0011FFFF, 0, 0, 19 },
}) })
/* GPP 0 */ /* GPP 0 */
Name(PS4, Package(){ Name(PS4, Package(){
Package(){0x0000FFFF, 0, INTA, 0 }, Package(){0x0000FFFF, 0, INTA, 0 },

1
src/mainboard/amd/inagua/OemCustomize.c
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@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <AGESA.h> #include <AGESA.h>
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
#include <PlatformMemoryConfiguration.h> #include <PlatformMemoryConfiguration.h>

1
src/mainboard/amd/inagua/acpi/gpe.asl
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@ -30,7 +30,6 @@ Scope(\_GPE) { /* Start Scope GPE */
/* DBGO("\\_GPE\\_L10\n") */ /* DBGO("\\_GPE\\_L10\n") */
} }
/* ExtEvent1 SCI event */ /* ExtEvent1 SCI event */
Method(_L11) { Method(_L11) {
/* DBGO("\\_GPE\\_L11\n") */ /* DBGO("\\_GPE\\_L11\n") */

1
src/mainboard/amd/inagua/acpi/sata.asl
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@ -58,7 +58,6 @@ Device(PMRY)
} /* end of PSLA */ } /* end of PSLA */
} /* end of PMRY */ } /* end of PMRY */
Device(SEDY) Device(SEDY)
{ {
Name(_ADR, 1) /* IDE Scondary Channel */ Name(_ADR, 1) /* IDE Scondary Channel */

1
src/mainboard/amd/inagua/mainboard.c
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@ -31,7 +31,6 @@ static void init_gpios(void)
gpio_100_write8(0x32, 0x48); gpio_100_write8(0x32, 0x48);
} }
/********************************************** /**********************************************
* Enable the dedicated functions of the board. * Enable the dedicated functions of the board.
**********************************************/ **********************************************/

2
src/mainboard/amd/inagua/platform_cfg.h
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@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#ifndef _PLATFORM_CFG_H_ #ifndef _PLATFORM_CFG_H_
#define _PLATFORM_CFG_H_ #define _PLATFORM_CFG_H_
@ -109,7 +108,6 @@
*/ */
#define SATA_PORT_MULT_CAP_RESERVED 1 #define SATA_PORT_MULT_CAP_RESERVED 1
/** /**
* @def AZALIA_AUTO * @def AZALIA_AUTO
* @brief Detect Azalia controller automatically. * @brief Detect Azalia controller automatically.

2
src/mainboard/amd/olivehill/acpi/routing.asl
View File

@ -10,7 +10,6 @@ Name(PR0, Package(){
Package(){0x0001FFFF, 0, INTB, 0 }, Package(){0x0001FFFF, 0, INTB, 0 },
Package(){0x0001FFFF, 1, INTC, 0 }, Package(){0x0001FFFF, 1, INTC, 0 },
/* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */ /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */
Package(){0x0002FFFF, 0, INTC, 0 }, Package(){0x0002FFFF, 0, INTC, 0 },
Package(){0x0002FFFF, 1, INTD, 0 }, Package(){0x0002FFFF, 1, INTD, 0 },
@ -58,7 +57,6 @@ Name(APR0, Package(){
Package(){0x0002FFFF, 2, 0, 26 }, Package(){0x0002FFFF, 2, 0, 26 },
Package(){0x0002FFFF, 3, 0, 27 }, Package(){0x0002FFFF, 3, 0, 27 },
/* SB devices in APIC mode */ /* SB devices in APIC mode */
/* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */
Package(){0x0014FFFF, 0, 0, 16 }, Package(){0x0014FFFF, 0, 0, 16 },

1
src/mainboard/amd/padmelon/acpi/routing.asl
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@ -10,7 +10,6 @@ Name(PR0, Package(){
Package(){0x0001FFFF, 0, INTB, 0 }, Package(){0x0001FFFF, 0, INTB, 0 },
Package(){0x0001FFFF, 1, INTC, 0 }, Package(){0x0001FFFF, 1, INTC, 0 },
/* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */ /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */
Package(){0x0002FFFF, 0, INTC, 0 }, Package(){0x0002FFFF, 0, INTC, 0 },
Package(){0x0002FFFF, 1, INTD, 0 }, Package(){0x0002FFFF, 1, INTD, 0 },

1
src/mainboard/amd/padmelon/bootblock/OemCustomize.c
View File

@ -95,7 +95,6 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
}; };
static const PCIe_DDI_DESCRIPTOR DdiList[] = { static const PCIe_DDI_DESCRIPTOR DdiList[] = {
/* DP0 */ /* DP0 */
{ {

1
src/mainboard/amd/parmer/OemCustomize.c
View File

@ -5,7 +5,6 @@
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
/* /*
* Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping) * Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping)
* *

1
src/mainboard/amd/parmer/acpi/gpe.asl
View File

@ -35,7 +35,6 @@ Scope(\_GPE) { /* Start Scope GPE */
/* DBGO("\\_GPE\\_L10\n") */ /* DBGO("\\_GPE\\_L10\n") */
} }
/* ExtEvent1 SCI event */ /* ExtEvent1 SCI event */
Method(_L11) { Method(_L11) {
/* DBGO("\\_GPE\\_L11\n") */ /* DBGO("\\_GPE\\_L11\n") */

2
src/mainboard/amd/persimmon/OemCustomize.c
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@ -1,11 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <AGESA.h> #include <AGESA.h>
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
#include <PlatformMemoryConfiguration.h> #include <PlatformMemoryConfiguration.h>
static const PCIe_PORT_DESCRIPTOR PortList[] = { static const PCIe_PORT_DESCRIPTOR PortList[] = {
// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
{ {

1
src/mainboard/amd/persimmon/acpi/gpe.asl
View File

@ -30,7 +30,6 @@ Scope(\_GPE) { /* Start Scope GPE */
/* DBGO("\\_GPE\\_L10\n") */ /* DBGO("\\_GPE\\_L10\n") */
} }
/* ExtEvent1 SCI event */ /* ExtEvent1 SCI event */
Method(_L11) { Method(_L11) {
/* DBGO("\\_GPE\\_L11\n") */ /* DBGO("\\_GPE\\_L11\n") */

1
src/mainboard/amd/persimmon/acpi/routing.asl
View File

@ -41,7 +41,6 @@ Scope(\_SB) {
/* Bus 0, Funct 8 - Southbridge port (normally hidden) */ /* Bus 0, Funct 8 - Southbridge port (normally hidden) */
/* SB devices */ /* SB devices */
/* Bus 0, Dev 17 - SATA controller */ /* Bus 0, Dev 17 - SATA controller */
Package(){0x0011FFFF, 0, INTD, 0 }, Package(){0x0011FFFF, 0, INTD, 0 },

1
src/mainboard/amd/persimmon/acpi/sata.asl
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@ -58,7 +58,6 @@ Device(PMRY)
} /* end of PSLA */ } /* end of PSLA */
} /* end of PMRY */ } /* end of PMRY */
Device(SEDY) Device(SEDY)
{ {
Name(_ADR, 1) /* IDE Scondary Channel */ Name(_ADR, 1) /* IDE Scondary Channel */

2
src/mainboard/amd/persimmon/platform_cfg.h
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@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#ifndef _PLATFORM_CFG_H_ #ifndef _PLATFORM_CFG_H_
#define _PLATFORM_CFG_H_ #define _PLATFORM_CFG_H_
@ -109,7 +108,6 @@
*/ */
#define SATA_PORT_MULT_CAP_RESERVED 1 #define SATA_PORT_MULT_CAP_RESERVED 1
/** /**
* @def AZALIA_AUTO * @def AZALIA_AUTO
* @brief Detect Azalia controller automatically. * @brief Detect Azalia controller automatically.

1
src/mainboard/amd/south_station/OemCustomize.c
View File

@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <AGESA.h> #include <AGESA.h>
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
#include <PlatformMemoryConfiguration.h> #include <PlatformMemoryConfiguration.h>

1
src/mainboard/amd/south_station/acpi/gpe.asl
View File

@ -30,7 +30,6 @@ Scope(\_GPE) { /* Start Scope GPE */
/* DBGO("\\_GPE\\_L10\n") */ /* DBGO("\\_GPE\\_L10\n") */
} }
/* ExtEvent1 SCI event */ /* ExtEvent1 SCI event */
Method(_L11) { Method(_L11) {
/* DBGO("\\_GPE\\_L11\n") */ /* DBGO("\\_GPE\\_L11\n") */

1
src/mainboard/amd/south_station/acpi/sata.asl
View File

@ -58,7 +58,6 @@ Device(PMRY)
} /* end of PSLA */ } /* end of PSLA */
} /* end of PMRY */ } /* end of PMRY */
Device(SEDY) Device(SEDY)
{ {
Name(_ADR, 1) /* IDE Scondary Channel */ Name(_ADR, 1) /* IDE Scondary Channel */

2
src/mainboard/amd/south_station/platform_cfg.h
View File

@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#ifndef _PLATFORM_CFG_H_ #ifndef _PLATFORM_CFG_H_
#define _PLATFORM_CFG_H_ #define _PLATFORM_CFG_H_
@ -109,7 +108,6 @@
*/ */
#define SATA_PORT_MULT_CAP_RESERVED 1 #define SATA_PORT_MULT_CAP_RESERVED 1
/** /**
* @def AZALIA_AUTO * @def AZALIA_AUTO
* @brief Detect Azalia controller automatically. * @brief Detect Azalia controller automatically.

1
src/mainboard/amd/thatcher/BiosCallOuts.c
View File

@ -154,7 +154,6 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
} }
} }
void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset) void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset)
{ {
FchParams_reset->LegacyFree = CONFIG(HUDSON_LEGACY_FREE); FchParams_reset->LegacyFree = CONFIG(HUDSON_LEGACY_FREE);

1
src/mainboard/amd/thatcher/OemCustomize.c
View File

@ -5,7 +5,6 @@
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
/* /*
* Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping) * Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping)
* *

1
src/mainboard/amd/thatcher/acpi/gpe.asl
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@ -35,7 +35,6 @@ Scope(\_GPE) { /* Start Scope GPE */
/* DBGO("\\_GPE\\_L10\n") */ /* DBGO("\\_GPE\\_L10\n") */
} }
/* ExtEvent1 SCI event */ /* ExtEvent1 SCI event */
Method(_L11) { Method(_L11) {
/* DBGO("\\_GPE\\_L11\n") */ /* DBGO("\\_GPE\\_L11\n") */

1
src/mainboard/amd/union_station/acpi/gpe.asl
View File

@ -30,7 +30,6 @@ Scope(\_GPE) { /* Start Scope GPE */
/* DBGO("\\_GPE\\_L10\n") */ /* DBGO("\\_GPE\\_L10\n") */
} }
/* ExtEvent1 SCI event */ /* ExtEvent1 SCI event */
Method(_L11) { Method(_L11) {
/* DBGO("\\_GPE\\_L11\n") */ /* DBGO("\\_GPE\\_L11\n") */

1
src/mainboard/amd/union_station/acpi/sata.asl
View File

@ -58,7 +58,6 @@ Device(PMRY)
} /* end of PSLA */ } /* end of PSLA */
} /* end of PMRY */ } /* end of PMRY */
Device(SEDY) Device(SEDY)
{ {
Name(_ADR, 1) /* IDE Scondary Channel */ Name(_ADR, 1) /* IDE Scondary Channel */

2
src/mainboard/amd/union_station/platform_cfg.h
View File

@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#ifndef _PLATFORM_CFG_H_ #ifndef _PLATFORM_CFG_H_
#define _PLATFORM_CFG_H_ #define _PLATFORM_CFG_H_
@ -109,7 +108,6 @@
*/ */
#define SATA_PORT_MULT_CAP_RESERVED 1 #define SATA_PORT_MULT_CAP_RESERVED 1
/** /**
* @def AZALIA_AUTO * @def AZALIA_AUTO
* @brief Detect Azalia controller automatically. * @brief Detect Azalia controller automatically.