mb/google/rex/var/deku: Update DPTF parameters

Adjust settings as recommended by thermal team.

Update DPTF parameters based on b:308704811#comment4.

BUG=b:308704811
BRANCH=firmware-rex-15709.B
TEST=emerge-ovis coreboot chromeos-bootimage
     built bootleg and verified test result by thermal team

Change-Id: I710682771bd0679ae4b44dd43be68f60e8984b2e
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <ericllai@google.com>
This commit is contained in:
Tony Huang
2024-05-14 17:14:48 +08:00
committed by Felix Held
parent 5ba17d5ccb
commit 86028de8d4

View File

@@ -70,6 +70,40 @@ chip soc/intel/meteorlake
device domain 0 on
device ref dtt on
chip drivers/intel/dptf
## sensor information
register "options.tsr[0].desc" = ""DDR_SOC""
register "options.tsr[1].desc" = ""Ambient""
register "options.tsr[2].desc" = ""IMVP_SOC""
register "options.tsr[3].desc" = ""NVME""
## Passive Policy
register "policies.passive" = "{
[0] = DPTF_PASSIVE(CPU, CPU, 65, 1000),
}"
## Critical Policy
register "policies.critical" = "{
[0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
}"
## Power Limits Control
register "controls.power_limits" = "{
.pl1 = {
.min_power = 28000,
.max_power = 28000,
.time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC,
.granularity = 200,
},
.pl2 = {
.min_power = 64000,
.max_power = 64000,
.time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC,
.granularity = 1000,
}
}"
device generic 0 alias dptf_policy on end
end
end