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mb/google/soraka: enable AER for PCIe root port 0

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Enable PCIe Advanced Error Reporting for PCIe root port 0.

Change-Id: I76742801e84449d0910ddadf31d39597df3263b9
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/21402
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Rizwan Qureshi 2017-09-05 14:23:27 +05:30 committed by Aaron Durbin
parent 6ab4ed40d3
commit 8688536ca2
1 changed files with 2 additions and 0 deletions
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src/mainboard/google/poppy/variants/soraka/devicetree.cb
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@ -152,6 +152,8 @@ chip soc/intel/skylake
register "PcieRpClkReqSupport[0]" = "1"
# RP 1 uses SRCCLKREQ1#
register "PcieRpClkReqNumber[0]" = "1"
# RP 1, Enable Advanced Error Reporting
register PcieRpAdvancedErrorReporting[0] = "1"
register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port