Hide MMCONFIG on TGL and set VBT to 8KB

Change-Id: I46d9535266e2ca1946213d899ddecc1b426d2294

src/lib/memrange.c

@@ -252,6 +252,17 @@ static void collect_ranges(void *gp, struct device *dev, struct resource *res)
 	if (res->size == 0)
 		return;
 
+#if CONFIG(SOC_INTEL_TIGERLAKE)
+    if (
+        ctx->tag == 0x10002 && /* BM_MEM_RESERVED */
+        res->base == CONFIG_MMCONF_BASE_ADDRESS &&
+        res->size == CONFIG_SA_PCIEX_LENGTH
+    ) {
+        printk(BIOS_WARNING, "Skipping MMCONF region\n");
+        return;
+    }
+#endif
+
 	if (ctx->filter == NULL || ctx->filter(dev, res))
 		memranges_insert(ctx->ranges, res->base, res->size, ctx->tag);
 }

src/mainboard/system76/galp5/Kconfig

@@ -51,22 +51,6 @@ config CONSOLE_POST
 	bool
 	default y
 
-config DRIVERS_SYSTEM76_DGPU_DEVICE
-	hex
-	default 0x1c
-
-config ONBOARD_VGA_IS_PRIMARY
-	bool
-	default y
-
-config UART_FOR_CONSOLE
-	int
-	default 2
-
-config MAX_CPUS
-	int
-	default 8
-
 config DIMM_MAX
 	int
 	default 4 # Hack to make soc code work
@@ -75,8 +59,28 @@ config DIMM_SPD_SIZE
 	int
 	default 512
 
+config DRIVERS_SYSTEM76_DGPU_DEVICE
+	hex
+	default 0x1c
+
+config MAX_CPUS
+	int
+	default 8
+
+config ONBOARD_VGA_IS_PRIMARY
+	bool
+	default y
+
 config POST_DEVICE
 	bool
 	default n
 
+config VBT_DATA_SIZE_KB
+	int
+	default 8
+
+config UART_FOR_CONSOLE
+	int
+	default 2
+
 endif

src/mainboard/system76/lemp10/Kconfig

@@ -50,14 +50,6 @@ config CONSOLE_POST
 	bool
 	default y
 
-config UART_FOR_CONSOLE
-	int
-	default 2
-
-config MAX_CPUS
-	int
-	default 8
-
 config DIMM_MAX
 	int
 	default 4 # Hack to make soc code work
@@ -66,8 +58,20 @@ config DIMM_SPD_SIZE
 	int
 	default 512
 
+config MAX_CPUS
+	int
+	default 8
+
 config POST_DEVICE
 	bool
 	default n
 
+config VBT_DATA_SIZE_KB
+	int
+	default 8
+
+config UART_FOR_CONSOLE
+	int
+	default 2
+
 endif

src/soc/intel/common/block/acpi/acpi/northbridge.asl

@@ -265,10 +265,12 @@ Device (PDRC)
 			 */
 			Memory32Fixed (ReadWrite, 0, EP_BASE_SIZE, EGPB)
 
+#if !CONFIG(SOC_INTEL_TIGERLAKE)
 			/* PCI Express BAR _BAS and _LEN will be updated in
 			 * _CRS below according to B0:D0:F0:Reg.60h
 			 */
 			Memory32Fixed (ReadWrite, 0, 0, PCIX)
+#endif
 
 			/* VTD engine memory range. */
 			Memory32Fixed (ReadOnly, VTD_BASE_ADDRESS, VTD_BASE_SIZE)
@@ -292,11 +294,13 @@ Device (PDRC)
 		CreateDwordField (BUF0, EGPB._BAS, EBR0)
 		EBR0 = \_SB.PCI0.GEPB ()
 
+#if !CONFIG(SOC_INTEL_TIGERLAKE)
 		CreateDwordField (BUF0, PCIX._BAS, XBR0)
 		XBR0 = \_SB.PCI0.GPCB ()
 
 		CreateDwordField (BUF0, PCIX._LEN, XSZ0)
 		XSZ0 = \_SB.PCI0.GPCL ()
+#endif
 
 		CreateDwordField (BUF0, FIOH._BAS, FBR0)
 		FBR0 = 0x100000000 - CONFIG_ROM_SIZE