ICH4 update, fix ATA init, drop SATA (chipset doesn't have SATA)

fix some PCI IDs, enable USB bus mastering, add some license headers, ...

LPC code needs another look, but I think we're getting there.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Joseph Smith <joe@settoplinux.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5207 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/southbridge/intel/i82801dx/Kconfig

@@ -1,3 +1,24 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008-2009 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of
+## the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+## MA 02110-1301 USA
+##
+
 config SOUTHBRIDGE_INTEL_I82801DX
 	bool
 	select IOAPIC

src/southbridge/intel/i82801dx/Makefile.inc

@@ -1,12 +1,33 @@
-driver-y += i82801dx.o
+##
-driver-y += i82801dx_usb.o
+## This file is part of the coreboot project.
-driver-y += i82801dx_lpc.o
+##
-driver-y += i82801dx_ide.o
+## Copyright (C) 2008-2009 coresystems GmbH
-driver-y += i82801dx_usb2.o
+##
-driver-y += i82801dx_ac97.o
+## This program is free software; you can redistribute it and/or
-#driver-y += i82801dx_nic.o
+## modify it under the terms of the GNU General Public License as
-#driver-y += i82801dx_pci.o
+## published by the Free Software Foundation; version 2 of
-obj-y += i82801dx_reset.o
+## the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+## MA 02110-1301 USA
+##
 
+driver-y += i82801dx.o
+driver-y += i82801dx_ac97.o
+driver-y += i82801dx_ide.o
+driver-y += i82801dx_lpc.o
+#driver-y += i82801dx_pci.o
+driver-y += i82801dx_usb.o
+driver-y += i82801dx_usb2.o
+
+obj-y += i82801dx_reset.o
 obj-$(CONFIG_HAVE_SMI_HANDLER) += i82801dx_smi.o
+
 smmobj-$(CONFIG_HAVE_SMI_HANDLER) += i82801dx_smihandler.o

src/southbridge/intel/i82801dx/chip.h

@@ -1,8 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Eric Biederman
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
 #ifndef I82801DX_CHIP_H
 #define I82801DX_CHIP_H
 
-struct southbridge_intel_i82801dx_config 
+struct southbridge_intel_i82801dx_config {
-{
 	int enable_usb;
 	int enable_native_ide;
 	/**

src/southbridge/intel/i82801dx/cmos_failover.c

@@ -1,13 +1,32 @@
-//kind of cmos_err for ich5
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Ron G. Minnich
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+// kind of cmos_err for ICH4
 #define RTC_FAILED    (1 <<2)
 #define GEN_PMCON_3     0xa4
 static void check_cmos_failed(void)
 {
-
+	u8 byte;
-                uint8_t byte;
+	byte = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
-                byte = pci_read_config8(PCI_DEV(0,0x1f,0),GEN_PMCON_3);
+	if (byte & RTC_FAILED) {
-                if( byte & RTC_FAILED){
+		//clear bit 1 and bit 2
-//clear bit 1 and bit 2
 		byte = cmos_read(RTC_BOOT_BYTE);
 		byte &= 0x0c;
 		byte |= CONFIG_MAX_REBOOT_CNT << 4;

src/southbridge/intel/i82801dx/i82801dx.c

@@ -1,3 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Ron G. Minnich
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -43,15 +63,16 @@ void i82801dx_enable(device_t dev)
 	} else if (PCI_SLOT(dev->path.pci.devfn) == 29) {
 		index = 8 + PCI_FUNC(dev->path.pci.devfn);
 
-		if ((PCI_FUNC(dev->path.pci.devfn) < 3) || (PCI_FUNC(dev->path.pci.devfn) == 7))
+		if ((PCI_FUNC(dev->path.pci.devfn) < 3)
+		    || (PCI_FUNC(dev->path.pci.devfn) == 7))
 			bHasDisableBit = 1;
 	}
 
 	if (bHasDisableBit) {
 		cur_disable_mask = pci_read_config16(lpc_dev, FUNC_DIS);
-		new_disable_mask = cur_disable_mask & ~(1<<index); 		// enable it
+		new_disable_mask = cur_disable_mask & ~(1 << index);	// enable it
 		if (!dev->enabled) {
-			new_disable_mask |= (1<<index);  // disable it
+			new_disable_mask |= (1 << index);	// disable it
 		}
 		if (new_disable_mask != cur_disable_mask) {
 			pci_write_config16(lpc_dev, FUNC_DIS, new_disable_mask);

src/southbridge/intel/i82801dx/i82801dx.h

@@ -1,3 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Ron G. Minnich
+ * Copyright (C) 2004 Eric Biederman
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
 /* the problem: we have 82801dbm support in fb1, and 82801er in fb2. 
  * fb1 code is what we want, fb2 structure is needed however. 
  * so we need to get fb1 code for 82801dbm into fb2 structure. 
@@ -23,15 +45,23 @@ extern void i82801dx_enable(device_t dev);
 #endif
 
 /*
-000 = Non-combined. P0 is primary master. P1 is secondary master.
+ * 000 = Non-combined. P0 is primary master. P1 is secondary master.
-001 = Non-combined. P0 is secondary master. P1 is primary master.
+ * 001 = Non-combined. P0 is secondary master. P1 is primary master.
-100 = Combined. P0 is primary master. P1 is primary slave. IDE is secondary; Primary IDE channel
+ * 100 = Combined. P0 is primary master. P1 is primary slave. IDE is secondary;
-disabled.
+ *       Primary IDE channel disabled.
-101 = Combined. P0 is primary slave. P1 is primary master. IDE is secondary.
+ * 101 = Combined. P0 is primary slave. P1 is primary master. IDE is secondary.
-110 = Combined. IDE is primary. P0 is secondary master. P1 is secondary slave; Secondary IDE
+ * 110 = Combined. IDE is primary. P0 is secondary master. P1 is secondary
-channel disabled.
+ *       slave; Secondary IDE channel disabled.
-111 = Combined. IDE is primary. P0 is secondary slave. P1 is secondary master.
+ * 111 = Combined. IDE is primary. P0 is secondary slave. P1 is secondary master.
-*/
+ */
+/* PCI Configuration Space (D31:F1) */
+#define IDE_TIM_PRI		0x40	/* IDE timings, primary */
+#define IDE_TIM_SEC		0x42	/* IDE timings, secondary */
+
+/* IDE_TIM bits */
+#define IDE_DECODE_ENABLE	(1 << 15)
+
+
 
 #define PCI_DMA_CFG     0x90
 #define SERIRQ_CNTL     0x64

src/southbridge/intel/i82801dx/i82801dx_early_smbus.c

@@ -1,3 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Ronald G. Minnich
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
 
 //#define SMBUS_IO_BASE 0x1000
 //#define SMBUS_IO_BASE 0x0f00
@@ -36,7 +55,6 @@ static void enable_smbus(void)
 	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
 }
 
-
 static inline void smbus_delay(void)
 {
 	outb(0x80, 0x80);
@@ -53,8 +71,8 @@ static int smbus_wait_until_active(void)
 		if ((val & 1)) {
 			break;
 		}
-	} while(--loops);
+	} while (--loops);
-	return loops?0:-4;
+	return loops ? 0 : -4;
 }
 
 static int smbus_wait_until_ready(void)
@@ -68,12 +86,12 @@ static int smbus_wait_until_ready(void)
 		if ((val & 1) == 0) {
 			break;
 		}
-		if(loops == (SMBUS_TIMEOUT / 2)) {
+		if (loops == (SMBUS_TIMEOUT / 2)) {
 			outb(inb(SMBUS_IO_BASE + SMBHSTSTAT),
 			     SMBUS_IO_BASE + SMBHSTSTAT);
 		}
-	} while(--loops);
+	} while (--loops);
-	return loops?0:-2;
+	return loops ? 0 : -2;
 }
 
 static int smbus_wait_until_done(void)
@@ -85,14 +103,14 @@ static int smbus_wait_until_done(void)
 		smbus_delay();
 
 		val = inb(SMBUS_IO_BASE + SMBHSTSTAT);
-		if ( (val & 1) == 0) {
+		if ((val & 1) == 0) {
 			break;
 		}
-		if ((val & ~((1<<6)|(1<<0)) ) != 0 ) {
+		if ((val & ~((1 << 6) | (1 << 0))) != 0) {
 			break;
 		}
-	} while(--loops);
+	} while (--loops);
-	return loops?0:-3;
+	return loops ? 0 : -3;
 }
 
 static int smbus_read_byte(unsigned device, unsigned address)
@@ -101,7 +119,7 @@ static int smbus_read_byte(unsigned device, unsigned address)
 	unsigned char global_status_register;
 	unsigned char byte;
 
-	/*print_err("smbus_read_byte\r\n");*/
+	/*print_err("smbus_read_byte\r\n"); */
 	if (smbus_wait_until_ready() < 0) {
 		print_err_hex8(-2);
 		return -2;
@@ -115,16 +133,18 @@ static int smbus_read_byte(unsigned device, unsigned address)
 	/* set the command/address... */
 	outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
 	/* set up for a byte data read */
-	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2<<2), SMBUS_IO_BASE + SMBHSTCTL);
+	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2 << 2),
+	     SMBUS_IO_BASE + SMBHSTCTL);
 
 	/* clear any lingering errors, so the transaction will run */
 	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
 
-	/* clear the data byte...*/
+	/* clear the data byte... */
 	outb(0, SMBUS_IO_BASE + SMBHSTDAT0);
 
 	/* start a byte read, with interrupts disabled */
-	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL);
+	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40),
+	     SMBUS_IO_BASE + SMBHSTCTL);
 	/* poll for it to start */
 	if (smbus_wait_until_active() < 0) {
 		print_err_hex8(-4);
@@ -137,7 +157,7 @@ static int smbus_read_byte(unsigned device, unsigned address)
 		return -3;
 	}
 
-	global_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT) & ~(1<<6); /* Ignore the In Use Status... */
+	global_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT) & ~(1 << 6);	/* Ignore the In Use Status... */
 
 	/* read results of transaction */
 	byte = inb(SMBUS_IO_BASE + SMBHSTDAT0);
@@ -153,15 +173,17 @@ static int smbus_read_byte(unsigned device, unsigned address)
  */
 	return byte;
 }
+
 #if 0
-static void smbus_write_byte(unsigned device, unsigned address, unsigned char val)
+static void smbus_write_byte(unsigned device, unsigned address,
+			     unsigned char val)
 {
 	if (smbus_wait_until_ready() < 0) {
 		return;
 	}
 
 	/* by LYH */
-	outb(0x37,SMBUS_IO_BASE + SMBHSTSTAT);
+	outb(0x37, SMBUS_IO_BASE + SMBHSTSTAT);
 	/* set the device I'm talking too */
 	outw(((device & 0x7f) << 1) | 0, SMBUS_IO_BASE + SMBHSTADDR);
 

src/southbridge/intel/i82801dx/i82801dx_ide.c

@@ -1,3 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Ronald G. Minnich
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -5,35 +25,37 @@
 #include <device/pci_ops.h>
 #include "i82801dx.h"
 
+typedef struct southbridge_intel_i82801dx_config config_t;
 
 static void ide_init(struct device *dev)
 {
-#if ICH5_SATA_ADDRESS_MAP<=1
+	/* Get the chip configuration */
-	/* Enable ide devices so the linux ide driver will work */
+	config_t *config = dev->chip_info;
-	uint16_t word;
-	uint8_t byte;
-	int enable_a=1, enable_b=1;
 
+	/* Enable IDE devices so the Linux IDE driver will work. */
+	uint16_t ideTimingConfig;
 
-	word = pci_read_config16(dev, 0x40);
+	ideTimingConfig = pci_read_config16(dev, IDE_TIM_PRI);
-	word &= ~((1 << 15));
+	ideTimingConfig &= ~IDE_DECODE_ENABLE;
-	if (enable_a) {
+	if (!config || config->ide0_enable) {
-		/* Enable first ide interface */
+		/* Enable primary IDE interface. */
-		word |= (1<<15);
+		ideTimingConfig |= IDE_DECODE_ENABLE;
-		printk_debug("IDE0 ");
+		printk_debug("IDE0: Primary IDE interface is enabled\n");
+	} else {
+		printk_info("IDE0: Primary IDE interface is disabled\n");
 	}
-	pci_write_config16(dev, 0x40, word);
+	pci_write_config16(dev, IDE_TIM_PRI, ideTimingConfig);
 
-        word = pci_read_config16(dev, 0x42);
+	ideTimingConfig = pci_read_config16(dev, IDE_TIM_SEC);
-        word &= ~((1 << 15));
+	ideTimingConfig &= ~IDE_DECODE_ENABLE;
-        if (enable_b) {
+	if (!config || config->ide1_enable) {
-                /* Enable secondary ide interface */
+		/* Enable secondary IDE interface. */
-                word |= (1<<15);
+		ideTimingConfig |= IDE_DECODE_ENABLE;
-                printk_debug("IDE1 ");
+		printk_debug("IDE1: Secondary IDE interface is enabled\n");
+	} else {
+		printk_info("IDE1: Secondary IDE interface is disabled\n");
 	}
-        pci_write_config16(dev, 0x42, word);
+	pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig);
-#endif
-
 }
 
 static struct device_operations ide_ops = {
@@ -45,9 +67,16 @@ static struct device_operations ide_ops  = {
 	.enable = i82801dx_enable,
 };
 
-static const struct pci_driver ide_driver __pci_driver = {
+/* 82801DB */
+static const struct pci_driver i82801db_ide __pci_driver = {
 	.ops = &ide_ops,
 	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_82801DBM_IDE,
+	.device = 0x24cb,
 };
 
+/* 82801DBM */
+static const struct pci_driver i82801dbm_ide __pci_driver = {
+	.ops = &ide_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = 0x24ca,
+};

src/southbridge/intel/i82801dx/i82801dx_lpc.c

@@ -1,7 +1,25 @@
 /*
- * (C) 2003 Linux Networx, SuSE Linux AG
+ * This file is part of the coreboot project.
- * (C) 2004 Tyan Computer
+ *
+ * Copyright (C) 2003 Linux Networx
+ * Copyright (C) 2004 SuSE Linux AG
+ * Copyright (C) 2004 Tyan Computer
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
+
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -12,31 +30,29 @@
 #include <arch/io.h>
 #include "i82801dx.h"
 
-
-
 #define NMI_OFF 0
 
-void i82801dx_enable_ioapic( struct device *dev) 
+void i82801dx_enable_ioapic(struct device *dev)
 {
-        uint32_t dword;
+	u32 dword;
-        volatile uint32_t *ioapic_sba = (volatile uint32_t *)0xfec00000;
+	volatile u32 *ioapic_sba = (volatile u32 *)0xfec00000;
-        volatile uint32_t *ioapic_sbd = (volatile uint32_t *)0xfec00010;
+	volatile u32 *ioapic_sbd = (volatile u32 *)0xfec00010;
 
 	dword = pci_read_config32(dev, GEN_CNTL);
 	dword |= (3 << 7);	/* enable ioapic */
-        dword |= (1 <<13); /* coprocessor error enable */
+	dword |= (1 << 13);	/* coprocessor error enable */
 	dword |= (1 << 1);	/* delay transaction enable */
 	dword |= (1 << 2);	/* DMA collection buf enable */
 	pci_write_config32(dev, GEN_CNTL, dword);
-        printk_debug("ioapic southbridge enabled %x\n",dword);
+	printk_debug("ioapic southbridge enabled %x\n", dword);
-        *ioapic_sba=0;
+	*ioapic_sba = 0;
-        *ioapic_sbd=(2<<24);
+	*ioapic_sbd = (2 << 24);
 	//lyh *ioapic_sba=3;
 	//lyh *ioapic_sbd=1;    
-        *ioapic_sba=0;
+	*ioapic_sba = 0;
-        dword=*ioapic_sbd;
+	dword = *ioapic_sbd;
-        printk_debug("Southbridge apic id = %x\n",dword);
+	printk_debug("Southbridge apic id = %x\n", dword);
-        if(dword!=(2<<24))
+	if (dword != (2 << 24))
 		die("");
 	//lyh *ioapic_sba=3;
 	//lyh dword=*ioapic_sbd;
@@ -44,29 +60,32 @@ void i82801dx_enable_ioapic( struct device *dev)
 	//lyh if(dword!=1)
 	//lyh   die("");
 
+}
 
-}
+void i82801dx_enable_serial_irqs(struct device *dev)
-void i82801dx_enable_serial_irqs( struct device *dev)
 {
-        pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0<< 0));
+	pci_write_config8(dev, SERIRQ_CNTL,
+			  (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
 }
-void i82801dx_lpc_route_dma( struct device *dev, uint8_t mask) 
+
+void i82801dx_lpc_route_dma(struct device *dev, u8 mask)
 {
-        uint16_t word;
+	u16 word;
 	int i;
 	word = pci_read_config16(dev, PCI_DMA_CFG);
 	word &= ((1 << 10) - (1 << 8));
-        for(i = 0; i < 8; i++) {
+	for (i = 0; i < 8; i++) {
 		if (i == 4)
 			continue;
-                word |= ((mask & (1 << i))? 3:1) << (i*2);
+		word |= ((mask & (1 << i)) ? 3 : 1) << (i * 2);
 	}
 	pci_write_config16(dev, PCI_DMA_CFG, word);
 }
+
 void i82801dx_rtc_init(struct device *dev)
 {
-        uint8_t byte;
+	u8 byte;
-        uint32_t dword;
+	u32 dword;
 	int rtc_failed;
 	byte = pci_read_config8(dev, GEN_PMCON_3);
 	rtc_failed = byte & RTC_FAILED;
@@ -79,7 +98,6 @@ void i82801dx_rtc_init(struct device *dev)
 	rtc_init(rtc_failed);
 }
 
-
 void i82801dx_1f0_misc(struct device *dev)
 {
 	pci_write_config16(dev, PCICMD, 0x014f);
@@ -98,8 +116,8 @@ static void enable_hpet(struct device *dev)
 {
 	const unsigned long hpet_address = 0xfed0000;
 
-        uint32_t dword;
+	u32 dword;
-	uint32_t code = (0 & 0x3);
+	u32 code = (0 & 0x3);
 
 	dword = pci_read_config32(dev, GEN_CNTL);
 	dword |= (1 << 17);	/* enable hpet */
@@ -107,18 +125,18 @@ static void enable_hpet(struct device *dev)
 	   00 FED0_0000h - FED0_03FFh
 	   01 FED0_1000h - FED0_13FFh
 	   10 FED0_2000h - FED0_23FFh
-	11 FED0_3000h - FED0_33FFh*/
+	   11 FED0_3000h - FED0_33FFh */
 
 	dword &= ~(3 << 15);	/* clear it */
-	dword |= (code<<15);
+	dword |= (code << 15);
 
-	printk_debug("enabling HPET @0x%x\n", hpet_address | (code <<12) );
+	printk_debug("enabling HPET @0x%x\n", hpet_address | (code << 12));
 }
 
 static void lpc_init(struct device *dev)
 {
-	uint8_t byte;
+	u8 byte;
-	int pwr_on=-1;
+	int pwr_on = -1;
 	int nmi_option;
 
 	/* IO APIC initialization */
@@ -133,7 +151,7 @@ static void lpc_init(struct device *dev)
 
 	/* posted memory write enable */
 	byte = pci_read_config8(dev, 0x46);
-	pci_write_config8(dev, 0x46, byte | (1<<0)); 
+	pci_write_config8(dev, 0x46, byte | (1 << 0));
 #endif
 
 	/* power after power fail */
@@ -142,8 +160,8 @@ static void lpc_init(struct device *dev)
 	 * 0 == S0 Full On
 	 * 1 == S5 Soft Off
 	 */
-        pci_write_config8(dev, GEN_PMCON_3, pwr_on?0:1);
+	pci_write_config8(dev, GEN_PMCON_3, pwr_on ? 0 : 1);
-        printk_info("set power %s after power fail\n", pwr_on?"on":"off");
+	printk_info("set power %s after power fail\n", pwr_on ? "on" : "off");
 #if 0
 	/* Enable Error reporting */
 	/* Set up sync flood detected */
@@ -219,7 +237,15 @@ static struct device_operations lpc_ops  = {
 	.enable = i82801dx_enable,
 };
 
-static const struct pci_driver lpc_driver __pci_driver = {
+/* 82801DB/DBL */
+static const struct pci_driver lpc_driver_db __pci_driver = {
+	.ops = &lpc_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_82801DB_LPC,
+};
+
+/* 82801DBM */
+static const struct pci_driver lpc_driver_dbm __pci_driver = {
 	.ops = &lpc_ops,
 	.vendor = PCI_VENDOR_ID_INTEL,
 	.device = PCI_DEVICE_ID_INTEL_82801DBM_LPC,

src/southbridge/intel/i82801dx/i82801dx_nic.c

@@ -1,21 +0,0 @@
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include "i82801dx.h"
-
-
-static struct device_operations nic_ops  = {
-	.read_resources   = pci_dev_read_resources,
-	.set_resources    = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init             = 0,
-	.scan_bus         = 0,
-};
-
-static const struct pci_driver nic_driver __pci_driver = {
-	.ops    = &nic_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = 0x103a,
-};

src/southbridge/intel/i82801dx/i82801dx_pci.c

@@ -1,3 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Ronald G. Minnich
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -11,10 +30,9 @@ static void pci_init(struct device *dev)
 	uint32_t dword;
 	/* System error enable */
 	dword = pci_read_config32(dev, 0x04);
-	dword |= (1<<8); /* SERR# Enable */
+	dword |= (1 << 8);	/* SERR# Enable */
-	dword |= (1<<6); /* Parity Error Response */
+	dword |= (1 << 6);	/* Parity Error Response */
 	pci_write_config32(dev, 0x04, dword);
-
 }
 
 static struct device_operations pci_ops = {
@@ -25,9 +43,16 @@ static struct device_operations pci_ops  = {
 	.scan_bus = pci_scan_bridge,
 };
 
-static const struct pci_driver pci_driver __pci_driver = {
+/* 82801DB */
+static const struct pci_driver pci_driver_db __pci_driver = {
+	.ops = &pci_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_82801DB_PCI,
+};
+
+/* 82801DBM/DBL */
+static const struct pci_driver pci_driver_dbm __pci_driver = {
 	.ops = &pci_ops,
 	.vendor = PCI_VENDOR_ID_INTEL,
 	.device = PCI_DEVICE_ID_INTEL_82801DBM_PCI,
 };
-

src/southbridge/intel/i82801dx/i82801dx_reset.c

@@ -1,7 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Ronald G. Minnich
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
 #include <arch/io.h>
 
 void hard_reset(void)
 {
 	/* Try rebooting through port 0xcf9 */
-        outb((0 <<3)|(1<<2)|(1<<1), 0xcf9);
+	outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
 }

src/southbridge/intel/i82801dx/i82801dx_sata.c

@@ -1,75 +0,0 @@
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include "i82801dx.h"
-
-static void sata_init(struct device *dev)
-{
-
-        uint16_t word;
-        uint8_t byte;
-	int enable_c=1, enable_d=1;
-	//	int i;
-                
-        //Enable Serial ATA port
-        byte = pci_read_config8(dev,0x90);
-        byte &= 0xf8;
-        byte |= ICH5_SATA_ADDRESS_MAP & 7;
-        pci_write_config8(dev,0x90,byte);
-
-//        for(i=0;i<10;i++) {
-		word = pci_read_config16(dev,0x92);
-                word &= 0xfffc;
-//                if( (word & 0x0003) == 0x0003) break;
-                word |= 0x0003; // enable P0/P1 
-                pci_write_config16(dev,0x92,word);
-//        }
-
-//        for(i=0;i<10;i++) {
-              /* enable ide0 */
-		word = pci_read_config16(dev, 0x40);
-        	word &= ~(1 << 15);
-                if(enable_c==0) {
-//                     	if( (word & 0x8000) == 0x0000) break;
-                       	word |= 0x0000;
-                }
-                else {
-//                       	if( (word & 0x8000) == 0x8000) break;
-                       	word |= 0x8000;
-                }
-                pci_write_config16(dev, 0x40, word);
-//	}
-                /* enable ide1 */
-//        for(i=0;i<10;i++) {
-              	word = pci_read_config16(dev, 0x42);
-                word &= ~(1 << 15);
-                if(enable_d==0) {
-//                       	if( (word & 0x8000) == 0x0000) break;
-                       	word |= 0x0000;
-                }
-                else {
-//                       	if( (word & 0x8000) == 0x8000) break;
-                       	word |= 0x8000;
-                }
-                pci_write_config16(dev, 0x42, word);
-//        }
-
-}
-
-static struct device_operations sata_ops  = {
-	.read_resources   = pci_dev_read_resources,
-	.set_resources    = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init             = sata_init,
-	.scan_bus         = 0,
-	.enable           = i82801dx_enable,
-};
-
-static const struct pci_driver stat_driver __pci_driver = {
-	.ops    = &sata_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_82801DBM_SATA,
-};
-

src/southbridge/intel/i82801dx/i82801dx_smbus.c

@@ -1,3 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Ronald G. Minnich
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
 #include "i82801dx.h"
 #include <smbus.h>
 #include <pci.h>
@@ -6,17 +25,6 @@
 #define PM_BUS 0
 #define PM_DEVFN PCI_DEVFN(0x1f,3)
 
-#if 0
-#define SMBUS_IO_BASE 0x1000
-#define SMBHSTSTAT 0
-#define SMBHSTCTL  2
-#define SMBHSTCMD  3
-#define SMBHSTADD  4
-#define SMBHSTDAT0 5
-#define SMBHSTDAT1 6
-#define SMBBLKDAT  7
-#endif
-
 void smbus_enable(void)
 {
 	unsigned char byte;
@@ -39,7 +47,7 @@ void smbus_setup(void)
 
 static void smbus_wait_until_ready(void)
 {
-	while((inb(SMBUS_IO_BASE + SMBHSTSTAT) & 1) == 1) {
+	while ((inb(SMBUS_IO_BASE + SMBHSTSTAT) & 1) == 1) {
 		/* nop */
 	}
 }
@@ -50,8 +58,8 @@ static void smbus_wait_until_done(void)
 	do {
 		byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
 	}
-	while((byte &1) == 1);
+	while ((byte & 1) == 1);
-	while( (byte & ~1) == 0) {
+	while ((byte & ~1) == 0) {
 		byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
 	}
 }
@@ -71,16 +79,18 @@ int smbus_read_byte(unsigned device, unsigned address, unsigned char *result)
 	/* set the command/address... */
 	outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
 	/* set up for a byte data read */
-	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2), SMBUS_IO_BASE + SMBHSTCTL);
+	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2),
+	     SMBUS_IO_BASE + SMBHSTCTL);
 
 	/* clear any lingering errors, so the transaction will run */
 	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
 
-	/* clear the data byte...*/
+	/* clear the data byte... */
 	outb(0, SMBUS_IO_BASE + SMBHSTDAT0);
 
 	/* start the command */
-	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL);
+	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40),
+	     SMBUS_IO_BASE + SMBHSTCTL);
 
 	/* poll for transaction completion */
 	smbus_wait_until_done();

src/southbridge/intel/i82801dx/i82801dx_tco_timer.c

@@ -3,9 +3,10 @@
  *
  * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
  *
- * This program is free software; you can redistribute it and/or modify
+ * This program is free software; you can redistribute it and/or
- * it under the terms of the GNU General Public License version 2 as
+ * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation.
+ * published by the Free Software Foundation; version 2 of
+ * the License.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -14,8 +15,8 @@
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- *
+ * MA 02110-1301 USA
  */
 
 static void i82801dx_halt_tco_timer(void)
@@ -33,5 +34,6 @@ static void i82801dx_halt_tco_timer(void)
 	pci_write_config8(dev, ACPI_CNTL, 0x10);
 
 	/* Halt the TCO timer, preventing SMI and automatic reboot */
-	outw(inw(PMBASE_ADDR + TCOBASE + TCO1_CNT) | (1 << 11), PMBASE_ADDR + TCOBASE + TCO1_CNT);
+	outw(inw(PMBASE_ADDR + TCOBASE + TCO1_CNT) | (1 << 11),
+	     PMBASE_ADDR + TCOBASE + TCO1_CNT);
 }

src/southbridge/intel/i82801dx/i82801dx_usb.c

@@ -1,3 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Ronald G. Minnich
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -7,20 +28,13 @@
 
 static void usb_init(struct device *dev)
 {
-
+	u32 cmd;
-
-#if 0
-	uint32_t cmd;
 	printk_debug("USB: Setting up controller.. ");
 	cmd = pci_read_config32(dev, PCI_COMMAND);
 	pci_write_config32(dev, PCI_COMMAND,
 			   cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
 			   PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE);
-
-
 	printk_debug("done.\n");
-#endif
-
 }
 
 static struct device_operations usb_ops = {
@@ -32,18 +46,23 @@ static struct device_operations usb_ops  = {
 	.enable = i82801dx_enable,
 };
 
+/* 82801DB/DBL/DBM USB1 */
 static const struct pci_driver usb_driver_1 __pci_driver = {
 	.ops = &usb_ops,
 	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_82801DBM_USB1,
+	.device = PCI_DEVICE_ID_INTEL_82801DB_USB1,
 };
+
+/* 82801DB/DBL/DBM USB2 */
 static const struct pci_driver usb_driver_2 __pci_driver = {
 	.ops = &usb_ops,
 	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_82801DBM_USB2,
+	.device = PCI_DEVICE_ID_INTEL_82801DB_USB2,
 };
+
+/* 82801DB/DBL/DBM USB3 */
 static const struct pci_driver usb_driver_3 __pci_driver = {
 	.ops = &usb_ops,
 	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_82801DBM_USB3,
+	.device = PCI_DEVICE_ID_INTEL_82801DB_USB3,
 };

src/southbridge/intel/i82801dx/i82801dx_usb2.c

@@ -1,4 +1,23 @@
-//2003 Copywright Tyan
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2003 Tyan
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
 
 #include <console/console.h>
 #include <device/device.h>
@@ -9,19 +28,13 @@
 
 static void usb2_init(struct device *dev)
 {
-
+	u32 cmd;
-
-#if 0  
-  uint32_t cmd;
 	printk_debug("USB: Setting up controller.. ");
 	cmd = pci_read_config32(dev, PCI_COMMAND);
 	pci_write_config32(dev, PCI_COMMAND,
 			   cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
 			   PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE);
-
-
 	printk_debug("done.\n");
-#endif
 }
 
 static struct device_operations usb2_ops = {
@@ -33,8 +46,9 @@ static struct device_operations usb2_ops  = {
 	.enable = i82801dx_enable,
 };
 
+/* 82801DB/DBM USB 2.0 */
 static const struct pci_driver usb2_driver __pci_driver = {
 	.ops = &usb2_ops,
 	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_82801DBM_EHCI,
+	.device = PCI_DEVICE_ID_INTEL_82801DB_EHCI,
 };