stoneyridge: Move agesa out of bootblock
This is Garrett's patch with a bit of cleanup. BUG=b:65442212 TEST=Was able to boot, suspend and resume on grunt. Change-Id: I55959b59a4e60b679d959ebd77de27e5d454f5f7 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/26478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
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Martin Roth
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f1eff68ef5
commit
873b4e70bc
@@ -52,27 +52,6 @@ static void amd_initmmio(void)
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set_var_mtrr(mtrr, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
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}
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/*
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* To move AGESA calls to romstage, just move agesa_call() and bsp_agesa_call()
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* to romstage.c. Also move the call to bsp_agesa_call() to the marked location
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* in romstage.c.
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*/
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static void agesa_call(void)
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{
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post_code(0x37);
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do_agesawrapper(agesawrapper_amdinitreset, "amdinitreset");
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post_code(0x38);
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/* APs will not exit amdinitearly */
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do_agesawrapper(agesawrapper_amdinitearly, "amdinitearly");
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}
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static void bsp_agesa_call(void)
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{
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set_ap_entry_ptr(agesa_call); /* indicate the path to the AP */
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agesa_call();
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}
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asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
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{
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amd_initmmio();
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@@ -97,37 +76,6 @@ void bootblock_soc_early_init(void)
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post_code(0x90);
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}
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/*
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* This step is in bootblock because the SMU FW1 must be loaded prior to
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* issuing any reset to the system. Set up just enough to get the command
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* to the PSP. A side effect of placing this step here is we will always
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* load a RO version of FW1 and never a RW version.
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*
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* todo: If AMD develops a more robust methodology, move this function to
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* romstage.
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*/
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static void load_smu_fw1(void)
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{
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u32 base, limit, cmd;
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/* Open a posted hole from 0x80000000 : 0xfed00000-1 */
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base = (0x80000000 >> 8) | MMIO_WE | MMIO_RE;
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limit = (ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8);
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pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_LIMIT0_LO, limit);
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pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_BASE0_LO, base);
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/* Preload a value into "BAR3" and enable it */
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pci_write_config32(SOC_PSP_DEV, PSP_MAILBOX_BAR, PSP_MAILBOX_BAR3_BASE);
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pci_write_config32(SOC_PSP_DEV, PSP_BAR_ENABLES, PSP_MAILBOX_BAR_EN);
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/* Enable memory access and master */
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cmd = pci_read_config32(SOC_PSP_DEV, PCI_COMMAND);
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cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
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pci_write_config32(SOC_PSP_DEV, PCI_COMMAND, cmd);
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psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW, "smu_fw");
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}
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void bootblock_soc_init(void)
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{
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if (IS_ENABLED(CONFIG_STONEYRIDGE_UART))
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@@ -137,11 +85,6 @@ void bootblock_soc_init(void)
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u32 val = cpuid_eax(1);
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printk(BIOS_DEBUG, "Family_Model: %08x\n", val);
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if (IS_ENABLED(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW))
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load_smu_fw1();
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bsp_agesa_call();
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/* Initialize any early i2c buses. */
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i2c_soc_early_init();
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}
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@@ -41,6 +41,44 @@ void __weak mainboard_romstage_entry(int s3_resume)
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/* By default, don't do anything */
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}
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static void load_smu_fw1(void)
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{
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u32 base, limit, cmd;
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/* Open a posted hole from 0x80000000 : 0xfed00000-1 */
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base = (0x80000000 >> 8) | MMIO_WE | MMIO_RE;
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limit = (ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8);
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pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_LIMIT0_LO, limit);
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pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_BASE0_LO, base);
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/* Preload a value into "BAR3" and enable it */
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pci_write_config32(SOC_PSP_DEV, PSP_MAILBOX_BAR, PSP_MAILBOX_BAR3_BASE);
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pci_write_config32(SOC_PSP_DEV, PSP_BAR_ENABLES, PSP_MAILBOX_BAR_EN);
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/* Enable memory access and master */
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cmd = pci_read_config32(SOC_PSP_DEV, PCI_COMMAND);
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cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
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pci_write_config32(SOC_PSP_DEV, PCI_COMMAND, cmd);
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psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW, "smu_fw");
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}
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static void agesa_call(void)
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{
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post_code(0x37);
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do_agesawrapper(agesawrapper_amdinitreset, "amdinitreset");
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post_code(0x38);
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/* APs will not exit amdinitearly */
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do_agesawrapper(agesawrapper_amdinitearly, "amdinitearly");
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}
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static void bsp_agesa_call(void)
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{
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set_ap_entry_ptr(agesa_call); /* indicate the path to the AP */
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agesa_call();
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}
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asmlinkage void car_stage_entry(void)
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{
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struct postcar_frame pcf;
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@@ -61,6 +99,12 @@ asmlinkage void car_stage_entry(void)
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console_init();
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if (IS_ENABLED(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW))
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load_smu_fw1();
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bsp_agesa_call();
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mainboard_romstage_entry(s3_resume);
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if (!s3_resume) {
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