sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

set up interrupt values for the southbridge, and add a function to

Browse Source 
manage them. Make pci_level_irq global. Add value settings for OLPC
rev_a board. Comment out no-longer-needed code in olpc mainboard.c 
-- it is replaced by the settings in Config.lb, and the support
in cs5536.c


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2328 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich
2006-06-22 04:37:27 +00:00
parent 9d0b30dd2b
commit 88fb1a6c37
5 changed files with 43 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/devices/pci_device.c
View File

@@ -1161,7 +1161,7 @@ unsigned int pci_scan_bridge(struct device *dev, unsigned int max)
Tell the EISA int controller this int must be level triggered
THIS IS A KLUDGE -- sorry, this needs to get cleaned up.
*/
static void pci_level_irq(unsigned char intNum)
void pci_level_irq(unsigned char intNum)
{
unsigned short intBits = inb(0x4d0) | (((unsigned) inb(0x4d1)) << 8);