soc/intel/meteorlake: transition full control over PM Timer from FSP to coreboot
Set `EnableTcoTimer=1` in order to keep FSP from 1) enabling ACPI Timer emulation in uCode. 2) disabling the PM ACPI Timer. Both actions are now done in coreboot. `EnableTcoTimer=1` makes FSP skip these steps in any possible case including `SkipMpInit=0`, `SkipMpInit=1`, use of the MP PPI or FSP Multiphase Init. This way full control is left to coreboot. Port of commit 0e905801f8ff ("soc/intel: transition full control over PM Timer from FSP to coreboot"). NOTE: This will have a huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer emulation must be enabled, and WDAT table must not be exposed to the OS. BUG=none TEST=Boot to OS on google/rex. Excerpt from google/rex coreboot log: [SPEW ] EnableTcoTimer = 1 Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I2693f0390e6c9fa92fec366ab87589c3bcea9027 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
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@ -349,6 +349,19 @@ static void fill_fsps_8254_params(FSP_S_CONFIG *s_cfg,
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s_cfg->Enable8254ClockGatingOnS3 = !CONFIG(USE_LEGACY_8254_TIMER);
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}
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static void fill_fsps_pm_timer_params(FSP_S_CONFIG *s_cfg,
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const struct soc_intel_meteorlake_config *config)
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{
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/*
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* Legacy PM ACPI Timer (and TCO Timer)
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* This *must* be 1 in any case to keep FSP from
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* 1) enabling PM ACPI Timer emulation in uCode.
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* 2) disabling the PM ACPI Timer.
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* We handle both by ourself!
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*/
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s_cfg->EnableTcoTimer = 1;
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}
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static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg,
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const struct soc_intel_meteorlake_config *config)
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{
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@ -429,6 +442,7 @@ static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg,
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fill_fsps_vmd_params,
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fill_fsps_tbt_params,
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fill_fsps_8254_params,
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fill_fsps_pm_timer_params,
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fill_fsps_pcie_params,
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fill_fsps_misc_power_params,
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fill_fsps_ufs_params,
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