Add ACPI backlight code

Change-Id: I325fb544e2f2fa06606fd02138b95b236782fdbf

src/drivers/intel/gma/acpi/configure_brightness_levels.asl

@@ -148,7 +148,7 @@
 	{
 		If (LEqual(^BOX3.XBCM (Arg0), Ones))
 		{
-			^LEGA.XBCM (Arg0)
+			//TODO: fix Windows initial setup ^LEGA.XBCM (Arg0)
 		}
 	}
 

src/mainboard/system76/cml-u/acpi/backlight.asl

@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/intel/gma/acpi/gma.asl>
+
+Scope (GFX0)
+{
+       Name (BRIG, Package (22)
+       {
+                40, /* default AC */
+                40, /* default Battery */
+                 5,
+                10,
+                15,
+                20,
+                25,
+                30,
+                35,
+                40,
+                45,
+                50,
+                55,
+                60,
+                65,
+                70,
+                75,
+                80,
+                85,
+                90,
+                95,
+               100
+       })
+}

src/mainboard/system76/cml-u/acpi/ec.asl

@@ -39,6 +39,10 @@ Device (EC0)
 			^^^^BAT0.UPBI()
 			^^^^BAT0.UPBS()
 
+			// Notify of changes
+			Notify(^^^^AC, Zero)
+			Notify(^^^^BAT0, Zero)
+
 			PNOT ()
 
 			// EC is now available

src/mainboard/system76/cml-u/devicetree.cb

@@ -169,6 +169,9 @@ chip soc/intel/cannonlake
 	# Serial IRQ Continuous
 	register "serirq_mode" = "SERIRQ_CONTINUOUS"
 
+# Graphics (soc/intel/cannonlake/graphics.c)
+    register "gfx" = "GMA_STATIC_DISPLAYS(0)"
+
 # LPC (soc/intel/cannonlake/lpc.c)
 	# LPC configuration from lspci -s 1f.0 -xxx
 	# Address 0x84: Decode 0x80 - 0x8F (Port 80)

src/mainboard/system76/cml-u/dsdt.asl

@@ -18,6 +18,7 @@ DefinitionBlock(
 	{
 		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
 		#include <soc/intel/cannonlake/acpi/southbridge.asl>
+		#include "acpi/backlight.asl"
 	}
 
 	#include <southbridge/intel/common/acpi/sleepstates.asl>

src/mainboard/system76/gaze15/acpi/backlight.asl

@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/intel/gma/acpi/gma.asl>
+
+Scope (GFX0)
+{
+       Name (BRIG, Package (22)
+       {
+                40, /* default AC */
+                40, /* default Battery */
+                 5,
+                10,
+                15,
+                20,
+                25,
+                30,
+                35,
+                40,
+                45,
+                50,
+                55,
+                60,
+                65,
+                70,
+                75,
+                80,
+                85,
+                90,
+                95,
+               100
+       })
+}

src/mainboard/system76/gaze15/devicetree.cb

@@ -189,6 +189,9 @@ chip soc/intel/cannonlake
 	# Serial IRQ Continuous
 	register "serirq_mode" = "SERIRQ_CONTINUOUS"
 
+# Graphics (soc/intel/cannonlake/graphics.c)
+    register "gfx" = "GMA_STATIC_DISPLAYS(0)"
+
 # LPC (soc/intel/cannonlake/lpc.c)
 	# LPC configuration from lspci -s 1f.0 -xxx
 	# Address 0x84: Decode 0x80 - 0x8F (Port 80)

src/mainboard/system76/gaze15/dsdt.asl

@@ -18,6 +18,7 @@ DefinitionBlock(
 	{
 		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
 		#include <soc/intel/cannonlake/acpi/southbridge.asl>
+		#include "acpi/backlight.asl"
 		#include "acpi/pegp.asl"
 		#include "acpi/dgpu.asl"
 	}

src/mainboard/system76/lemp9/acpi/backlight.asl

@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/intel/gma/acpi/gma.asl>
+
+Scope (GFX0)
+{
+       Name (BRIG, Package (22)
+       {
+                40, /* default AC */
+                40, /* default Battery */
+                 5,
+                10,
+                15,
+                20,
+                25,
+                30,
+                35,
+                40,
+                45,
+                50,
+                55,
+                60,
+                65,
+                70,
+                75,
+                80,
+                85,
+                90,
+                95,
+               100
+       })
+}

src/mainboard/system76/lemp9/acpi/ec.asl

@@ -39,6 +39,10 @@ Device (EC0)
 			^^^^BAT0.UPBI()
 			^^^^BAT0.UPBS()
 
+			// Notify of changes
+			Notify(^^^^AC, Zero)
+			Notify(^^^^BAT0, Zero)
+
 			PNOT ()
 
 			// EC is now available

src/mainboard/system76/lemp9/devicetree.cb

@@ -169,6 +169,9 @@ chip soc/intel/cannonlake
 	# Serial IRQ Continuous
 	register "serirq_mode" = "SERIRQ_CONTINUOUS"
 
+# Graphics (soc/intel/cannonlake/graphics.c)
+    register "gfx" = "GMA_STATIC_DISPLAYS(0)"
+
 # LPC (soc/intel/cannonlake/lpc.c)
 	# LPC configuration from lspci -s 1f.0 -xxx
 	# Address 0x84: Decode 0x80 - 0x8F (Port 80)

src/mainboard/system76/lemp9/dsdt.asl

@@ -18,6 +18,7 @@ DefinitionBlock(
 	{
 		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
 		#include <soc/intel/cannonlake/acpi/southbridge.asl>
+		#include "acpi/backlight.asl"
 	}
 
 	#include <southbridge/intel/common/acpi/sleepstates.asl>

src/mainboard/system76/oryp6/acpi/backlight.asl

@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/intel/gma/acpi/gma.asl>
+
+Scope (GFX0)
+{
+       Name (BRIG, Package (22)
+       {
+                40, /* default AC */
+                40, /* default Battery */
+                 5,
+                10,
+                15,
+                20,
+                25,
+                30,
+                35,
+                40,
+                45,
+                50,
+                55,
+                60,
+                65,
+                70,
+                75,
+                80,
+                85,
+                90,
+                95,
+               100
+       })
+}

src/mainboard/system76/oryp6/devicetree.cb

@@ -208,6 +208,9 @@ chip soc/intel/cannonlake
 	# Serial IRQ Continuous
 	register "serirq_mode" = "SERIRQ_CONTINUOUS"
 
+# Graphics (soc/intel/cannonlake/graphics.c)
+    register "gfx" = "GMA_STATIC_DISPLAYS(0)"
+
 # LPC (soc/intel/cannonlake/lpc.c)
 	# LPC configuration from lspci -s 1f.0 -xxx
 	# Address 0x84: Decode 0x80 - 0x8F (Port 80)

src/mainboard/system76/oryp6/dsdt.asl

@@ -18,6 +18,7 @@ DefinitionBlock(
 	{
 		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
 		#include <soc/intel/cannonlake/acpi/southbridge.asl>
+		#include "acpi/backlight.asl"
 		#include "acpi/pegp.asl"
 		#include "acpi/dgpu.asl"
 	}

src/mainboard/system76/whl-u/acpi/backlight.asl

@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/intel/gma/acpi/gma.asl>
+
+Scope (GFX0)
+{
+       Name (BRIG, Package (22)
+       {
+                40, /* default AC */
+                40, /* default Battery */
+                 5,
+                10,
+                15,
+                20,
+                25,
+                30,
+                35,
+                40,
+                45,
+                50,
+                55,
+                60,
+                65,
+                70,
+                75,
+                80,
+                85,
+                90,
+                95,
+               100
+       })
+}

src/mainboard/system76/whl-u/acpi/ec.asl

@@ -39,6 +39,10 @@ Device (EC0)
 			^^^^BAT0.UPBI()
 			^^^^BAT0.UPBS()
 
+			// Notify of changes
+			Notify(^^^^AC, Zero)
+			Notify(^^^^BAT0, Zero)
+
 			PNOT ()
 
 			// EC is now available

src/mainboard/system76/whl-u/devicetree.cb

@@ -169,6 +169,9 @@ chip soc/intel/cannonlake
 	# Serial IRQ Continuous
 	register "serirq_mode" = "SERIRQ_CONTINUOUS"
 
+# Graphics (soc/intel/cannonlake/graphics.c)
+    register "gfx" = "GMA_STATIC_DISPLAYS(0)"
+
 # LPC (soc/intel/cannonlake/lpc.c)
 	# LPC configuration from lspci -s 1f.0 -xxx
 	# Address 0x84: Decode 0x80 - 0x8F (Port 80)

src/mainboard/system76/whl-u/dsdt.asl

@@ -18,6 +18,7 @@ DefinitionBlock(
 	{
 		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
 		#include <soc/intel/cannonlake/acpi/southbridge.asl>
+		#include "acpi/backlight.asl"
 	}
 
 	#include <southbridge/intel/common/acpi/sleepstates.asl>

src/soc/intel/cannonlake/Makefile.inc

@@ -38,6 +38,7 @@ ramstage-y += finalize.c
 ramstage-y += fsp_params.c
 ramstage-y += gspi.c
 ramstage-y += i2c.c
+ramstage-y += graphics.c
 ramstage-y += lockdown.c
 ramstage-y += lpc.c
 ramstage-y += me.c

src/soc/intel/cannonlake/acpi/southbridge.asl

@@ -17,7 +17,7 @@
 #endif
 
 /* GFX 00:02.0 */
-#include "gfx.asl"
+//TODO: fix inclusion when using gma ACPI #include "gfx.asl"
 
 /* LPC 0:1f.0 */
 #include <soc/intel/common/block/acpi/acpi/lpc.asl>

src/soc/intel/cannonlake/chip.h

@@ -5,6 +5,7 @@
 
 #include <intelblocks/cfg.h>
 #include <drivers/i2c/designware/dw_i2c.h>
+#include <drivers/intel/gma/gma.h>
 #include <intelblocks/gpio.h>
 #include <intelblocks/gspi.h>
 #include <intelblocks/lpc_lib.h>
@@ -434,6 +435,9 @@ struct soc_intel_cannonlake_config {
 	 * Only override CPU flex ratio if don't want to boot with non-turbo max.
 	 */
 	uint8_t cpu_ratio_override;
+
+	/* i915 struct for GMA backlight control */
+	struct i915_gpu_controller_info gfx;
 };
 
 typedef struct soc_intel_cannonlake_config config_t;

src/soc/intel/cannonlake/graphics.c

@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <intelblocks/graphics.h>
+#include <soc/ramstage.h>
+
+const struct i915_gpu_controller_info *
+intel_igd_get_controller_info(const struct device *device)
+{
+	struct soc_intel_cannonlake_config *chip = device->chip_info;
+	return &chip->gfx;
+}