{cpu,drivers,nb,sb}/amd: Replace {MSR,MTRR} addresses with macros
Change-Id: I7e8de35dcdad52bb311b34bfa9b272d17ed3186b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29243 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
committed by
Martin Roth
parent
50f2e4ccec
commit
8a643703b8
@@ -15,6 +15,7 @@
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#include <cpu/x86/mtrr.h>
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#include <cpu/amd/msr.h>
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#include <cpu/amd/mtrr.h>
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#include <northbridge/amd/agesa/agesa_helper.h>
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#include <AGESA.h>
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#include "amdlib.h"
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@@ -40,7 +41,7 @@ void amd_initcpuio(void)
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);
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PciData = 0x00DFFF00;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader);
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LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
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MsrReg = (MsrReg >> 8) | 3;
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
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PciData = (UINT32) MsrReg;
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@@ -15,6 +15,7 @@
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#include <cpu/x86/mtrr.h>
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#include <cpu/amd/msr.h>
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#include <cpu/amd/mtrr.h>
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#include <northbridge/amd/agesa/agesa_helper.h>
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#include <AGESA.h>
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#include "amdlib.h"
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@@ -51,7 +52,7 @@ void amd_initcpuio(void)
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);
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PciData = 0x00FECF00; // last address before non-posted range
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader);
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LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
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MsrReg = (MsrReg >> 8) | 3;
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
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PciData = (UINT32) MsrReg;
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@@ -15,6 +15,7 @@
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#include <cpu/x86/mtrr.h>
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#include <cpu/amd/msr.h>
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#include <cpu/amd/mtrr.h>
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#include <northbridge/amd/agesa/agesa_helper.h>
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#include <AGESA.h>
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#include "amdlib.h"
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@@ -47,7 +48,7 @@ void amd_initcpuio(void)
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PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
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PciData = 0x00FECF00; /* last address before non-posted range */
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
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LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
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MsrReg = (MsrReg >> 8) | 3;
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PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
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PciData = (UINT32)MsrReg;
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@@ -15,6 +15,7 @@
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#include <cpu/x86/mtrr.h>
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#include <cpu/amd/msr.h>
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#include <cpu/amd/mtrr.h>
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#include <northbridge/amd/agesa/agesa_helper.h>
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#include <AGESA.h>
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#include "amdlib.h"
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@@ -47,7 +48,7 @@ void amd_initcpuio(void)
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PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
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PciData = 0x00FECF00; /* last address before non-posted range */
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
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LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
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MsrReg = (MsrReg >> 8) | 3;
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PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
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PciData = (UINT32)MsrReg;
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@@ -90,7 +90,7 @@ static void model_10xxx_init(struct device *dev)
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disable_cache();
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for (i = 0x2; i < 0x10; i++) {
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wrmsr(0x00000200 | i, msr);
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wrmsr(MTRR_PHYS_BASE(0) | i, msr);
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}
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enable_cache();
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@@ -15,6 +15,7 @@
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#include <cpu/x86/mtrr.h>
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#include <cpu/amd/msr.h>
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#include <cpu/amd/mtrr.h>
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#include <northbridge/amd/agesa/agesa_helper.h>
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#include <Porting.h>
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#include <AGESA.h>
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@@ -52,7 +53,7 @@ void amd_initcpuio(void)
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/* last address before non-posted range */
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PciData = 0x00FECF00;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader);
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LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
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MsrReg = (MsrReg >> 8) | 3;
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
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PciData = (UINT32)MsrReg;
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@@ -15,6 +15,7 @@
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#include <cpu/x86/mtrr.h>
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#include <cpu/amd/msr.h>
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#include <cpu/amd/mtrr.h>
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#include <northbridge/amd/agesa/agesa_helper.h>
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#include <Porting.h>
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#include <AGESA.h>
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@@ -51,7 +52,7 @@ void amd_initcpuio(void)
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);
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PciData = 0x00FECF00; /* last address before non-posted range */
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader);
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LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
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MsrReg = (MsrReg >> 8) | 3;
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
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PciData = (UINT32)MsrReg;
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@@ -15,6 +15,7 @@
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#include <cpu/x86/mtrr.h>
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#include <cpu/amd/msr.h>
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#include <cpu/amd/mtrr.h>
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#include <northbridge/amd/agesa/agesa_helper.h>
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#include <Porting.h>
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#include <AGESA.h>
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@@ -51,7 +52,7 @@ void amd_initcpuio(void)
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);
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PciData = 0x00FECF00; /* last address before non-posted range */
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader);
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LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
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MsrReg = (MsrReg >> 8) | 3;
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
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PciData = (UINT32)MsrReg;
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@@ -61,9 +61,9 @@ void backup_mtrr(void *mtrr_store, u32 *mtrr_store_size)
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/* SYSCFG_MSR */
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write_mtrr(&nvram_pos, SYSCFG_MSR);
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/* TOM */
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write_mtrr(&nvram_pos, 0xC001001A);
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write_mtrr(&nvram_pos, TOP_MEM);
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/* TOM2 */
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write_mtrr(&nvram_pos, 0xC001001D);
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write_mtrr(&nvram_pos, TOP_MEM2);
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*mtrr_store_size = nvram_pos - (u8*) mtrr_store;
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}
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@@ -1,6 +1,18 @@
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#ifndef CPU_AMD_MTRR_H
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#define CPU_AMD_MTRR_H
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/* FIXME
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* Replace
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* #define IORR_FIRST 0xC0010016
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* #define IORR_LAST 0xC0010019
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* with
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* #define IORR0_BASE 0xC0010016
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* #define IORR0_MASK 0xC0010017
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* #define IORR1_BASE 0xC0010018
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* #define IORR1_MASK 0xC0010019
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* those are also defined in vendorcode <AGESA.h> file.
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*/
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#define IORR_FIRST 0xC0010016
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#define IORR_LAST 0xC0010019
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@@ -3255,7 +3255,7 @@ static void mct_init(struct MCTStatStruc *pMCTstat,
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pDCTstat->DRPresent = 1;
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/* enable extend PCI configuration access */
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addr = 0xC001001F;
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addr = NB_CFG_MSR;
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_RDMSR(addr, &lo, &hi);
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if (hi & (1 << (46-32))) {
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pDCTstat->Status |= 1 << SB_ExtConfig;
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@@ -3556,7 +3556,7 @@ static u8 CheckNBCOFEarlyArbEn(struct MCTStatStruc *pMCTstat,
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*/
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/* 3*(Fn2xD4[NBFid]+4)/(2^NbDid)/(3+Fn2x94[MemClkFreq]) */
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_RDMSR(0xC0010071, &lo, &hi);
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_RDMSR(MSR_COFVID_STS, &lo, &hi);
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if (lo & (1 << 22))
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NbDid |= 1;
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@@ -816,7 +816,7 @@ void SetTargetWTIO_D(u32 TestAddr)
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u32 lo, hi;
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hi = TestAddr >> 24;
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lo = TestAddr << 8;
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_WRMSR(0xC0010016, lo, hi); /* IORR0 Base */
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_WRMSR(IORR_FIRST, lo, hi); /* IORR0 Base */
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hi = 0xFF;
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lo = 0xFC000800; /* 64MB Mask */
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_WRMSR(0xC0010017, lo, hi); /* IORR0 Mask */
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@@ -6789,7 +6789,7 @@ static void mct_InitialMCT_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc
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boost_states = (Get_NB32(pDCTstat->dev_link, 0x15c) >> 2) & 0x7;
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/* Retrieve and store the TSC frequency (P0 COF) */
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p0_state_msr = rdmsr(0xc0010064 + boost_states);
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p0_state_msr = rdmsr(PSTATE_0_MSR + boost_states);
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cpu_fid = p0_state_msr.lo & 0x3f;
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cpu_did = (p0_state_msr.lo >> 6) & 0x7;
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cpu_divisor = (0x1 << cpu_did);
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@@ -6833,7 +6833,7 @@ static void mct_init(struct MCTStatStruc *pMCTstat,
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pDCTstat->DRPresent = 1;
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/* enable extend PCI configuration access */
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addr = 0xC001001F;
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addr = NB_CFG_MSR;
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_RDMSR(addr, &lo, &hi);
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if (hi & (1 << (46-32))) {
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pDCTstat->Status |= 1 << SB_ExtConfig;
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@@ -7333,7 +7333,7 @@ static u8 CheckNBCOFEarlyArbEn(struct MCTStatStruc *pMCTstat,
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*/
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/* 3*(Fn2xD4[NBFid]+4)/(2^NbDid)/(3+Fn2x94[MemClkFreq]) */
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_RDMSR(0xC0010071, &lo, &hi);
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_RDMSR(MSR_COFVID_STS, &lo, &hi);
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if (lo & (1 << 22))
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NbDid |= 1;
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@@ -2148,7 +2148,7 @@ void SetTargetWTIO_D(u32 TestAddr)
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u32 lo, hi;
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hi = TestAddr >> 24;
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lo = TestAddr << 8;
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_WRMSR(0xC0010016, lo, hi); /* IORR0 Base */
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_WRMSR(IORR_FIRST, lo, hi); /* IORR0 Base */
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hi = 0xFF;
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lo = 0xFC000800; /* 64MB Mask */
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_WRMSR(0xC0010017, lo, hi); /* IORR0 Mask */
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@@ -17,6 +17,9 @@
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#include <arch/cpu.h>
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#include <arch/acpi.h>
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#include <cpu/x86/msr.h>
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#include <cpu/amd/msr.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/amd/mtrr.h>
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#include <device/device.h>
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#include <device/pci_def.h>
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#include <device/pci_ops.h>
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@@ -358,17 +361,18 @@ void copy_mct_data_to_save_variable(struct amd_s3_persistent_data *persistent_da
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data->f2x1b0 = pci_read_config32(dev_fn2, 0x1b0);
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data->f3x44 = pci_read_config32(dev_fn3, 0x44);
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for (i = 0; i < 16; i++) {
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data->msr0000020[i] = rdmsr_uint64_t(0x00000200 | i);
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data->msr0000020[i] =
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rdmsr_uint64_t(MTRR_PHYS_BASE(0) | i);
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}
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data->msr00000250 = rdmsr_uint64_t(0x00000250);
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data->msr00000258 = rdmsr_uint64_t(0x00000258);
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data->msr00000250 = rdmsr_uint64_t(MTRR_FIX_64K_00000);
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data->msr00000258 = rdmsr_uint64_t(MTRR_FIX_16K_80000);
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for (i = 0; i < 8; i++)
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data->msr0000026[i] = rdmsr_uint64_t(0x00000260 | (i + 8));
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data->msr000002ff = rdmsr_uint64_t(0x000002ff);
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data->msrc0010010 = rdmsr_uint64_t(0xc0010010);
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data->msrc001001a = rdmsr_uint64_t(0xc001001a);
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data->msrc001001d = rdmsr_uint64_t(0xc001001d);
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data->msrc001001f = rdmsr_uint64_t(0xc001001f);
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data->msr000002ff = rdmsr_uint64_t(MTRR_DEF_TYPE_MSR);
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data->msrc0010010 = rdmsr_uint64_t(SYSCFG_MSR);
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data->msrc001001a = rdmsr_uint64_t(TOP_MEM);
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data->msrc001001d = rdmsr_uint64_t(TOP_MEM2);
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data->msrc001001f = rdmsr_uint64_t(NB_CFG_MSR);
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/* Stage 3 */
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data->f2x40 = read_config32_dct(dev_fn2, node, channel, 0x40);
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@@ -697,10 +701,11 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data *persiste
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write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x1b0, data->f2x1b0);
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write_config32_dct(PCI_DEV(0, 0x18 + node, 3), node, channel, 0x44, data->f3x44);
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for (i = 0; i < 16; i++) {
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wrmsr_uint64_t(0x00000200 | i, data->msr0000020[i]);
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wrmsr_uint64_t(MTRR_PHYS_BASE(0) | i,
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data->msr0000020[i]);
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}
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wrmsr_uint64_t(0x00000250, data->msr00000250);
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wrmsr_uint64_t(0x00000258, data->msr00000258);
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wrmsr_uint64_t(MTRR_FIX_64K_00000, data->msr00000250);
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wrmsr_uint64_t(MTRR_FIX_16K_80000, data->msr00000258);
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/* FIXME
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* Restoring these MSRs causes a hang on resume due to
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* destroying CAR while still executing from CAR!
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@@ -708,11 +713,11 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data *persiste
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*/
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// for (i = 0; i < 8; i++)
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// wrmsr_uint64_t(0x00000260 | (i + 8), data->msr0000026[i]);
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wrmsr_uint64_t(0x000002ff, data->msr000002ff);
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wrmsr_uint64_t(0xc0010010, data->msrc0010010);
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wrmsr_uint64_t(0xc001001a, data->msrc001001a);
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wrmsr_uint64_t(0xc001001d, data->msrc001001d);
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wrmsr_uint64_t(0xc001001f, data->msrc001001f);
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wrmsr_uint64_t(MTRR_DEF_TYPE_MSR, data->msr000002ff);
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wrmsr_uint64_t(SYSCFG_MSR, data->msrc0010010);
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wrmsr_uint64_t(TOP_MEM, data->msrc001001a);
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wrmsr_uint64_t(TOP_MEM2, data->msrc001001d);
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wrmsr_uint64_t(NB_CFG_MSR, data->msrc001001f);
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}
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}
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@@ -34,6 +34,7 @@
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#include <device/pci_ops.h>
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#include <delay.h>
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#include <cpu/x86/msr.h>
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#include <cpu/amd/mtrr.h>
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#include "rs780.h"
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/* Trust the original resource allocation. Don't do it again. */
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@@ -762,11 +763,11 @@ static void rs780_internal_gfx_enable(struct device *dev)
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printk(BIOS_DEBUG, "rs780_internal_gfx_enable dev = 0x%p, nb_dev = 0x%p.\n", dev, nb_dev);
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/* The system top memory in 780. */
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sysmem = rdmsr(0xc001001a);
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sysmem = rdmsr(TOP_MEM);
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printk(BIOS_DEBUG, "Sysmem TOM = %x_%x\n", sysmem.hi, sysmem.lo);
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pci_write_config32(nb_dev, 0x90, sysmem.lo);
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sysmem = rdmsr(0xc001001D);
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sysmem = rdmsr(TOP_MEM2);
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printk(BIOS_DEBUG, "Sysmem TOM2 = %x_%x\n", sysmem.hi, sysmem.lo);
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htiu_write_index(nb_dev, 0x31, sysmem.hi);
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htiu_write_index(nb_dev, 0x30, sysmem.lo | 1);
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@@ -304,11 +304,11 @@ void sr5650_set_tom(struct device *nb_dev)
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msr_t sysmem;
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/* The system top memory in SR56X0. */
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sysmem = rdmsr(0xc001001A);
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sysmem = rdmsr(TOP_MEM);
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printk(BIOS_DEBUG, "Sysmem TOM = %x_%x\n", sysmem.hi, sysmem.lo);
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pci_write_config32(nb_dev, 0x90, sysmem.lo);
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sysmem = rdmsr(0xc001001D);
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sysmem = rdmsr(TOP_MEM2);
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printk(BIOS_DEBUG, "Sysmem TOM2 = %x_%x\n", sysmem.hi, sysmem.lo);
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htiu_write_index(nb_dev, 0x31, sysmem.hi);
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htiu_write_index(nb_dev, 0x30, sysmem.lo | 1);
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