Initial AMD Barcelona support for rev Bx.
These are the core files for HyperTransport, DDR2 Memory, and multi-core initialization. Signed-off-by: Marc Jones <marc.jones@amd.com> Reviewed-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Myles Watson <myles@pel.cs.byu.edu> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3014 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Marc Jones
@ -291,6 +291,11 @@ define USE_DCACHE_RAM
|
||||
export always
|
||||
comment "Use data cache as temporary RAM if possible"
|
||||
end
|
||||
define CAR_FAM10
|
||||
default 0
|
||||
export always
|
||||
comment "AMD family 10 CAR requires additional setup"
|
||||
end
|
||||
define DCACHE_RAM_BASE
|
||||
default 0xc0000
|
||||
format "0x%x"
|
||||
@ -937,6 +942,12 @@ define MMCONF_SUPPORT
|
||||
comment "enable mmconfig for pci conf"
|
||||
end
|
||||
|
||||
define MMCONF_SUPPORT_DEFAULT
|
||||
default 0
|
||||
export always
|
||||
comment "enable mmconfig for pci conf"
|
||||
end
|
||||
|
||||
define HW_MEM_HOLE_SIZEK
|
||||
default 0
|
||||
export always
|
||||
@ -949,6 +960,12 @@ define HW_MEM_HOLE_SIZE_AUTO_INC
|
||||
comment "Opteron E0 later memory hole size auto increase to avoid hole startk equal to basek"
|
||||
end
|
||||
|
||||
define CONFIG_VAR_MTRR_HOLE
|
||||
default 1
|
||||
export always
|
||||
comment "using hole in MTRR instead of increasing method"
|
||||
end
|
||||
|
||||
define K8_HT_FREQ_1G_SUPPORT
|
||||
default 0
|
||||
export always
|
||||
@ -973,6 +990,24 @@ define CDB
|
||||
comment "Opteron cpu device num base"
|
||||
end
|
||||
|
||||
define HT3_SUPPORT
|
||||
default 0
|
||||
export always
|
||||
comment "Hypertransport 3 support, include ac HT and unganged sublink feature"
|
||||
end
|
||||
|
||||
define EXT_RT_TBL_SUPPORT
|
||||
default 0
|
||||
export always
|
||||
comment "support AMD family 10 extended routing table via F0x158, normally is enabled when node nums is greater than 8"
|
||||
end
|
||||
|
||||
define EXT_CONF_SUPPORT
|
||||
default 0
|
||||
export always
|
||||
comment "support AMD family 10 extended config space for ram, bus, io, mmio via F1x110, normally is enabled when HT3 is enabled and non ht chain nums is greater than 4"
|
||||
end
|
||||
|
||||
define DIMM_SUPPORT
|
||||
default 0x0108
|
||||
format "0x%x"
|
||||
@ -989,7 +1024,7 @@ end
|
||||
define CPU_ADDR_BITS
|
||||
default 36
|
||||
export always
|
||||
comment "CPU hardware address lines num, for AMD K8 could be 40, and GH could be 48"
|
||||
comment "CPU hardware address lines num, for AMD K8 could be 40, and AMD family 10 could be 48"
|
||||
end
|
||||
|
||||
define CONFIG_PCI_ROM_RUN
|
||||
@ -1004,10 +1039,10 @@ define CONFIG_PCI_64BIT_PREF_MEM
|
||||
comment "allow PCI device get 4G above Region as pref mem"
|
||||
end
|
||||
|
||||
define CONFIG_AGESA
|
||||
define CONFIG_AMDMCT
|
||||
default 0
|
||||
export always
|
||||
comment "use AMD AGESA to init RAM instead of native code"
|
||||
comment "use AMD MCT to init RAM instead of native code"
|
||||
end
|
||||
|
||||
define CONFIG_VIDEO_MB
|
||||
|
||||
@ -23,16 +23,23 @@
|
||||
/* leave some space for global variable to pass to RAM stage */
|
||||
#define GlobalVarSize DCACHE_RAM_GLOBAL_VAR_SIZE
|
||||
|
||||
#if CAR_FAM10 == 1
|
||||
#define CacheSizeAPStack 0x400 /* 1K */
|
||||
#endif
|
||||
|
||||
#include <cpu/x86/mtrr.h>
|
||||
#include <cpu/amd/mtrr.h>
|
||||
|
||||
/* Save the BIST result */
|
||||
movl %eax, %ebp
|
||||
|
||||
/* for normal part %ebx already contain cpu_init_detected from fallback call */
|
||||
/*for normal part %ebx already contain cpu_init_detected from fallback call */
|
||||
|
||||
cache_as_ram_setup:
|
||||
|
||||
movb $0xA0, %al
|
||||
outb %al, $0x80
|
||||
|
||||
/* hope we can skip the double set for normal part */
|
||||
#if ((HAVE_FAILOVER_BOOT == 1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT == 0) && (USE_FALLBACK_IMAGE == 1))
|
||||
|
||||
@ -42,6 +49,53 @@ cache_as_ram_setup:
|
||||
andl $(1 << 11), %eax
|
||||
movl %eax, %ebx /* We store the status */
|
||||
|
||||
#if CAR_FAM10 == 1
|
||||
/* for GH, CAR need to set DRAM Base/Limit Registers to direct that to node0 */
|
||||
|
||||
/* Only BSP needed, for other nodes set during HT/memory init. */
|
||||
/* So we need to check if it is BSP */
|
||||
movl $0x1b, %ecx
|
||||
rdmsr
|
||||
bt $8, %eax /*BSC */
|
||||
jnc CAR_FAM10_out
|
||||
|
||||
/* Enable RT tables on BSP */
|
||||
movl $0x8000c06c, %eax
|
||||
movw $0xcf8, %dx
|
||||
outl %eax, %dx
|
||||
addw $4, %dx
|
||||
inl %dx, %eax
|
||||
btr $0, %eax
|
||||
outl %eax, %dx
|
||||
|
||||
/* Setup temporary DRAM map: [0,16M) bit 0-23 */
|
||||
movl $0x8000c144, %eax
|
||||
movw $0xcf8, %dx
|
||||
outl %eax, %dx
|
||||
addw $4, %dx
|
||||
movl $0, %eax
|
||||
outl %eax, %dx
|
||||
|
||||
movl $0x8000c140, %eax
|
||||
movw $0xcf8, %dx
|
||||
outl %eax, %dx
|
||||
addw $4, %dx
|
||||
movl $3, %eax
|
||||
outl %eax, %dx
|
||||
|
||||
CAR_FAM10_out:
|
||||
|
||||
#endif
|
||||
|
||||
#if CAR_FAM10 == 1
|
||||
/* Errata 193: Disable clean copybacks to L3 cache to allow cached ROM.
|
||||
Re-enable it in after RAM is initialized and before CAR is disabled */
|
||||
movl $0xc001102a, %ecx
|
||||
rdmsr
|
||||
bts $15, %eax
|
||||
wrmsr
|
||||
#endif
|
||||
|
||||
/* Set MtrrFixDramModEn for clear fixed mtrr */
|
||||
enable_fixed_mtrr_dram_modify:
|
||||
movl $SYSCFG_MSR, %ecx
|
||||
@ -68,9 +122,14 @@ clear_fixed_var_mtrr_out:
|
||||
|
||||
#if CacheSize == 0x10000
|
||||
/* enable caching for 64K using fixed mtrr */
|
||||
movl $0x268, %ecx /* fix4k_c0000 */
|
||||
movl $0x06060606, %eax /* WB IO type */
|
||||
movl %eax, %edx
|
||||
movl $0x268, %ecx /* fix4k_c0000*/
|
||||
#if CAR_FAM10 == 1
|
||||
movl $0x1e1e1e1e, %edx /* WB MEM type */
|
||||
#else
|
||||
movl $0x06060606, %edx /* WB IO type */
|
||||
#endif
|
||||
|
||||
movl %edx, %eax
|
||||
wrmsr
|
||||
movl $0x269, %ecx
|
||||
wrmsr
|
||||
@ -78,38 +137,62 @@ clear_fixed_var_mtrr_out:
|
||||
|
||||
#if CacheSize == 0xc000
|
||||
/* enable caching for 16K using fixed mtrr */
|
||||
movl $0x268, %ecx /* fix4k_c4000 */
|
||||
movl $0x268, %ecx /* fix4k_c4000*/
|
||||
#if CAR_FAM10 == 1
|
||||
movl $0x1e1e1e1e, %edx /* WB MEM type */
|
||||
#else
|
||||
movl $0x06060606, %edx /* WB IO type */
|
||||
#endif
|
||||
xorl %eax, %eax
|
||||
wrmsr
|
||||
/* enable caching for 32K using fixed mtrr */
|
||||
movl $0x269, %ecx /* fix4k_c8000 */
|
||||
movl $0x06060606, %eax /* WB IO type */
|
||||
movl %eax, %edx
|
||||
movl $0x269, %ecx /* fix4k_c8000*/
|
||||
#if CAR_FAM10 == 1
|
||||
movl $0x1e1e1e1e, %edx /* WB MEM type */
|
||||
#else
|
||||
movl $0x06060606, %edx /* WB IO type */
|
||||
#endif
|
||||
movl %edx, %eax
|
||||
wrmsr
|
||||
#endif
|
||||
|
||||
|
||||
#if CacheSize == 0x8000
|
||||
/* enable caching for 32K using fixed mtrr */
|
||||
movl $0x269, %ecx /* fix4k_c8000 */
|
||||
movl $0x06060606, %eax /* WB IO type */
|
||||
movl %eax, %edx
|
||||
movl $0x269, %ecx /* fix4k_c8000*/
|
||||
#if CAR_FAM10 == 1
|
||||
movl $0x1e1e1e1e, %edx /* WB MEM type */
|
||||
#else
|
||||
movl $0x06060606, %edx /* WB IO type */
|
||||
#endif
|
||||
movl %edx, %eax
|
||||
wrmsr
|
||||
#endif
|
||||
|
||||
#if CacheSize < 0x8000
|
||||
/* enable caching for 16K/8K/4K using fixed mtrr */
|
||||
movl $0x269, %ecx /* fix4k_cc000*/
|
||||
#if CacheSize == 0x4000
|
||||
#if CacheSize == 0x4000
|
||||
#if CAR_FAM10 == 1
|
||||
movl $0x1e1e1e1e, %edx /* WB MEM type */
|
||||
#else
|
||||
movl $0x06060606, %edx /* WB IO type */
|
||||
#endif
|
||||
#if CacheSize == 0x2000
|
||||
#endif
|
||||
#endif
|
||||
#if CacheSize == 0x2000
|
||||
#if CAR_FAM10 == 1
|
||||
movl $0x1e1e0000, %edx /* WB MEM type */
|
||||
#else
|
||||
movl $0x06060000, %edx /* WB IO type */
|
||||
#endif
|
||||
#if CacheSize == 0x1000
|
||||
#endif
|
||||
#endif
|
||||
#if CacheSize == 0x1000
|
||||
#if CAR_FAM10 == 1
|
||||
movl $0x1e000000, %edx /* WB MEM type */
|
||||
#else
|
||||
movl $0x06000000, %edx /* WB IO type */
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
xorl %eax, %eax
|
||||
wrmsr
|
||||
#endif
|
||||
@ -160,13 +243,27 @@ clear_fixed_var_mtrr_out:
|
||||
wrmsr
|
||||
#endif
|
||||
|
||||
movb $0xA1, %al
|
||||
outb %al, $0x80
|
||||
|
||||
/* enable cache */
|
||||
movl %cr0, %eax
|
||||
andl $0x9fffffff, %eax
|
||||
movl %eax, %cr0
|
||||
|
||||
#if ((HAVE_FAILOVER_BOOT == 1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT == 0) && (USE_FALLBACK_IMAGE == 1))
|
||||
|
||||
#if CAR_FAM10 == 1
|
||||
/* So we need to check if it is BSP */
|
||||
movl $0x1b, %ecx
|
||||
rdmsr
|
||||
bt $8, %eax /*BSC */
|
||||
jnc CAR_FAM10_ap
|
||||
#endif
|
||||
|
||||
movb $0xA2, %al
|
||||
outb %al, $0x80
|
||||
|
||||
#if ((HAVE_FAILOVER_BOOT == 1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT == 0) && (USE_FALLBACK_IMAGE == 1))
|
||||
/* Read the range with lodsl*/
|
||||
cld
|
||||
movl $CacheBase, %esi
|
||||
@ -184,6 +281,60 @@ clear_fixed_var_mtrr_out:
|
||||
movl $(CacheBase + CacheSize - GlobalVarSize), %eax
|
||||
movl %eax, %esp
|
||||
|
||||
movb $0xA3, %al
|
||||
outb %al, $0x80
|
||||
|
||||
#if CAR_FAM10 == 1
|
||||
|
||||
jmp CAR_FAM10_ap_out
|
||||
CAR_FAM10_ap:
|
||||
/* need to set stack pointer for AP */
|
||||
/* it will be from CacheBase + (CacheSize - GlobalVarSize)/2 - (NodeID<<CoreIDbits + CoreID) * CacheSizeAPStack*/
|
||||
/* So need to get the NodeID and CoreID at first */
|
||||
/* If NB_CFG bit 54 is set just use initial apicid, otherwise need to reverse it */
|
||||
|
||||
/* store our init detected */
|
||||
movl %ebx, %esi
|
||||
|
||||
/* get the coreid bits at first */
|
||||
movl $0x80000008, %eax
|
||||
cpuid
|
||||
shrl $12, %ecx
|
||||
andl $0x0f, %ecx
|
||||
movl %ecx, %edi
|
||||
|
||||
/* get the initial apic id */
|
||||
movl $1, %eax
|
||||
cpuid
|
||||
shrl $24, %ebx
|
||||
|
||||
/* get the nb cfg bit 54 */
|
||||
movl $0xc001001f, %ecx /* NB_CFG_MSR */
|
||||
rdmsr
|
||||
movl %edi, %ecx /* CoreID bits */
|
||||
bt $(54-32), %edx
|
||||
jc roll_cfg
|
||||
rolb %cl, %bl
|
||||
roll_cfg:
|
||||
|
||||
/* calculate stack pointer */
|
||||
movl $CacheSizeAPStack, %eax
|
||||
mull %ebx
|
||||
movl $(CacheBase + (CacheSize - GlobalVarSize)/2), %esp
|
||||
subl %eax, %esp
|
||||
|
||||
/* retrive init detected */
|
||||
movl %esi, %ebx
|
||||
|
||||
movb $0xA4, %al
|
||||
outb %al, $0x80
|
||||
|
||||
CAR_FAM10_ap_out:
|
||||
#endif
|
||||
|
||||
movb $0xA5, %al
|
||||
outb %al, $0x80
|
||||
|
||||
/* Restore the BIST result */
|
||||
movl %ebp, %eax
|
||||
|
||||
@ -194,6 +345,9 @@ clear_fixed_var_mtrr_out:
|
||||
call cache_as_ram_main
|
||||
/* We will not go back */
|
||||
|
||||
movb $0xAF, %al /* Should never see this postcode */
|
||||
outb %al, $0x80
|
||||
|
||||
fixed_mtrr_msr:
|
||||
.long 0x250, 0x258, 0x259
|
||||
.long 0x268, 0x269, 0x26A
|
||||
|
||||
@ -17,6 +17,8 @@
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef __ROMCC__
|
||||
|
||||
#include <stdint.h>
|
||||
#include <console/console.h>
|
||||
#include <cpu/cpu.h>
|
||||
@ -24,6 +26,8 @@
|
||||
#include <cpu/amd/microcode.h>
|
||||
#include <cpu/x86/cache.h>
|
||||
|
||||
#endif
|
||||
|
||||
struct microcode {
|
||||
u32 date_code;
|
||||
u32 patch_id;
|
||||
@ -56,8 +60,11 @@ struct microcode {
|
||||
static int need_apply_patch(struct microcode *m, u32 equivalent_processor_rev_id)
|
||||
{
|
||||
|
||||
if (m->processor_rev_id != equivalent_processor_rev_id) return 0;
|
||||
|
||||
if (m->processor_rev_id != equivalent_processor_rev_id) {
|
||||
printk_debug("microcode: rev id does not match this patch.\n");
|
||||
printk_debug("microcode: Not updated! Fix microcode_updates[] \n");
|
||||
return 0;
|
||||
}
|
||||
if (m->nb_dev_id) {
|
||||
//look at the device id, if not found return;
|
||||
//if(m->nb_rev_id != installed_nb_rev_id) return 0;
|
||||
@ -86,7 +93,7 @@ void amd_update_microcode(void *microcode_updates, u32 equivalent_processor_rev_
|
||||
msr = rdmsr(0x8b);
|
||||
patch_id = msr.lo;
|
||||
|
||||
printk_debug("microcode: equivalent processor rev id = 0x%04x, patch id = 0x%08x\n", equivalent_processor_rev_id, patch_id);
|
||||
printk_debug("microcode: equivalent rev id = 0x%04x, current patch id = 0x%08x\n", equivalent_processor_rev_id, patch_id);
|
||||
|
||||
m = microcode_updates;
|
||||
|
||||
@ -100,13 +107,13 @@ void amd_update_microcode(void *microcode_updates, u32 equivalent_processor_rev_
|
||||
|
||||
wrmsr(0xc0010020, msr);
|
||||
|
||||
printk_debug("microcode: patch id that want to apply= 0x%08x\n", m->patch_id);
|
||||
printk_debug("microcode: patch id to apply = 0x%08x\n", m->patch_id);
|
||||
|
||||
//read the patch_id again
|
||||
msr = rdmsr(0x8b);
|
||||
new_patch_id = msr.lo;
|
||||
|
||||
printk_debug("microcode: updated to patch id = 0x%08x %s\r\n", new_patch_id , (new_patch_id == m->patch_id)?" success":" fail" );
|
||||
printk_debug("microcode: updated to patch id = 0x%08x %s\n", new_patch_id , (new_patch_id == m->patch_id)?" success\n":" fail\n" );
|
||||
break;
|
||||
}
|
||||
c += 2048;
|
||||
|
||||
40
src/cpu/amd/model_10xxx/Config.lb
Normal file
40
src/cpu/amd/model_10xxx/Config.lb
Normal file
@ -0,0 +1,40 @@
|
||||
#
|
||||
# This file is part of the LinuxBIOS project.
|
||||
#
|
||||
# Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; version 2 of the License.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
#
|
||||
|
||||
uses HAVE_INIT_TIMER
|
||||
uses HAVE_MOVNTI
|
||||
uses CPU_ADDR_BITS
|
||||
|
||||
default HAVE_INIT_TIMER=1
|
||||
default HAVE_MOVNTI=1
|
||||
default CPU_ADDR_BITS=48
|
||||
dir /cpu/x86/tsc
|
||||
dir /cpu/x86/fpu
|
||||
dir /cpu/x86/mmx
|
||||
dir /cpu/x86/sse
|
||||
dir /cpu/x86/lapic
|
||||
dir /cpu/x86/cache
|
||||
dir /cpu/x86/pae
|
||||
dir /cpu/amd/mtrr
|
||||
dir /cpu/amd/quadcore
|
||||
dir /cpu/amd/microcode
|
||||
driver model_10xxx_init.o
|
||||
object update_microcode.o
|
||||
object apic_timer.o
|
||||
object pstate.o
|
||||
55
src/cpu/amd/model_10xxx/apic_timer.c
Normal file
55
src/cpu/amd/model_10xxx/apic_timer.c
Normal file
@ -0,0 +1,55 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <delay.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
|
||||
/* NOTE: We use the APIC TIMER register is to hold flags for AP init during
|
||||
* pre-memory init (ROMCC). Don't use init_timer() and udelay is redirected
|
||||
* to udelay_tsc().
|
||||
*/
|
||||
|
||||
|
||||
void init_timer(void)
|
||||
{
|
||||
/* Set the apic timer to no interrupts and periodic mode */
|
||||
lapic_write(LAPIC_LVTT, (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0));
|
||||
|
||||
/* Set the divider to 1, no divider */
|
||||
lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1);
|
||||
|
||||
/* Set the initial counter to 0xffffffff */
|
||||
lapic_write(LAPIC_TMICT, 0xffffffff);
|
||||
|
||||
}
|
||||
|
||||
|
||||
void udelay(u32 usecs)
|
||||
{
|
||||
u32 start, value, ticks;
|
||||
/* Calculate the number of ticks to run, our FSB runs a 200Mhz */
|
||||
ticks = usecs * 200;
|
||||
start = lapic_read(LAPIC_TMCCT);
|
||||
do {
|
||||
value = lapic_read(LAPIC_TMCCT);
|
||||
} while((start - value) < ticks);
|
||||
|
||||
}
|
||||
455
src/cpu/amd/model_10xxx/fidvid.c
Normal file
455
src/cpu/amd/model_10xxx/fidvid.c
Normal file
@ -0,0 +1,455 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#if FAM10_SET_FIDVID == 1
|
||||
|
||||
#define FAM10_SET_FIDVID_DEBUG 1
|
||||
|
||||
// if we are tight of CAR stack, disable it
|
||||
#define FAM10_SET_FIDVID_STORE_AP_APICID_AT_FIRST 1
|
||||
|
||||
static inline void print_debug_fv(const char *str, u32 val)
|
||||
{
|
||||
#if FAM10_SET_FIDVID_DEBUG == 1
|
||||
printk_debug("%s%x\n", str, val);
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void print_debug_fv_8(const char *str, u8 val)
|
||||
{
|
||||
#if FAM10_SET_FIDVID_DEBUG == 1
|
||||
printk_debug("%s%02x\n", str, val);
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void print_debug_fv_64(const char *str, u32 val, u32 val2)
|
||||
{
|
||||
#if FAM10_SET_FIDVID_DEBUG == 1
|
||||
printk_debug("%s%x%x\n", str, val, val2);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
static void enable_fid_change(u8 fid)
|
||||
{
|
||||
u32 dword;
|
||||
u32 nodes;
|
||||
device_t dev;
|
||||
int i;
|
||||
|
||||
nodes = ((pci_read_config32(PCI_DEV(CBB, CDB, 0), 0x60) >> 4) & 7) + 1;
|
||||
|
||||
for(i = 0; i < nodes; i++) {
|
||||
dev = NODE_PCI(i,3);
|
||||
dword = pci_read_config32(dev, 0xd4);
|
||||
dword &= ~0x1F;
|
||||
dword |= (u32) fid & 0x1F;
|
||||
dword |= 1 << 5; // enable
|
||||
pci_write_config32(dev, 0xd4, dword);
|
||||
printk_debug("FID Change Node:%02x, F3xD4: %08x \n", i, dword);
|
||||
}
|
||||
}
|
||||
|
||||
static void prep_fid_change(void)
|
||||
{
|
||||
u32 dword;
|
||||
u32 nodes;
|
||||
device_t dev;
|
||||
int i;
|
||||
|
||||
/* This needs to be run before any Pstate changes are requested */
|
||||
|
||||
nodes = ((pci_read_config32(PCI_DEV(CBB, CDB, 0), 0x60) >> 4) & 7) + 1;
|
||||
|
||||
for(i = 0; i < nodes; i++) {
|
||||
printk_debug("Node:%02x \n", i);
|
||||
dev = NODE_PCI(i,3);
|
||||
|
||||
dword = pci_read_config32(dev, 0xa0);
|
||||
dword &= ~(1<<29);
|
||||
dword |= ((~dword >> 8) & 1) << 29; // SlamVidMode is the inverse to the PviMode
|
||||
dword |= PLLLOCK_DFT_L; /* Force per BKDG */
|
||||
pci_write_config32(dev, 0xa0, dword);
|
||||
printk_debug(" F3xA0: %08x \n", dword);
|
||||
|
||||
dword = pci_read_config32(dev, 0xd8);
|
||||
dword &= ~0x77;
|
||||
dword |= (1<<4) | 6; // VSRampTime, and VSSlamTime
|
||||
dword |= 3 << 24; // ReConDel set to 3 per BKDG
|
||||
pci_write_config32(dev, 0xd8, dword);
|
||||
printk_debug(" F3xD8: %08x \n", dword);
|
||||
|
||||
dword = pci_read_config32(dev, 0xd4);
|
||||
dword &= 0x1F;
|
||||
dword |= 0xC331AF00; // per BKDG
|
||||
pci_write_config32(dev, 0xd4, dword);
|
||||
printk_debug(" F3xD4: %08x \n", dword);
|
||||
|
||||
dword = pci_read_config32(dev, 0xdc);
|
||||
dword |= 0x5 << 12; // NbsynPtrAdj set to 0x5 per BKDG (needs reset)
|
||||
pci_write_config32(dev, 0xdc, dword);
|
||||
printk_debug(" F3xDC: %08x \n", dword);
|
||||
|
||||
// Rev B settings - FIXME: support other revs.
|
||||
dword = 0xA0E641E6;
|
||||
pci_write_config32(dev, 0x84, dword);
|
||||
printk_debug(" F3x84: %08x \n", dword);
|
||||
|
||||
dword = 0xE600A681;
|
||||
pci_write_config32(dev, 0x80, dword);
|
||||
printk_debug(" F3x80: %08x \n", dword);
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#include "fidvid_common.c"
|
||||
|
||||
|
||||
|
||||
static void init_fidvid_ap(u32 bsp_apicid, u32 apicid, u32 nodeid, u32 coreid)
|
||||
{
|
||||
|
||||
msr_t msr;
|
||||
device_t dev;
|
||||
u8 vid_max;
|
||||
u8 fid_max;
|
||||
u8 startup_pstate;
|
||||
u8 nb_cof_vid_update;
|
||||
u8 pvimode;
|
||||
u32 reg1fc;
|
||||
u32 dword;
|
||||
u32 send;
|
||||
|
||||
printk_debug("FIDVID on AP: %02x\n", apicid);
|
||||
|
||||
/* Only support single plane system at this time. */
|
||||
/* Steps 1-6 of BIOS NB COF and VID Configuration
|
||||
* for Single-Plane PVI Systems
|
||||
*/
|
||||
dev = NODE_PCI(nodeid,3);
|
||||
reg1fc = pci_read_config32(dev, 0x1FC);
|
||||
nb_cof_vid_update = reg1fc & 1;
|
||||
if (nb_cof_vid_update) {
|
||||
/* Get fused settings */
|
||||
dword = pci_read_config32(dev, 0xa0);
|
||||
pvimode = (dword >> 8) & 1;
|
||||
|
||||
vid_max = (reg1fc >> 7) & 0x7F; // per node
|
||||
fid_max = (reg1fc >> 2) & 0x1F; // per system
|
||||
|
||||
if (pvimode) {
|
||||
/* FIXME: support daul plane mode */
|
||||
die("PVImode not supported\n");
|
||||
/* fidmax = vidmax - (reg1fc >> 17) & 0x1F;
|
||||
fidmax = fidmax + (reg1fc >> 14) & 0x03;
|
||||
*/
|
||||
}
|
||||
|
||||
} else {
|
||||
/* Use current values */
|
||||
msr = rdmsr(0xc0010071);
|
||||
fid_max = ((msr.hi >> (59-32)) & 0x1f); //max nb fid
|
||||
vid_max = ((msr.hi >> (35-32)) & 0x7f); //max vid
|
||||
}
|
||||
|
||||
/* Note this is the single plane setup. Need to add dual plane path */
|
||||
msr = rdmsr(0xc0010071);
|
||||
startup_pstate = (msr.hi >> (32-32)) & 0x07;
|
||||
|
||||
|
||||
/* Copy startup pstate to P1 and P0 MSRs. Set the maxvid for this node in P0.
|
||||
Then transition to P1 for corex and P0 for core0. */
|
||||
msr = rdmsr(0xC0010064 + startup_pstate);
|
||||
wrmsr(0xC0010065, msr);
|
||||
wrmsr(0xC0010064, msr);
|
||||
|
||||
msr.lo &= ~0xFE000000; // clear nbvid
|
||||
msr.lo |= vid_max << 25;
|
||||
wrmsr(0xC0010064, msr);
|
||||
|
||||
// Transition to P1 for all APs and P0 for core0.
|
||||
msr = rdmsr(0xC0010062);
|
||||
msr.lo = (msr.lo & ~0x07) | 1;
|
||||
wrmsr(0xC0010062, msr);
|
||||
|
||||
// Wait for P1 to set.
|
||||
do {
|
||||
msr = rdmsr(0xC0010063);
|
||||
} while (msr.lo != 1);
|
||||
|
||||
if (coreid == 0) {
|
||||
msr.lo = msr.lo & ~0x07;
|
||||
wrmsr(0xC0010062, msr);
|
||||
// Wait for P0 to set.
|
||||
do {
|
||||
msr = rdmsr(0xC0010063);
|
||||
} while (msr.lo != 0);
|
||||
}
|
||||
|
||||
|
||||
send = (nb_cof_vid_update << 16) | (fid_max << 8);
|
||||
send |= (apicid << 24); // ap apicid
|
||||
|
||||
// Send signal to BSP about this AP max fid
|
||||
// This also indicates this AP is ready for warm reset (if required).
|
||||
lapic_write(LAPIC_MSG_REG, send | 1);
|
||||
}
|
||||
|
||||
static u32 calc_common_fid(u32 fid_packed, u32 fid_packed_new)
|
||||
{
|
||||
u32 fidmax;
|
||||
u32 fidmax_new;
|
||||
|
||||
fidmax = (fid_packed >> 8) & 0xFF;
|
||||
|
||||
fidmax_new = (fid_packed_new >> 8) & 0xFF;
|
||||
|
||||
if(fidmax > fidmax_new) {
|
||||
fidmax = fidmax_new;
|
||||
}
|
||||
|
||||
fid_packed &= 0xFF << 16;
|
||||
fid_packed |= (fidmax << 8);
|
||||
fid_packed |= fid_packed_new & (0xFF << 16); // set nb_cof_vid_update
|
||||
|
||||
return fid_packed;
|
||||
}
|
||||
|
||||
struct fidvid_st {
|
||||
u32 common_fid;
|
||||
};
|
||||
|
||||
static void init_fidvid_bsp_stage1(u32 ap_apicid, void *gp )
|
||||
{
|
||||
u32 readback = 0;
|
||||
u32 timeout = 1;
|
||||
|
||||
struct fidvid_st *fvp = gp;
|
||||
int loop;
|
||||
|
||||
print_debug_fv("Wait for AP stage 1: ap_apicid = ", ap_apicid);
|
||||
|
||||
loop = 100000;
|
||||
while(--loop > 0) {
|
||||
if(lapic_remote_read(ap_apicid, LAPIC_MSG_REG, &readback) != 0) continue;
|
||||
if((readback & 0x3f) == 1) {
|
||||
timeout = 0;
|
||||
break; //target ap is in stage 1
|
||||
}
|
||||
}
|
||||
|
||||
if(timeout) {
|
||||
print_initcpu8("fidvid_bsp_stage1: time out while reading from ap ", ap_apicid);
|
||||
return;
|
||||
}
|
||||
|
||||
print_debug_fv("\treadback = ", readback);
|
||||
|
||||
fvp->common_fid = calc_common_fid(fvp->common_fid, readback);
|
||||
|
||||
print_debug_fv("\tcommon_fid(packed) = ", fvp->common_fid);
|
||||
|
||||
}
|
||||
|
||||
|
||||
static void init_fidvid_stage2(u32 apicid, u32 nodeid)
|
||||
{
|
||||
msr_t msr;
|
||||
device_t dev;
|
||||
u32 reg1fc;
|
||||
u8 StartupPstate;
|
||||
u8 nbvid;
|
||||
int i;
|
||||
|
||||
/* After warm reset finish the fid/vid setup for all cores. */
|
||||
dev = NODE_PCI(nodeid,3);
|
||||
reg1fc = pci_read_config32(dev, 0x1FC);
|
||||
nbvid = (reg1fc >> 7) & 0x7F;
|
||||
|
||||
if (reg1fc & 0x02) { // NbVidUpdateAll ?
|
||||
for( i = 0; i < 5; i++) {
|
||||
msr = rdmsr(0xC0010064 + i);
|
||||
if ((msr.hi >> 31) & 1) { // PstateEn?
|
||||
msr.lo &= ~(0x7F << 25);
|
||||
msr.lo |= (nbvid & 0x7F) << 25;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
for( i = 0; i < 5; i++) {
|
||||
msr = rdmsr(0xC0010064 + i);
|
||||
if (((msr.hi >> 31) & 1) && (((msr.lo >> 22) & 1) == 0)) { // PstateEn and PDid == 0?
|
||||
msr.lo &= ~(0x7F << 25);
|
||||
msr.lo |= (nbvid & 0x7F) << 25;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// For each processor in the system, transition all cores to StartupPstate
|
||||
msr = rdmsr(0xC0010071);
|
||||
StartupPstate = msr.hi >> (32-32) & 0x03;
|
||||
msr = rdmsr(0xC0010062);
|
||||
msr.lo = StartupPstate;
|
||||
wrmsr(0xC0010062, msr);
|
||||
}
|
||||
|
||||
|
||||
#if FAM10_SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
|
||||
struct ap_apicid_st {
|
||||
u32 num;
|
||||
// it could use 256 bytes for 64 node quad core system
|
||||
u8 apicid[NODE_NUMS * 4];
|
||||
};
|
||||
|
||||
static void store_ap_apicid(unsigned ap_apicid, void *gp)
|
||||
{
|
||||
struct ap_apicid_st *p = gp;
|
||||
|
||||
p->apicid[p->num++] = ap_apicid;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
static int init_fidvid_bsp(u32 bsp_apicid, u32 nodes)
|
||||
{
|
||||
#if FAM10_SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
|
||||
struct ap_apicid_st ap_apicidx;
|
||||
u32 i;
|
||||
#endif
|
||||
struct fidvid_st fv;
|
||||
msr_t msr;
|
||||
device_t dev;
|
||||
u8 vid_max;
|
||||
u8 fid_max;
|
||||
u8 startup_pstate;
|
||||
u8 nb_cof_vid_update;
|
||||
u32 reg1fc;
|
||||
u32 dword;
|
||||
u8 pvimode;
|
||||
|
||||
printk_debug("FIDVID on BSP, APIC_id: %02x\n", bsp_apicid);
|
||||
|
||||
/* FIXME: Only support single plane system at this time. */
|
||||
/* Steps 1-6 of BIOS NB COF and VID Configuration
|
||||
* for Single-Plane PVI Systems
|
||||
*/
|
||||
dev = NODE_PCI(0,3); // nodeid for the BSP is 0
|
||||
reg1fc = pci_read_config32(dev, 0x1FC);
|
||||
nb_cof_vid_update = reg1fc & 1;
|
||||
if (nb_cof_vid_update) {
|
||||
/* Get fused settings */
|
||||
dword = pci_read_config32(dev, 0xa0);
|
||||
pvimode = (dword >> 8) & 1;
|
||||
|
||||
vid_max = (reg1fc >> 7) & 0x7F; // per node
|
||||
fid_max = (reg1fc >> 2) & 0x1F; // per system
|
||||
|
||||
if (pvimode) {
|
||||
/* FIXME: support daul plane mode */
|
||||
die("PVImode not supported\n");
|
||||
/* fidmax = vidmax - (reg1fc >> 17) & 0x1F;
|
||||
fidmax = fidmax + (reg1fc >> 14) & 0x03;
|
||||
*/
|
||||
}
|
||||
|
||||
} else {
|
||||
/* Use current values */
|
||||
msr = rdmsr(0xc0010071);
|
||||
fid_max = ((msr.hi >> (59-32)) & 0x1f); //max nb fid
|
||||
vid_max = ((msr.hi >> (35-32)) & 0x7f); //max vid
|
||||
}
|
||||
|
||||
/* Note this is the single plane setup. Need to add dual plane path */
|
||||
msr = rdmsr(0xc0010071);
|
||||
startup_pstate = (msr.hi >> (32-32)) & 0x07;
|
||||
|
||||
|
||||
/* Copy startup pstate to P1 and P0 MSRs. Set the maxvid for this node in P0.
|
||||
Then transition to P1 for corex and P0 for core0. */
|
||||
msr = rdmsr(0xC0010064 + startup_pstate);
|
||||
wrmsr(0xC0010065, msr);
|
||||
wrmsr(0xC0010064, msr);
|
||||
|
||||
msr.lo &= ~0xFE000000; // clear nbvid
|
||||
msr.lo |= vid_max << 25;
|
||||
wrmsr(0xC0010064, msr);
|
||||
|
||||
// Transition to P1 and then P0 for core0.
|
||||
msr = rdmsr(0xC0010062);
|
||||
msr.lo = (msr.lo & ~0x07) | 1;
|
||||
wrmsr(0xC0010062, msr);
|
||||
|
||||
// Wait for P1 to set.
|
||||
do {
|
||||
msr = rdmsr(0xC0010063);
|
||||
} while (msr.lo != 1);
|
||||
|
||||
msr.lo = msr.lo & ~0x07;
|
||||
wrmsr(0xC0010062, msr);
|
||||
// Wait for P0 to set.
|
||||
do {
|
||||
msr = rdmsr(0xC0010063);
|
||||
} while (msr.lo != 0);
|
||||
|
||||
|
||||
fv.common_fid = (nb_cof_vid_update << 16) | (fid_max << 8) ;
|
||||
print_debug_fv("BSP fid = ", fv.common_fid);
|
||||
|
||||
#if FAM10_SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 && FAM10_SET_FIDVID_CORE0_ONLY == 0
|
||||
/* For all APs (We know the APIC ID of all APs even when the APIC ID
|
||||
is lifted) remote read from AP LAPIC_MSG_REG about max fid.
|
||||
Then calculate the common max fid that can be used for all
|
||||
APs and BSP */
|
||||
ap_apicidx.num = 0;
|
||||
|
||||
for_each_ap(bsp_apicid, FAM10_SET_FIDVID_CORE_RANGE, store_ap_apicid, &ap_apicidx);
|
||||
|
||||
for(i = 0; i < ap_apicidx.num; i++) {
|
||||
init_fidvid_bsp_stage1(ap_apicidx.apicid[i], &fv);
|
||||
}
|
||||
#else
|
||||
for_each_ap(bsp_apicid, FAM10_SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage1, &fv);
|
||||
#endif
|
||||
|
||||
print_debug_fv("common_fid = ", fv.common_fid);
|
||||
|
||||
if (fv.common_fid & ~(0xFF << 16)) { // check nb_cof_vid_update
|
||||
|
||||
// Enable the common fid and other settings.
|
||||
enable_fid_change((fv.common_fid >> 8) & 0x1F);
|
||||
|
||||
// nbfid change need warm reset, so reset at first
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0; // No FID/VID changes. Don't reset
|
||||
}
|
||||
static void set_p0(void)
|
||||
{
|
||||
msr_t msr;
|
||||
|
||||
// Transition P0 for calling core.
|
||||
msr = rdmsr(0xC0010062);
|
||||
msr.lo = (msr.lo & ~0x07);
|
||||
wrmsr(0xC0010062, msr);
|
||||
|
||||
// Don't bother to wait around for the P state to change.
|
||||
}
|
||||
#endif
|
||||
312
src/cpu/amd/model_10xxx/fidvid_common.c
Normal file
312
src/cpu/amd/model_10xxx/fidvid_common.c
Normal file
@ -0,0 +1,312 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
|
||||
#include <cpu/x86/tsc.h>
|
||||
|
||||
|
||||
static u32 get_vstime(u32 nodeid, u32 slam)
|
||||
{
|
||||
u32 val;
|
||||
u32 v;
|
||||
device_t dev;
|
||||
|
||||
#if defined(__ROMCC__)
|
||||
dev = NODE_PCI(nodeid, 3);
|
||||
#else
|
||||
dev = get_node_pci(nodeid, 3);
|
||||
#endif
|
||||
|
||||
val = pci_read_config32(dev, 0xd8);
|
||||
|
||||
val >>= slam?0:4;
|
||||
val &= 7;
|
||||
|
||||
switch (val) {
|
||||
case 4: v = 60; break;
|
||||
case 5: v = 100; break;
|
||||
case 6: v = 200; break;
|
||||
case 7: v = 500; break;
|
||||
default:
|
||||
v = (val+1)*10; // in us
|
||||
}
|
||||
|
||||
return v;
|
||||
}
|
||||
|
||||
static void udelay_tsc(u32 us)
|
||||
{
|
||||
/* Use TSC to delay because it is fixed, ie. it will not changed with p-states.
|
||||
* Also, We use the APIC TIMER register is to hold flags for AP init.
|
||||
*/
|
||||
u32 dword;
|
||||
tsc_t tsc, tsc1, tscd;
|
||||
u32 d = 0x00000200; //800Mhz or 200Mhz or 1.6G or get the NBFID at first
|
||||
u32 dn = 0x1000000/2; // howmany us need to use hi
|
||||
|
||||
tscd.hi = us/dn;
|
||||
tscd.lo = (us - tscd.hi * dn) * d;
|
||||
|
||||
tsc1 = rdtsc();
|
||||
dword = tsc1.lo + tscd.lo;
|
||||
if((dword<tsc1.lo) || (dword<tscd.lo)) {
|
||||
tsc1.hi++;
|
||||
}
|
||||
tsc1.lo = dword;
|
||||
tsc1.hi+= tscd.hi;
|
||||
|
||||
do {
|
||||
tsc = rdtsc();
|
||||
} while ((tsc.hi>tsc1.hi) || ((tsc.hi==tsc1.hi) && (tsc.lo>tsc1.lo)));
|
||||
|
||||
}
|
||||
|
||||
#ifdef __ROMCC__
|
||||
void udelay(u32 usecs)
|
||||
{
|
||||
udelay_tsc(usecs);
|
||||
}
|
||||
#endif
|
||||
|
||||
static u32 set_vid(u32 newvid, u32 bit_offset, u32 nodeid, u32 coreid)
|
||||
{
|
||||
u32 val;
|
||||
msr_t msr;
|
||||
u32 curvid;
|
||||
u32 slam;
|
||||
u32 delay;
|
||||
u32 count = 3;
|
||||
device_t dev;
|
||||
|
||||
msr = rdmsr(0xc0010071);//status
|
||||
curvid = (msr.lo >> bit_offset) & 0x7f; // seven bits
|
||||
|
||||
if(newvid == curvid) return curvid;
|
||||
|
||||
#if defined(__ROMCC__)
|
||||
dev = NODE_PCI(nodeid, 3);
|
||||
#else
|
||||
dev = get_node_pci(nodeid, 3);
|
||||
#endif
|
||||
|
||||
val = pci_read_config32(dev, 0xa0);
|
||||
|
||||
slam = (val >> 29) & 1;
|
||||
delay = get_vstime(nodeid, slam);
|
||||
|
||||
if(!slam) {
|
||||
if(curvid>newvid) {
|
||||
count = (curvid - newvid) * 2;
|
||||
} else {
|
||||
count = (newvid - curvid) * 2;
|
||||
}
|
||||
}
|
||||
|
||||
while(count-->0) {
|
||||
if(slam) {
|
||||
curvid = newvid;
|
||||
}
|
||||
else { //ramp
|
||||
if(curvid>newvid) {
|
||||
curvid--;
|
||||
} else {
|
||||
curvid++;
|
||||
}
|
||||
}
|
||||
|
||||
msr = rdmsr(0xc0010070); //control
|
||||
msr.lo &= ~(0x7f<<bit_offset);
|
||||
msr.lo |= (curvid<<bit_offset);
|
||||
wrmsr(0xc0010070, msr); // how about all copys, APIC or PCI conf space?
|
||||
|
||||
udelay_tsc(delay);
|
||||
|
||||
msr = rdmsr(0xc0010071);//status
|
||||
curvid = (msr.lo >> bit_offset) & 0x7f; // seven bits
|
||||
|
||||
if(curvid == newvid) break;
|
||||
|
||||
}
|
||||
|
||||
return curvid;
|
||||
}
|
||||
|
||||
|
||||
static u32 set_nb_vid(u32 newvid, u32 nodeid, u32 coreid)
|
||||
{
|
||||
return set_vid(newvid, 25, nodeid, coreid);
|
||||
}
|
||||
|
||||
|
||||
static u32 set_core_vid(u32 newvid, u32 nodeid, u32 coreid)
|
||||
{
|
||||
return set_vid(newvid, 9, nodeid, coreid);
|
||||
}
|
||||
|
||||
|
||||
static unsigned set_cof(u32 val, u32 mask, u32 nodeid, u32 coreid)
|
||||
{
|
||||
msr_t msr;
|
||||
int count = 3;
|
||||
|
||||
val &= mask;
|
||||
|
||||
// FIXME: What is count for? Why 3 times? What about node and core id?
|
||||
while(count-- > 0) {
|
||||
|
||||
msr = rdmsr(0xc0010071);
|
||||
msr.lo &= mask;
|
||||
if(msr.lo == val) break;
|
||||
|
||||
msr = rdmsr(0xc0010070);
|
||||
msr.lo &= ~(mask);
|
||||
msr.lo |= val;
|
||||
wrmsr(0xc0010070, msr);
|
||||
}
|
||||
|
||||
return msr.lo;
|
||||
}
|
||||
|
||||
static u32 set_core_cof(u32 fid, u32 did, u32 nodeid, u32 coreid)
|
||||
{
|
||||
u32 val;
|
||||
u32 mask;
|
||||
|
||||
mask = (7<<6) | 0x3f;
|
||||
val = ((did & 7)<<6) | (fid & 0x3f);
|
||||
|
||||
return set_cof(val, mask, nodeid, coreid);
|
||||
|
||||
}
|
||||
|
||||
|
||||
static u32 set_nb_cof(u32 did, u32 nodeid, u32 coreid) // fid need warmreset
|
||||
{
|
||||
u32 val;
|
||||
u32 mask;
|
||||
|
||||
mask = 1<<22;
|
||||
val = (did & 1)<<22;
|
||||
|
||||
return set_cof(val, mask, nodeid, coreid);
|
||||
|
||||
}
|
||||
|
||||
|
||||
/* set vid and cof for core and nb after warm reset is not started by BIOS */
|
||||
static void set_core_nb_max_pstate_after_other_warm_reset(u32 nodeid, u32 coreid) // P0
|
||||
{
|
||||
msr_t msr;
|
||||
u32 val;
|
||||
u32 vid;
|
||||
u32 mask;
|
||||
u32 did;
|
||||
device_t dev;
|
||||
|
||||
msr = rdmsr(0xc0010064);
|
||||
|
||||
#if defined(__ROMCC__)
|
||||
dev = NODE_PCI(nodeid, 3);
|
||||
#else
|
||||
dev = get_node_pci(nodeid, 3);
|
||||
#endif
|
||||
|
||||
val = pci_read_config32(dev, 0xa0);
|
||||
if((val>>8) & 1) { // PVI
|
||||
vid = (msr.lo >> 25) & 0x7f;
|
||||
} else { //SVI
|
||||
vid = (msr.lo >> 9) & 0x7f;
|
||||
}
|
||||
set_core_vid(vid, nodeid, coreid);
|
||||
|
||||
mask = (0x7<<6) | 0x3f;
|
||||
val = msr.lo & mask;
|
||||
set_cof(val, mask, nodeid, coreid);
|
||||
|
||||
//set nb cof and vid
|
||||
did = (msr.lo >> 22) & 1;
|
||||
vid = (msr.lo >> 25) & 0x7f;
|
||||
if(did) {
|
||||
set_nb_cof(did, nodeid, coreid);
|
||||
set_nb_vid(vid, nodeid, coreid);
|
||||
} else {
|
||||
set_nb_vid(vid, nodeid, coreid);
|
||||
set_nb_cof(did, nodeid, coreid);
|
||||
}
|
||||
|
||||
//set the p state
|
||||
msr.hi = 0;
|
||||
msr.lo = 0;
|
||||
wrmsr(0xc0010062, msr);
|
||||
|
||||
}
|
||||
|
||||
|
||||
/* set vid and cof for core and nb after warm reset is not started by BIOS */
|
||||
static void set_core_nb_min_pstate_after_other_warm_reset(u32 nodeid, u32 coreid) // Px
|
||||
{
|
||||
msr_t msr;
|
||||
u32 val;
|
||||
u32 vid;
|
||||
u32 mask;
|
||||
u32 did;
|
||||
u32 pstate;
|
||||
device_t dev;
|
||||
|
||||
#if defined(__ROMCC__)
|
||||
dev = NODE_PCI(nodeid, 3);
|
||||
#else
|
||||
dev = get_node_pci(nodeid, 3);
|
||||
#endif
|
||||
|
||||
|
||||
val = pci_read_config32(dev, 0xdc); //PstateMaxVal
|
||||
|
||||
pstate = (val >> 8) & 0x7;
|
||||
|
||||
msr = rdmsr(0xc0010064 + pstate);
|
||||
|
||||
mask = (7<<6) | 0x3f;
|
||||
val = msr.lo & mask;
|
||||
set_cof(val, mask, nodeid, coreid);
|
||||
|
||||
val = pci_read_config32(dev, 0xa0);
|
||||
if((val>>8) & 1) { // PVI
|
||||
vid = (msr.lo>>25) & 0x7f;
|
||||
} else { //SVI
|
||||
vid = (msr.lo>>9) & 0x7f;
|
||||
}
|
||||
set_core_vid(vid, nodeid, coreid);
|
||||
|
||||
//set nb cof and vid
|
||||
did = (msr.lo >> 22) & 1;
|
||||
vid = (msr.lo >> 25) & 0x7f;
|
||||
if(did) {
|
||||
set_nb_cof(did, nodeid, coreid);
|
||||
set_nb_vid(vid, nodeid, coreid);
|
||||
} else {
|
||||
set_nb_vid(vid, nodeid, coreid);
|
||||
set_nb_cof(did, nodeid, coreid);
|
||||
}
|
||||
|
||||
//set the p state
|
||||
msr.hi = 0;
|
||||
msr.lo = pstate;
|
||||
wrmsr(0xc0010062, msr);
|
||||
}
|
||||
553
src/cpu/amd/model_10xxx/init_cpus.c
Normal file
553
src/cpu/amd/model_10xxx/init_cpus.c
Normal file
@ -0,0 +1,553 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
|
||||
//it takes the ENABLE_APIC_EXT_ID and APIC_ID_OFFSET and LIFT_BSP_APIC_ID
|
||||
#ifndef FAM10_SET_FIDVID
|
||||
#define FAM10_SET_FIDVID 1
|
||||
#endif
|
||||
|
||||
#ifndef FAM10_SET_FIDVID_CORE0_ONLY
|
||||
/* MSR FIDVID_CTL and FIDVID_STATUS are shared by cores,
|
||||
Need to do every AP to set common FID/VID*/
|
||||
#define FAM10_SET_FIDVID_CORE0_ONLY 0
|
||||
#endif
|
||||
|
||||
|
||||
static inline void print_initcpu8 (const char *strval, u8 val)
|
||||
{
|
||||
printk_debug("%s%02x\n", strval, val);
|
||||
}
|
||||
|
||||
static inline void print_initcpu8_nocr (const char *strval, u8 val)
|
||||
{
|
||||
printk_debug("%s%02x", strval, val);
|
||||
}
|
||||
|
||||
|
||||
static inline void print_initcpu16 (const char *strval, u16 val)
|
||||
{
|
||||
printk_debug("%s%04x\n", strval, val);
|
||||
}
|
||||
|
||||
|
||||
static inline void print_initcpu(const char *strval, u32 val)
|
||||
{
|
||||
printk_debug("%s%08x\n", strval, val);
|
||||
}
|
||||
|
||||
|
||||
static void prep_fid_change(void);
|
||||
static void init_fidvid_stage2(u32 apicid, u32 nodeid);
|
||||
|
||||
#if PCI_IO_CFG_EXT == 1
|
||||
static inline void set_EnableCf8ExtCfg(void)
|
||||
{
|
||||
// set the NB_CFG[46]=1;
|
||||
msr_t msr;
|
||||
msr = rdmsr(NB_CFG_MSR);
|
||||
// EnableCf8ExtCfg: We need that to access PCI_IO_CFG_EXT 4K range
|
||||
msr.hi |= (1<<(46-32));
|
||||
wrmsr(NB_CFG_MSR, msr);
|
||||
}
|
||||
#else
|
||||
static inline void set_EnableCf8ExtCfg(void) { }
|
||||
#endif
|
||||
|
||||
|
||||
/*[39:8] */
|
||||
#define PCI_MMIO_BASE 0xfe000000
|
||||
/* because we will use gs to store hi, so need to make sure lo can start
|
||||
from 0, So PCI_MMIO_BASE & 0x00ffffff should be equal to 0*/
|
||||
|
||||
static inline void set_pci_mmio_conf_reg(void)
|
||||
{
|
||||
#if MMCONF_SUPPORT
|
||||
msr_t msr;
|
||||
msr = rdmsr(0xc0010058);
|
||||
msr.lo &= ~(0xfff00000 | (0xf << 2));
|
||||
// 256 bus per segment, MMIO reg will be 4G , enable MMIO Config space
|
||||
msr.lo |= ((8+PCI_BUS_SEGN_BITS) << 2) | (1 << 0);
|
||||
msr.hi &= ~(0x0000ffff);
|
||||
msr.hi |= (PCI_MMIO_BASE >> (32-8));
|
||||
wrmsr(0xc0010058, msr); // MMIO Config Base Address Reg
|
||||
|
||||
//mtrr for that range?
|
||||
// set_var_mtrr_x(7, PCI_MMIO_BASE<<8, PCI_MMIO_BASE>>(32-8), 0x00000000, 0x01, MTRR_TYPE_UNCACHEABLE);
|
||||
|
||||
set_wrap32dis();
|
||||
|
||||
msr.hi = (PCI_MMIO_BASE >> (32-8));
|
||||
msr.lo = 0;
|
||||
wrmsr(0xc0000101, msr); //GS_Base Reg
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
typedef void (*process_ap_t)(u32 apicid, void *gp);
|
||||
|
||||
//core_range = 0 : all cores
|
||||
//core range = 1 : core 0 only
|
||||
//core range = 2 : cores other than core0
|
||||
|
||||
static void for_each_ap(u32 bsp_apicid, u32 core_range,
|
||||
process_ap_t process_ap, void *gp)
|
||||
{
|
||||
// here assume the OS don't change our apicid
|
||||
u32 ap_apicid;
|
||||
|
||||
u32 nodes;
|
||||
u32 siblings;
|
||||
u32 disable_siblings;
|
||||
u32 cores_found;
|
||||
u32 nb_cfg_54;
|
||||
int i,j;
|
||||
u32 ApicIdCoreIdSize;
|
||||
|
||||
/* get_nodes define in ht_wrapper.c */
|
||||
nodes = get_nodes();
|
||||
|
||||
disable_siblings = !CONFIG_LOGICAL_CPUS;
|
||||
|
||||
#if CONFIG_LOGICAL_CPUS == 1
|
||||
if(read_option(CMOS_VSTART_quad_core, CMOS_VLEN_quad_core, 0) != 0) { // 0 mean quad core
|
||||
disable_siblings = 1;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Assume that all node are same stepping, otherwise we can use use
|
||||
nb_cfg_54 from bsp for all nodes */
|
||||
nb_cfg_54 = read_nb_cfg_54();
|
||||
|
||||
ApicIdCoreIdSize = (cpuid_ecx(0x80000008) >> 12 & 0xf);
|
||||
if(ApicIdCoreIdSize) {
|
||||
siblings = ((1 << ApicIdCoreIdSize) - 1);
|
||||
} else {
|
||||
siblings = 3; //quad core
|
||||
}
|
||||
|
||||
for (i = 0; i < nodes; i++) {
|
||||
cores_found = get_core_num_in_bsp(i);
|
||||
|
||||
u32 jstart, jend;
|
||||
|
||||
if (core_range == 2) {
|
||||
jstart = 1;
|
||||
} else {
|
||||
jstart = 0;
|
||||
}
|
||||
|
||||
if (disable_siblings || (core_range==1)) {
|
||||
jend = 0;
|
||||
} else {
|
||||
jend = cores_found;
|
||||
}
|
||||
|
||||
|
||||
for (j = jstart; j <= jend; j++) {
|
||||
ap_apicid = i * (nb_cfg_54 ? (siblings + 1):1) + j * (nb_cfg_54 ? 1:64);
|
||||
|
||||
#if (ENABLE_APIC_EXT_ID == 1) && (APIC_ID_OFFSET > 0)
|
||||
#if LIFT_BSP_APIC_ID == 0
|
||||
if( (i != 0) || (j != 0)) /* except bsp */
|
||||
#endif
|
||||
ap_apicid += APIC_ID_OFFSET;
|
||||
#endif
|
||||
|
||||
if(ap_apicid == bsp_apicid) continue;
|
||||
|
||||
process_ap(ap_apicid, gp);
|
||||
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* FIXME: Duplicate of what is in lapic.h? */
|
||||
static inline int lapic_remote_read(int apicid, int reg, u32 *pvalue)
|
||||
{
|
||||
int timeout;
|
||||
u32 status;
|
||||
int result;
|
||||
lapic_wait_icr_idle();
|
||||
lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
|
||||
lapic_write(LAPIC_ICR, LAPIC_DM_REMRD | (reg >> 4));
|
||||
timeout = 0;
|
||||
|
||||
do {
|
||||
status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
|
||||
} while (status == LAPIC_ICR_BUSY && timeout++ < 1000);
|
||||
|
||||
timeout = 0;
|
||||
do {
|
||||
status = lapic_read(LAPIC_ICR) & LAPIC_ICR_RR_MASK;
|
||||
} while (status == LAPIC_ICR_RR_INPROG && timeout++ < 1000);
|
||||
|
||||
result = -1;
|
||||
|
||||
if (status == LAPIC_ICR_RR_VALID) {
|
||||
*pvalue = lapic_read(LAPIC_RRR);
|
||||
result = 0;
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
|
||||
/* Use the LAPIC timer count register to hold each cores init status */
|
||||
#define LAPIC_MSG_REG 0x380
|
||||
|
||||
|
||||
#if FAM10_SET_FIDVID == 1
|
||||
static void init_fidvid_ap(u32 bsp_apicid, u32 apicid, u32 nodeid, u32 coreid);
|
||||
#endif
|
||||
|
||||
static inline __attribute__((always_inline)) void print_apicid_nodeid_coreid(u32 apicid, struct node_core_id id, const char *str)
|
||||
{
|
||||
printk_debug("%s --- { APICID = %02x NODEID = %02x COREID = %02x} ---\n", str, apicid, id.nodeid, id.coreid);
|
||||
}
|
||||
|
||||
|
||||
static unsigned wait_cpu_state(u32 apicid, u32 state)
|
||||
{
|
||||
u32 readback = 0;
|
||||
u32 timeout = 1;
|
||||
int loop = 4000000;
|
||||
while (--loop > 0) {
|
||||
if (lapic_remote_read(apicid, LAPIC_MSG_REG, &readback) != 0) continue;
|
||||
if ((readback & 0x3f) == state) {
|
||||
timeout = 0;
|
||||
break; //target cpu is in stage started
|
||||
}
|
||||
}
|
||||
if (timeout) {
|
||||
if (readback) {
|
||||
timeout = readback;
|
||||
}
|
||||
}
|
||||
|
||||
return timeout;
|
||||
}
|
||||
|
||||
|
||||
static void wait_ap_started(u32 ap_apicid, void *gp )
|
||||
{
|
||||
u32 timeout;
|
||||
timeout = wait_cpu_state(ap_apicid, 0x13); // started
|
||||
if(timeout) {
|
||||
print_initcpu8_nocr("* AP ", ap_apicid);
|
||||
print_initcpu(" didn't start timeout:", timeout);
|
||||
}
|
||||
else {
|
||||
print_initcpu8_nocr("AP started: ", ap_apicid);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static void wait_all_aps_started(u32 bsp_apicid)
|
||||
{
|
||||
for_each_ap(bsp_apicid, 0 , wait_ap_started, (void *)0);
|
||||
}
|
||||
|
||||
|
||||
static void wait_all_other_cores_started(u32 bsp_apicid)
|
||||
{
|
||||
// all aps other than core0
|
||||
print_debug("started ap apicid: ");
|
||||
for_each_ap(bsp_apicid, 2 , wait_ap_started, (void *)0);
|
||||
print_debug("\n");
|
||||
}
|
||||
|
||||
|
||||
static void allow_all_aps_stop(u32 bsp_apicid)
|
||||
{
|
||||
/* Called by the BSP to indicate AP can stop */
|
||||
|
||||
/* FIXME Do APs use this?
|
||||
Looks like wait_till_sysinfo_in_ram is used instead. */
|
||||
|
||||
// allow aps to stop use 6 bits for state
|
||||
lapic_write(LAPIC_MSG_REG, (bsp_apicid << 24) | 0x14);
|
||||
}
|
||||
|
||||
|
||||
static void STOP_CAR_AND_CPU()
|
||||
{
|
||||
disable_cache_as_ram(); // inline
|
||||
stop_this_cpu();
|
||||
}
|
||||
|
||||
|
||||
#ifndef MEM_TRAIN_SEQ
|
||||
#define MEM_TRAIN_SEQ 0
|
||||
#endif
|
||||
|
||||
#if RAMINIT_SYSINFO == 1
|
||||
static u32 init_cpus(u32 cpu_init_detectedx ,struct sys_info *sysinfo)
|
||||
#else
|
||||
static u32 init_cpus(u32 cpu_init_detectedx)
|
||||
#endif
|
||||
{
|
||||
u32 bsp_apicid = 0;
|
||||
u32 apicid;
|
||||
struct node_core_id id;
|
||||
|
||||
/*
|
||||
* already set early mtrr in cache_as_ram.inc
|
||||
*/
|
||||
|
||||
/* enable access pci conf via mmio*/
|
||||
set_pci_mmio_conf_reg();
|
||||
|
||||
/* that is from initial apicid, we need nodeid and coreid
|
||||
later */
|
||||
id = get_node_core_id_x();
|
||||
|
||||
/* NB_CFG MSR is shared between cores, so we need make sure
|
||||
core0 is done at first --- use wait_all_core0_started */
|
||||
if(id.coreid == 0) {
|
||||
set_apicid_cpuid_lo(); /* only set it on core0 */
|
||||
set_EnableCf8ExtCfg(); /* only set it on core0 */
|
||||
#if (ENABLE_APIC_EXT_ID == 1)
|
||||
enable_apic_ext_id(id.nodeid);
|
||||
#endif
|
||||
}
|
||||
|
||||
enable_lapic();
|
||||
|
||||
|
||||
#if (ENABLE_APIC_EXT_ID == 1) && (APIC_ID_OFFSET > 0)
|
||||
u32 initial_apicid = get_initial_apicid();
|
||||
|
||||
#if LIFT_BSP_APIC_ID == 0
|
||||
if( initial_apicid != 0 ) // other than bsp
|
||||
#endif
|
||||
{
|
||||
/* use initial apic id to lift it */
|
||||
u32 dword = lapic_read(LAPIC_ID);
|
||||
dword &= ~(0xff << 24);
|
||||
dword |= (((initial_apicid + APIC_ID_OFFSET) & 0xff) << 24);
|
||||
|
||||
lapic_write(LAPIC_ID, dword);
|
||||
}
|
||||
|
||||
#if LIFT_BSP_APIC_ID == 1
|
||||
bsp_apicid += APIC_ID_OFFSET;
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
/* get the apicid, it may be lifted already */
|
||||
apicid = lapicid();
|
||||
|
||||
// show our apicid, nodeid, and coreid
|
||||
if( id.coreid==0 ) {
|
||||
if (id.nodeid!=0) //all core0 except bsp
|
||||
print_apicid_nodeid_coreid(apicid, id, " core0: ");
|
||||
}
|
||||
else { //all other cores
|
||||
print_apicid_nodeid_coreid(apicid, id, " corex: ");
|
||||
}
|
||||
|
||||
|
||||
if (cpu_init_detectedx) {
|
||||
print_apicid_nodeid_coreid(apicid, id, "\n\n\nINIT detected from ");
|
||||
print_debug("\nIssuing SOFT_RESET...\n");
|
||||
soft_reset();
|
||||
}
|
||||
|
||||
if(id.coreid == 0) {
|
||||
if(!(warm_reset_detect(id.nodeid))) //FIXME: INIT is checked above but check for more resets?
|
||||
distinguish_cpu_resets(id.nodeid); // Also indicates we are started
|
||||
}
|
||||
|
||||
// Mark the core as started.
|
||||
lapic_write(LAPIC_MSG_REG, (apicid << 24) | 0x13);
|
||||
|
||||
|
||||
if(apicid != bsp_apicid) {
|
||||
#if FAM10_SET_FIDVID == 1
|
||||
#if (CONFIG_LOGICAL_CPUS == 1) && (FAM10_SET_FIDVID_CORE0_ONLY == 1)
|
||||
// Run on all AP for proper FID/VID setup.
|
||||
if(id.coreid == 0 ) // only need set fid for core0
|
||||
#endif
|
||||
{
|
||||
// check warm(bios) reset to call stage2 otherwise do stage1
|
||||
if (warm_reset_detect(id.nodeid)) {
|
||||
printk_debug("init_fidvid_stage2 apicid: %02x\n", apicid);
|
||||
init_fidvid_stage2(apicid, id.nodeid);
|
||||
} else {
|
||||
printk_debug("init_fidvid_ap(stage1) apicid: %02x\n", apicid);
|
||||
init_fidvid_ap(bsp_apicid, apicid, id.nodeid, id.coreid);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/* AP is ready, Wait for the BSP to get memory configured */
|
||||
/* FIXME: many cores spinning on node0 pci register seems to be bad.
|
||||
* Why do we need to wait? These APs are just going to go sit in a hlt.
|
||||
*/
|
||||
//wait_till_sysinfo_in_ram();
|
||||
|
||||
set_init_ram_access();
|
||||
|
||||
STOP_CAR_AND_CPU();
|
||||
printk_debug("\nAP %02x should be halted but you are reading this....\n", apicid);
|
||||
}
|
||||
|
||||
return bsp_apicid;
|
||||
}
|
||||
|
||||
|
||||
static u32 is_core0_started(u32 nodeid)
|
||||
{
|
||||
u32 htic;
|
||||
device_t device;
|
||||
device = NODE_PCI(nodeid, 0);
|
||||
htic = pci_read_config32(device, HT_INIT_CONTROL);
|
||||
htic &= HTIC_ColdR_Detect;
|
||||
return htic;
|
||||
}
|
||||
|
||||
|
||||
static void wait_all_core0_started(void)
|
||||
{
|
||||
/* When core0 is started, it will distingush_cpu_resets
|
||||
. So wait for that to finish */
|
||||
u32 i;
|
||||
u32 nodes = get_nodes();
|
||||
|
||||
printk_debug("Wait all core0s started \n");
|
||||
for(i=1;i<nodes;i++) { // skip bsp, because it is running on bsp
|
||||
while(!is_core0_started(i)) {}
|
||||
print_initcpu8(" Core0 started on node: ", i);
|
||||
}
|
||||
printk_debug("Wait all core0s started done\n");
|
||||
}
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 1
|
||||
/**
|
||||
* void start_node(u32 node)
|
||||
*
|
||||
* start the core0 in node, so it can generate HT packet to feature code.
|
||||
*
|
||||
* This function starts the AP nodes core0s. wait_all_core0_started() in
|
||||
* cache_as_ram_auto.c waits for all the AP to be finished before continuing
|
||||
* system init.
|
||||
*/
|
||||
static void start_node(u8 node)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
/* Enable routing table */
|
||||
printk_debug("Start node %02x", node);
|
||||
|
||||
#if CAR_FAM10 == 1
|
||||
/* For CAR_FAM10 support, we need to set Dram base/limit for the new node */
|
||||
pci_write_config32(NODE_MP(node), 0x44, 0);
|
||||
pci_write_config32(NODE_MP(node), 0x40, 3);
|
||||
#endif
|
||||
|
||||
/* Allow APs to make requests (ROM fetch) */
|
||||
val=pci_read_config32(NODE_HT(node), 0x6c);
|
||||
val &= ~(1 << 1);
|
||||
pci_write_config32(NODE_HT(node), 0x6c, val);
|
||||
|
||||
printk_debug(" done.\n");
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* static void setup_remote_node(u32 node)
|
||||
*
|
||||
* Copy the BSP Adress Map to each AP.
|
||||
*/
|
||||
static void setup_remote_node(u8 node)
|
||||
{
|
||||
/* There registers can be used with F1x114_x Address Map at the
|
||||
same time, So must set them even 32 node */
|
||||
static const u16 pci_reg[] = {
|
||||
/* DRAM Base/Limits Registers */
|
||||
0x44, 0x4c, 0x54, 0x5c, 0x64, 0x6c, 0x74, 0x7c,
|
||||
0x40, 0x48, 0x50, 0x58, 0x60, 0x68, 0x70, 0x78,
|
||||
0x144, 0x14c, 0x154, 0x15c, 0x164, 0x16c, 0x174, 0x17c,
|
||||
0x140, 0x148, 0x150, 0x158, 0x160, 0x168, 0x170, 0x178,
|
||||
/* MMIO Base/Limits Registers */
|
||||
0x84, 0x8c, 0x94, 0x9c, 0xa4, 0xac, 0xb4, 0xbc,
|
||||
0x80, 0x88, 0x90, 0x98, 0xa0, 0xa8, 0xb0, 0xb8,
|
||||
/* IO Base/Limits Registers */
|
||||
0xc4, 0xcc, 0xd4, 0xdc,
|
||||
0xc0, 0xc8, 0xd0, 0xd8,
|
||||
/* Configuration Map Registers */
|
||||
0xe0, 0xe4, 0xe8, 0xec,
|
||||
};
|
||||
u16 i;
|
||||
|
||||
printk_debug("setup_remote_node: %02x", node);
|
||||
|
||||
/* copy the default resource map from node 0 */
|
||||
for(i = 0; i < sizeof(pci_reg)/sizeof(pci_reg[0]); i++) {
|
||||
u32 value;
|
||||
u16 reg;
|
||||
reg = pci_reg[i];
|
||||
value = pci_read_config32(NODE_MP(0), reg);
|
||||
pci_write_config32(NODE_MP(node), reg, value);
|
||||
|
||||
}
|
||||
printk_debug(" done\n");
|
||||
}
|
||||
#endif
|
||||
/**
|
||||
* finalize_node_setup()
|
||||
*
|
||||
* Do any additional post HT init
|
||||
*
|
||||
* This could really be moved to cache_as_ram_auto.c since it really isn't HT init.
|
||||
*/
|
||||
void finalize_node_setup(struct sys_info *sysinfo)
|
||||
{
|
||||
u8 i;
|
||||
u8 nodes = get_nodes();
|
||||
u32 reg;
|
||||
|
||||
#if RAMINIT_SYSINFO == 1
|
||||
/* read Node0 F0_0x64 bit [8:10] to find out SbLink # */
|
||||
reg = pci_read_config32(NODE_HT(0), 0x64);
|
||||
sysinfo->sblk = (reg>>8) & 7;
|
||||
sysinfo->sbbusn = 0;
|
||||
sysinfo->nodes = nodes;
|
||||
sysinfo->sbdn = get_sbdn(sysinfo->sbbusn);
|
||||
#endif
|
||||
|
||||
setup_link_trans_cntrl();
|
||||
|
||||
#if FAM10_SET_FIDVID == 1
|
||||
// Prep each node for FID/VID setup.
|
||||
prep_fid_change();
|
||||
#endif
|
||||
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 1
|
||||
/* Skip the BSP, start at node 1 */
|
||||
for(i=1; i<nodes; i++) {
|
||||
setup_remote_node(i);
|
||||
start_node(i);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
163
src/cpu/amd/model_10xxx/mc_patch_01000018.h
Normal file
163
src/cpu/amd/model_10xxx/mc_patch_01000018.h
Normal file
@ -0,0 +1,163 @@
|
||||
/*
|
||||
============================================================
|
||||
(c) Advanced Micro Devices, Inc., 2004-2005
|
||||
|
||||
The enclosed microcode is intended to be used with AMD
|
||||
Microprocessors. You may copy, view and install the
|
||||
enclosed microcode only for development and deployment of
|
||||
firmware, BIOS, or operating system code for computer
|
||||
systems that contain AMD processors. You are not
|
||||
authorized to use the enclosed microcode for any other
|
||||
purpose.
|
||||
|
||||
THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR
|
||||
IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO
|
||||
WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT,
|
||||
TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES
|
||||
ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
AMD does not assume any responsibility for any errors which
|
||||
may appear in this microcode or any other related
|
||||
information provided to you by AMD, or result from use of
|
||||
this microcode. AMD is not obligated to furnish, support,
|
||||
or make any further information, software, technical
|
||||
information, know-how, or show-how available related to this
|
||||
microcode.
|
||||
|
||||
The microcode is provided with "RESTRICTED RIGHTS." Use,
|
||||
duplication, or disclosure by the U.S. Government is subject
|
||||
to the restrictions as set forth in FAR 52.227-14 and
|
||||
DFAR252.227-7013, et seq., or its successor. Use of the
|
||||
microcode by the U.S. Government constitutes
|
||||
acknowledgement of AMD's proprietary rights in them.
|
||||
============================================================
|
||||
*/
|
||||
|
||||
0x07, 0x20, 0x08, 0x02, 0x18, 0x00, 0x00, 0x01, 0x00, 0x80, 0x20, 0x00,
|
||||
0x66, 0x70, 0x30, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x10, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0x44, 0x06, 0x00, 0x00,
|
||||
0xff, 0xff, 0xff, 0xff, 0xa4, 0x06, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
|
||||
0x72, 0x09, 0x00, 0x00, 0x70, 0x09, 0x00, 0x00, 0x9b, 0x0b, 0x00, 0x00,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0x81, 0x7f, 0x00, 0xc3, 0x3f, 0x80, 0x37,
|
||||
0xfc, 0x07, 0xfe, 0x01, 0x0d, 0xff, 0x00, 0xfe, 0xf0, 0x1f, 0xf8, 0x07,
|
||||
0x37, 0xfc, 0x03, 0xf8, 0xc0, 0xff, 0xf7, 0x00, 0x80, 0xff, 0xc0, 0x3f,
|
||||
0x9b, 0xe1, 0x1f, 0xc0, 0x00, 0xfe, 0x03, 0xff, 0xff, 0x86, 0x7f, 0x00,
|
||||
0x03, 0xf8, 0x0f, 0xfc, 0xfc, 0x1b, 0xfe, 0x01, 0x00, 0x40, 0x37, 0x6b,
|
||||
0xff, 0xfb, 0xfd, 0xff, 0x57, 0x7d, 0xf0, 0xcd, 0xff, 0x1f, 0xb7, 0xfe,
|
||||
0xc0, 0xcf, 0xc3, 0x3f, 0xff, 0x01, 0xff, 0xf7, 0x00, 0x02, 0x07, 0xff,
|
||||
0x35, 0x00, 0x90, 0x8b, 0xf0, 0x0f, 0xe0, 0x3f, 0x07, 0xf0, 0x6f, 0xf8,
|
||||
0xc0, 0x3f, 0x80, 0xff, 0x1f, 0xc0, 0xbf, 0xe1, 0x03, 0xff, 0x00, 0xfe,
|
||||
0x7f, 0x00, 0xff, 0x86, 0xff, 0x1e, 0x00, 0xf8, 0x1f, 0xf8, 0x07, 0xf0,
|
||||
0xfc, 0x03, 0x78, 0x33, 0x7f, 0xe0, 0x1f, 0xc0, 0xf0, 0x0f, 0xe0, 0xdf,
|
||||
0xff, 0x81, 0x7f, 0x00, 0xc3, 0x3f, 0x80, 0x7f, 0xfc, 0x7f, 0x0f, 0x00,
|
||||
0xf8, 0x0f, 0xfc, 0x03, 0x19, 0xfe, 0x01, 0xbc, 0xe0, 0x3f, 0xf0, 0x0f,
|
||||
0x6f, 0xf8, 0x07, 0xf0, 0x80, 0xff, 0xc0, 0x3f, 0xbf, 0xe1, 0x1f, 0xc0,
|
||||
0x00, 0xb4, 0xb2, 0x06, 0xbf, 0xdf, 0xff, 0xff, 0xd5, 0x07, 0xdf, 0x7c,
|
||||
0x67, 0xb2, 0xe7, 0xf9, 0xfc, 0x3c, 0xfc, 0x03, 0x1f, 0xf0, 0x7f, 0xff,
|
||||
0x20, 0x70, 0xf0, 0x0f, 0x03, 0x00, 0xed, 0x58, 0xff, 0x00, 0xfe, 0x03,
|
||||
0x00, 0xff, 0x86, 0x7f, 0xfc, 0x03, 0xf8, 0x0f, 0x01, 0xfc, 0x1b, 0xfe,
|
||||
0xf0, 0x0f, 0xe0, 0x3f, 0x07, 0xf0, 0x6f, 0xf8, 0xef, 0x01, 0x80, 0xff,
|
||||
0xff, 0xff, 0x29, 0x2a, 0x5f, 0xd0, 0xc1, 0xc3, 0xff, 0xff, 0xb3, 0xdd,
|
||||
0xff, 0x7e, 0xfd, 0x0f, 0x1f, 0xf8, 0x57, 0xf6, 0xbc, 0x63, 0x2d, 0x3c,
|
||||
0x03, 0xd4, 0x00, 0x40, 0xff, 0xd7, 0xbf, 0xb7, 0xe1, 0xdf, 0xeb, 0xe7,
|
||||
0xef, 0xff, 0xff, 0x57, 0x87, 0x7f, 0xbf, 0xea, 0xfa, 0x0f, 0xfc, 0x03,
|
||||
0x1f, 0xbe, 0xf5, 0xfc, 0x80, 0x02, 0x4b, 0x00, 0x8a, 0xca, 0xff, 0x7f,
|
||||
0xf0, 0xf0, 0x17, 0x74, 0x6c, 0xf7, 0xff, 0xff, 0xff, 0xc3, 0xbf, 0x5f,
|
||||
0x95, 0xfd, 0x07, 0xfe, 0x0b, 0x0f, 0xef, 0x58, 0x00, 0xd0, 0x00, 0x35,
|
||||
0xab, 0xea, 0xff, 0xfb, 0x05, 0x78, 0xf4, 0x67, 0xff, 0xd5, 0xfb, 0xff,
|
||||
0xaf, 0xfa, 0xe1, 0xdf, 0xff, 0x80, 0xfe, 0x03, 0x3d, 0xff, 0x87, 0x6f,
|
||||
0x12, 0x00, 0xa0, 0xc0, 0xff, 0x0f, 0xf0, 0xaf, 0x03, 0xf8, 0x3f, 0xfc,
|
||||
0xff, 0x2f, 0xc0, 0xff, 0x2d, 0x65, 0xff, 0xf0, 0x0d, 0xfe, 0x04, 0xb6,
|
||||
0x2f, 0x03, 0xad, 0xc3, 0x51, 0x0d, 0x00, 0x8c, 0xff, 0xfe, 0x03, 0xf8,
|
||||
0xff, 0xb9, 0xc9, 0x19, 0x3f, 0xf0, 0x0f, 0xe0, 0xf8, 0x07, 0xf0, 0x6f,
|
||||
0xff, 0xc0, 0x3f, 0x80, 0xe1, 0x1f, 0xc0, 0xbf, 0xf2, 0xb9, 0x06, 0x00,
|
||||
0xfc, 0x07, 0xfe, 0x01, 0x0d, 0xff, 0x00, 0xfe, 0xf0, 0x1f, 0xf8, 0x07,
|
||||
0x37, 0xfc, 0x03, 0xf8, 0xc0, 0x7f, 0xe0, 0x1f, 0xdf, 0xf0, 0x0f, 0xe0,
|
||||
0x00, 0xff, 0xdf, 0x03, 0x00, 0xfe, 0x03, 0xff, 0xff, 0x86, 0x7f, 0x00,
|
||||
0x03, 0xf8, 0x0f, 0xfc, 0xfc, 0x1b, 0xfe, 0x01, 0x0f, 0xe0, 0x3f, 0xf0,
|
||||
0xf0, 0x6f, 0xf8, 0x07, 0x01, 0x80, 0xff, 0xef, 0x7f, 0x00, 0xff, 0x81,
|
||||
0x80, 0x7f, 0xc3, 0x3f, 0xfe, 0x01, 0xfc, 0x07, 0x00, 0xfe, 0x0d, 0xff,
|
||||
0xf8, 0x07, 0xf0, 0x1f, 0x03, 0xf8, 0x37, 0xfc, 0xd7, 0x00, 0x40, 0x34,
|
||||
0xc0, 0x3f, 0x80, 0xff, 0x1f, 0xc0, 0xbf, 0xe1, 0x03, 0xff, 0x00, 0xfe,
|
||||
0x7f, 0x00, 0xff, 0x86, 0x0f, 0xfc, 0x03, 0xf8, 0xfe, 0x01, 0xfc, 0x1b,
|
||||
0x9a, 0x6b, 0x00, 0x00, 0x7f, 0xe0, 0x1f, 0xc0, 0xf0, 0x0f, 0xe0, 0xdf,
|
||||
0xff, 0x81, 0x7f, 0x00, 0xc3, 0x3f, 0x80, 0x7f, 0xfc, 0x07, 0xfe, 0x01,
|
||||
0x0d, 0xff, 0x00, 0xfe, 0xf0, 0xff, 0x3d, 0x00, 0xf4, 0x3f, 0xf0, 0xaf,
|
||||
0x72, 0xf8, 0x55, 0xaa, 0xd2, 0x7b, 0xcf, 0x3f, 0xfc, 0xe1, 0x5b, 0xa9,
|
||||
0x80, 0xff, 0x93, 0xff, 0x81, 0x87, 0x7f, 0x00, 0x00, 0xf8, 0xff, 0x1e,
|
||||
0x67, 0xf2, 0x1f, 0xf8, 0xfc, 0x3c, 0xfc, 0x03, 0x1f, 0xc0, 0x7f, 0xe0,
|
||||
0xe0, 0xdf, 0xf0, 0x0f, 0x7f, 0x00, 0xff, 0x81, 0x80, 0x7f, 0xc3, 0x3f,
|
||||
0x0f, 0x00, 0xdc, 0x7f, 0xfe, 0x73, 0xfb, 0xff, 0xf4, 0x22, 0x1f, 0xde,
|
||||
0xc0, 0x9f, 0x40, 0x5d, 0x63, 0xc0, 0x75, 0xf8, 0xe5, 0x3f, 0xb5, 0xff,
|
||||
0xdd, 0xef, 0xf8, 0xe1, 0xbf, 0x07, 0x00, 0xfe, 0x7f, 0xff, 0x9d, 0xfc,
|
||||
0xff, 0x00, 0x3f, 0x0f, 0xfe, 0xff, 0x7f, 0xf2, 0xfc, 0x03, 0xfc, 0x3c,
|
||||
0xff, 0xff, 0x3f, 0xc0, 0xf0, 0xfd, 0x64, 0xf0, 0x08, 0x90, 0x00, 0x00,
|
||||
0xfe, 0xbf, 0xff, 0xdc, 0x87, 0x37, 0xae, 0x88, 0xfb, 0x0f, 0xfc, 0x33,
|
||||
0x1f, 0xfe, 0x98, 0x96, 0xcd, 0xff, 0xff, 0x5f, 0x7e, 0x78, 0xa7, 0xba,
|
||||
0x00, 0x04, 0x48, 0x00, 0x00, 0xff, 0x81, 0x7f, 0xf2, 0xc3, 0x3b, 0x13,
|
||||
0xfd, 0xfd, 0x37, 0xff, 0x3f, 0x0f, 0xff, 0x7e, 0xd6, 0xf7, 0xff, 0xfd,
|
||||
0xe5, 0x3b, 0xfc, 0x71, 0x00, 0x80, 0xff, 0xef, 0x3f, 0x80, 0xff, 0xc0,
|
||||
0xc0, 0xbf, 0xe1, 0x1f, 0xff, 0x00, 0xfe, 0x03, 0x00, 0xff, 0x86, 0x7f,
|
||||
0xfc, 0x03, 0xf8, 0x0f, 0x01, 0xfc, 0x1b, 0xfe, 0x7b, 0x00, 0xe0, 0xff,
|
||||
0xe0, 0x1f, 0xc0, 0x7f, 0x0f, 0xe0, 0xdf, 0xf0, 0x81, 0x7f, 0x00, 0xff,
|
||||
0x3f, 0x80, 0x7f, 0xc3, 0x07, 0xfe, 0x01, 0xfc, 0xff, 0x00, 0xfe, 0x0d,
|
||||
0xff, 0x3d, 0x00, 0xf0, 0x3f, 0xf0, 0x0f, 0xe0, 0xf8, 0x07, 0xf0, 0x6f,
|
||||
0xff, 0xc0, 0x3f, 0x80, 0xe1, 0x1f, 0xc0, 0xbf, 0xfe, 0x03, 0xff, 0x00,
|
||||
0x86, 0x7f, 0x00, 0xff, 0xf8, 0xff, 0x1e, 0x00, 0xf0, 0x1f, 0xf8, 0x07,
|
||||
0x37, 0xfc, 0x03, 0xf8, 0xc0, 0x7f, 0xe0, 0x1f, 0xdf, 0xf0, 0x0f, 0xe0,
|
||||
0x00, 0xff, 0x81, 0x7f, 0x7f, 0xc3, 0x3f, 0x80, 0x00, 0xfc, 0x7f, 0x0f,
|
||||
0x03, 0xf8, 0x0f, 0xfc, 0xfc, 0x1b, 0xfe, 0x01, 0x0f, 0xe0, 0x3f, 0xf0,
|
||||
0xf0, 0x6f, 0xf8, 0x07, 0x3f, 0x80, 0xff, 0xc0, 0xc0, 0xbf, 0xe1, 0x1f,
|
||||
0x07, 0x00, 0xfe, 0xbf, 0xfe, 0x01, 0xfc, 0x07, 0x00, 0xfe, 0x0d, 0xff,
|
||||
0xf8, 0x07, 0xf0, 0x1f, 0x03, 0xf8, 0x37, 0xfc, 0xe0, 0x1f, 0xc0, 0x7f,
|
||||
0x0f, 0xe0, 0xdf, 0xf0, 0xdf, 0x03, 0x00, 0xff, 0x03, 0xff, 0x00, 0xfe,
|
||||
0x7f, 0x00, 0xff, 0x86, 0x0f, 0xfc, 0x03, 0xf8, 0xfe, 0x01, 0xfc, 0x1b,
|
||||
0x3f, 0xf0, 0x0f, 0xe0, 0xf8, 0x07, 0xf0, 0x6f, 0xff, 0xef, 0x01, 0x80,
|
||||
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
||||
163
src/cpu/amd/model_10xxx/mc_patch_01000020.h
Normal file
163
src/cpu/amd/model_10xxx/mc_patch_01000020.h
Normal file
@ -0,0 +1,163 @@
|
||||
/*
|
||||
============================================================
|
||||
(c) Advanced Micro Devices, Inc., 2004-2005
|
||||
|
||||
The enclosed microcode is intended to be used with AMD
|
||||
Microprocessors. You may copy, view and install the
|
||||
enclosed microcode only for development and deployment of
|
||||
firmware, BIOS, or operating system code for computer
|
||||
systems that contain AMD processors. You are not
|
||||
authorized to use the enclosed microcode for any other
|
||||
purpose.
|
||||
|
||||
THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR
|
||||
IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO
|
||||
WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT,
|
||||
TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES
|
||||
ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
AMD does not assume any responsibility for any errors which
|
||||
may appear in this microcode or any other related
|
||||
information provided to you by AMD, or result from use of
|
||||
this microcode. AMD is not obligated to furnish, support,
|
||||
or make any further information, software, technical
|
||||
information, know-how, or show-how available related to this
|
||||
microcode.
|
||||
|
||||
The microcode is provided with "RESTRICTED RIGHTS." Use,
|
||||
duplication, or disclosure by the U.S. Government is subject
|
||||
to the restrictions as set forth in FAR 52.227-14 and
|
||||
DFAR252.227-7013, et seq., or its successor. Use of the
|
||||
microcode by the U.S. Government constitutes
|
||||
acknowledgement of AMD's proprietary rights in them.
|
||||
============================================================
|
||||
*/
|
||||
|
||||
0x07, 0x20, 0x26, 0x03, 0x20, 0x00, 0x00, 0x01, 0x00, 0x80, 0x20, 0x00,
|
||||
0x66, 0x68, 0x30, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
|
||||
0x00, 0x10, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0x44, 0x06, 0x00, 0x00,
|
||||
0xff, 0xff, 0xff, 0xff, 0xa4, 0x06, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
|
||||
0x72, 0x09, 0x00, 0x00, 0x70, 0x09, 0x00, 0x00, 0x9b, 0x0b, 0x00, 0x00,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0x81, 0x7f, 0x00, 0xc3, 0x3f, 0x80, 0x37,
|
||||
0xfc, 0x07, 0xfe, 0x01, 0x0d, 0xff, 0x00, 0xfe, 0xf0, 0x1f, 0xf8, 0x07,
|
||||
0x37, 0xfc, 0x03, 0xf8, 0xc0, 0xff, 0xf7, 0x00, 0x80, 0xff, 0xc0, 0x3f,
|
||||
0x9b, 0xe1, 0x1f, 0xc0, 0x00, 0xfe, 0x03, 0xff, 0xff, 0x86, 0x7f, 0x00,
|
||||
0x03, 0xf8, 0x0f, 0xfc, 0xfc, 0x1b, 0xfe, 0x01, 0x00, 0x40, 0x37, 0x6b,
|
||||
0xff, 0xfb, 0xfd, 0xff, 0x57, 0x7d, 0xf0, 0xcd, 0xff, 0x1f, 0xb7, 0xfe,
|
||||
0xc0, 0xcf, 0xc3, 0x3f, 0xff, 0x01, 0xff, 0xf7, 0x00, 0x02, 0x07, 0xff,
|
||||
0x35, 0x00, 0x90, 0x8b, 0xf0, 0x0f, 0xe0, 0x3f, 0x07, 0xf0, 0x6f, 0xf8,
|
||||
0xc0, 0x3f, 0x80, 0xff, 0x1f, 0xc0, 0xbf, 0xe1, 0x03, 0xff, 0x00, 0xfe,
|
||||
0x7f, 0x00, 0xff, 0x86, 0xff, 0x1e, 0x00, 0xf8, 0x1f, 0xf8, 0x07, 0xf0,
|
||||
0xfc, 0x03, 0x78, 0x33, 0x7f, 0xe0, 0x1f, 0xc0, 0xf0, 0x0f, 0xe0, 0xdf,
|
||||
0xff, 0x81, 0x7f, 0x00, 0xc3, 0x3f, 0x80, 0x7f, 0xfc, 0x7f, 0x0f, 0x00,
|
||||
0xf8, 0x0f, 0xfc, 0x03, 0x19, 0xfe, 0x01, 0xbc, 0xe0, 0x3f, 0xf0, 0x0f,
|
||||
0x6f, 0xf8, 0x07, 0xf0, 0x80, 0xff, 0xc0, 0x3f, 0xbf, 0xe1, 0x1f, 0xc0,
|
||||
0x00, 0xb4, 0xb2, 0x06, 0xbf, 0xdf, 0xff, 0xff, 0xd5, 0x07, 0xdf, 0x7c,
|
||||
0x67, 0xb2, 0xe7, 0xf9, 0xfc, 0x3c, 0xfc, 0x03, 0x1f, 0xf0, 0x7f, 0xff,
|
||||
0x20, 0x70, 0xf0, 0x0f, 0x03, 0x00, 0xed, 0x58, 0xff, 0x00, 0xfe, 0x03,
|
||||
0x00, 0xff, 0x86, 0x7f, 0xfc, 0x03, 0xf8, 0x0f, 0x01, 0xfc, 0x1b, 0xfe,
|
||||
0xf0, 0x0f, 0xe0, 0x3f, 0x07, 0xf0, 0x6f, 0xf8, 0xef, 0x01, 0x80, 0xff,
|
||||
0xff, 0xff, 0x29, 0x2a, 0x5f, 0xd0, 0xc1, 0xc3, 0xff, 0xff, 0xb3, 0xdd,
|
||||
0xff, 0x7e, 0xfd, 0x0f, 0x1f, 0xf8, 0x57, 0xf6, 0xbc, 0x63, 0x2d, 0x3c,
|
||||
0x03, 0xd4, 0x00, 0x40, 0xff, 0xd7, 0xbf, 0xb7, 0xe1, 0xdf, 0xeb, 0xe7,
|
||||
0xef, 0xff, 0xff, 0x57, 0x87, 0x7f, 0xbf, 0xea, 0xfa, 0x0f, 0xfc, 0x03,
|
||||
0x1f, 0xbe, 0xf5, 0xfc, 0x80, 0x02, 0x4b, 0x00, 0x8a, 0xca, 0xff, 0x7f,
|
||||
0xf0, 0xf0, 0x17, 0x74, 0x6c, 0xef, 0xff, 0xff, 0xff, 0xc3, 0xbf, 0x5f,
|
||||
0x95, 0xfd, 0x07, 0xfe, 0x0b, 0x0f, 0xef, 0x58, 0x00, 0xd0, 0x00, 0x35,
|
||||
0xab, 0xea, 0xff, 0xfb, 0x05, 0x78, 0xf4, 0x67, 0xff, 0xd5, 0xfb, 0xff,
|
||||
0xaf, 0xfa, 0xe1, 0xdf, 0xff, 0x80, 0xfe, 0x03, 0x3d, 0xff, 0x87, 0x6f,
|
||||
0x12, 0x00, 0xa0, 0xc0, 0xff, 0x0f, 0xf0, 0xaf, 0x03, 0xf8, 0x3f, 0xfc,
|
||||
0xff, 0x2f, 0xc0, 0xff, 0x2d, 0x65, 0xff, 0xf0, 0x0d, 0xfe, 0x04, 0xb6,
|
||||
0x2f, 0x03, 0xad, 0xc3, 0x51, 0x0d, 0x00, 0x8c, 0xff, 0xfe, 0x03, 0xf8,
|
||||
0xff, 0xb9, 0xc9, 0x19, 0x3f, 0xf0, 0x0f, 0xe0, 0xf8, 0x07, 0xf0, 0x6f,
|
||||
0xff, 0xc0, 0x3f, 0x80, 0xe1, 0x1f, 0xc0, 0xbf, 0xf2, 0xb9, 0x06, 0x00,
|
||||
0xfc, 0x07, 0xfe, 0x01, 0x0d, 0xff, 0x00, 0xfe, 0xf0, 0x1f, 0xf8, 0x07,
|
||||
0x37, 0xfc, 0x03, 0xf8, 0xc0, 0x7f, 0xe0, 0x1f, 0xdf, 0xf0, 0x0f, 0xe0,
|
||||
0x00, 0xff, 0xdf, 0x03, 0x00, 0xfe, 0x03, 0xff, 0xff, 0x86, 0x7f, 0x00,
|
||||
0x03, 0xf8, 0x0f, 0xfc, 0xfc, 0x1b, 0xfe, 0x01, 0x0f, 0xe0, 0x3f, 0xf0,
|
||||
0xf0, 0x6f, 0xf8, 0x07, 0x01, 0x80, 0xff, 0xef, 0x7f, 0x00, 0xff, 0x81,
|
||||
0x80, 0x7f, 0xc3, 0x3f, 0xfe, 0x01, 0xfc, 0x07, 0x00, 0xfe, 0x0d, 0xff,
|
||||
0xf8, 0x07, 0xf0, 0x1f, 0x03, 0xf8, 0x37, 0xfc, 0xd7, 0x00, 0x40, 0x34,
|
||||
0xc0, 0x3f, 0x80, 0xff, 0x1f, 0xc0, 0xbf, 0xe1, 0x03, 0xff, 0x00, 0xfe,
|
||||
0x7f, 0x00, 0xff, 0x86, 0x0f, 0xfc, 0x03, 0xf8, 0xfe, 0x01, 0xfc, 0x1b,
|
||||
0x9a, 0x6b, 0x00, 0x00, 0x7f, 0xe0, 0x1f, 0xc0, 0xf0, 0x0f, 0xe0, 0xdf,
|
||||
0xff, 0x81, 0x7f, 0x00, 0xc3, 0x3f, 0x80, 0x7f, 0xfc, 0x07, 0xfe, 0x01,
|
||||
0x0d, 0xff, 0x00, 0xfe, 0xf0, 0xff, 0x3d, 0x00, 0xf4, 0x3f, 0xf0, 0xaf,
|
||||
0x72, 0xf8, 0x55, 0xaa, 0xd2, 0x7b, 0xcf, 0x3f, 0xfc, 0xe1, 0x5b, 0xa9,
|
||||
0x80, 0xff, 0x93, 0xff, 0x81, 0x87, 0x7f, 0x00, 0x00, 0xf8, 0xff, 0x1e,
|
||||
0x67, 0xf2, 0x1f, 0xf8, 0xfc, 0x3c, 0xfc, 0x03, 0x1f, 0xc0, 0x7f, 0xe0,
|
||||
0xe0, 0xdf, 0xf0, 0x0f, 0x7f, 0x00, 0xff, 0x81, 0x80, 0x7f, 0xc3, 0x3f,
|
||||
0x0f, 0x00, 0xdc, 0x7f, 0xfe, 0x73, 0xfb, 0xff, 0xf4, 0x22, 0x1f, 0xde,
|
||||
0xc0, 0x9f, 0x40, 0x5d, 0x63, 0xc0, 0x75, 0xf8, 0xe5, 0x3f, 0xb5, 0xff,
|
||||
0xdd, 0xef, 0xf8, 0xe1, 0xbf, 0x07, 0x00, 0xfe, 0x7f, 0xff, 0x9d, 0xfc,
|
||||
0xff, 0x00, 0x3f, 0x0f, 0xfe, 0xff, 0x7f, 0xf2, 0xfc, 0x03, 0xfc, 0x3c,
|
||||
0xff, 0xff, 0x3f, 0xc0, 0xf0, 0xfd, 0x64, 0xf0, 0x08, 0x90, 0x00, 0x00,
|
||||
0xfe, 0xbf, 0xff, 0xdc, 0x87, 0x37, 0xae, 0x88, 0xfb, 0x0f, 0xfc, 0x33,
|
||||
0x1f, 0xfe, 0x98, 0x96, 0xcd, 0xff, 0xff, 0x5f, 0x7e, 0x78, 0xa7, 0xba,
|
||||
0x00, 0x04, 0x48, 0x00, 0x00, 0xff, 0x81, 0x7f, 0xf2, 0xc3, 0x3b, 0x13,
|
||||
0xfd, 0xfd, 0x37, 0xff, 0x3f, 0x0f, 0xff, 0x7e, 0xd6, 0xf7, 0xff, 0xfd,
|
||||
0xe5, 0x3b, 0xfc, 0x71, 0x00, 0x80, 0xff, 0xef, 0x3f, 0x80, 0xff, 0xc0,
|
||||
0xc0, 0xbf, 0xe1, 0x1f, 0xff, 0x00, 0xfe, 0x03, 0x00, 0xff, 0x86, 0x7f,
|
||||
0xfc, 0x03, 0xf8, 0x0f, 0x01, 0xfc, 0x1b, 0xfe, 0x7b, 0x00, 0xe0, 0xff,
|
||||
0xe0, 0x1f, 0xc0, 0x7f, 0x0f, 0xe0, 0xdf, 0xf0, 0x81, 0x7f, 0x00, 0xff,
|
||||
0x3f, 0x80, 0x7f, 0xc3, 0x07, 0xfe, 0x01, 0xfc, 0xff, 0x00, 0xfe, 0x0d,
|
||||
0xff, 0x3d, 0x00, 0xf0, 0x3f, 0xf0, 0x0f, 0xe0, 0xf8, 0x07, 0xf0, 0x6f,
|
||||
0xff, 0xc0, 0x3f, 0x80, 0xe1, 0x1f, 0xc0, 0xbf, 0xfe, 0x03, 0xff, 0x00,
|
||||
0x86, 0x7f, 0x00, 0xff, 0xf8, 0xff, 0x1e, 0x00, 0xf0, 0x1f, 0xf8, 0x07,
|
||||
0x37, 0xfc, 0x03, 0xf8, 0xc0, 0x7f, 0xe0, 0x1f, 0xdf, 0xf0, 0x0f, 0xe0,
|
||||
0x00, 0xff, 0x81, 0x7f, 0x7f, 0xc3, 0x3f, 0x80, 0x00, 0xfc, 0x7f, 0x0f,
|
||||
0x03, 0xf8, 0x0f, 0xfc, 0xfc, 0x1b, 0xfe, 0x01, 0x0f, 0xe0, 0x3f, 0xf0,
|
||||
0xf0, 0x6f, 0xf8, 0x07, 0x3f, 0x80, 0xff, 0xc0, 0xc0, 0xbf, 0xe1, 0x1f,
|
||||
0x07, 0x00, 0xfe, 0xbf, 0xfe, 0x01, 0xfc, 0x07, 0x00, 0xfe, 0x0d, 0xff,
|
||||
0xf8, 0x07, 0xf0, 0x1f, 0x03, 0xf8, 0x37, 0xfc, 0xe0, 0x1f, 0xc0, 0x7f,
|
||||
0x0f, 0xe0, 0xdf, 0xf0, 0xdf, 0x03, 0x00, 0xff, 0x03, 0xff, 0x00, 0xfe,
|
||||
0x7f, 0x00, 0xff, 0x86, 0x0f, 0xfc, 0x03, 0xf8, 0xfe, 0x01, 0xfc, 0x1b,
|
||||
0x3f, 0xf0, 0x0f, 0xe0, 0xf8, 0x07, 0xf0, 0x6f, 0xff, 0xef, 0x01, 0x80,
|
||||
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
||||
163
src/cpu/amd/model_10xxx/mc_patch_01000033.h
Normal file
163
src/cpu/amd/model_10xxx/mc_patch_01000033.h
Normal file
@ -0,0 +1,163 @@
|
||||
/*
|
||||
============================================================
|
||||
(c) Advanced Micro Devices, Inc., 2004-2005
|
||||
|
||||
The enclosed microcode is intended to be used with AMD
|
||||
Microprocessors. You may copy, view and install the
|
||||
enclosed microcode only for development and deployment of
|
||||
firmware, BIOS, or operating system code for computer
|
||||
systems that contain AMD processors. You are not
|
||||
authorized to use the enclosed microcode for any other
|
||||
purpose.
|
||||
|
||||
THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR
|
||||
IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO
|
||||
WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT,
|
||||
TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES
|
||||
ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
AMD does not assume any responsibility for any errors which
|
||||
may appear in this microcode or any other related
|
||||
information provided to you by AMD, or result from use of
|
||||
this microcode. AMD is not obligated to furnish, support,
|
||||
or make any further information, software, technical
|
||||
information, know-how, or show-how available related to this
|
||||
microcode.
|
||||
|
||||
The microcode is provided with "RESTRICTED RIGHTS." Use,
|
||||
duplication, or disclosure by the U.S. Government is subject
|
||||
to the restrictions as set forth in FAR 52.227-14 and
|
||||
DFAR252.227-7013, et seq., or its successor. Use of the
|
||||
microcode by the U.S. Government constitutes
|
||||
acknowledgement of AMD's proprietary rights in them.
|
||||
============================================================
|
||||
*/
|
||||
|
||||
0x07, 0x20, 0x27, 0x06, 0x33, 0x00, 0x00, 0x01, 0x00, 0x80, 0x20, 0x00,
|
||||
0xDE, 0x76, 0xD5, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x20, 0x10, 0x00, 0x00, 0x00, 0xAA, 0xAA, 0xAA, 0x70, 0x09, 0x00, 0x00,
|
||||
0x49, 0x01, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xC1, 0x08, 0x00, 0x00,
|
||||
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF, 0x2A, 0xFF, 0xFF, 0x29, 0xC3, 0x5F, 0xD0, 0xC1,
|
||||
0xBD, 0xFF, 0xFF, 0xB3, 0x0F, 0xFF, 0x7E, 0xFD, 0xF6, 0x1F, 0xF8, 0x57,
|
||||
0x3C, 0xBC, 0x63, 0x2D, 0x80, 0x96, 0xD6, 0x00, 0xAA, 0xFF, 0xEF, 0xAF,
|
||||
0xE0, 0xD1, 0x9F, 0x15, 0x57, 0xEF, 0xFF, 0xFF, 0xEA, 0x87, 0x7F, 0xBF,
|
||||
0x03, 0xFA, 0x0F, 0xFC, 0xFC, 0x1F, 0xBE, 0xF5, 0x00, 0xE0, 0x4A, 0x4B,
|
||||
0x7F, 0xC8, 0xFF, 0xF7, 0xB4, 0xF8, 0xF0, 0x2F, 0xFF, 0x1F, 0xC5, 0xFE,
|
||||
0xC0, 0xCF, 0xC3, 0x3F, 0xFF, 0x03, 0xD4, 0xFF, 0x40, 0xC8, 0x0F, 0xEF,
|
||||
0x3D, 0x00, 0xF0, 0xFF, 0xFB, 0xAF, 0xE5, 0xBF, 0xD7, 0xFA, 0x3F, 0xF8,
|
||||
0xEB, 0x3F, 0x97, 0xFF, 0x9F, 0xEB, 0xFF, 0xE0, 0x97, 0xFF, 0x5E, 0xFE,
|
||||
0x7F, 0xAE, 0xFA, 0x83, 0xC9, 0x1A, 0x00, 0x08, 0x9F, 0xFC, 0x07, 0xF0,
|
||||
0x7C, 0x7B, 0xD9, 0x1F, 0x7F, 0xE0, 0x1F, 0xC0, 0xF0, 0x0F, 0xE0, 0xDF,
|
||||
0xFF, 0x81, 0x7F, 0x00, 0xC3, 0x3F, 0x80, 0x7F, 0xFC, 0x7F, 0x0F, 0x00,
|
||||
0xF8, 0x0F, 0xFC, 0x03, 0x1B, 0xFE, 0x01, 0xFC, 0xE0, 0x3F, 0xF0, 0x0F,
|
||||
0x6F, 0xF8, 0x07, 0xF0, 0x80, 0xFF, 0xC0, 0x3F, 0xBF, 0xE1, 0x1F, 0xC0,
|
||||
0x00, 0xFE, 0xBF, 0x07, 0x01, 0xFC, 0x67, 0xEB, 0x00, 0x07, 0xFE, 0xDE,
|
||||
0xFF, 0x02, 0x00, 0xE0, 0xFD, 0x3F, 0xBC, 0x63, 0xFF, 0x8B, 0xFF, 0xFF,
|
||||
0xF5, 0x7F, 0xF0, 0xEF, 0x03, 0x00, 0x3D, 0x57, 0xFF, 0x58, 0xFE, 0xBF,
|
||||
0xAC, 0x7C, 0x83, 0x3F, 0xFF, 0x7F, 0xF9, 0xE2, 0x01, 0x7E, 0x1E, 0xFE,
|
||||
0x1B, 0x0F, 0xE0, 0xBF, 0xF7, 0xF6, 0x3A, 0xF0, 0xAF, 0x01, 0x80, 0xB4,
|
||||
0x81, 0x7F, 0x00, 0xFF, 0x3F, 0x80, 0x7F, 0xC3, 0x07, 0xFE, 0x01, 0xFC,
|
||||
0xFF, 0x00, 0xFE, 0x0D, 0x1F, 0xF8, 0x07, 0xF0, 0xFC, 0x03, 0xF8, 0x37,
|
||||
0xFF, 0xF7, 0x00, 0xC0, 0xFF, 0xC0, 0x3F, 0x80, 0xE1, 0x1F, 0xC0, 0xBF,
|
||||
0xFE, 0x03, 0xFF, 0x00, 0x86, 0x7F, 0x00, 0xFF, 0xF8, 0x0F, 0xFC, 0x03,
|
||||
0x1B, 0xFE, 0x01, 0xFC, 0xE0, 0xFF, 0x7B, 0x00, 0xC0, 0x7F, 0xE0, 0x1F,
|
||||
0xDF, 0xF0, 0x0F, 0xE0, 0x00, 0xFF, 0x81, 0x7F, 0x7F, 0xC3, 0x3F, 0x80,
|
||||
0x01, 0xFC, 0x07, 0xFE, 0xFE, 0x0D, 0xFF, 0x00, 0x00, 0xF0, 0xFF, 0x3D,
|
||||
0x0F, 0xE0, 0x3F, 0xF0, 0xF0, 0x6F, 0xF8, 0x07, 0x3F, 0x80, 0xFF, 0xC0,
|
||||
0xC0, 0xBF, 0xE1, 0x1F, 0xFF, 0x00, 0xFE, 0x03, 0x00, 0xFF, 0x86, 0x7F,
|
||||
0x1E, 0x00, 0xF8, 0xFF, 0xF8, 0x07, 0xF0, 0x1F, 0x03, 0xF8, 0x37, 0xFC,
|
||||
0xE0, 0x1F, 0xC0, 0x7F, 0x0F, 0xE0, 0xDF, 0xF0, 0x81, 0x7F, 0x00, 0xFF,
|
||||
0x3F, 0x80, 0x7F, 0xC3, 0x7F, 0x0F, 0x00, 0xFC, 0x0F, 0xFC, 0x03, 0xF8,
|
||||
0xFE, 0x01, 0xFC, 0x1B, 0x3F, 0xF0, 0x0F, 0xE0, 0xF8, 0x07, 0xF0, 0x6F,
|
||||
0xFF, 0xC0, 0x3F, 0x80, 0xE1, 0x1F, 0xC0, 0xBF, 0xFE, 0xBF, 0x07, 0x00,
|
||||
0xFC, 0x07, 0xFE, 0x01, 0x0D, 0xFF, 0x00, 0xFE, 0xF0, 0x1F, 0xF8, 0x07,
|
||||
0x37, 0xFC, 0x03, 0xF8, 0xC0, 0x7F, 0xE0, 0x1F, 0xDF, 0xF0, 0x0F, 0xE0,
|
||||
0x00, 0xFF, 0xDF, 0x03, 0x00, 0xFE, 0x03, 0xFF, 0xFF, 0x86, 0x7F, 0x00,
|
||||
0x03, 0xF8, 0x0F, 0xFC, 0xFC, 0x1B, 0xFE, 0x01, 0x0F, 0xE0, 0x3F, 0xF0,
|
||||
0xF0, 0x6F, 0xF8, 0x07, 0x01, 0x80, 0xFF, 0xEF, 0x7F, 0x00, 0xFF, 0x81,
|
||||
0x80, 0x7F, 0xC3, 0x3F, 0xFE, 0x01, 0xFC, 0x07, 0x00, 0xFE, 0x0D, 0xFF,
|
||||
0xF8, 0x07, 0xF0, 0x1F, 0x03, 0xF8, 0x37, 0xFC, 0xD7, 0x00, 0x40, 0x34,
|
||||
0xC0, 0x3F, 0x80, 0xFF, 0x1F, 0xC0, 0xBF, 0xE1, 0x03, 0xFF, 0x00, 0xFE,
|
||||
0x7F, 0x00, 0xFF, 0x86, 0x0F, 0xFC, 0x03, 0xF8, 0xFE, 0x01, 0xFC, 0x1B,
|
||||
0x9A, 0x6B, 0x00, 0x00, 0x7F, 0xE0, 0x1F, 0xC0, 0xF0, 0x0F, 0xE0, 0xDF,
|
||||
0xFF, 0x81, 0x7F, 0x00, 0xC3, 0x3F, 0x80, 0x7F, 0xFC, 0x07, 0xFE, 0x01,
|
||||
0x0D, 0xFF, 0x00, 0xFE, 0xF0, 0xFF, 0x3D, 0x00, 0xE0, 0x3F, 0xF0, 0x0F,
|
||||
0x6F, 0xF8, 0x07, 0xF0, 0x80, 0xFF, 0xC0, 0x3F, 0xBF, 0xE1, 0x1F, 0xC0,
|
||||
0x00, 0xFE, 0x03, 0xFF, 0xFF, 0x86, 0x7F, 0x00, 0x00, 0xF8, 0xFF, 0x1E,
|
||||
0x07, 0xF0, 0x1F, 0xF8, 0xF8, 0x37, 0xFC, 0x03, 0x1F, 0xC0, 0x7F, 0xE0,
|
||||
0xE0, 0xDF, 0xF0, 0x0F, 0x7F, 0x00, 0xFF, 0x81, 0x80, 0x7F, 0xC3, 0x3F,
|
||||
0x0F, 0x00, 0xFC, 0x7F, 0xFC, 0x03, 0xF8, 0x0F, 0x01, 0xFC, 0x1B, 0xFE,
|
||||
0xF0, 0x0F, 0xE0, 0x3F, 0x07, 0xF0, 0x6F, 0xF8, 0xC0, 0x3F, 0x80, 0xFF,
|
||||
0x1F, 0xC0, 0xBF, 0xE1, 0xBF, 0x07, 0x00, 0xFE, 0x07, 0xFE, 0x01, 0xFC,
|
||||
0xFF, 0x00, 0xFE, 0x0D, 0x1F, 0xF8, 0x07, 0xF0, 0xFC, 0x03, 0xF8, 0x37,
|
||||
0x7F, 0xE0, 0x1F, 0xC0, 0xF0, 0x0F, 0xE0, 0xDF, 0xFF, 0xDF, 0x03, 0x00,
|
||||
0xFE, 0x03, 0xFF, 0x00, 0x86, 0x7F, 0x00, 0xFF, 0xF8, 0x0F, 0xFC, 0x03,
|
||||
0x1B, 0xFE, 0x01, 0xFC, 0xE0, 0x3F, 0xF0, 0x0F, 0x6F, 0xF8, 0x07, 0xF0,
|
||||
0x80, 0xFF, 0xEF, 0x01, 0x00, 0xFF, 0x81, 0x7F, 0x7F, 0xC3, 0x3F, 0x80,
|
||||
0x01, 0xFC, 0x07, 0xFE, 0xFE, 0x0D, 0xFF, 0x00, 0x07, 0xF0, 0x1F, 0xF8,
|
||||
0xF8, 0x37, 0xFC, 0x03, 0x00, 0xC0, 0xFF, 0xF7, 0x3F, 0x80, 0xFF, 0xC0,
|
||||
0xC0, 0xBF, 0xE1, 0x1F, 0xFF, 0x00, 0xFE, 0x03, 0x00, 0xFF, 0x86, 0x7F,
|
||||
0xFC, 0x03, 0xF8, 0x0F, 0x01, 0xFC, 0x1B, 0xFE, 0x7B, 0x00, 0xE0, 0xFF,
|
||||
0xE0, 0x1F, 0xC0, 0x7F, 0x0F, 0xE0, 0xDF, 0xF0, 0x81, 0x7F, 0x00, 0xFF,
|
||||
0x3F, 0x80, 0x7F, 0xC3, 0x07, 0xFE, 0x01, 0xFC, 0xFF, 0x00, 0xFE, 0x0D,
|
||||
0xFF, 0x3D, 0x00, 0xF0, 0x3F, 0xF0, 0x0F, 0xE0, 0xF8, 0x07, 0xF0, 0x6F,
|
||||
0xFF, 0xC0, 0x3F, 0x80, 0xE1, 0x1F, 0xC0, 0xBF, 0xFE, 0x03, 0xFF, 0x00,
|
||||
0x86, 0x7F, 0x00, 0xFF, 0xF8, 0xFF, 0x1E, 0x00, 0xF0, 0x1F, 0xF8, 0x07,
|
||||
0x37, 0xFC, 0x03, 0xF8, 0xC0, 0x7F, 0xE0, 0x1F, 0xDF, 0xF0, 0x0F, 0xE0,
|
||||
0x00, 0xFF, 0x81, 0x7F, 0x7F, 0xC3, 0x3F, 0x80, 0x00, 0xFC, 0x7F, 0x0F,
|
||||
0x03, 0xF8, 0x0F, 0xFC, 0xFC, 0x1B, 0xFE, 0x01, 0x0F, 0xE0, 0x3F, 0xF0,
|
||||
0xF0, 0x6F, 0xF8, 0x07, 0x3F, 0x80, 0xFF, 0xC0, 0xC0, 0xBF, 0xE1, 0x1F,
|
||||
0x07, 0x00, 0xFE, 0xBF, 0xFE, 0x01, 0xFC, 0x07, 0x00, 0xFE, 0x0D, 0xFF,
|
||||
0xF8, 0x07, 0xF0, 0x1F, 0x03, 0xF8, 0x37, 0xFC, 0xE0, 0x1F, 0xC0, 0x7F,
|
||||
0x0F, 0xE0, 0xDF, 0xF0, 0xDF, 0x03, 0x00, 0xFF, 0x03, 0xFF, 0x00, 0xFE,
|
||||
0x7F, 0x00, 0xFF, 0x86, 0x0F, 0xFC, 0x03, 0xF8, 0xFE, 0x01, 0xFC, 0x1B,
|
||||
0x3F, 0xF0, 0x0F, 0xE0, 0xF8, 0x07, 0xF0, 0x6F, 0xFF, 0xEF, 0x01, 0x80,
|
||||
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
||||
163
src/cpu/amd/model_10xxx/mc_patch_01000035.h
Normal file
163
src/cpu/amd/model_10xxx/mc_patch_01000035.h
Normal file
@ -0,0 +1,163 @@
|
||||
/*
|
||||
============================================================
|
||||
(c) Advanced Micro Devices, Inc., 2004-2005
|
||||
|
||||
The enclosed microcode is intended to be used with AMD
|
||||
Microprocessors. You may copy, view and install the
|
||||
enclosed microcode only for development and deployment of
|
||||
firmware, BIOS, or operating system code for computer
|
||||
systems that contain AMD processors. You are not
|
||||
authorized to use the enclosed microcode for any other
|
||||
purpose.
|
||||
|
||||
THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR
|
||||
IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO
|
||||
WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT,
|
||||
TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES
|
||||
ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
|
||||
AMD does not assume any responsibility for any errors which
|
||||
may appear in this microcode or any other related
|
||||
information provided to you by AMD, or result from use of
|
||||
this microcode. AMD is not obligated to furnish, support,
|
||||
or make any further information, software, technical
|
||||
information, know-how, or show-how available related to this
|
||||
microcode.
|
||||
|
||||
The microcode is provided with "RESTRICTED RIGHTS." Use,
|
||||
duplication, or disclosure by the U.S. Government is subject
|
||||
to the restrictions as set forth in FAR 52.227-14 and
|
||||
DFAR252.227-7013, et seq., or its successor. Use of the
|
||||
microcode by the U.S. Government constitutes
|
||||
acknowledgement of AMD's proprietary rights in them.
|
||||
============================================================
|
||||
*/
|
||||
|
||||
0x07, 0x20, 0x23, 0x07, 0x35, 0x00, 0x00, 0x01, 0x00, 0x80, 0x20, 0x00,
|
||||
0xDE, 0x76, 0xD5, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x22, 0x10, 0x00, 0x00, 0x00, 0xAA, 0xAA, 0xAA, 0x70, 0x09, 0x00, 0x00,
|
||||
0x49, 0x01, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xC1, 0x08, 0x00, 0x00,
|
||||
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF, 0x2A, 0xFF, 0xFF, 0x29, 0xC3, 0x5F, 0xD0, 0xC1,
|
||||
0xBD, 0xFF, 0xFF, 0xB3, 0x0F, 0xFF, 0x7E, 0xFD, 0xF6, 0x1F, 0xF8, 0x57,
|
||||
0x3C, 0xBC, 0x63, 0x2D, 0x80, 0x96, 0xD6, 0x00, 0xAA, 0xFF, 0xEF, 0xAF,
|
||||
0xE0, 0xD1, 0x9F, 0x15, 0x57, 0xEF, 0xFF, 0xFF, 0xEA, 0x87, 0x7F, 0xBF,
|
||||
0x03, 0xFA, 0x0F, 0xFC, 0xFC, 0x1F, 0xBE, 0xF5, 0x00, 0xE0, 0x4A, 0x4B,
|
||||
0x7F, 0xC8, 0xFF, 0xF7, 0xB4, 0xF8, 0xF0, 0x2F, 0xFF, 0x1F, 0xC5, 0xFE,
|
||||
0xC0, 0xCF, 0xC3, 0x3F, 0xFF, 0x03, 0xD4, 0xFF, 0x40, 0xC8, 0x0F, 0xEF,
|
||||
0x3D, 0x00, 0xF0, 0xFF, 0xFB, 0xAF, 0xE5, 0xBF, 0xD7, 0xFA, 0x3F, 0xF8,
|
||||
0xEB, 0x3F, 0x97, 0xFF, 0x9F, 0xEB, 0xFF, 0xE0, 0x97, 0xFF, 0x5E, 0xFE,
|
||||
0x7F, 0xAE, 0xFA, 0x83, 0xC9, 0x1A, 0x00, 0x08, 0x9F, 0xFC, 0x07, 0xF0,
|
||||
0x7C, 0x7B, 0xD9, 0x1F, 0x7F, 0xE0, 0x1F, 0xC0, 0xF0, 0x0F, 0xE0, 0xDF,
|
||||
0xFF, 0x81, 0x7F, 0x00, 0xC3, 0x3F, 0x80, 0x7F, 0xFC, 0x7F, 0x0F, 0x00,
|
||||
0xF8, 0x0F, 0xFC, 0x03, 0x1B, 0xFE, 0x01, 0xFC, 0xE0, 0x3F, 0xF0, 0x0F,
|
||||
0x6F, 0xF8, 0x07, 0xF0, 0x80, 0xFF, 0xC0, 0x3F, 0xBF, 0xE1, 0x1F, 0xC0,
|
||||
0x00, 0xFE, 0xBF, 0x07, 0x01, 0xFC, 0x67, 0xEB, 0x00, 0x07, 0xFE, 0xDE,
|
||||
0xFF, 0x02, 0x00, 0xE0, 0xFD, 0x3F, 0xBC, 0x63, 0xFF, 0x8B, 0xFF, 0xFF,
|
||||
0xF5, 0x7F, 0xF0, 0xEF, 0x03, 0x00, 0x3D, 0x57, 0xFF, 0x58, 0xFE, 0xBF,
|
||||
0xAC, 0x7C, 0x83, 0x3F, 0xFF, 0x7F, 0xF9, 0xE2, 0x01, 0x7E, 0x1E, 0xFE,
|
||||
0x1B, 0x0F, 0xE0, 0xBF, 0xF7, 0xF6, 0x3A, 0xF0, 0xAF, 0x01, 0x80, 0xB4,
|
||||
0x81, 0x7F, 0x00, 0xFF, 0x3F, 0x80, 0x7F, 0xC3, 0x07, 0xFE, 0x01, 0xFC,
|
||||
0xFF, 0x00, 0xFE, 0x0D, 0x1F, 0xF8, 0x07, 0xF0, 0xFC, 0x03, 0xF8, 0x37,
|
||||
0xFF, 0xF7, 0x00, 0xC0, 0xFF, 0xC0, 0x3F, 0x80, 0xE1, 0x1F, 0xC0, 0xBF,
|
||||
0xFE, 0x03, 0xFF, 0x00, 0x86, 0x7F, 0x00, 0xFF, 0xF8, 0x0F, 0xFC, 0x03,
|
||||
0x1B, 0xFE, 0x01, 0xFC, 0xE0, 0xFF, 0x7B, 0x00, 0xC0, 0x7F, 0xE0, 0x1F,
|
||||
0xDF, 0xF0, 0x0F, 0xE0, 0x00, 0xFF, 0x81, 0x7F, 0x7F, 0xC3, 0x3F, 0x80,
|
||||
0x01, 0xFC, 0x07, 0xFE, 0xFE, 0x0D, 0xFF, 0x00, 0x00, 0xF0, 0xFF, 0x3D,
|
||||
0x0F, 0xE0, 0x3F, 0xF0, 0xF0, 0x6F, 0xF8, 0x07, 0x3F, 0x80, 0xFF, 0xC0,
|
||||
0xC0, 0xBF, 0xE1, 0x1F, 0xFF, 0x00, 0xFE, 0x03, 0x00, 0xFF, 0x86, 0x7F,
|
||||
0x1E, 0x00, 0xF8, 0xFF, 0xF8, 0x07, 0xF0, 0x1F, 0x03, 0xF8, 0x37, 0xFC,
|
||||
0xE0, 0x1F, 0xC0, 0x7F, 0x0F, 0xE0, 0xDF, 0xF0, 0x81, 0x7F, 0x00, 0xFF,
|
||||
0x3F, 0x80, 0x7F, 0xC3, 0x7F, 0x0F, 0x00, 0xFC, 0x0F, 0xFC, 0x03, 0xF8,
|
||||
0xFE, 0x01, 0xFC, 0x1B, 0x3F, 0xF0, 0x0F, 0xE0, 0xF8, 0x07, 0xF0, 0x6F,
|
||||
0xFF, 0xC0, 0x3F, 0x80, 0xE1, 0x1F, 0xC0, 0xBF, 0xFE, 0xBF, 0x07, 0x00,
|
||||
0xFC, 0x07, 0xFE, 0x01, 0x0D, 0xFF, 0x00, 0xFE, 0xF0, 0x1F, 0xF8, 0x07,
|
||||
0x37, 0xFC, 0x03, 0xF8, 0xC0, 0x7F, 0xE0, 0x1F, 0xDF, 0xF0, 0x0F, 0xE0,
|
||||
0x00, 0xFF, 0xDF, 0x03, 0x00, 0xFE, 0x03, 0xFF, 0xFF, 0x86, 0x7F, 0x00,
|
||||
0x03, 0xF8, 0x0F, 0xFC, 0xFC, 0x1B, 0xFE, 0x01, 0x0F, 0xE0, 0x3F, 0xF0,
|
||||
0xF0, 0x6F, 0xF8, 0x07, 0x01, 0x80, 0xFF, 0xEF, 0x7F, 0x00, 0xFF, 0x81,
|
||||
0x80, 0x7F, 0xC3, 0x3F, 0xFE, 0x01, 0xFC, 0x07, 0x00, 0xFE, 0x0D, 0xFF,
|
||||
0xF8, 0x07, 0xF0, 0x1F, 0x03, 0xF8, 0x37, 0xFC, 0xD7, 0x00, 0x40, 0x34,
|
||||
0xC0, 0x3F, 0x80, 0xFF, 0x1F, 0xC0, 0xBF, 0xE1, 0x03, 0xFF, 0x00, 0xFE,
|
||||
0x7F, 0x00, 0xFF, 0x86, 0x0F, 0xFC, 0x03, 0xF8, 0xFE, 0x01, 0xFC, 0x1B,
|
||||
0x9A, 0x6B, 0x00, 0x00, 0x7F, 0xE0, 0x1F, 0xC0, 0xF0, 0x0F, 0xE0, 0xDF,
|
||||
0xFF, 0x81, 0x7F, 0x00, 0xC3, 0x3F, 0x80, 0x7F, 0xFC, 0x07, 0xFE, 0x01,
|
||||
0x0D, 0xFF, 0x00, 0xFE, 0xF0, 0xFF, 0x3D, 0x00, 0xE0, 0x3F, 0xF0, 0x0F,
|
||||
0x6F, 0xF8, 0x07, 0xF0, 0x80, 0xFF, 0xC0, 0x3F, 0xBF, 0xE1, 0x1F, 0xC0,
|
||||
0x00, 0xFE, 0x03, 0xFF, 0xFF, 0x86, 0x7F, 0x00, 0x00, 0xF8, 0xFF, 0x1E,
|
||||
0x07, 0xF0, 0x1F, 0xF8, 0xF8, 0x37, 0xFC, 0x03, 0x1F, 0xC0, 0x7F, 0xE0,
|
||||
0xE0, 0xDF, 0xF0, 0x0F, 0x7F, 0x00, 0xFF, 0x81, 0x80, 0x7F, 0xC3, 0x3F,
|
||||
0x0F, 0x00, 0xFC, 0x7F, 0xFC, 0x03, 0xF8, 0x0F, 0x01, 0xFC, 0x1B, 0xFE,
|
||||
0xF0, 0x0F, 0xE0, 0x3F, 0x07, 0xF0, 0x6F, 0xF8, 0xC0, 0x3F, 0x80, 0xFF,
|
||||
0x1F, 0xC0, 0xBF, 0xE1, 0xBF, 0x07, 0x00, 0xFE, 0x07, 0xFE, 0x01, 0xFC,
|
||||
0xFF, 0x00, 0xFE, 0x0D, 0x1F, 0xF8, 0x07, 0xF0, 0xFC, 0x03, 0xF8, 0x37,
|
||||
0x7F, 0xE0, 0x1F, 0xC0, 0xF0, 0x0F, 0xE0, 0xDF, 0xFF, 0xDF, 0x03, 0x00,
|
||||
0xFE, 0x03, 0xFF, 0x00, 0x86, 0x7F, 0x00, 0xFF, 0xF8, 0x0F, 0xFC, 0x03,
|
||||
0x1B, 0xFE, 0x01, 0xFC, 0xE0, 0x3F, 0xF0, 0x0F, 0x6F, 0xF8, 0x07, 0xF0,
|
||||
0x80, 0xFF, 0xEF, 0x01, 0x00, 0xFF, 0x81, 0x7F, 0x7F, 0xC3, 0x3F, 0x80,
|
||||
0x01, 0xFC, 0x07, 0xFE, 0xFE, 0x0D, 0xFF, 0x00, 0x07, 0xF0, 0x1F, 0xF8,
|
||||
0xF8, 0x37, 0xFC, 0x03, 0x00, 0xC0, 0xFF, 0xF7, 0x3F, 0x80, 0xFF, 0xC0,
|
||||
0xC0, 0xBF, 0xE1, 0x1F, 0xFF, 0x00, 0xFE, 0x03, 0x00, 0xFF, 0x86, 0x7F,
|
||||
0xFC, 0x03, 0xF8, 0x0F, 0x01, 0xFC, 0x1B, 0xFE, 0x7B, 0x00, 0xE0, 0xFF,
|
||||
0xE0, 0x1F, 0xC0, 0x7F, 0x0F, 0xE0, 0xDF, 0xF0, 0x81, 0x7F, 0x00, 0xFF,
|
||||
0x3F, 0x80, 0x7F, 0xC3, 0x07, 0xFE, 0x01, 0xFC, 0xFF, 0x00, 0xFE, 0x0D,
|
||||
0xFF, 0x3D, 0x00, 0xF0, 0x3F, 0xF0, 0x0F, 0xE0, 0xF8, 0x07, 0xF0, 0x6F,
|
||||
0xFF, 0xC0, 0x3F, 0x80, 0xE1, 0x1F, 0xC0, 0xBF, 0xFE, 0x03, 0xFF, 0x00,
|
||||
0x86, 0x7F, 0x00, 0xFF, 0xF8, 0xFF, 0x1E, 0x00, 0xF0, 0x1F, 0xF8, 0x07,
|
||||
0x37, 0xFC, 0x03, 0xF8, 0xC0, 0x7F, 0xE0, 0x1F, 0xDF, 0xF0, 0x0F, 0xE0,
|
||||
0x00, 0xFF, 0x81, 0x7F, 0x7F, 0xC3, 0x3F, 0x80, 0x00, 0xFC, 0x7F, 0x0F,
|
||||
0x03, 0xF8, 0x0F, 0xFC, 0xFC, 0x1B, 0xFE, 0x01, 0x0F, 0xE0, 0x3F, 0xF0,
|
||||
0xF0, 0x6F, 0xF8, 0x07, 0x3F, 0x80, 0xFF, 0xC0, 0xC0, 0xBF, 0xE1, 0x1F,
|
||||
0x07, 0x00, 0xFE, 0xBF, 0xFE, 0x01, 0xFC, 0x07, 0x00, 0xFE, 0x0D, 0xFF,
|
||||
0xF8, 0x07, 0xF0, 0x1F, 0x03, 0xF8, 0x37, 0xFC, 0xE0, 0x1F, 0xC0, 0x7F,
|
||||
0x0F, 0xE0, 0xDF, 0xF0, 0xDF, 0x03, 0x00, 0xFF, 0x03, 0xFF, 0x00, 0xFE,
|
||||
0x7F, 0x00, 0xFF, 0x86, 0x0F, 0xFC, 0x03, 0xF8, 0xFE, 0x01, 0xFC, 0x1B,
|
||||
0x3F, 0xF0, 0x0F, 0xE0, 0xF8, 0x07, 0xF0, 0x6F, 0xFF, 0xEF, 0x01, 0x80,
|
||||
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
||||
463
src/cpu/amd/model_10xxx/model_10xxx_init.c
Normal file
463
src/cpu/amd/model_10xxx/model_10xxx_init.c
Normal file
@ -0,0 +1,463 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/amd/mtrr.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/x86/pae.h>
|
||||
#include <pc80/mc146818rtc.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
|
||||
#include "../../../northbridge/amd/amdfam10/amdfam10.h"
|
||||
|
||||
#include <cpu/amd/model_10xxx_rev.h>
|
||||
#include <cpu/cpu.h>
|
||||
#include <cpu/x86/cache.h>
|
||||
#include <cpu/x86/mtrr.h>
|
||||
#include <cpu/x86/mem.h>
|
||||
|
||||
#include <cpu/amd/quadcore.h>
|
||||
|
||||
#include <cpu/amd/model_10xxx_msr.h>
|
||||
|
||||
extern void prep_pstates_all(void);
|
||||
extern void init_pstates(device_t dev, u32 nodeid, u32 coreid);
|
||||
extern device_t get_node_pci(u32 nodeid, u32 fn);
|
||||
|
||||
|
||||
|
||||
void cpus_ready_for_init(void)
|
||||
{
|
||||
prep_pstates_all();
|
||||
#if MEM_TRAIN_SEQ == 1
|
||||
struct sys_info *sysinfox = (struct sys_info *)((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE);
|
||||
// wait for ap memory to trained
|
||||
wait_all_core0_mem_trained(sysinfox);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
#define MCI_STATUS 0x401
|
||||
|
||||
|
||||
static inline msr_t rdmsr_amd(u32 index)
|
||||
{
|
||||
msr_t result;
|
||||
__asm__ __volatile__ (
|
||||
"rdmsr"
|
||||
: "=a" (result.lo), "=d" (result.hi)
|
||||
: "c" (index), "D" (0x9c5a203a)
|
||||
);
|
||||
return result;
|
||||
}
|
||||
|
||||
|
||||
static inline void wrmsr_amd(u32 index, msr_t msr)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"wrmsr"
|
||||
: /* No outputs */
|
||||
: "c" (index), "a" (msr.lo), "d" (msr.hi), "D" (0x9c5a203a)
|
||||
);
|
||||
}
|
||||
|
||||
|
||||
#define MTRR_COUNT 8
|
||||
#define ZERO_CHUNK_KB 0x800UL /* 2M */
|
||||
#define TOLM_KB 0x400000UL
|
||||
|
||||
struct mtrr {
|
||||
msr_t base;
|
||||
msr_t mask;
|
||||
};
|
||||
|
||||
|
||||
struct mtrr_state {
|
||||
struct mtrr mtrrs[MTRR_COUNT];
|
||||
msr_t top_mem, top_mem2;
|
||||
msr_t def_type;
|
||||
};
|
||||
|
||||
|
||||
static void save_mtrr_state(struct mtrr_state *state)
|
||||
{
|
||||
int i;
|
||||
for(i = 0; i < MTRR_COUNT; i++) {
|
||||
state->mtrrs[i].base = rdmsr(MTRRphysBase_MSR(i));
|
||||
state->mtrrs[i].mask = rdmsr(MTRRphysMask_MSR(i));
|
||||
}
|
||||
state->top_mem = rdmsr(TOP_MEM);
|
||||
state->top_mem2 = rdmsr(TOP_MEM2);
|
||||
state->def_type = rdmsr(MTRRdefType_MSR);
|
||||
}
|
||||
|
||||
|
||||
static void restore_mtrr_state(struct mtrr_state *state)
|
||||
{
|
||||
int i;
|
||||
disable_cache();
|
||||
|
||||
for(i = 0; i < MTRR_COUNT; i++) {
|
||||
wrmsr(MTRRphysBase_MSR(i), state->mtrrs[i].base);
|
||||
wrmsr(MTRRphysMask_MSR(i), state->mtrrs[i].mask);
|
||||
}
|
||||
wrmsr(TOP_MEM, state->top_mem);
|
||||
wrmsr(TOP_MEM2, state->top_mem2);
|
||||
wrmsr(MTRRdefType_MSR, state->def_type);
|
||||
|
||||
enable_cache();
|
||||
}
|
||||
|
||||
|
||||
#if 0
|
||||
static void print_mtrr_state(struct mtrr_state *state)
|
||||
{
|
||||
int i;
|
||||
for(i = 0; i < MTRR_COUNT; i++) {
|
||||
printk_debug("var mtrr %d: %08x%08x mask: %08x%08x\n",
|
||||
i,
|
||||
state->mtrrs[i].base.hi, state->mtrrs[i].base.lo,
|
||||
state->mtrrs[i].mask.hi, state->mtrrs[i].mask.lo);
|
||||
}
|
||||
printk_debug("top_mem: %08x%08x\n",
|
||||
state->top_mem.hi, state->top_mem.lo);
|
||||
printk_debug("top_mem2: %08x%08x\n",
|
||||
state->top_mem2.hi, state->top_mem2.lo);
|
||||
printk_debug("def_type: %08x%08x\n",
|
||||
state->def_type.hi, state->def_type.lo);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
static void set_init_ecc_mtrrs(void)
|
||||
{
|
||||
msr_t msr;
|
||||
int i;
|
||||
disable_cache();
|
||||
|
||||
/* First clear all of the msrs to be safe */
|
||||
for(i = 0; i < MTRR_COUNT; i++) {
|
||||
msr_t zero;
|
||||
zero.lo = zero.hi = 0;
|
||||
wrmsr(MTRRphysBase_MSR(i), zero);
|
||||
wrmsr(MTRRphysMask_MSR(i), zero);
|
||||
}
|
||||
|
||||
/* Write back cache the first 1MB */
|
||||
msr.hi = 0x00000000;
|
||||
msr.lo = 0x00000000 | MTRR_TYPE_WRBACK;
|
||||
wrmsr(MTRRphysBase_MSR(0), msr);
|
||||
msr.hi = 0x000000ff;
|
||||
msr.lo = ~((CONFIG_LB_MEM_TOPK << 10) - 1) | 0x800;
|
||||
wrmsr(MTRRphysMask_MSR(0), msr);
|
||||
|
||||
/* Set the default type to write combining */
|
||||
msr.hi = 0x00000000;
|
||||
msr.lo = 0xc00 | MTRR_TYPE_WRCOMB;
|
||||
wrmsr(MTRRdefType_MSR, msr);
|
||||
|
||||
/* Set TOP_MEM to 4G */
|
||||
msr.hi = 0x00000001;
|
||||
msr.lo = 0x00000000;
|
||||
wrmsr(TOP_MEM, msr);
|
||||
|
||||
enable_cache();
|
||||
}
|
||||
|
||||
|
||||
static inline void clear_2M_ram(unsigned long basek, struct mtrr_state *mtrr_state)
|
||||
{
|
||||
unsigned long limitk;
|
||||
unsigned long size;
|
||||
void *addr;
|
||||
|
||||
/* Report every 64M */
|
||||
if ((basek % (64*1024)) == 0) {
|
||||
|
||||
/* Restore the normal state */
|
||||
map_2M_page(0);
|
||||
restore_mtrr_state(mtrr_state);
|
||||
enable_lapic();
|
||||
|
||||
/* Print a status message */
|
||||
printk_debug("%c", (basek >= TOLM_KB)?'+':'-');
|
||||
|
||||
/* Return to the initialization state */
|
||||
set_init_ecc_mtrrs();
|
||||
disable_lapic();
|
||||
|
||||
}
|
||||
|
||||
limitk = (basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1);
|
||||
|
||||
size = (limitk - basek) << 10;
|
||||
addr = map_2M_page(basek >> 11);
|
||||
if (addr == MAPPING_ERROR) {
|
||||
printk_err("Cannot map page: %x\n", basek >> 11);
|
||||
return;
|
||||
}
|
||||
|
||||
/* clear memory 2M (limitk - basek) */
|
||||
addr = (void *)(((u32)addr) | ((basek & 0x7ff) << 10));
|
||||
clear_memory(addr, size);
|
||||
}
|
||||
|
||||
|
||||
static void init_ecc_memory(u32 node_id)
|
||||
{
|
||||
unsigned long startk, begink, endk;
|
||||
unsigned long hole_startk = 0;
|
||||
unsigned long basek;
|
||||
struct mtrr_state mtrr_state;
|
||||
|
||||
device_t f1_dev, f2_dev, f3_dev;
|
||||
int enable_scrubbing;
|
||||
u32 dcl;
|
||||
|
||||
f1_dev = get_node_pci(node_id, 1);
|
||||
|
||||
if (!f1_dev) {
|
||||
die("Cannot find cpu function 1\n");
|
||||
}
|
||||
f2_dev = get_node_pci(node_id, 2);
|
||||
if (!f2_dev) {
|
||||
die("Cannot find cpu function 2\n");
|
||||
}
|
||||
f3_dev = get_node_pci(node_id, 3);
|
||||
if (!f3_dev) {
|
||||
die("Cannot find cpu function 3\n");
|
||||
}
|
||||
|
||||
/* See if we scrubbing should be enabled */
|
||||
enable_scrubbing = 1;
|
||||
get_option(&enable_scrubbing, "hw_scrubber");
|
||||
|
||||
/* Enable cache scrubbing at the lowest possible rate */
|
||||
if (enable_scrubbing) {
|
||||
pci_write_config32(f3_dev, DRAM_SCRUB_RATE_CTRL,
|
||||
(SCRUB_84ms << 16) | (SCRUB_84ms << 8) | (SCRUB_NONE << 0));
|
||||
} else {
|
||||
pci_write_config32(f3_dev, DRAM_SCRUB_RATE_CTRL,
|
||||
(SCRUB_NONE << 16) | (SCRUB_NONE << 8) | (SCRUB_NONE << 0));
|
||||
printk_debug("Scrubbing Disabled\n");
|
||||
}
|
||||
|
||||
|
||||
/* If ecc support is not enabled don't touch memory */
|
||||
dcl = pci_read_config32(f2_dev, DRAM_CONFIG_LOW);
|
||||
if (!(dcl & DCL_DimmEccEn)) {
|
||||
printk_debug("ECC Disabled\n");
|
||||
return;
|
||||
}
|
||||
|
||||
startk = (pci_read_config32(f1_dev, 0x40 + (node_id*8)) & 0xffff0000) >> 2;
|
||||
endk = ((pci_read_config32(f1_dev, 0x44 + (node_id*8)) & 0xffff0000) >> 2) + 0x4000;
|
||||
|
||||
#if HW_MEM_HOLE_SIZEK != 0
|
||||
u32 val;
|
||||
val = pci_read_config32(f1_dev, 0xf0);
|
||||
if(val & 1) {
|
||||
hole_startk = ((val & (0xff<<24)) >> 10);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/* Don't start too early */
|
||||
begink = startk;
|
||||
if (begink < CONFIG_LB_MEM_TOPK) {
|
||||
begink = CONFIG_LB_MEM_TOPK;
|
||||
}
|
||||
|
||||
printk_debug("Clearing memory %uK - %uK: ", begink, endk);
|
||||
|
||||
/* Save the normal state */
|
||||
save_mtrr_state(&mtrr_state);
|
||||
|
||||
/* Switch to the init ecc state */
|
||||
set_init_ecc_mtrrs();
|
||||
disable_lapic();
|
||||
|
||||
/* Walk through 2M chunks and zero them */
|
||||
#if HW_MEM_HOLE_SIZEK != 0
|
||||
/* here hole_startk can not be equal to begink, never. Also hole_startk is in 2M boundary, 64M? */
|
||||
if ( (hole_startk != 0) && ((begink < hole_startk) && (endk>(4*1024*1024)))) {
|
||||
for(basek = begink; basek < hole_startk;
|
||||
basek = ((basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1)))
|
||||
{
|
||||
clear_2M_ram(basek, &mtrr_state);
|
||||
}
|
||||
for(basek = 4*1024*1024; basek < endk;
|
||||
basek = ((basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1)))
|
||||
{
|
||||
clear_2M_ram(basek, &mtrr_state);
|
||||
}
|
||||
} else
|
||||
#endif
|
||||
for(basek = begink; basek < endk;
|
||||
basek = ((basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1))) {
|
||||
clear_2M_ram(basek, &mtrr_state);
|
||||
}
|
||||
|
||||
|
||||
/* Restore the normal state */
|
||||
map_2M_page(0);
|
||||
restore_mtrr_state(&mtrr_state);
|
||||
enable_lapic();
|
||||
|
||||
/* Set the scrub base address registers */
|
||||
pci_write_config32(f3_dev, DRAM_SCRUB_ADDR_LOW, startk << 10);
|
||||
pci_write_config32(f3_dev, DRAM_SCRUB_ADDR_HIGH, startk >> 22);
|
||||
|
||||
/* Enable the scrubber? */
|
||||
if (enable_scrubbing) {
|
||||
/* Enable scrubbing at the lowest possible rate */
|
||||
pci_write_config32(f3_dev, DRAM_SCRUB_RATE_CTRL,
|
||||
(SCRUB_84ms << 16) | (SCRUB_84ms << 8) | (SCRUB_84ms << 0));
|
||||
}
|
||||
|
||||
printk_debug(" done\n");
|
||||
}
|
||||
|
||||
|
||||
static inline void fam10_errata(void)
|
||||
{
|
||||
msr_t msr;
|
||||
/* FIXME: Is doing errata here too late? */
|
||||
|
||||
/* 298 : FIXME: Fixed in B3/C1 */
|
||||
/* msr = rdmsr(0xC0010015);
|
||||
msr.lo |= 1 << 3;
|
||||
wrmsr(0xC0010015, msr);
|
||||
|
||||
msr = rdmsr(0xC0010023);
|
||||
msr.lo |= 1 << 1;
|
||||
wrmsr(0xC0010023, msr);
|
||||
*/
|
||||
}
|
||||
|
||||
static void smash1Gpages(void)
|
||||
{
|
||||
msr_t msr;
|
||||
|
||||
/* 1G pages are smashed and installed in the TLB as 2M pages.
|
||||
BIOS must set this bit for revision B. */
|
||||
/* FIXME: What about RevC? */
|
||||
|
||||
msr = rdmsr(0xC001102A);
|
||||
msr.lo |= 1 << 29;
|
||||
wrmsr(0xC001102A, msr);
|
||||
|
||||
}
|
||||
|
||||
extern void update_microcode(u32 cpu_deviceid);
|
||||
|
||||
|
||||
void model_10xxx_init(device_t dev)
|
||||
{
|
||||
unsigned long i;
|
||||
msr_t msr;
|
||||
struct node_core_id id;
|
||||
#if CONFIG_LOGICAL_CPUS == 1
|
||||
unsigned siblings;
|
||||
#endif
|
||||
|
||||
/* Turn on caching if we haven't already */
|
||||
x86_enable_cache();
|
||||
amd_setup_mtrrs();
|
||||
x86_mtrr_check();
|
||||
|
||||
|
||||
/* Update the microcode */
|
||||
update_microcode(dev->device);
|
||||
|
||||
disable_cache();
|
||||
|
||||
/* zero the machine check error status registers */
|
||||
msr.lo = 0;
|
||||
msr.hi = 0;
|
||||
for(i=0; i < 5; i++) {
|
||||
wrmsr(MCI_STATUS + (i * 4),msr);
|
||||
}
|
||||
|
||||
fam10_errata();
|
||||
|
||||
enable_cache();
|
||||
|
||||
/* Enable the local cpu apics */
|
||||
setup_lapic();
|
||||
|
||||
#if CONFIG_LOGICAL_CPUS == 1
|
||||
siblings = cpuid_ecx(0x80000008) & 0xff;
|
||||
|
||||
if (siblings > 0) {
|
||||
msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
|
||||
msr.lo |= 1 << 28;
|
||||
wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
|
||||
|
||||
msr = rdmsr_amd(LOGICAL_CPUS_NUM_MSR);
|
||||
msr.lo = (siblings+1)<<16;
|
||||
wrmsr_amd(LOGICAL_CPUS_NUM_MSR, msr);
|
||||
|
||||
msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
|
||||
msr.hi |= 1<<(33-32);
|
||||
wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
|
||||
}
|
||||
printk_debug("siblings = %02d, ", siblings);
|
||||
#endif
|
||||
|
||||
id = get_node_core_id(read_nb_cfg_54()); // pre e0 nb_cfg_54 can not be set
|
||||
|
||||
printk_debug("nodeid = %02d, coreid = %02d\n", id.nodeid, id.coreid);
|
||||
|
||||
init_pstates(dev, id.nodeid, id.coreid); // is it a good place? some cores are clearing their ram
|
||||
|
||||
/* Is this a bad location? In particular can another node prefecth
|
||||
* data from this node before we have initialized it?
|
||||
*/
|
||||
if (id.coreid == 0) init_ecc_memory(id.nodeid); // only do it for core 0
|
||||
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
/* Start up my cpu siblings */
|
||||
// if(id.coreid==0) amd_sibling_init(dev); // Don't need core1 is already be put in the CPU BUS in bus_cpu_scan
|
||||
#endif
|
||||
|
||||
smash1Gpages();
|
||||
}
|
||||
|
||||
static struct device_operations cpu_dev_ops = {
|
||||
.init = model_10xxx_init,
|
||||
};
|
||||
static struct cpu_device_id cpu_table[] = {
|
||||
//AMD_GH_SUPPORT
|
||||
{ X86_VENDOR_AMD, 0x100f00 }, /* SH-F0 L1 */
|
||||
{ X86_VENDOR_AMD, 0x100f10 }, /* M2 */
|
||||
{ X86_VENDOR_AMD, 0x100f20 }, /* S1g1 */
|
||||
{ X86_VENDOR_AMD, 0x100f21 },
|
||||
{ X86_VENDOR_AMD, 0x100f2A },
|
||||
{ X86_VENDOR_AMD, 0x100f22 },
|
||||
{ 0, 0 },
|
||||
};
|
||||
static struct cpu_driver model_10xxx __cpu_driver = {
|
||||
.ops = &cpu_dev_ops,
|
||||
.id_table = cpu_table,
|
||||
};
|
||||
456
src/cpu/amd/model_10xxx/pstate.c
Normal file
456
src/cpu/amd/model_10xxx/pstate.c
Normal file
@ -0,0 +1,456 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/amd/mtrr.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/x86/pae.h>
|
||||
#include <pc80/mc146818rtc.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
|
||||
#include "../../../northbridge/amd/amdfam10/amdfam10.h"
|
||||
|
||||
#include <cpu/amd/model_10xxx_rev.h>
|
||||
#include <cpu/cpu.h>
|
||||
#include <cpu/x86/cache.h>
|
||||
#include <cpu/x86/mtrr.h>
|
||||
#include <cpu/x86/mem.h>
|
||||
|
||||
#include <cpu/amd/quadcore.h>
|
||||
|
||||
#include <cpu/amd/model_10xxx_msr.h>
|
||||
#include <cpu/amd/amdfam10_sysconf.h>
|
||||
|
||||
extern device_t get_node_pci(u32 nodeid, u32 fn);
|
||||
|
||||
#include "fidvid_common.c"
|
||||
|
||||
#define PSTATES_DEBUG 0
|
||||
|
||||
|
||||
|
||||
static void inline dump_msr_pstates(u32 nodes)
|
||||
{
|
||||
#if PSTATES_DEBUG==1
|
||||
int i, j;
|
||||
for(j=0; j<5; j++) {
|
||||
printk_debug("P%d:", j);
|
||||
for(i=0;i<nodes;i++) {
|
||||
printk_debug(" [%08x %08x] ", sysconf.msr_pstate[i*5+j].hi, sysconf.msr_pstate[i*5+j].lo);
|
||||
}
|
||||
printk_debug("\n");
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
static void inline dump_p(const char *p_c, u32 nodes, u32 *p)
|
||||
{
|
||||
#if PSTATES_DEBUG==1
|
||||
int i, j;
|
||||
printk_debug(p_c);
|
||||
printk_debug("p:");
|
||||
for(i=0;i<nodes;i++) {
|
||||
printk_debug(" %d ", p[i]);
|
||||
}
|
||||
printk_debug("\n");
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
//according the pstate and make it work conformed to mixed conf system
|
||||
static u32 get_pwrvalue(u32 val)
|
||||
{
|
||||
u32 times;
|
||||
switch((val>>8)&3) {
|
||||
case 0: times = 1000; break;
|
||||
case 1: times = 100; break;
|
||||
case 2: times = 10; break;
|
||||
default:
|
||||
//error
|
||||
times = 1;
|
||||
}
|
||||
|
||||
return (val & 0xff) * times;
|
||||
|
||||
}
|
||||
|
||||
|
||||
static u32 get_powerstep(u32 val)
|
||||
{
|
||||
u32 time;
|
||||
if(val<4) {time = (4 - val)*100;}
|
||||
else if(val<8) { time = (9+4-val)*10;}
|
||||
else { time = (10+8-val) * 5; }
|
||||
|
||||
return time;
|
||||
|
||||
}
|
||||
|
||||
|
||||
static u32 get_plllocktime(u32 val)
|
||||
{
|
||||
u32 time;
|
||||
switch(val) {
|
||||
case 0:
|
||||
case 1:
|
||||
case 2:
|
||||
case 3:
|
||||
time = val+1; break;
|
||||
case 4: time = 8; break;
|
||||
case 5: time = 16; break;
|
||||
default:
|
||||
//erro2
|
||||
time = 1;
|
||||
}
|
||||
return time;
|
||||
}
|
||||
|
||||
|
||||
static void disable_pstate(u32 nodes, u32 *p)
|
||||
{
|
||||
int i;
|
||||
|
||||
for(i=0;i<nodes; i++) {
|
||||
sysconf.msr_pstate[i*5+p[i]].hi &= ~(1<<(63-32));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static void match_pstate(u32 nodes, u32 *p)
|
||||
{
|
||||
int i;
|
||||
u32 corecof_min, pwrvalue_max, pwrval_max;
|
||||
u32 enable;
|
||||
enable = (sysconf.msr_pstate[0*5+p[0]].hi >> 31);
|
||||
if(!enable) {
|
||||
disable_pstate(nodes, p);
|
||||
return;
|
||||
}
|
||||
corecof_min = ((sysconf.msr_pstate[0*5+p[0]].lo & 0x3f) + 0x10)>>((sysconf.msr_pstate[0*5+p[0]].lo>>6) & 7);
|
||||
pwrval_max = sysconf.msr_pstate[0*5+p[0]].hi & 0x3ff;
|
||||
pwrvalue_max = get_pwrvalue(pwrval_max);
|
||||
|
||||
for(i=1; i<nodes; i++) {
|
||||
enable = (sysconf.msr_pstate[0*5+p[i]].hi >> 31);
|
||||
if(!enable) {
|
||||
disable_pstate(nodes, p);
|
||||
return;
|
||||
}
|
||||
|
||||
u32 coredid = ((sysconf.msr_pstate[i*5+p[i]].lo>>6) & 7);
|
||||
u32 corecof = ((sysconf.msr_pstate[i*5+p[i]].lo & 0x3f) + 0x10)>>coredid;
|
||||
if(corecof<corecof_min) corecof_min = corecof;
|
||||
u32 pwrval, pwrvalue;
|
||||
pwrval = sysconf.msr_pstate[i*5+p[i]].hi & 0x3ff;
|
||||
pwrvalue = get_pwrvalue(pwrval);
|
||||
if(pwrvalue>pwrvalue_max) {
|
||||
pwrvalue_max = pwrvalue;
|
||||
pwrval_max = pwrval;
|
||||
}
|
||||
}
|
||||
|
||||
for(i=0; i<nodes; i++) {
|
||||
u32 coredid = ((sysconf.msr_pstate[i*5+p[i]].lo>>6) & 7);
|
||||
u32 corefid = (corecof_min<<coredid);
|
||||
while(corefid<0x10) {
|
||||
coredid++;
|
||||
corefid = (corecof_min<<coredid);
|
||||
}
|
||||
sysconf.msr_pstate[i*5+p[i]].lo &= ~(0x1ff);
|
||||
sysconf.msr_pstate[i*5+p[i]].lo |= (corefid - 0x10) | (coredid << 6);
|
||||
sysconf.msr_pstate[i*5+p[i]].hi &= ~(0x3ff);
|
||||
sysconf.msr_pstate[i*5+p[i]].hi |= pwrval_max;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static void match_pstates(u32 nodes, u32 *p, u32 *px)
|
||||
{
|
||||
int i;
|
||||
int j;
|
||||
u32 p_int[NODE_NUMS];
|
||||
|
||||
int jj=1;
|
||||
u32 end = 0;
|
||||
for(i=0;i<nodes; i++) {
|
||||
p_int[i] = px[i];
|
||||
}
|
||||
while(1){
|
||||
for(i=0;i<nodes; i++) {
|
||||
if(px[i]<=(p[i]+jj)) {
|
||||
end = 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if(!end) {
|
||||
for(i=0; i<nodes; i++) {
|
||||
p_int[i] = px[i] - jj;
|
||||
}
|
||||
match_pstate(nodes, p_int);
|
||||
dump_p("P int\n", nodes, p_int);
|
||||
jj++;
|
||||
}
|
||||
else {
|
||||
for(i=0;i<nodes; i++) {
|
||||
for(j=p[i]+1; j<p_int[i]; j++) {
|
||||
sysconf.msr_pstate[i*5+j].hi &= ~(1<<(63-32));
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void prep_pstates_all(void)
|
||||
{
|
||||
device_t f3_dev[NODE_NUMS], f4_dev[NODE_NUMS];
|
||||
u32 p[NODE_NUMS];
|
||||
u32 p_htc[NODE_NUMS];
|
||||
u32 p_lowest[NODE_NUMS];
|
||||
u32 htc_cap = 1;
|
||||
u32 lowest_htc_equal = 0;
|
||||
|
||||
u32 nodes = sysconf.nodes;
|
||||
int i;
|
||||
int j;
|
||||
u32 val;
|
||||
u32 nbdid;
|
||||
u32 nbvid0;
|
||||
u32 nbvid1;
|
||||
|
||||
for(i=0;i<nodes; i++) { // get the value from F4x1F0:E0 or we can get that msr in CAR stage...
|
||||
f3_dev[i] = get_node_pci(i, 3);
|
||||
f4_dev[i] = get_node_pci(i, 4);
|
||||
}
|
||||
|
||||
for(i=0;i<nodes; i++) { // get the value from F4x1F0:E0 or we can get that msr in CAR stage...
|
||||
val = pci_read_config32(f4_dev[i], 0x1f4);
|
||||
nbvid0 = val & 0x3f;
|
||||
nbvid1 = (val>>7) & 0x3f;
|
||||
for(j=0; j<5; j++) {
|
||||
val = pci_read_config32(f4_dev[i], 0x1e0 + (j<<2));
|
||||
nbdid = ((val>>16) & 1);
|
||||
sysconf.msr_pstate[i*5+j].lo = (val & 0xffff) | (nbdid<<22) | ((nbdid?nbvid1:nbvid0)<<25);
|
||||
sysconf.msr_pstate[i*5+j].hi = (((val>>17) & 0x3ff) << (32-32)) | (((val>>27) & 1)<<(63-32));
|
||||
}
|
||||
}
|
||||
|
||||
dump_msr_pstates(nodes);
|
||||
|
||||
sysconf.needs_update_pstate_msrs = 0; // normal case for all sockets are installed same conf CPU
|
||||
|
||||
for(i=1; (i<nodes) && (!sysconf.needs_update_pstate_msrs); i++) {
|
||||
for(j=0; j<5; j++) {
|
||||
if((sysconf.msr_pstate[i*5+j].lo != sysconf.msr_pstate[0*5+j].lo) || (sysconf.msr_pstate[i*5+j].hi != sysconf.msr_pstate[0*5+j].hi)) {
|
||||
sysconf.needs_update_pstate_msrs = 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if(sysconf.needs_update_pstate_msrs) {
|
||||
|
||||
// update msr_pstate for mixed conf
|
||||
|
||||
//P0
|
||||
/* Match P0 cpu cof for all cpu cores to the lowest P0 cpu cof value in the coherent fabric, and match P0 power for all cpu cores to the highest P0 power value */
|
||||
for(i=0;i<nodes; i++) p[i] = 0;
|
||||
match_pstate(nodes, p);
|
||||
dump_p("P0\n", nodes, p);
|
||||
dump_msr_pstates(nodes);
|
||||
|
||||
|
||||
//p_htc
|
||||
for(i=0;i<nodes; i++) {
|
||||
val = pci_read_config32(f3_dev[i], 0xe8); //htc cap
|
||||
if(!(val & (1<<10))) {
|
||||
htc_cap = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
//HtcPstateLimit
|
||||
val = pci_read_config32(f3_dev[i], 0x64);
|
||||
p_htc[i] = (((val>>28) & 7));
|
||||
if(p_htc[i] == 0) {
|
||||
val |= 1<<28;
|
||||
pci_write_config32(f3_dev[i], 0x64, val);
|
||||
val = pci_read_config32(f3_dev[i], 0x68); //stc
|
||||
val &= ~(7<<28);
|
||||
val |= (1<<28);
|
||||
pci_write_config32(f3_dev[i], 0x68, val);
|
||||
|
||||
p_htc[i] = 1;
|
||||
}
|
||||
}
|
||||
if(htc_cap) {
|
||||
match_pstate(nodes, p_htc);
|
||||
|
||||
dump_p("P_htc\n", nodes, p_htc);
|
||||
dump_msr_pstates(nodes);
|
||||
}
|
||||
|
||||
//p_lowest
|
||||
for(i=0;i<nodes; i++) {
|
||||
p_lowest[i] = 0;
|
||||
for(j=1; j<5; j++) {
|
||||
if(sysconf.msr_pstate[i*5+j].hi & (1<<(63-32))) {
|
||||
p_lowest[i] = j;
|
||||
}
|
||||
}
|
||||
// PstateMaxVal
|
||||
val = pci_read_config32(f3_dev[i], 0xdc);
|
||||
if(p_lowest[i]>((val>>8) & 7)) {
|
||||
val &= ~(7<<8);
|
||||
val |= (p_lowest[i])<<8;
|
||||
pci_write_config32(f3_dev[i], 0xdc, val);
|
||||
}
|
||||
else {
|
||||
p_lowest[i] = (val>>8) & 7;
|
||||
}
|
||||
}
|
||||
if(htc_cap) {
|
||||
for(i=0;i<nodes; i++) {
|
||||
if(p_lowest[i]==p_htc[i]){
|
||||
lowest_htc_equal = 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
if(lowest_htc_equal) {
|
||||
for(i=0;i<nodes; i++) {
|
||||
// PstateMaxVal
|
||||
val = pci_read_config32(f3_dev[i], 0xdc);
|
||||
val &= ~(7<<8);
|
||||
val |= p_htc[i];
|
||||
pci_write_config32(f3_dev[i], 0xdc, val);
|
||||
for(j=p_htc[i]+1; j<5; j++) {
|
||||
sysconf.msr_pstate[i*5+j].hi &= ~(1<<(63-32));
|
||||
}
|
||||
}
|
||||
} else {
|
||||
match_pstate(nodes, p_lowest);
|
||||
for(i=0; i<nodes; i++) {
|
||||
for(j=p_lowest[i]+1; j<5; j++) {
|
||||
sysconf.msr_pstate[i*5+j].hi &= ~(1<<(63-32));
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
dump_p("Px\n", nodes, p_lowest);
|
||||
dump_msr_pstates(nodes);
|
||||
|
||||
|
||||
if(htc_cap) {
|
||||
//p_up_int
|
||||
match_pstates(nodes, p, p_htc);
|
||||
|
||||
dump_msr_pstates(nodes);
|
||||
|
||||
//p_lower_int
|
||||
match_pstates(nodes, p_htc, p_lowest);
|
||||
} else {
|
||||
match_pstates(nodes, p, p_lowest);
|
||||
}
|
||||
|
||||
dump_msr_pstates(nodes);
|
||||
|
||||
}
|
||||
|
||||
// fill data into p_state
|
||||
for(i=0; i<nodes; i++) {
|
||||
sysconf.p_state_num = 0;
|
||||
u32 corefid_equal = 1;
|
||||
u32 corefid;
|
||||
corefid = (sysconf.msr_pstate[i*5+0].lo & 0x3f);
|
||||
for(j=1; j<5; j++) {
|
||||
msr_t *msr_pstate;
|
||||
msr_pstate = &(sysconf.msr_pstate[i*5+j]);
|
||||
if(!(msr_pstate->hi & (1<<(63-32)) )) continue;
|
||||
if((msr_pstate->lo & 0x3f) != corefid) {
|
||||
corefid_equal = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
for(j=0; j<5; j++) {
|
||||
struct p_state_t *p_state;
|
||||
msr_t *msr_pstate;
|
||||
msr_pstate = &sysconf.msr_pstate[i*5+j];
|
||||
if(!(msr_pstate->hi & (1<<(63-32)) )) continue;
|
||||
p_state = &sysconf.p_state[i*5+sysconf.p_state_num];
|
||||
u32 coredid = ((msr_pstate->lo>>6) & 7);
|
||||
u32 corecof = ((msr_pstate->lo & 0x3f) + 0x10)>>coredid;
|
||||
p_state->corefreq = corecof;
|
||||
|
||||
u32 pwrval, pwrvalue;
|
||||
pwrval = msr_pstate->hi & 0x3ff;
|
||||
pwrvalue = get_pwrvalue(pwrval);
|
||||
p_state->power = pwrvalue;
|
||||
|
||||
u32 lat;
|
||||
val = pci_read_config32(f3_dev[i], 0xd4);
|
||||
lat = 15 * (get_powerstep((val>>24)& 0xf)+get_powerstep((val>>20)& 0xf)) /1000;
|
||||
if(!corefid_equal) {
|
||||
val = pci_read_config32(f3_dev[i], 0xa0);
|
||||
lat += get_plllocktime((val >> 11 ) & 7);
|
||||
}
|
||||
p_state->transition_lat = lat;
|
||||
p_state->busmaster_lat = lat;
|
||||
|
||||
p_state->control = j;
|
||||
p_state->status = j;
|
||||
|
||||
sysconf.p_state_num++;
|
||||
}
|
||||
// don't need look at other nodes
|
||||
if(!sysconf.p_state_num) break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
//it will update pstates info from ram into MSR
|
||||
void init_pstates(device_t dev, u32 nodeid, u32 coreid)
|
||||
{
|
||||
int j;
|
||||
msr_t msr;
|
||||
|
||||
if(sysconf.needs_update_pstate_msrs) {
|
||||
for(j=0; j < 5; j++) {
|
||||
wrmsr(0xC0010064 + j, sysconf.msr_pstate[nodeid * 5 + j]);
|
||||
}
|
||||
}
|
||||
|
||||
/* Set TSC Freq Select: TSC increments at the rate of the core P-state 0 */
|
||||
msr = rdmsr(0xC0010015);
|
||||
msr.lo |= 1 << 24;
|
||||
wrmsr(0xC0010015, msr);
|
||||
|
||||
// Enter the state P0
|
||||
//FIXME I don't think that this works correctly. May depend on early fid/vid setup.
|
||||
if(sysconf.p_state_num)
|
||||
set_core_nb_max_pstate_after_other_warm_reset(nodeid, coreid);
|
||||
|
||||
}
|
||||
90
src/cpu/amd/model_10xxx/update_microcode.c
Normal file
90
src/cpu/amd/model_10xxx/update_microcode.c
Normal file
@ -0,0 +1,90 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
|
||||
#ifndef __ROMCC__
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
|
||||
#include <cpu/amd/microcode.h>
|
||||
#endif
|
||||
|
||||
static const u8 microcode_updates[] __attribute__ ((aligned(16))) = {
|
||||
|
||||
#ifdef __ROMCC__
|
||||
|
||||
// Barcelona revAx
|
||||
// #include "mc_patch_01000020.h"
|
||||
|
||||
// Barcelona revBx
|
||||
#include "mc_patch_01000033.h"
|
||||
|
||||
// Barcelona rev Cx??
|
||||
// #include "mc_patch_01000035.h"
|
||||
|
||||
#endif
|
||||
/* Dummy terminator */
|
||||
0x0, 0x0, 0x0, 0x0,
|
||||
0x0, 0x0, 0x0, 0x0,
|
||||
0x0, 0x0, 0x0, 0x0,
|
||||
0x0, 0x0, 0x0, 0x0,
|
||||
};
|
||||
|
||||
static u32 get_equivalent_processor_rev_id(u32 orig_id) {
|
||||
static unsigned id_mapping_table[] = {
|
||||
0x100f00, 0x1000,
|
||||
0x100f01, 0x1000,
|
||||
0x100f02, 0x1000,
|
||||
0x100f20, 0x1020,
|
||||
0x100f21, 0x1020,
|
||||
0x100f2A, 0x1020,
|
||||
0x100f22, 0x1022,
|
||||
};
|
||||
|
||||
u32 new_id;
|
||||
int i;
|
||||
|
||||
new_id = 0;
|
||||
|
||||
for (i = 0; i < sizeof(id_mapping_table); i += 2 ) {
|
||||
if(id_mapping_table[i]==orig_id) {
|
||||
new_id = id_mapping_table[i + 1];
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return new_id;
|
||||
|
||||
}
|
||||
|
||||
void update_microcode(u32 cpu_deviceid)
|
||||
{
|
||||
u32 equivalent_processor_rev_id;
|
||||
|
||||
/* Update the microcode */
|
||||
equivalent_processor_rev_id = get_equivalent_processor_rev_id(cpu_deviceid );
|
||||
if (equivalent_processor_rev_id != 0) {
|
||||
amd_update_microcode((void *) microcode_updates, equivalent_processor_rev_id);
|
||||
} else {
|
||||
printk_debug("microcode: rev id not found. Skipping microcode patch!\n");
|
||||
}
|
||||
|
||||
}
|
||||
20
src/cpu/amd/quadcore/Config.lb
Normal file
20
src/cpu/amd/quadcore/Config.lb
Normal file
@ -0,0 +1,20 @@
|
||||
#
|
||||
# This file is part of the LinuxBIOS project.
|
||||
#
|
||||
# Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; version 2 of the License.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
#
|
||||
|
||||
object amd_sibling.o
|
||||
122
src/cpu/amd/quadcore/amd_sibling.c
Normal file
122
src/cpu/amd/quadcore/amd_sibling.c
Normal file
@ -0,0 +1,122 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
|
||||
#include <console/console.h>
|
||||
#include <cpu/cpu.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <pc80/mc146818rtc.h>
|
||||
#include <smp/spinlock.h>
|
||||
#include <cpu/x86/mtrr.h>
|
||||
#include <cpu/amd/model_10xxx_msr.h>
|
||||
#include <cpu/amd/model_10xxx_rev.h>
|
||||
#include <cpu/amd/amdfam10_sysconf.h>
|
||||
|
||||
extern device_t get_node_pci(u32 nodeid, u32 fn);
|
||||
|
||||
#if 0
|
||||
static int first_time = 1;
|
||||
#endif
|
||||
|
||||
#include "quadcore_id.c"
|
||||
|
||||
static u32 get_max_siblings(u32 nodes)
|
||||
{
|
||||
device_t dev;
|
||||
u32 nodeid;
|
||||
u32 siblings=0;
|
||||
|
||||
//get max siblings from all the nodes
|
||||
for(nodeid=0; nodeid<nodes; nodeid++){
|
||||
int j;
|
||||
dev = get_node_pci(nodeid, 3);
|
||||
j = (pci_read_config32(dev, 0xe8) >> 12) & 3;
|
||||
if(siblings < j) {
|
||||
siblings = j;
|
||||
}
|
||||
}
|
||||
|
||||
return siblings;
|
||||
}
|
||||
|
||||
|
||||
static void enable_apic_ext_id(u32 nodes)
|
||||
{
|
||||
device_t dev;
|
||||
u32 nodeid;
|
||||
|
||||
//enable APIC_EXIT_ID all the nodes
|
||||
for(nodeid=0; nodeid<nodes; nodeid++){
|
||||
u32 val;
|
||||
dev = get_node_pci(nodeid, 0);
|
||||
val = pci_read_config32(dev, 0x68);
|
||||
val |= (1<<17)|(1<<18);
|
||||
pci_write_config32(dev, 0x68, val);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
u32 get_apicid_base(u32 ioapic_num)
|
||||
{
|
||||
u32 apicid_base;
|
||||
u32 siblings;
|
||||
u32 nb_cfg_54;
|
||||
|
||||
u32 disable_siblings = !CONFIG_LOGICAL_CPUS;
|
||||
|
||||
get_option(&disable_siblings, "quad_core");
|
||||
|
||||
siblings = get_max_siblings(sysconf.nodes);
|
||||
|
||||
if(sysconf.bsp_apicid > 0) { // io apic could start from 0
|
||||
return 0;
|
||||
} else if (sysconf.enabled_apic_ext_id) { // enabled ext id but bsp = 0
|
||||
return 1;
|
||||
}
|
||||
|
||||
nb_cfg_54 = read_nb_cfg_54();
|
||||
|
||||
|
||||
//contruct apicid_base
|
||||
|
||||
if((!disable_siblings) && (siblings>0) ) {
|
||||
/* for 8 way dual core, we will used up apicid 16:16, actualy
|
||||
16 is not allowed by current kernel and the kernel will try
|
||||
to get one that is small than 16 to make io apic work. I don't
|
||||
know when the kernel can support 256 apic id.
|
||||
(APIC_EXT_ID is enabled) */
|
||||
|
||||
//4:10 for two way 8:12 for four way 16:16 for eight way
|
||||
//Use CONFIG_MAX_PHYSICAL_CPUS instead of nodes for better consistency?
|
||||
apicid_base = nb_cfg_54 ? (siblings+1) * sysconf.nodes : 8 * siblings + sysconf.nodes;
|
||||
|
||||
} else {
|
||||
apicid_base = sysconf.nodes;
|
||||
}
|
||||
|
||||
if((apicid_base+ioapic_num-1)>0xf) {
|
||||
// We need to enable APIC EXT ID
|
||||
printk_spew("if the IO APIC device doesn't support 256 apic id, \r\n you need to set ENABLE_APIC_EXT_ID in MB Option.lb so you can spare 16 id for ioapic\r\n");
|
||||
enable_apic_ext_id(sysconf.nodes);
|
||||
}
|
||||
|
||||
return apicid_base;
|
||||
}
|
||||
102
src/cpu/amd/quadcore/quadcore.c
Normal file
102
src/cpu/amd/quadcore/quadcore.c
Normal file
@ -0,0 +1,102 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
|
||||
#ifndef SET_NB_CFG_54
|
||||
#define SET_NB_CFG_54 1
|
||||
#endif
|
||||
|
||||
#include "cpu/amd/quadcore/quadcore_id.c"
|
||||
|
||||
static inline u32 get_core_num_in_bsp(u32 nodeid)
|
||||
{
|
||||
u32 dword;
|
||||
dword = pci_read_config32(NODE_PCI(nodeid, 3), 0xe8);
|
||||
dword >>= 12;
|
||||
dword &= 3;
|
||||
return dword;
|
||||
}
|
||||
|
||||
#if SET_NB_CFG_54 == 1
|
||||
static inline u8 set_apicid_cpuid_lo(void)
|
||||
{
|
||||
// set the NB_CFG[54]=1; why the OS will be happy with that ???
|
||||
msr_t msr;
|
||||
msr = rdmsr(NB_CFG_MSR);
|
||||
msr.hi |= (1<<(54-32)); // InitApicIdCpuIdLo
|
||||
wrmsr(NB_CFG_MSR, msr);
|
||||
|
||||
return 1;
|
||||
}
|
||||
#else
|
||||
|
||||
static inline void set_apicid_cpuid_lo(void) { }
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
static inline void real_start_other_core(u32 nodeid, u32 cores)
|
||||
{
|
||||
u32 dword;
|
||||
|
||||
printk_debug("Start other core - nodeid: %02x cores: %02x\n", nodeid, cores);
|
||||
|
||||
/* set PCI_DEV(0, 0x18+nodeid, 3), 0x44 bit 27 to redirect all MC4
|
||||
accesses and error logging to core0 */
|
||||
dword = pci_read_config32(NODE_PCI(nodeid, 3), 0x44);
|
||||
dword |= 1 << 27; // NbMcaToMstCpuEn bit
|
||||
pci_write_config32(NODE_PCI(nodeid, 3), 0x44, dword);
|
||||
// set PCI_DEV(0, 0x18+nodeid, 0), 0x68 bit 5 to start core1
|
||||
dword = pci_read_config32(NODE_PCI(nodeid, 0), 0x68);
|
||||
dword |= 1 << 5;
|
||||
pci_write_config32(NODE_PCI(nodeid, 0), 0x68, dword);
|
||||
|
||||
if(cores > 1) {
|
||||
dword = pci_read_config32(NODE_PCI(nodeid, 0), 0x168);
|
||||
dword |= (1 << 0); // core2
|
||||
if(cores > 2) { // core3
|
||||
dword |= (1 << 1);
|
||||
}
|
||||
pci_write_config32(NODE_PCI(nodeid, 0), 0x168, dword);
|
||||
}
|
||||
}
|
||||
|
||||
//it is running on core0 of node0
|
||||
static inline void start_other_cores(void)
|
||||
{
|
||||
u32 nodes;
|
||||
u32 nodeid;
|
||||
|
||||
// disable quad_core
|
||||
if (read_option(CMOS_VSTART_quad_core, CMOS_VLEN_quad_core, 0) != 0) {
|
||||
printk_debug("Skip additional core init\n");
|
||||
return;
|
||||
}
|
||||
|
||||
nodes = get_nodes();
|
||||
|
||||
for (nodeid = 0; nodeid < nodes; nodeid++) {
|
||||
u32 cores = get_core_num_in_bsp(nodeid);
|
||||
printk_debug("init node: %02x cores: %02x \n", nodeid, cores);
|
||||
if (cores > 0) {
|
||||
real_start_other_core(nodeid, cores);
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
79
src/cpu/amd/quadcore/quadcore_id.c
Normal file
79
src/cpu/amd/quadcore/quadcore_id.c
Normal file
@ -0,0 +1,79 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
|
||||
#include <arch/cpu.h>
|
||||
#include <cpu/amd/quadcore.h>
|
||||
#ifdef __ROMCC__
|
||||
#include <cpu/amd/model_10xxx_msr.h>
|
||||
#endif
|
||||
|
||||
//called by bus_cpu_scan too
|
||||
u32 read_nb_cfg_54(void)
|
||||
{
|
||||
msr_t msr;
|
||||
msr = rdmsr(NB_CFG_MSR);
|
||||
return ( ( msr.hi >> (54-32)) & 1);
|
||||
}
|
||||
|
||||
static inline u32 get_initial_apicid(void)
|
||||
{
|
||||
return ((cpuid_ebx(1) >> 24) & 0xff);
|
||||
}
|
||||
|
||||
//called by amd_siblings too
|
||||
#define CORE_ID_BIT 2
|
||||
#define NODE_ID_BIT 6
|
||||
struct node_core_id get_node_core_id(u32 nb_cfg_54)
|
||||
{
|
||||
struct node_core_id id;
|
||||
u32 core_id_bits;
|
||||
|
||||
u32 ApicIdCoreIdSize = (cpuid_ecx(0x80000008)>>12 & 0xf);
|
||||
if(ApicIdCoreIdSize) {
|
||||
core_id_bits = ApicIdCoreIdSize;
|
||||
} else {
|
||||
core_id_bits = CORE_ID_BIT; //quad core
|
||||
}
|
||||
|
||||
// get the apicid via cpuid(1) ebx[31:24]
|
||||
if( nb_cfg_54) {
|
||||
// when NB_CFG[54] is set, nodeid = ebx[31:26], coreid = ebx[25:24]
|
||||
id.coreid = (cpuid_ebx(1) >> 24) & 0xff;
|
||||
id.nodeid = (id.coreid>>core_id_bits);
|
||||
id.coreid &= ((1<<core_id_bits)-1);
|
||||
} else {
|
||||
// when NB_CFG[54] is clear, nodeid = ebx[29:24], coreid = ebx[31:30]
|
||||
id.nodeid = (cpuid_ebx(1) >> 24) & 0xff;
|
||||
id.coreid = (id.nodeid>>NODE_ID_BIT);
|
||||
id.nodeid &= ((1<<NODE_ID_BIT)-1);
|
||||
}
|
||||
return id;
|
||||
}
|
||||
|
||||
static inline u32 get_core_num(void)
|
||||
{
|
||||
return (cpuid_ecx(0x80000008) & 0xff);
|
||||
}
|
||||
|
||||
static inline struct node_core_id get_node_core_id_x(void) {
|
||||
|
||||
return get_node_core_id( read_nb_cfg_54() );
|
||||
}
|
||||
|
||||
57
src/cpu/amd/socket_F_1207/Config.lb
Normal file
57
src/cpu/amd/socket_F_1207/Config.lb
Normal file
@ -0,0 +1,57 @@
|
||||
#
|
||||
# This file is part of the LinuxBIOS project.
|
||||
#
|
||||
# Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; version 2 of the License.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
#
|
||||
|
||||
uses CONFIG_CHIP_NAME
|
||||
uses PCI_IO_CFG_EXT
|
||||
uses MMCONF_SUPPORT
|
||||
uses HT3_SUPPORT
|
||||
uses EXT_RT_TBL_SUPPORT
|
||||
uses EXT_CONF_SUPPORT
|
||||
uses DIMM_SUPPORT
|
||||
uses CPU_SOCKET_TYPE
|
||||
uses CBB
|
||||
uses CDB
|
||||
uses PCI_BUS_SEGN_BITS
|
||||
uses CAR_FAM10
|
||||
|
||||
if CONFIG_CHIP_NAME
|
||||
config chip.h
|
||||
end
|
||||
|
||||
default PCI_IO_CFG_EXT=1
|
||||
|
||||
default HT3_SUPPORT=1
|
||||
default EXT_RT_TBL_SUPPORT=0
|
||||
default EXT_CONF_SUPPORT=0
|
||||
default DIMM_SUPPORT=0x0104 #DDR2 and REG
|
||||
default CPU_SOCKET_TYPE=0x10
|
||||
|
||||
default CAR_FAM10=1
|
||||
|
||||
if EXT_RT_TBL_SUPPORT
|
||||
default CBB=0xff
|
||||
default CDB=0
|
||||
end
|
||||
|
||||
#default MMCONF_SUPPORT=1
|
||||
#default MMCONF_SUPPORT_DEFAULT=1
|
||||
|
||||
object socket_F_1207.o
|
||||
|
||||
dir /cpu/amd/model_10xxx
|
||||
23
src/cpu/amd/socket_F_1207/chip.h
Normal file
23
src/cpu/amd/socket_F_1207/chip.h
Normal file
@ -0,0 +1,23 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
extern struct chip_operations cpu_amd_socket_F_1207_ops;
|
||||
|
||||
struct cpu_amd_socket_F_1207_config {
|
||||
};
|
||||
25
src/cpu/amd/socket_F_1207/socket_F_1207.c
Normal file
25
src/cpu/amd/socket_F_1207/socket_F_1207.c
Normal file
@ -0,0 +1,25 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <device/device.h>
|
||||
#include "chip.h"
|
||||
|
||||
struct chip_operations cpu_amd_socket_F_1207_ops = {
|
||||
CHIP_NAME("socket F_1207")
|
||||
};
|
||||
73
src/include/cpu/amd/amdfam10_sysconf.h
Normal file
73
src/include/cpu/amd/amdfam10_sysconf.h
Normal file
@ -0,0 +1,73 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef AMDFAM10_SYSCONF_H
|
||||
#define AMDFAM10_SYSCONF_H
|
||||
|
||||
#include "../../../northbridge/amd/amdfam10/amdfam10_nums.h"
|
||||
|
||||
#include <cpu/x86/msr.h>
|
||||
|
||||
struct p_state_t {
|
||||
unsigned corefreq;
|
||||
unsigned power;
|
||||
unsigned transition_lat;
|
||||
unsigned busmaster_lat;
|
||||
unsigned control;
|
||||
unsigned status;
|
||||
};
|
||||
|
||||
struct amdfam10_sysconf_t {
|
||||
//ht
|
||||
unsigned hc_possible_num;
|
||||
unsigned pci1234[HC_POSSIBLE_NUM];
|
||||
unsigned hcdn[HC_POSSIBLE_NUM];
|
||||
unsigned hcid[HC_POSSIBLE_NUM]; //record ht chain type
|
||||
unsigned sbdn;
|
||||
unsigned sblk;
|
||||
|
||||
unsigned nodes;
|
||||
unsigned ht_c_num; // we only can have 32 ht chain at most
|
||||
unsigned ht_c_conf_bus[HC_NUMS]; // 4-->32: 4:segn, 8:bus_max, 8:bus_min, 4:linkn, 6: nodeid, 2: enable
|
||||
unsigned io_addr_num;
|
||||
unsigned conf_io_addr[HC_NUMS];
|
||||
unsigned conf_io_addrx[HC_NUMS];
|
||||
unsigned mmio_addr_num;
|
||||
unsigned conf_mmio_addr[HC_NUMS*2]; // mem and pref mem
|
||||
unsigned conf_mmio_addrx[HC_NUMS*2];
|
||||
unsigned segbit;
|
||||
unsigned hcdn_reg[HC_NUMS]; // it will be used by get_pci1234
|
||||
|
||||
msr_t msr_pstate[NODE_NUMS * 5]; // quad cores all cores in one node should be the same, and p0,..p5
|
||||
unsigned needs_update_pstate_msrs;
|
||||
struct p_state_t p_state[NODE_NUMS * 5];
|
||||
unsigned p_state_num;
|
||||
|
||||
unsigned bsp_apicid;
|
||||
int enabled_apic_ext_id;
|
||||
unsigned lift_bsp_apicid;
|
||||
int apicid_offset;
|
||||
|
||||
void *mb; // pointer for mb releated struct
|
||||
|
||||
};
|
||||
|
||||
extern struct amdfam10_sysconf_t sysconf;
|
||||
|
||||
#endif
|
||||
35
src/include/cpu/amd/model_10xxx_msr.h
Normal file
35
src/include/cpu/amd/model_10xxx_msr.h
Normal file
@ -0,0 +1,35 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef CPU_AMD_MODEL_10XXX_MSR_H
|
||||
#define CPU_AMD_MODEL_10XXX_MSR_H
|
||||
|
||||
#define HWCR_MSR 0xC0010015
|
||||
#define NB_CFG_MSR 0xC001001f
|
||||
#define LS_CFG_MSR 0xC0011020
|
||||
#define IC_CFG_MSR 0xC0011021
|
||||
#define DC_CFG_MSR 0xC0011022
|
||||
#define BU_CFG_MSR 0xC0011023
|
||||
|
||||
#define CPU_ID_FEATURES_MSR 0xC0011004
|
||||
#define CPU_ID_HYPER_EXT_FEATURES 0xC001100d
|
||||
#define LOGICAL_CPUS_NUM_MSR 0xC001100d
|
||||
#define CPU_ID_EXT_FEATURES_MSR 0xC0011005
|
||||
|
||||
#endif /* CPU_AMD_MODEL_10XXX_MSR_H */
|
||||
22
src/include/cpu/amd/model_10xxx_rev.h
Normal file
22
src/include/cpu/amd/model_10xxx_rev.h
Normal file
@ -0,0 +1,22 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <arch/cpu.h>
|
||||
|
||||
/* place holder for Family 10 revision code */
|
||||
43
src/include/cpu/amd/quadcore.h
Normal file
43
src/include/cpu/amd/quadcore.h
Normal file
@ -0,0 +1,43 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef CPU_AMD_QUADCORE_H
|
||||
#define CPU_AMD_QUADCORE_H
|
||||
|
||||
#if defined(__GNUC__)
|
||||
unsigned int read_nb_cfg_54(void);
|
||||
#endif
|
||||
|
||||
struct node_core_id {
|
||||
u32 nodeid;
|
||||
u32 coreid;
|
||||
};
|
||||
|
||||
#if defined(__GNUC__)
|
||||
// it can be used to get unitid and coreid it running only
|
||||
struct node_core_id get_node_core_id(u32 nb_cfg_54);
|
||||
#endif
|
||||
|
||||
#ifndef __ROMCC__
|
||||
struct device;
|
||||
u32 get_apicid_base(u32 ioapic_num);
|
||||
void amd_sibling_init(struct device *cpu);
|
||||
#endif
|
||||
|
||||
#endif /* CPU_AMD_QUADCORE_H */
|
||||
79
src/northbridge/amd/amdfam10/Config.lb
Normal file
79
src/northbridge/amd/amdfam10/Config.lb
Normal file
@ -0,0 +1,79 @@
|
||||
#
|
||||
# This file is part of the LinuxBIOS project.
|
||||
#
|
||||
# Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; version 2 of the License.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
#
|
||||
|
||||
uses CONFIG_CHIP_NAME
|
||||
uses AGP_APERTURE_SIZE
|
||||
uses HAVE_ACPI_TABLES
|
||||
|
||||
default AGP_APERTURE_SIZE=0x4000000
|
||||
|
||||
if CONFIG_CHIP_NAME
|
||||
config chip.h
|
||||
end
|
||||
|
||||
object northbridge.o
|
||||
driver misc_control.o
|
||||
|
||||
if HAVE_ACPI_TABLES
|
||||
object amdfam10_acpi.o
|
||||
makerule ssdt.c
|
||||
depends "$(TOP)/src/northbridge/amd/amdfam10/ssdt.dsl"
|
||||
action "iasl -tc $(TOP)/src/northbridge/amd/amdfam10/ssdt.dsl"
|
||||
action "perl -pi -e 's/AmlCode/AmlCode_ssdt/g' ssdt.hex"
|
||||
action "mv ssdt.hex ssdt.c"
|
||||
end
|
||||
object ./ssdt.o
|
||||
makerule sspr1.c
|
||||
depends "$(TOP)/src/northbridge/amd/amdfam10/sspr1.dsl"
|
||||
action "iasl -tc $(TOP)/src/northbridge/amd/amdfam10/sspr1.dsl"
|
||||
action "perl -pi -e 's/AmlCode/AmlCode_sspr1/g' sspr1.hex"
|
||||
action "mv sspr1.hex sspr1.c"
|
||||
end
|
||||
object ./sspr1.o
|
||||
makerule sspr2.c
|
||||
depends "$(TOP)/src/northbridge/amd/amdfam10/sspr2.dsl"
|
||||
action "iasl -tc $(TOP)/src/northbridge/amd/amdfam10/sspr2.dsl"
|
||||
action "perl -pi -e 's/AmlCode/AmlCode_sspr2/g' sspr2.hex"
|
||||
action "mv sspr2.hex sspr2.c"
|
||||
end
|
||||
object ./sspr2.o
|
||||
makerule sspr3.c
|
||||
depends "$(TOP)/src/northbridge/amd/amdfam10/sspr3.dsl"
|
||||
action "iasl -tc $(TOP)/src/northbridge/amd/amdfam10/sspr3.dsl"
|
||||
action "perl -pi -e 's/AmlCode/AmlCode_sspr3/g' sspr3.hex"
|
||||
action "mv sspr3.hex sspr3.c"
|
||||
end
|
||||
object ./sspr3.o
|
||||
makerule sspr4.c
|
||||
depends "$(TOP)/src/northbridge/amd/amdfam10/sspr4.dsl"
|
||||
action "iasl -tc $(TOP)/src/northbridge/amd/amdfam10/sspr4.dsl"
|
||||
action "perl -pi -e 's/AmlCode/AmlCode_sspr4/g' sspr4.hex"
|
||||
action "mv sspr4.hex sspr4.c"
|
||||
end
|
||||
object ./sspr4.o
|
||||
makerule sspr5.c
|
||||
depends "$(TOP)/src/northbridge/amd/amdfam10/sspr5.dsl"
|
||||
action "iasl -tc $(TOP)/src/northbridge/amd/amdfam10/sspr5.dsl"
|
||||
action "perl -pi -e 's/AmlCode/AmlCode_sspr5/g' sspr5.hex"
|
||||
action "mv sspr5.hex sspr5.c"
|
||||
end
|
||||
object ./sspr5.o
|
||||
end
|
||||
|
||||
object get_pci1234.o
|
||||
1164
src/northbridge/amd/amdfam10/amdfam10.h
Normal file
1164
src/northbridge/amd/amdfam10/amdfam10.h
Normal file
File diff suppressed because it is too large
Load Diff
382
src/northbridge/amd/amdfam10/amdfam10_acpi.c
Normal file
382
src/northbridge/amd/amdfam10/amdfam10_acpi.c
Normal file
@ -0,0 +1,382 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <string.h>
|
||||
#include <arch/acpi.h>
|
||||
#include <device/pci.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/amd/mtrr.h>
|
||||
#include <cpu/amd/amdfam10_sysconf.h>
|
||||
#include "amdfam10.h"
|
||||
|
||||
//it seems some functions can be moved arch/i386/boot/acpi.c
|
||||
|
||||
unsigned long acpi_create_madt_lapics(unsigned long current)
|
||||
{
|
||||
device_t cpu;
|
||||
int cpu_index = 0;
|
||||
|
||||
for(cpu = all_devices; cpu; cpu = cpu->next) {
|
||||
if ((cpu->path.type != DEVICE_PATH_APIC) ||
|
||||
(cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) {
|
||||
continue;
|
||||
}
|
||||
if (!cpu->enabled) {
|
||||
continue;
|
||||
}
|
||||
current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, cpu_index, cpu->path.u.apic.apic_id);
|
||||
cpu_index++;
|
||||
}
|
||||
return current;
|
||||
}
|
||||
|
||||
unsigned long acpi_create_madt_lapic_nmis(unsigned long current, u16 flags, u8 lint)
|
||||
{
|
||||
device_t cpu;
|
||||
int cpu_index = 0;
|
||||
|
||||
for(cpu = all_devices; cpu; cpu = cpu->next) {
|
||||
if ((cpu->path.type != DEVICE_PATH_APIC) ||
|
||||
(cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) {
|
||||
continue;
|
||||
}
|
||||
if (!cpu->enabled) {
|
||||
continue;
|
||||
}
|
||||
current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, cpu_index, flags, lint);
|
||||
cpu_index++;
|
||||
}
|
||||
return current;
|
||||
}
|
||||
|
||||
|
||||
unsigned long acpi_create_srat_lapics(unsigned long current)
|
||||
{
|
||||
device_t cpu;
|
||||
int cpu_index = 0;
|
||||
|
||||
for(cpu = all_devices; cpu; cpu = cpu->next) {
|
||||
if ((cpu->path.type != DEVICE_PATH_APIC) ||
|
||||
(cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) {
|
||||
continue;
|
||||
}
|
||||
if (!cpu->enabled) {
|
||||
continue;
|
||||
}
|
||||
printk_debug("SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", cpu_index, cpu->path.u.apic.node_id, cpu->path.u.apic.apic_id);
|
||||
current += acpi_create_srat_lapic((acpi_srat_lapic_t *)current, cpu->path.u.apic.node_id, cpu->path.u.apic.apic_id);
|
||||
cpu_index++;
|
||||
}
|
||||
return current;
|
||||
}
|
||||
|
||||
static unsigned long resk(uint64_t value)
|
||||
{
|
||||
unsigned long resultk;
|
||||
if (value < (1ULL << 42)) {
|
||||
resultk = value >> 10;
|
||||
} else {
|
||||
resultk = 0xffffffff;
|
||||
}
|
||||
return resultk;
|
||||
}
|
||||
|
||||
|
||||
struct acpi_srat_mem_state {
|
||||
unsigned long current;
|
||||
};
|
||||
|
||||
void set_srat_mem(void *gp, struct device *dev, struct resource *res)
|
||||
{
|
||||
struct acpi_srat_mem_state *state = gp;
|
||||
unsigned long basek, sizek;
|
||||
basek = resk(res->base);
|
||||
sizek = resk(res->size);
|
||||
|
||||
printk_debug("set_srat_mem: dev %s, res->index=%04x startk=%08x, sizek=%08x\n",
|
||||
dev_path(dev), res->index, basek, sizek);
|
||||
/*
|
||||
0-640K must be on node 0
|
||||
next range is from 1M---
|
||||
So will cut off before 1M in the mem range
|
||||
*/
|
||||
if((basek+sizek)<1024) return;
|
||||
|
||||
if(basek<1024) {
|
||||
sizek -= 1024 - basek;
|
||||
basek = 1024;
|
||||
}
|
||||
|
||||
// need to figure out NV
|
||||
state->current += acpi_create_srat_mem((acpi_srat_mem_t *)state->current, (res->index & 0xf), basek, sizek, 1);
|
||||
}
|
||||
|
||||
|
||||
unsigned long acpi_fill_srat(unsigned long current)
|
||||
{
|
||||
struct acpi_srat_mem_state srat_mem_state;
|
||||
|
||||
/* create all subtables for processors */
|
||||
current = acpi_create_srat_lapics(current);
|
||||
|
||||
/* create all subteble for memory range */
|
||||
|
||||
/* 0-640K must be on node 0 */
|
||||
current += acpi_create_srat_mem((acpi_srat_mem_t *)current, 0, 0, 640, 1);//enable
|
||||
|
||||
srat_mem_state.current = current;
|
||||
search_global_resources(
|
||||
IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
|
||||
set_srat_mem, &srat_mem_state);
|
||||
|
||||
current = srat_mem_state.current;
|
||||
return current;
|
||||
}
|
||||
|
||||
unsigned long acpi_fill_slit(unsigned long current)
|
||||
{
|
||||
/* need to find out the node num at first */
|
||||
/* fill the first 8 byte with that num */
|
||||
/* fill the next num*num byte with distance, local is 10, 1 hop mean 20, and 2 hop with 30.... */
|
||||
|
||||
struct sys_info *sysinfox = (struct sys_info *)((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE);
|
||||
u8 *ln = sysinfox->ln;
|
||||
|
||||
|
||||
u8 *p = (u8 *)current;
|
||||
int nodes = sysconf.nodes;
|
||||
int i,j;
|
||||
u32 hops;
|
||||
|
||||
memset(p, 0, 8+nodes*nodes);
|
||||
*p = (u8) nodes;
|
||||
p += 8;
|
||||
|
||||
for(i=0;i<nodes;i++) {
|
||||
for(j=0;j<nodes; j++) {
|
||||
if(i==j) {
|
||||
p[i*nodes+j] = 10;
|
||||
} else {
|
||||
hops = (((ln[i*NODE_NUMS+j]>>4) & 0x7)+1);
|
||||
p[i*nodes+j] = hops * 2 + 10;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
current += 8+nodes*nodes;
|
||||
return current;
|
||||
}
|
||||
|
||||
|
||||
// moved from mb acpi_tables.c
|
||||
static void intx_to_stream(u32 val, u32 len, u8 *dest)
|
||||
{
|
||||
int i;
|
||||
for(i=0;i<len;i++) {
|
||||
*(dest+i) = (val >> (8*i)) & 0xff;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static void int_to_stream(u32 val, u8 *dest)
|
||||
{
|
||||
return intx_to_stream(val, 4, dest);
|
||||
}
|
||||
|
||||
|
||||
// used by acpi_tables.h
|
||||
void update_ssdt(void *ssdt)
|
||||
{
|
||||
u8 *BUSN;
|
||||
u8 *MMIO;
|
||||
u8 *PCIO;
|
||||
u8 *SBLK;
|
||||
u8 *TOM1;
|
||||
u8 *SBDN;
|
||||
u8 *HCLK;
|
||||
u8 *HCDN;
|
||||
u8 *CBST;
|
||||
u8 *CBBX;
|
||||
u8 *CBS2;
|
||||
u8 *CBB2;
|
||||
|
||||
|
||||
int i;
|
||||
u32 dword;
|
||||
msr_t msr;
|
||||
|
||||
// the offset could be different if have different HC_NUMS, and HC_POSSIBLE_NUM and ssdt.asl
|
||||
BUSN = ssdt+0x3b; //+5 will be next BUSN
|
||||
MMIO = ssdt+0xe4; //+5 will be next MMIO
|
||||
PCIO = ssdt+0x36d; //+5 will be next PCIO
|
||||
SBLK = ssdt+0x4b2; // one byte
|
||||
TOM1 = ssdt+0x4b9; //
|
||||
SBDN = ssdt+0x4c3;//
|
||||
HCLK = ssdt+0x4d1; //+5 will be next HCLK
|
||||
HCDN = ssdt+0x57a; //+5 will be next HCDN
|
||||
CBBX = ssdt+0x61f; //
|
||||
CBST = ssdt+0x626;
|
||||
CBB2 = ssdt+0x62d; //
|
||||
CBS2 = ssdt+0x634;
|
||||
|
||||
for(i=0;i<HC_NUMS;i++) {
|
||||
dword = sysconf.ht_c_conf_bus[i];
|
||||
int_to_stream(dword, BUSN+i*5);
|
||||
}
|
||||
|
||||
for(i=0;i<(HC_NUMS*2);i++) { // FIXME: change to more chain
|
||||
dword = sysconf.conf_mmio_addrx[i]; //base
|
||||
int_to_stream(dword, MMIO+(i*2)*5);
|
||||
dword = sysconf.conf_mmio_addr[i]; //mask
|
||||
int_to_stream(dword, MMIO+(i*2+1)*5);
|
||||
}
|
||||
for(i=0;i<HC_NUMS;i++) { // FIXME: change to more chain
|
||||
dword = sysconf.conf_io_addrx[i];
|
||||
int_to_stream(dword, PCIO+(i*2)*5);
|
||||
dword = sysconf.conf_io_addr[i];
|
||||
int_to_stream(dword, PCIO+(i*2+1)*5);
|
||||
}
|
||||
|
||||
*SBLK = (u8)(sysconf.sblk);
|
||||
|
||||
msr = rdmsr(TOP_MEM);
|
||||
int_to_stream(msr.lo, TOM1);
|
||||
|
||||
int_to_stream(sysconf.sbdn, SBDN);
|
||||
|
||||
for(i=0;i<sysconf.hc_possible_num;i++) {
|
||||
int_to_stream(sysconf.pci1234[i], HCLK + i*5);
|
||||
int_to_stream(sysconf.hcdn[i], HCDN + i*5);
|
||||
}
|
||||
for(i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8
|
||||
int_to_stream(0x00000000, HCLK + i*5);
|
||||
int_to_stream(0x20202020, HCDN + i*5);
|
||||
}
|
||||
|
||||
*CBBX = (u8)(CBB);
|
||||
|
||||
if(CBB == 0xff) {
|
||||
*CBST = (u8) (0x0f);
|
||||
} else {
|
||||
if((sysconf.pci1234[0] >> 12) & 0xff) { //sb chain on other than bus 0
|
||||
*CBST = (u8) (0x0f);
|
||||
}
|
||||
else {
|
||||
*CBST = (u8) (0x00);
|
||||
}
|
||||
}
|
||||
|
||||
if((CBB == 0xff) && (sysconf.nodes>32)) {
|
||||
*CBS2 = 0x0f;
|
||||
*CBB2 = (u8)(CBB-1);
|
||||
} else {
|
||||
*CBS2 = 0x00;
|
||||
*CBB2 = 0x00;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
void update_sspr(void *sspr, u32 nodeid, u32 cpuindex)
|
||||
{
|
||||
u8 *CPU;
|
||||
u8 *CPUIN;
|
||||
u8 *COREFREQ;
|
||||
u8 *POWER;
|
||||
u8 *TRANSITION_LAT;
|
||||
u8 *BUSMASTER_LAT;
|
||||
u8 *CONTROL;
|
||||
u8 *STATUS;
|
||||
unsigned offset = 0x94 - 0x7f;
|
||||
int i;
|
||||
|
||||
CPU = sspr + 0x38;
|
||||
CPUIN = sspr + 0x3a;
|
||||
|
||||
COREFREQ = sspr + 0x7f; //2 byte
|
||||
POWER = sspr + 0x82; //3 bytes
|
||||
TRANSITION_LAT = sspr + 0x87; //two bytes
|
||||
BUSMASTER_LAT = sspr + 0x8a; //two bytes
|
||||
CONTROL = sspr + 0x8d;
|
||||
STATUS = sspr + 0x8f;
|
||||
|
||||
sprintf(CPU, "%02x", (u8)cpuindex);
|
||||
*CPUIN = (u8) cpuindex;
|
||||
|
||||
for(i=0;i<sysconf.p_state_num;i++) {
|
||||
struct p_state_t *p_state = &sysconf.p_state[nodeid * 5 + i];
|
||||
intx_to_stream(COREFREQ + i*offset, 2, p_state->corefreq);
|
||||
intx_to_stream(POWER + i*offset, 3, p_state->power);
|
||||
intx_to_stream(TRANSITION_LAT + i*offset, 2, p_state->transition_lat);
|
||||
intx_to_stream(BUSMASTER_LAT + i*offset, 2, p_state->busmaster_lat);
|
||||
*((u8 *)(CONTROL + i*offset)) =(u8) p_state->control;
|
||||
*((u8 *)(STATUS + i*offset)) =(u8) p_state->status;
|
||||
}
|
||||
}
|
||||
|
||||
extern unsigned char AmlCode_sspr5[];
|
||||
extern unsigned char AmlCode_sspr4[];
|
||||
extern unsigned char AmlCode_sspr3[];
|
||||
extern unsigned char AmlCode_sspr2[];
|
||||
extern unsigned char AmlCode_sspr1[];
|
||||
|
||||
/* fixme: find one good way for different p_state_num */
|
||||
unsigned long acpi_add_ssdt_pstates(acpi_rsdt_t *rsdt, unsigned long current)
|
||||
{
|
||||
device_t cpu;
|
||||
int cpu_index = 0;
|
||||
|
||||
acpi_header_t *ssdt;
|
||||
|
||||
if(!sysconf.p_state_num) return current;
|
||||
|
||||
u8 *AmlCode_sspr;
|
||||
switch(sysconf.p_state_num) {
|
||||
case 1: AmlCode_sspr = AmlCode_sspr1; break;
|
||||
case 2: AmlCode_sspr = AmlCode_sspr2; break;
|
||||
case 3: AmlCode_sspr = AmlCode_sspr3; break;
|
||||
case 4: AmlCode_sspr = AmlCode_sspr4; break;
|
||||
default: AmlCode_sspr = AmlCode_sspr5; break;
|
||||
}
|
||||
|
||||
for(cpu = all_devices; cpu; cpu = cpu->next) {
|
||||
if ((cpu->path.type != DEVICE_PATH_APIC) ||
|
||||
(cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) {
|
||||
continue;
|
||||
}
|
||||
if (!cpu->enabled) {
|
||||
continue;
|
||||
}
|
||||
printk_debug("ACPI: pstate cpu_index=%02x, node_id=%02x, core_id=%02x\n", cpu_index, cpu->path.u.apic.node_id, cpu->path.u.apic.core_id);
|
||||
|
||||
current = ( current + 0x0f) & -0x10;
|
||||
ssdt = (acpi_header_t *)current;
|
||||
current += ((acpi_header_t *)AmlCode_sspr)->length;
|
||||
memcpy((void *)ssdt, (void *)AmlCode_sspr, ((acpi_header_t *)AmlCode_sspr)->length);
|
||||
update_sspr((void*)ssdt,cpu->path.u.apic.node_id, cpu_index);
|
||||
/* recalculate checksum */
|
||||
ssdt->checksum = 0;
|
||||
ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length);
|
||||
acpi_add_table(rsdt,ssdt);
|
||||
|
||||
cpu_index++;
|
||||
}
|
||||
return current;
|
||||
}
|
||||
874
src/northbridge/amd/amdfam10/amdfam10_conf.c
Normal file
874
src/northbridge/amd/amdfam10/amdfam10_conf.c
Normal file
@ -0,0 +1,874 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#if defined(__ROMCC__)
|
||||
typedef struct sys_info sys_info_conf_t;
|
||||
#else
|
||||
typedef struct amdfam10_sysconf_t sys_info_conf_t;
|
||||
#endif
|
||||
|
||||
struct dram_base_mask_t {
|
||||
u32 base; //[47:27] at [28:8]
|
||||
u32 mask; //[47:27] at [28:8] and enable at bit 0
|
||||
};
|
||||
|
||||
static struct dram_base_mask_t get_dram_base_mask(u32 nodeid)
|
||||
{
|
||||
device_t dev;
|
||||
struct dram_base_mask_t d;
|
||||
#if defined(__ROMCC__)
|
||||
dev = PCI_DEV(CBB, CDB, 1);
|
||||
#else
|
||||
dev = __f1_dev[0];
|
||||
#endif
|
||||
|
||||
#if EXT_CONF_SUPPORT == 1
|
||||
// I will use ext space only for simple
|
||||
pci_write_config32(dev, 0x110, nodeid | (1<<28)); // [47:27] at [28:8]
|
||||
d.mask = pci_read_config32(dev, 0x114); // enable is bit 0
|
||||
pci_write_config32(dev, 0x110, nodeid | (0<<28));
|
||||
d.base = pci_read_config32(dev, 0x114) & 0x1fffff00; //[47:27] at [28:8];
|
||||
#else
|
||||
u32 temp;
|
||||
temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16]
|
||||
d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too
|
||||
temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]
|
||||
d.mask |= temp<<21;
|
||||
|
||||
temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16]
|
||||
d.mask |= (temp & 1); // enable bit
|
||||
|
||||
d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too
|
||||
temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]
|
||||
d.base |= temp<<21;
|
||||
#endif
|
||||
return d;
|
||||
}
|
||||
|
||||
static void set_dram_base_mask(u32 nodeid, struct dram_base_mask_t d, u32 nodes)
|
||||
{
|
||||
u32 i;
|
||||
device_t dev;
|
||||
#if EXT_CONF_SUPPORT == 1
|
||||
// I will use ext space only for simple
|
||||
u32 d_base_i, d_base_d, d_mask_i, d_mask_d;
|
||||
d_base_i = nodeid | (0<<28);
|
||||
d_base_d = d.base | nodeid; //[47:27] at [28:8];
|
||||
d_mask_i = nodeid | (1<<28); // [47:27] at [28:8]
|
||||
d_mask_d = d.mask; // enable is bit 0
|
||||
|
||||
#else
|
||||
u32 d_base_lo, d_base_hi, d_mask_lo, d_mask_hi;
|
||||
u32 d_base_lo_reg, d_base_hi_reg, d_mask_lo_reg, d_mask_hi_reg;
|
||||
d_mask_lo = (((d.mask<<(8+3))|(0x07<<16)) & 0xffff0000)|nodeid; // need to fill DramMask[26:24] with ones
|
||||
d_mask_hi = (d.mask>>21) & 0xff;
|
||||
d_base_lo = ((d.base<<(8+3)) & 0xffff0000);
|
||||
if(d.mask & 1) d_base_lo |= 3;
|
||||
d_base_hi = (d.base>>21) & 0xff;
|
||||
d_mask_lo_reg = 0x44+(nodeid<<3);
|
||||
d_mask_hi_reg = 0x144+(nodeid<<3);
|
||||
d_base_lo_reg = 0x40+(nodeid<<3);
|
||||
d_base_hi_reg = 0x140+(nodeid<<3);
|
||||
#endif
|
||||
|
||||
for(i=0;i<nodes;i++) {
|
||||
#if defined(__ROMCC__)
|
||||
dev = NODE_PCI(i, 1);
|
||||
#else
|
||||
dev = __f1_dev[i];
|
||||
#endif
|
||||
|
||||
#if EXT_CONF_SUPPORT == 1
|
||||
// I will use ext space only for simple
|
||||
pci_write_config32(dev, 0x110, d_base_i);
|
||||
pci_write_config32(dev, 0x114, d_base_d); //[47:27] at [28:8];
|
||||
pci_write_config32(dev, 0x110, d_mask_i); // [47:27] at [28:8]
|
||||
pci_write_config32(dev, 0x114, d_mask_d); // enable is bit 0
|
||||
#else
|
||||
pci_write_config32(dev, d_mask_lo_reg, d_mask_lo); // need to fill DramMask[26:24] with ones
|
||||
pci_write_config32(dev, d_mask_hi_reg, d_mask_hi);
|
||||
pci_write_config32(dev, d_base_lo_reg, d_base_lo);
|
||||
pci_write_config32(dev, d_base_hi_reg, d_base_hi);
|
||||
#endif
|
||||
}
|
||||
|
||||
#if defined(__ROMCC__)
|
||||
dev = NODE_PCI(nodeid, 1);
|
||||
#else
|
||||
dev = __f1_dev[nodeid];
|
||||
#endif
|
||||
pci_write_config32(dev, 0x120, d.base>>8);
|
||||
pci_write_config32(dev, 0x124, d.mask>>8);
|
||||
|
||||
}
|
||||
|
||||
|
||||
static void set_DctSelBaseAddr(u32 i, u32 sel_m)
|
||||
{
|
||||
device_t dev;
|
||||
#if defined(__ROMCC__)
|
||||
dev = NODE_PCI(i, 2);
|
||||
#else
|
||||
dev = __f2_dev[i];
|
||||
#endif
|
||||
u32 dcs_lo;
|
||||
dcs_lo = pci_read_config32(dev, DRAM_CTRL_SEL_LOW);
|
||||
dcs_lo &= ~(DCSL_DctSelBaseAddr_47_27_MASK<<DCSL_DctSelBaseAddr_47_27_SHIFT);
|
||||
dcs_lo |= (sel_m<<(20+DCSL_DctSelBaseAddr_47_27_SHIFT-27));
|
||||
pci_write_config32(dev, DRAM_CTRL_SEL_LOW, dcs_lo);
|
||||
|
||||
}
|
||||
|
||||
|
||||
static u32 get_DctSelBaseAddr(u32 i)
|
||||
{
|
||||
device_t dev;
|
||||
#if defined(__ROMCC__)
|
||||
dev = NODE_PCI(i, 2);
|
||||
#else
|
||||
dev = __f2_dev[i];
|
||||
#endif
|
||||
u32 sel_m;
|
||||
u32 dcs_lo;
|
||||
dcs_lo = pci_read_config32(dev, DRAM_CTRL_SEL_LOW);
|
||||
dcs_lo &= DCSL_DctSelBaseAddr_47_27_MASK<<DCSL_DctSelBaseAddr_47_27_SHIFT;
|
||||
sel_m = dcs_lo>>(20+DCSL_DctSelBaseAddr_47_27_SHIFT-27);
|
||||
return sel_m;
|
||||
}
|
||||
|
||||
|
||||
static void set_DctSelHiEn(u32 i, u32 val)
|
||||
{
|
||||
device_t dev;
|
||||
#if defined(__ROMCC__)
|
||||
dev = NODE_PCI(i, 2);
|
||||
#else
|
||||
dev = __f2_dev[i];
|
||||
#endif
|
||||
u32 dcs_lo;
|
||||
dcs_lo = pci_read_config32(dev, DRAM_CTRL_SEL_LOW);
|
||||
dcs_lo &= ~(7);
|
||||
dcs_lo |= (val & 7);
|
||||
pci_write_config32(dev, DRAM_CTRL_SEL_LOW, dcs_lo);
|
||||
|
||||
}
|
||||
|
||||
static u32 get_DctSelHiEn(u32 i)
|
||||
{
|
||||
device_t dev;
|
||||
#if defined(__ROMCC__)
|
||||
dev = NODE_PCI(i, 2);
|
||||
#else
|
||||
dev = __f2_dev[i];
|
||||
#endif
|
||||
u32 dcs_lo;
|
||||
dcs_lo = pci_read_config32(dev, DRAM_CTRL_SEL_LOW);
|
||||
dcs_lo &= 7;
|
||||
return dcs_lo;
|
||||
|
||||
}
|
||||
|
||||
static void set_DctSelBaseOffset(u32 i, u32 sel_off_m)
|
||||
{
|
||||
device_t dev;
|
||||
#if defined(__ROMCC__)
|
||||
dev = NODE_PCI(i, 2);
|
||||
#else
|
||||
dev = __f2_dev[i];
|
||||
#endif
|
||||
u32 dcs_hi;
|
||||
dcs_hi = pci_read_config32(dev, DRAM_CTRL_SEL_HIGH);
|
||||
dcs_hi &= ~(DCSH_DctSelBaseOffset_47_26_MASK<<DCSH_DctSelBaseOffset_47_26_SHIFT);
|
||||
dcs_hi |= sel_off_m<<(20+DCSH_DctSelBaseOffset_47_26_SHIFT-26);
|
||||
pci_write_config32(dev, DRAM_CTRL_SEL_HIGH, dcs_hi);
|
||||
|
||||
}
|
||||
|
||||
static u32 get_DctSelBaseOffset(u32 i)
|
||||
{
|
||||
device_t dev;
|
||||
#if defined(__ROMCC__)
|
||||
dev = NODE_PCI(i, 2);
|
||||
#else
|
||||
dev = __f2_dev[i];
|
||||
#endif
|
||||
u32 sel_off_m;
|
||||
u32 dcs_hi;
|
||||
dcs_hi = pci_read_config32(dev, DRAM_CTRL_SEL_HIGH);
|
||||
dcs_hi &= DCSH_DctSelBaseOffset_47_26_MASK<<DCSH_DctSelBaseOffset_47_26_SHIFT;
|
||||
sel_off_m = dcs_hi>>(20+DCSH_DctSelBaseOffset_47_26_SHIFT-26);
|
||||
return sel_off_m;
|
||||
}
|
||||
#if CONFIG_AMDMCT == 0
|
||||
|
||||
static u32 get_one_DCT(struct mem_info *meminfo)
|
||||
{
|
||||
u32 one_DCT = 1;
|
||||
if(meminfo->is_Width128) {
|
||||
one_DCT = 1;
|
||||
} else {
|
||||
u32 dimm_mask = meminfo->dimm_mask;
|
||||
if((dimm_mask >> DIMM_SOCKETS) && (dimm_mask & ((1<<DIMM_SOCKETS)-1))) {
|
||||
one_DCT = 0;
|
||||
}
|
||||
}
|
||||
|
||||
return one_DCT;
|
||||
}
|
||||
#endif
|
||||
#if HW_MEM_HOLE_SIZEK != 0
|
||||
|
||||
static u32 hoist_memory(u32 hole_startk, u32 i, u32 one_DCT, u32 nodes)
|
||||
{
|
||||
u32 ii;
|
||||
u32 carry_over;
|
||||
device_t dev;
|
||||
struct dram_base_mask_t d;
|
||||
u32 sel_m;
|
||||
u32 sel_hi_en;
|
||||
u32 hoist;
|
||||
|
||||
|
||||
carry_over = (4*1024*1024) - hole_startk;
|
||||
|
||||
for(ii=nodes - 1;ii>i;ii--) {
|
||||
d = get_dram_base_mask(ii);
|
||||
if(!(d.mask & 1)) continue;
|
||||
d.base += (carry_over>>9);
|
||||
d.mask += (carry_over>>9);
|
||||
set_dram_base_mask(ii, d, nodes);
|
||||
|
||||
if(get_DctSelHiEn(ii) & 1) {
|
||||
sel_m = get_DctSelBaseAddr(ii);
|
||||
sel_m += carry_over>>10;
|
||||
set_DctSelBaseAddr(ii, sel_m);
|
||||
}
|
||||
|
||||
}
|
||||
d = get_dram_base_mask(i);
|
||||
d.mask += (carry_over>>9);
|
||||
set_dram_base_mask(i,d, nodes);
|
||||
#if defined(__ROMCC__)
|
||||
dev = NODE_PCI(i, 1);
|
||||
#else
|
||||
dev = __f1_dev[i];
|
||||
#endif
|
||||
sel_hi_en = get_DctSelHiEn(i);
|
||||
if(sel_hi_en & 1) {
|
||||
sel_m = get_DctSelBaseAddr(i);
|
||||
}
|
||||
if(d.base == (hole_startk>>9)) {
|
||||
//don't need set memhole here, because hole off set will be 0, overflow
|
||||
//so need to change base reg instead, new basek will be 4*1024*1024
|
||||
d.base = (4*1024*1024)>>9;
|
||||
set_dram_base_mask(i, d, nodes);
|
||||
|
||||
if(sel_hi_en & 1) {
|
||||
sel_m += carry_over>>10;
|
||||
set_DctSelBaseAddr(i, sel_m);
|
||||
}
|
||||
} else {
|
||||
hoist = /* hole start address */
|
||||
((hole_startk << 10) & 0xff000000) +
|
||||
/* enable */
|
||||
1;
|
||||
if(one_DCT||(sel_m>=(hole_startk>>10))) { //one DCT or hole in DCT0
|
||||
hoist +=
|
||||
/* hole address to memory controller address */
|
||||
((((d.base<<9) + carry_over) >> 6) & 0x0000ff00) ;
|
||||
|
||||
if(sel_hi_en & 1) {
|
||||
sel_m += (carry_over>>10);
|
||||
set_DctSelBaseAddr(i, sel_m);
|
||||
set_DctSelBaseOffset(i, sel_m);
|
||||
}
|
||||
} else { // hole in DCT1 range
|
||||
hoist +=
|
||||
/* hole address to memory controller address */
|
||||
((((sel_m<<10) + carry_over) >> 6) & 0x0000ff00) ;
|
||||
// don't need to update DctSelBaseAddr
|
||||
if(sel_hi_en & 1) {
|
||||
set_DctSelBaseOffset(i, sel_m);
|
||||
}
|
||||
}
|
||||
pci_write_config32(dev, 0xf0, hoist);
|
||||
|
||||
}
|
||||
|
||||
return carry_over;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#if EXT_CONF_SUPPORT
|
||||
static void set_addr_map_reg_4_6_in_one_node(u32 nodeid, u32 cfg_map_dest,
|
||||
u32 busn_min, u32 busn_max,
|
||||
u32 type)
|
||||
{
|
||||
device_t dev;
|
||||
u32 i;
|
||||
u32 tempreg;
|
||||
u32 index_min, index_max;
|
||||
u32 dest_min, dest_max;
|
||||
index_min = busn_min>>2; dest_min = busn_min - (index_min<<2);
|
||||
index_max = busn_max>>2; dest_max = busn_max - (index_max<<2);
|
||||
|
||||
// three case: index_min==index_max, index_min+1=index_max; index_min+1<index_max
|
||||
#if defined(__ROMCC__)
|
||||
dev = NODE_PCI(nodeid, 1);
|
||||
#else
|
||||
dev = __f1_dev[nodeid];
|
||||
#endif
|
||||
if(index_min== index_max) {
|
||||
pci_write_config32(dev, 0x110, index_min | (type<<28));
|
||||
tempreg = pci_read_config32(dev, 0x114);
|
||||
for(i=dest_min; i<=dest_max; i++) {
|
||||
tempreg &= ~(0xff<<(i*8));
|
||||
tempreg |= (cfg_map_dest<<(i*8));
|
||||
}
|
||||
pci_write_config32(dev, 0x110, index_min | (type<<28)); // do i need to write it again
|
||||
pci_write_config32(dev, 0x114, tempreg);
|
||||
} else if(index_min<index_max) {
|
||||
pci_write_config32(dev, 0x110, index_min | (type<<28));
|
||||
tempreg = pci_read_config32(dev, 0x114);
|
||||
for(i=dest_min; i<=3; i++) {
|
||||
tempreg &= ~(0xff<<(i*8));
|
||||
tempreg |= (cfg_map_dest<<(i*8));
|
||||
}
|
||||
pci_write_config32(dev, 0x110, index_min | (type<<28)); // do i need to write it again
|
||||
pci_write_config32(dev, 0x114, tempreg);
|
||||
|
||||
pci_write_config32(dev, 0x110, index_max | (type<<28));
|
||||
tempreg = pci_read_config32(dev, 0x114);
|
||||
for(i=0; i<=dest_max; i++) {
|
||||
tempreg &= ~(0xff<<(i*8));
|
||||
tempreg |= (cfg_map_dest<<(i*8));
|
||||
}
|
||||
pci_write_config32(dev, 0x110, index_max | (type<<28)); // do i need to write it again
|
||||
pci_write_config32(dev, 0x114, tempreg);
|
||||
if((index_max-index_min)>1) {
|
||||
tempreg = 0;
|
||||
for(i=0; i<=3; i++) {
|
||||
tempreg &= ~(0xff<<(i*8));
|
||||
tempreg |= (cfg_map_dest<<(i*8));
|
||||
}
|
||||
for(i=index_min+1; i<index_max;i++) {
|
||||
pci_write_config32(dev, 0x110, i | (type<<28));
|
||||
pci_write_config32(dev, 0x114, tempreg);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
static void set_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
|
||||
u32 busn_min, u32 busn_max, u32 segbit,
|
||||
u32 nodes)
|
||||
{
|
||||
u32 tempreg;
|
||||
u32 i;
|
||||
device_t dev;
|
||||
|
||||
busn_min>>=segbit;
|
||||
busn_max>>=segbit;
|
||||
|
||||
#if EXT_CONF_SUPPORT
|
||||
if(ht_c_index < 4) {
|
||||
#endif
|
||||
tempreg = 3 | ((nodeid&0xf)<<4) | ((nodeid & 0x30)<<(12-4))|(linkn<<8)|((busn_min & 0xff)<<16)|((busn_max&0xff)<<24);
|
||||
for(i=0; i<nodes; i++) {
|
||||
#if defined(__ROMCC__)
|
||||
dev = NODE_PCI(i, 1);
|
||||
#else
|
||||
dev = __f1_dev[i];
|
||||
#endif
|
||||
pci_write_config32(dev, 0xe0 + ht_c_index * 4, tempreg);
|
||||
}
|
||||
#if EXT_CONF_SUPPORT
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
// if ht_c_index > 3, We should use extend space x114_x6
|
||||
u32 cfg_map_dest;
|
||||
u32 j;
|
||||
|
||||
// for nodeid at first
|
||||
cfg_map_dest = (1<<7) | (1<<6) | (linkn<<0);
|
||||
|
||||
set_addr_map_reg_4_6_in_one_node(nodeid, cfg_map_dest, busn_min, busn_max, 6);
|
||||
|
||||
// all other nodes
|
||||
cfg_map_dest = (1<<7) | (0<<6) | (nodeid<<0);
|
||||
for(j = 0; j< nodes; j++) {
|
||||
if(j== nodeid) continue;
|
||||
set_addr_map_reg_4_6_in_one_node(j,cfg_map_dest, busn_min, busn_max, 6);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
static void clear_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
|
||||
u32 busn_min, u32 busn_max, u32 nodes)
|
||||
{
|
||||
u32 i;
|
||||
device_t dev;
|
||||
|
||||
#if EXT_CONF_SUPPORT
|
||||
if(ht_c_index<4) {
|
||||
#endif
|
||||
for(i=0; i<nodes; i++) {
|
||||
#if defined(__ROMCC__)
|
||||
dev = NODE_PCI(i, 1);
|
||||
#else
|
||||
dev = __f1_dev[i];
|
||||
#endif
|
||||
pci_write_config32(dev, 0xe0 + ht_c_index * 4, 0);
|
||||
}
|
||||
#if EXT_CONF_SUPPORT
|
||||
return;
|
||||
}
|
||||
|
||||
// if hc_c_index >3, We should use busn_min and busn_max to clear extend space
|
||||
u32 cfg_map_dest;
|
||||
u32 j;
|
||||
|
||||
|
||||
// all nodes
|
||||
cfg_map_dest = 0;
|
||||
for(j = 0; j< nodes; j++) {
|
||||
set_addr_map_reg_4_6_in_one_node(j,cfg_map_dest, busn_min, busn_max, 6);
|
||||
}
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
#if PCI_BUS_SEGN_BITS
|
||||
static u32 check_segn(device_t dev, u32 segbusn, u32 nodes,
|
||||
sys_info_conf_t *sysinfo)
|
||||
{
|
||||
//check segbusn here, We need every node have the same segn
|
||||
if((segbusn & 0xff)>(0xe0-1)) {// use next segn
|
||||
u32 segn = (segbusn >> 8) & 0x0f;
|
||||
segn++;
|
||||
segbusn = segn<<8;
|
||||
}
|
||||
if(segbusn>>8) {
|
||||
u32 val;
|
||||
val = pci_read_config32(dev, 0x160);
|
||||
val &= ~(0xf<<25);
|
||||
val |= (segbusn & 0xf00)<<(25-8);
|
||||
pci_write_config32(dev, 0x160, val);
|
||||
}
|
||||
|
||||
return segbusn;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(__ROMCC__)
|
||||
static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
|
||||
u32 io_min, u32 io_max, u32 nodes)
|
||||
{
|
||||
u32 i;
|
||||
u32 tempreg;
|
||||
device_t dev;
|
||||
|
||||
#if EXT_CONF_SUPPORT
|
||||
if(ht_c_index<4) {
|
||||
#endif
|
||||
/* io range allocation */
|
||||
tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit
|
||||
for(i=0; i<nodes; i++) {
|
||||
#if defined(__ROMCC__)
|
||||
dev = NODE_PCI(i, 1);
|
||||
#else
|
||||
dev = __f1_dev[i];
|
||||
#endif
|
||||
pci_write_config32(dev, 0xC4 + ht_c_index * 8, tempreg);
|
||||
}
|
||||
tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?
|
||||
for(i=0; i<nodes; i++){
|
||||
#if defined(__ROMCC__)
|
||||
dev = NODE_PCI(i, 1);
|
||||
#else
|
||||
dev = __f1_dev[i];
|
||||
#endif
|
||||
pci_write_config32(dev, 0xC0 + ht_c_index * 8, tempreg);
|
||||
}
|
||||
#if EXT_CONF_SUPPORT
|
||||
return;
|
||||
}
|
||||
|
||||
u32 cfg_map_dest;
|
||||
u32 j;
|
||||
|
||||
// if ht_c_index > 3, We should use extend space
|
||||
|
||||
if(io_min>io_max) return;
|
||||
|
||||
// for nodeid at first
|
||||
cfg_map_dest = (1<<7) | (1<<6) | (linkn<<0);
|
||||
|
||||
set_addr_map_reg_4_6_in_one_node(nodeid, cfg_map_dest, io_min, io_max, 4);
|
||||
|
||||
// all other nodes
|
||||
cfg_map_dest = (1<<7) | (0<<6) | (nodeid<<0);
|
||||
for(j = 0; j< nodes; j++) {
|
||||
if(j== nodeid) continue;
|
||||
set_addr_map_reg_4_6_in_one_node(j,cfg_map_dest, io_min, io_max, 4);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
static void clear_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
|
||||
u32 io_min, u32 io_max, u32 nodes)
|
||||
{
|
||||
u32 i;
|
||||
device_t dev;
|
||||
#if EXT_CONF_SUPPORT
|
||||
if(ht_c_index<4) {
|
||||
#endif
|
||||
/* io range allocation */
|
||||
for(i=0; i<nodes; i++) {
|
||||
#if defined(__ROMCC__)
|
||||
dev = NODE_PCI(i, 1);
|
||||
#else
|
||||
dev = __f1_dev[i];
|
||||
#endif
|
||||
pci_write_config32(dev, 0xC4 + ht_c_index * 8, 0);
|
||||
pci_write_config32(dev, 0xC0 + ht_c_index * 8, 0);
|
||||
}
|
||||
#if EXT_CONF_SUPPORT
|
||||
return;
|
||||
}
|
||||
// : if hc_c_index > 3, We should use io_min, io_max to clear extend space
|
||||
u32 cfg_map_dest;
|
||||
u32 j;
|
||||
|
||||
|
||||
// all nodes
|
||||
cfg_map_dest = 0;
|
||||
for(j = 0; j< nodes; j++) {
|
||||
set_addr_map_reg_4_6_in_one_node(j,cfg_map_dest, io_min, io_max, 4);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
static void re_set_all_config_map_reg(u32 nodes, u32 segbit,
|
||||
sys_info_conf_t *sysinfo)
|
||||
{
|
||||
u32 ht_c_index;
|
||||
device_t dev;
|
||||
|
||||
set_config_map_reg(0, sysinfo->sblk, 0, 0, sysinfo->ht_c_conf_bus[0]>>20, segbit, nodes);
|
||||
|
||||
/* clean others */
|
||||
for(ht_c_index=1;ht_c_index<4; ht_c_index++) {
|
||||
u32 i;
|
||||
for(i=0; i<nodes; i++) {
|
||||
#if defined(__ROMCC__)
|
||||
dev = NODE_PCI(i, 1);
|
||||
#else
|
||||
dev = __f1_dev[i];
|
||||
#endif
|
||||
pci_write_config32(dev, 0xe0 + ht_c_index * 4, 0);
|
||||
}
|
||||
}
|
||||
#if EXT_CONF_SUPPORT
|
||||
u32 j;
|
||||
// clear the extend space
|
||||
for(j = 0; j< nodes; j++) {
|
||||
set_addr_map_reg_4_6_in_one_node(j,0, 0, 0xff, 6);
|
||||
}
|
||||
#endif
|
||||
|
||||
for(ht_c_index = 1; ht_c_index<sysinfo->ht_c_num; ht_c_index++) {
|
||||
u32 nodeid, linkn;
|
||||
u32 busn_max;
|
||||
u32 busn_min;
|
||||
nodeid = (sysinfo->ht_c_conf_bus[ht_c_index] >> 2) & 0x3f;
|
||||
linkn = (sysinfo->ht_c_conf_bus[ht_c_index]>>8) & 0x7;
|
||||
busn_max = sysinfo->ht_c_conf_bus[ht_c_index]>>20;
|
||||
busn_min = (sysinfo->ht_c_conf_bus[ht_c_index]>>12) & 0xff;
|
||||
busn_min |= busn_max & 0xf00;
|
||||
set_config_map_reg(nodeid, linkn, ht_c_index, busn_min, busn_max, segbit, nodes);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
static u32 get_ht_c_index(u32 nodeid, u32 linkn, sys_info_conf_t *sysinfo)
|
||||
{
|
||||
u32 tempreg;
|
||||
u32 ht_c_index = 0;
|
||||
|
||||
#if 0
|
||||
tempreg = 3 | ((nodeid & 0xf) <<4) | ((nodeid & 0x30)<<(12-4)) | (linkn<<8);
|
||||
|
||||
for(ht_c_index=0;ht_c_index<4; ht_c_index++) {
|
||||
reg = pci_read_config32(PCI_DEV(CBB, CDB, 1), 0xe0 + ht_c_index * 4);
|
||||
if(((reg & 0xffff) == 0x0000)) { /*found free*/
|
||||
break;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
tempreg = 3 | ((nodeid & 0x3f)<<2) | (linkn<<8);
|
||||
for(ht_c_index=0; ht_c_index<32; ht_c_index++) {
|
||||
if(((sysinfo->ht_c_conf_bus[ht_c_index] & 0xfff) == tempreg)){
|
||||
return ht_c_index;
|
||||
}
|
||||
}
|
||||
|
||||
for(ht_c_index=0; ht_c_index<32; ht_c_index++) {
|
||||
if((sysinfo->ht_c_conf_bus[ht_c_index] == 0)){
|
||||
return ht_c_index;
|
||||
}
|
||||
}
|
||||
|
||||
return -1;
|
||||
|
||||
}
|
||||
|
||||
static void store_ht_c_conf_bus(u32 nodeid, u32 linkn, u32 ht_c_index,
|
||||
u32 busn_min, u32 busn_max,
|
||||
sys_info_conf_t *sysinfo)
|
||||
{
|
||||
u32 val;
|
||||
val = 3 | ((nodeid & 0x3f)<<2) | (linkn<<8);
|
||||
sysinfo->ht_c_conf_bus[ht_c_index] = val | ((busn_min & 0xff) <<12) | (busn_max<<20); // same node need segn are same
|
||||
|
||||
}
|
||||
|
||||
|
||||
static void set_BusSegmentEn(u32 node, u32 segbit)
|
||||
{
|
||||
#if PCI_BUS_SEGN_BITS
|
||||
u32 dword;
|
||||
device_t dev;
|
||||
|
||||
#if defined(__ROMCC__)
|
||||
dev = NODE_PCI(node, 0);
|
||||
#else
|
||||
dev = __f0_dev[node];
|
||||
#endif
|
||||
|
||||
dword = pci_read_config32(dev, 0x68);
|
||||
dword &= ~(7<<28);
|
||||
dword |= (segbit<<28); /* bus segment enable */
|
||||
pci_write_config32(dev, 0x68, dword);
|
||||
#endif
|
||||
}
|
||||
|
||||
#if !defined(__ROMCC__)
|
||||
static u32 get_io_addr_index(u32 nodeid, u32 linkn)
|
||||
{
|
||||
u32 index;
|
||||
|
||||
for(index=0; index<256; index++) {
|
||||
if((sysconf.conf_io_addrx[index+4] == 0)){
|
||||
sysconf.conf_io_addr[index+4] = (nodeid & 0x3f) ;
|
||||
sysconf.conf_io_addrx[index+4] = 1 | ((linkn & 0x7)<<4);
|
||||
return index;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
}
|
||||
|
||||
static u32 get_mmio_addr_index(u32 nodeid, u32 linkn)
|
||||
{
|
||||
u32 index;
|
||||
|
||||
|
||||
for(index=0; index<64; index++) {
|
||||
if((sysconf.conf_mmio_addrx[index+8] == 0)){
|
||||
sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f) ;
|
||||
sysconf.conf_mmio_addrx[index+8] = 1 | ((linkn & 0x7)<<4);
|
||||
return index;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
}
|
||||
|
||||
static void store_conf_io_addr(u32 nodeid, u32 linkn, u32 reg, u32 index,
|
||||
u32 io_min, u32 io_max)
|
||||
{
|
||||
u32 val;
|
||||
#if EXT_CONF_SUPPORT
|
||||
if(reg!=0x110) {
|
||||
#endif
|
||||
/* io range allocation */
|
||||
index = (reg-0xc0)>>3;
|
||||
#if EXT_CONF_SUPPORT
|
||||
} else {
|
||||
index+=4;
|
||||
}
|
||||
#endif
|
||||
|
||||
val = (nodeid & 0x3f); // 6 bits used
|
||||
sysconf.conf_io_addr[index] = val | ((io_max<<8) & 0xfffff000); //limit : with nodeid
|
||||
val = 3 | ((linkn & 0x7)<<4) ; // 8 bits used
|
||||
sysconf.conf_io_addrx[index] = val | ((io_min<<8) & 0xfffff000); // base : with enable bit
|
||||
|
||||
if( sysconf.io_addr_num<(index+1))
|
||||
sysconf.io_addr_num = index+1;
|
||||
}
|
||||
|
||||
|
||||
static void store_conf_mmio_addr(u32 nodeid, u32 linkn, u32 reg, u32 index,
|
||||
u32 mmio_min, u32 mmio_max)
|
||||
{
|
||||
u32 val;
|
||||
#if EXT_CONF_SUPPORT
|
||||
if(reg!=0x110) {
|
||||
#endif
|
||||
/* io range allocation */
|
||||
index = (reg-0x80)>>3;
|
||||
#if EXT_CONF_SUPPORT
|
||||
} else {
|
||||
index+=8;
|
||||
}
|
||||
#endif
|
||||
|
||||
val = (nodeid & 0x3f) ; // 6 bits used
|
||||
sysconf.conf_mmio_addr[index] = val | (mmio_max & 0xffffff00); //limit : with nodeid and linkn
|
||||
val = 3 | ((linkn & 0x7)<<4) ; // 8 bits used
|
||||
sysconf.conf_mmio_addrx[index] = val | (mmio_min & 0xffffff00); // base : with enable bit
|
||||
|
||||
if( sysconf.mmio_addr_num<(index+1))
|
||||
sysconf.mmio_addr_num = index+1;
|
||||
}
|
||||
|
||||
|
||||
static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
|
||||
u32 io_min, u32 io_max)
|
||||
{
|
||||
|
||||
u32 i;
|
||||
u32 tempreg;
|
||||
#if EXT_CONF_SUPPORT
|
||||
if(reg!=0x110) {
|
||||
#endif
|
||||
/* io range allocation */
|
||||
tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit
|
||||
for(i=0; i<sysconf.nodes; i++)
|
||||
pci_write_config32(__f1_dev[i], reg+4, tempreg);
|
||||
|
||||
tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?
|
||||
#if 0
|
||||
// FIXME: can we use VGA reg instead?
|
||||
if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
|
||||
printk_spew("%s, enabling legacy VGA IO forwarding for %s link %s\n",
|
||||
__func__, dev_path(dev), link);
|
||||
tempreg |= PCI_IO_BASE_VGA_EN;
|
||||
}
|
||||
if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) {
|
||||
tempreg |= PCI_IO_BASE_NO_ISA;
|
||||
}
|
||||
#endif
|
||||
for(i=0; i<sysconf.nodes; i++)
|
||||
pci_write_config32(__f1_dev[i], reg, tempreg);
|
||||
#if EXT_CONF_SUPPORT
|
||||
return;
|
||||
}
|
||||
|
||||
u32 cfg_map_dest;
|
||||
u32 j;
|
||||
// if ht_c_index > 3, We should use extend space
|
||||
if(io_min>io_max) return;
|
||||
// for nodeid at first
|
||||
cfg_map_dest = (1<<7) | (1<<6) | (linkn<<0);
|
||||
|
||||
set_addr_map_reg_4_6_in_one_node(nodeid, cfg_map_dest, io_min, io_max, 4);
|
||||
|
||||
// all other nodes
|
||||
cfg_map_dest = (1<<7) | (0<<6) | (nodeid<<0);
|
||||
for(j = 0; j< sysconf.nodes; j++) {
|
||||
if(j== nodeid) continue;
|
||||
set_addr_map_reg_4_6_in_one_node(j,cfg_map_dest, io_min, io_max, 4);
|
||||
}
|
||||
#endif
|
||||
|
||||
}
|
||||
static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes)
|
||||
{
|
||||
|
||||
u32 i;
|
||||
u32 tempreg;
|
||||
#if EXT_CONF_SUPPORT
|
||||
if(reg!=0x110) {
|
||||
#endif
|
||||
/* io range allocation */
|
||||
tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit
|
||||
for(i=0; i<nodes; i++)
|
||||
pci_write_config32(__f1_dev[i], reg+4, tempreg);
|
||||
tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);
|
||||
for(i=0; i<sysconf.nodes; i++)
|
||||
pci_write_config32(__f1_dev[i], reg, tempreg);
|
||||
#if EXT_CONF_SUPPORT
|
||||
return;
|
||||
}
|
||||
|
||||
device_t dev;
|
||||
u32 j;
|
||||
// if ht_c_index > 3, We should use extend space
|
||||
// for nodeid at first
|
||||
u32 enable;
|
||||
|
||||
if(mmio_min>mmio_max) {
|
||||
return;
|
||||
}
|
||||
|
||||
enable = 1;
|
||||
|
||||
dev = __f1_dev[nodeid];
|
||||
tempreg = ((mmio_min>>3) & 0x1fffff00)| (1<<6) | (linkn<<0);
|
||||
pci_write_config32(dev, 0x110, index | (2<<28));
|
||||
pci_write_config32(dev, 0x114, tempreg);
|
||||
|
||||
tempreg = ((mmio_max>>3) & 0x1fffff00) | enable;
|
||||
pci_write_config32(dev, 0x110, index | (3<<28));
|
||||
pci_write_config32(dev, 0x114, tempreg);
|
||||
|
||||
|
||||
// all other nodes
|
||||
tempreg = ((mmio_min>>3) & 0x1fffff00) | (0<<6) | (nodeid<<0);
|
||||
for(j = 0; j< sysconf.nodes; j++) {
|
||||
if(j== nodeid) continue;
|
||||
dev = __f1_dev[j];
|
||||
pci_write_config32(dev, 0x110, index | (2<<28));
|
||||
pci_write_config32(dev, 0x114, tempreg);
|
||||
}
|
||||
|
||||
tempreg = ((mmio_max>>3) & 0x1fffff00) | enable;
|
||||
for(j = 0; j< sysconf.nodes; j++) {
|
||||
if(j==nodeid) continue;
|
||||
dev = __f1_dev[j];
|
||||
pci_write_config32(dev, 0x110, index | (3<<28));
|
||||
pci_write_config32(dev, 0x114, tempreg);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif
|
||||
41
src/northbridge/amd/amdfam10/amdfam10_nums.h
Normal file
41
src/northbridge/amd/amdfam10/amdfam10_nums.h
Normal file
@ -0,0 +1,41 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef AMDFAM10_NUMS_H
|
||||
|
||||
#define AMDFAM10_NUMS_H
|
||||
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 8
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 32
|
||||
#define NODE_NUMS 64
|
||||
#else
|
||||
#define NODE_NUMS 32
|
||||
#endif
|
||||
#else
|
||||
#define NODE_NUMS 8
|
||||
#endif
|
||||
|
||||
// max HC installed at the same time. ...could be bigger than (48+24) if we have 3x4x4
|
||||
#define HC_NUMS 32
|
||||
|
||||
//it could be more bigger
|
||||
#define HC_POSSIBLE_NUM 32
|
||||
|
||||
#endif
|
||||
|
||||
73
src/northbridge/amd/amdfam10/amdfam10_pci.c
Normal file
73
src/northbridge/amd/amdfam10/amdfam10_pci.c
Normal file
@ -0,0 +1,73 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
|
||||
#ifndef AMDFAM10_PCI_C
|
||||
#define AMDFAM10_PCI_C
|
||||
/* bit [10,8] are dev func, bit[1,0] are dev index */
|
||||
|
||||
|
||||
static u32 pci_read_config32_index(device_t dev, u32 index_reg, u32 index)
|
||||
{
|
||||
u32 dword;
|
||||
|
||||
pci_write_config32(dev, index_reg, index);
|
||||
dword = pci_read_config32(dev, index_reg+0x4);
|
||||
return dword;
|
||||
}
|
||||
|
||||
static void pci_write_config32_index(device_t dev, u32 index_reg, u32 index, u32 data)
|
||||
{
|
||||
|
||||
pci_write_config32(dev, index_reg, index);
|
||||
|
||||
pci_write_config32(dev, index_reg + 0x4, data);
|
||||
|
||||
}
|
||||
|
||||
static u32 pci_read_config32_index_wait(device_t dev, u32 index_reg, u32 index)
|
||||
{
|
||||
|
||||
u32 dword;
|
||||
|
||||
index &= ~(1<<30);
|
||||
pci_write_config32(dev, index_reg, index);
|
||||
do {
|
||||
dword = pci_read_config32(dev, index_reg);
|
||||
} while (!(dword & (1<<31)));
|
||||
dword = pci_read_config32(dev, index_reg+0x4);
|
||||
return dword;
|
||||
}
|
||||
|
||||
static void pci_write_config32_index_wait(device_t dev, u32 index_reg, u32 index, u32 data)
|
||||
{
|
||||
|
||||
u32 dword;
|
||||
|
||||
pci_write_config32(dev, index_reg + 0x4, data);
|
||||
index |= (1<<30);
|
||||
pci_write_config32(dev, index_reg, index);
|
||||
do {
|
||||
dword = pci_read_config32(dev, index_reg);
|
||||
} while (!(dword & (1<<31)));
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
24
src/northbridge/amd/amdfam10/chip.h
Normal file
24
src/northbridge/amd/amdfam10/chip.h
Normal file
@ -0,0 +1,24 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
struct northbridge_amd_amdfam10_config
|
||||
{
|
||||
};
|
||||
|
||||
extern struct chip_operations northbridge_amd_amdfam10_ops;
|
||||
331
src/northbridge/amd/amdfam10/debug.c
Normal file
331
src/northbridge/amd/amdfam10/debug.c
Normal file
@ -0,0 +1,331 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* Generic FAM10 debug code, used by mainboard specific car_auto.c
|
||||
*/
|
||||
|
||||
#include "amdfam10_pci.c"
|
||||
|
||||
static void udelay_tsc(u32 us);
|
||||
|
||||
static void print_debug_addr(const char *str, void *val)
|
||||
{
|
||||
#if CACHE_AS_RAM_ADDRESS_DEBUG == 1
|
||||
printk_debug("------Address debug: %s%x------\n", str, val);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void print_debug_pci_dev(u32 dev)
|
||||
{
|
||||
#if PCI_BUS_SEGN_BITS==0
|
||||
printk_debug("PCI: %02x:%02x.%02x", (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7);
|
||||
#else
|
||||
printk_debug("PCI: %04x:%02x:%02x.%02x", (dev>>28) & 0x0f, (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void print_pci_devices(void)
|
||||
{
|
||||
device_t dev;
|
||||
for(dev = PCI_DEV(0, 0, 0);
|
||||
dev <= PCI_DEV(0xff, 0x1f, 0x7);
|
||||
dev += PCI_DEV(0,0,1)) {
|
||||
u32 id;
|
||||
id = pci_read_config32(dev, PCI_VENDOR_ID);
|
||||
if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
|
||||
(((id >> 16) & 0xffff) == 0xffff) ||
|
||||
(((id >> 16) & 0xffff) == 0x0000)) {
|
||||
continue;
|
||||
}
|
||||
print_debug_pci_dev(dev);
|
||||
printk_debug(" %04x:%04x\n", (id & 0xffff), (id>>16));
|
||||
if(((dev>>12) & 0x07) == 0) {
|
||||
u8 hdr_type;
|
||||
hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
|
||||
if((hdr_type & 0x80) != 0x80) {
|
||||
dev += PCI_DEV(0,0,7);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void print_pci_devices_on_bus(u32 busn)
|
||||
{
|
||||
device_t dev;
|
||||
for(dev = PCI_DEV(busn, 0, 0);
|
||||
dev <= PCI_DEV(busn, 0x1f, 0x7);
|
||||
dev += PCI_DEV(0,0,1)) {
|
||||
u32 id;
|
||||
id = pci_read_config32(dev, PCI_VENDOR_ID);
|
||||
if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
|
||||
(((id >> 16) & 0xffff) == 0xffff) ||
|
||||
(((id >> 16) & 0xffff) == 0x0000)) {
|
||||
continue;
|
||||
}
|
||||
print_debug_pci_dev(dev);
|
||||
printk_debug(" %04x:%04x\n", (id & 0xffff), (id>>16));
|
||||
if(((dev>>12) & 0x07) == 0) {
|
||||
u8 hdr_type;
|
||||
hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
|
||||
if((hdr_type & 0x80) != 0x80) {
|
||||
dev += PCI_DEV(0,0,7);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
static void dump_pci_device_range(u32 dev, u32 start_reg, u32 size)
|
||||
{
|
||||
int i;
|
||||
print_debug_pci_dev(dev);
|
||||
int j;
|
||||
int end = start_reg + size;
|
||||
|
||||
for(i = start_reg; i < end; i+=4) {
|
||||
u32 val;
|
||||
if ((i & 0x0f) == 0) {
|
||||
printk_debug("\n%04x:",i);
|
||||
}
|
||||
val = pci_read_config32(dev, i);
|
||||
for(j=0;j<4;j++) {
|
||||
printk_debug(" %02x", val & 0xff);
|
||||
val >>= 8;
|
||||
}
|
||||
}
|
||||
print_debug("\n");
|
||||
}
|
||||
static void dump_pci_device(u32 dev)
|
||||
{
|
||||
dump_pci_device_range(dev, 0, 4096);
|
||||
}
|
||||
static u32 pci_read_config32_index_wait(device_t dev, u32 index_reg, u32 index);
|
||||
static void dump_pci_device_index_wait_range(u32 dev, u32 index_reg, u32 start,
|
||||
u32 size)
|
||||
{
|
||||
int i;
|
||||
int end = start + size;
|
||||
print_debug_pci_dev(dev);
|
||||
print_debug(" -- index_reg="); print_debug_hex32(index_reg);
|
||||
|
||||
for(i = start; i < end; i++) {
|
||||
u32 val;
|
||||
int j;
|
||||
printk_debug("\n%02x:",i);
|
||||
val = pci_read_config32_index_wait(dev, index_reg, i);
|
||||
for(j=0;j<4;j++) {
|
||||
printk_debug(" %02x", val & 0xff);
|
||||
val >>= 8;
|
||||
}
|
||||
|
||||
}
|
||||
print_debug("\n");
|
||||
}
|
||||
static void dump_pci_device_index_wait(u32 dev, u32 index_reg)
|
||||
{
|
||||
dump_pci_device_index_wait_range(dev, index_reg, 0, 0x54);
|
||||
dump_pci_device_index_wait_range(dev, index_reg, 0x100, 0x08); //DIMM1 when memclk > 400Hz
|
||||
// dump_pci_device_index_wait_range(dev, index_reg, 0x200, 0x08); //DIMM2
|
||||
// dump_pci_device_index_wait_range(dev, index_reg, 0x300, 0x08); //DIMM3
|
||||
|
||||
}
|
||||
|
||||
static void dump_pci_device_index(u32 dev, u32 index_reg, u32 type, u32 length)
|
||||
{
|
||||
int i;
|
||||
print_debug_pci_dev(dev);
|
||||
|
||||
print_debug(" index reg: "); print_debug_hex16(index_reg); print_debug(" type: "); print_debug_hex8(type);
|
||||
|
||||
type<<=28;
|
||||
|
||||
for(i = 0; i < length; i++) {
|
||||
u32 val;
|
||||
if ((i & 0x0f) == 0) {
|
||||
printk_debug("\n%02x:",i);
|
||||
}
|
||||
val = pci_read_config32_index(dev, index_reg, i|type);
|
||||
printk_debug(" %08x", val);
|
||||
}
|
||||
print_debug("\n");
|
||||
}
|
||||
|
||||
|
||||
static void dump_pci_devices(void)
|
||||
{
|
||||
device_t dev;
|
||||
for(dev = PCI_DEV(0, 0, 0);
|
||||
dev <= PCI_DEV(0xff, 0x1f, 0x7);
|
||||
dev += PCI_DEV(0,0,1)) {
|
||||
u32 id;
|
||||
id = pci_read_config32(dev, PCI_VENDOR_ID);
|
||||
if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
|
||||
(((id >> 16) & 0xffff) == 0xffff) ||
|
||||
(((id >> 16) & 0xffff) == 0x0000)) {
|
||||
continue;
|
||||
}
|
||||
dump_pci_device(dev);
|
||||
|
||||
if(((dev>>12) & 0x07) == 0) {
|
||||
u8 hdr_type;
|
||||
hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
|
||||
if((hdr_type & 0x80) != 0x80) {
|
||||
dev += PCI_DEV(0,0,7);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static void dump_pci_devices_on_bus(u32 busn)
|
||||
{
|
||||
device_t dev;
|
||||
for(dev = PCI_DEV(busn, 0, 0);
|
||||
dev <= PCI_DEV(busn, 0x1f, 0x7);
|
||||
dev += PCI_DEV(0,0,1)) {
|
||||
u32 id;
|
||||
id = pci_read_config32(dev, PCI_VENDOR_ID);
|
||||
if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
|
||||
(((id >> 16) & 0xffff) == 0xffff) ||
|
||||
(((id >> 16) & 0xffff) == 0x0000)) {
|
||||
continue;
|
||||
}
|
||||
dump_pci_device(dev);
|
||||
|
||||
if(((dev>>12) & 0x07) == 0) {
|
||||
u8 hdr_type;
|
||||
hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
|
||||
if((hdr_type & 0x80) != 0x80) {
|
||||
dev += PCI_DEV(0,0,7);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#ifndef DEBUG_SMBUS
|
||||
#define DEBUG_SMBUS 0
|
||||
#endif
|
||||
|
||||
#if DEBUG_SMBUS == 1
|
||||
|
||||
static void dump_spd_registers(const struct mem_controller *ctrl)
|
||||
{
|
||||
int i;
|
||||
print_debug("\n");
|
||||
for(i = 0; i < DIMM_SOCKETS; i++) {
|
||||
u32 device;
|
||||
device = ctrl->spd_addr[i];
|
||||
if (device) {
|
||||
int j;
|
||||
printk_debug("dimm: %02x.0: %02x", i, device);
|
||||
for(j = 0; j < 128; j++) {
|
||||
int status;
|
||||
u8 byte;
|
||||
if ((j & 0xf) == 0) {
|
||||
printk_debug("\n%02x: ", j);
|
||||
}
|
||||
status = smbus_read_byte(device, j);
|
||||
if (status < 0) {
|
||||
break;
|
||||
}
|
||||
byte = status & 0xff;
|
||||
printk_debug("%02x ", byte);
|
||||
}
|
||||
print_debug("\n");
|
||||
}
|
||||
device = ctrl->spd_addr[i+DIMM_SOCKETS];
|
||||
if (device) {
|
||||
int j;
|
||||
printk_debug("dimm: %02x.1: %02x", i, device);
|
||||
for(j = 0; j < 128; j++) {
|
||||
int status;
|
||||
u8 byte;
|
||||
if ((j & 0xf) == 0) {
|
||||
printk_debug("\n%02x: ", j);
|
||||
}
|
||||
status = smbus_read_byte(device, j);
|
||||
if (status < 0) {
|
||||
break;
|
||||
}
|
||||
byte = status & 0xff;
|
||||
printk_debug("%02x ", byte);
|
||||
}
|
||||
print_debug("\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
static void dump_smbus_registers(void)
|
||||
{
|
||||
u32 device;
|
||||
print_debug("\n");
|
||||
for(device = 1; device < 0x80; device++) {
|
||||
int j;
|
||||
if( smbus_read_byte(device, 0) < 0 ) continue;
|
||||
printk_debug("smbus: %02x", device);
|
||||
for(j = 0; j < 256; j++) {
|
||||
int status;
|
||||
u8 byte;
|
||||
status = smbus_read_byte(device, j);
|
||||
if (status < 0) {
|
||||
break;
|
||||
}
|
||||
if ((j & 0xf) == 0) {
|
||||
printk_debug("\n%02x: ",j);
|
||||
}
|
||||
byte = status & 0xff;
|
||||
printk_debug("%02x ", byte);
|
||||
}
|
||||
print_debug("\n");
|
||||
}
|
||||
}
|
||||
#endif
|
||||
static void dump_io_resources(u32 port)
|
||||
{
|
||||
|
||||
int i;
|
||||
udelay_tsc(2000);
|
||||
printk_debug("%04x:\n", port);
|
||||
for(i=0;i<256;i++) {
|
||||
u8 val;
|
||||
if ((i & 0x0f) == 0) {
|
||||
printk_debug("%02x:", i);
|
||||
}
|
||||
val = inb(port);
|
||||
printk_debug(" %02x",val);
|
||||
if ((i & 0x0f) == 0x0f) {
|
||||
print_debug("\n");
|
||||
}
|
||||
port++;
|
||||
}
|
||||
}
|
||||
|
||||
static void dump_mem(u32 start, u32 end)
|
||||
{
|
||||
u32 i;
|
||||
print_debug("dump_mem:");
|
||||
for(i=start;i<end;i++) {
|
||||
if((i & 0xf)==0) {
|
||||
printk_debug("\n%08x:", i);
|
||||
}
|
||||
printk_debug(" %02x", (u8)*((u8 *)i));
|
||||
}
|
||||
print_debug("\n");
|
||||
}
|
||||
175
src/northbridge/amd/amdfam10/early_ht.c
Normal file
175
src/northbridge/amd/amdfam10/early_ht.c
Normal file
@ -0,0 +1,175 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
// For SB HT chain only
|
||||
// mmconf is not ready yet
|
||||
static void set_bsp_node_CHtExtNodeCfgEn(void)
|
||||
{
|
||||
#if EXT_RT_TBL_SUPPORT == 1
|
||||
u32 dword;
|
||||
dword = pci_io_read_config32(PCI_DEV(0, 0x18, 0), 0x68);
|
||||
dword |= (1<<27) | (1<<25);
|
||||
/* CHtExtNodeCfgEn: coherent link extended node configuration enable,
|
||||
Nodes[31:0] will be 0xff:[31:0], Nodes[63:32] will be 0xfe:[31:0]
|
||||
---- 32 nodes now only
|
||||
It can be used even nodes less than 8 nodes.
|
||||
We can have 8 more device on bus 0 in that case
|
||||
*/
|
||||
|
||||
/* CHtExtAddrEn */
|
||||
pci_io_write_config32(PCI_DEV(0, 0x18, 0), 0x68, dword);
|
||||
// CPU on bus 0xff and 0xfe now. For now on we can use CBB and CDB.
|
||||
#endif
|
||||
}
|
||||
|
||||
static void enumerate_ht_chain(void)
|
||||
{
|
||||
#if HT_CHAIN_UNITID_BASE != 0
|
||||
/* HT_CHAIN_UNITID_BASE could be 0 (only one ht device in the ht chain),
|
||||
if so, don't need to go through the chain */
|
||||
|
||||
/* Assumption the HT chain that is bus 0 has the HT I/O Hub on it.
|
||||
* On most boards this just happens. If a cpu has multiple
|
||||
* non Coherent links the appropriate bus registers for the
|
||||
* links needs to be programed to point at bus 0.
|
||||
*/
|
||||
unsigned next_unitid, last_unitid = 0;
|
||||
#if HT_CHAIN_END_UNITID_BASE != 0x20
|
||||
// let't record the device of last ht device, So we can set the
|
||||
// Unitid to HT_CHAIN_END_UNITID_BASE
|
||||
unsigned real_last_unitid = 0;
|
||||
u8 real_last_pos = 0;
|
||||
int ht_dev_num = 0; // except host_bridge
|
||||
u8 end_used = 0;
|
||||
#endif
|
||||
|
||||
next_unitid = HT_CHAIN_UNITID_BASE;
|
||||
do {
|
||||
u32 id;
|
||||
u8 hdr_type, pos;
|
||||
last_unitid = next_unitid;
|
||||
|
||||
id = pci_io_read_config32(PCI_DEV(0,0,0), PCI_VENDOR_ID);
|
||||
/* If the chain is enumerated quit */
|
||||
if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
|
||||
(((id >> 16) & 0xffff) == 0xffff) ||
|
||||
(((id >> 16) & 0xffff) == 0x0000))
|
||||
{
|
||||
break;
|
||||
}
|
||||
|
||||
hdr_type = pci_io_read_config8(PCI_DEV(0,0,0), PCI_HEADER_TYPE);
|
||||
pos = 0;
|
||||
hdr_type &= 0x7f;
|
||||
|
||||
if ((hdr_type == PCI_HEADER_TYPE_NORMAL) ||
|
||||
(hdr_type == PCI_HEADER_TYPE_BRIDGE))
|
||||
{
|
||||
pos = pci_io_read_config8(PCI_DEV(0,0,0), PCI_CAPABILITY_LIST);
|
||||
}
|
||||
while(pos != 0) {
|
||||
u8 cap;
|
||||
cap = pci_io_read_config8(PCI_DEV(0,0,0), pos + PCI_CAP_LIST_ID);
|
||||
if (cap == PCI_CAP_ID_HT) {
|
||||
u16 flags;
|
||||
/* Read and write and reread flags so the link
|
||||
* direction bit is valid.
|
||||
*/
|
||||
flags = pci_io_read_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS);
|
||||
pci_io_write_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS, flags);
|
||||
flags = pci_io_read_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS);
|
||||
if ((flags >> 13) == 0) {
|
||||
unsigned count;
|
||||
unsigned ctrl, ctrl_off;
|
||||
device_t devx;
|
||||
|
||||
#if HT_CHAIN_END_UNITID_BASE != 0x20
|
||||
if(next_unitid>=0x18) {
|
||||
if(!end_used) {
|
||||
next_unitid = HT_CHAIN_END_UNITID_BASE;
|
||||
end_used = 1;
|
||||
} else {
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
real_last_unitid = next_unitid;
|
||||
real_last_pos = pos;
|
||||
ht_dev_num++ ;
|
||||
#endif
|
||||
#if HT_CHAIN_END_UNITID_BASE == 0
|
||||
if (!next_unitid)
|
||||
goto out;
|
||||
#endif
|
||||
flags &= ~0x1f;
|
||||
flags |= next_unitid & 0x1f;
|
||||
count = (flags >> 5) & 0x1f;
|
||||
devx = PCI_DEV(0, next_unitid, 0);
|
||||
next_unitid += count;
|
||||
|
||||
pci_io_write_config16(PCI_DEV(0, 0, 0), pos + PCI_CAP_FLAGS, flags);
|
||||
|
||||
/* Test for end of chain */
|
||||
ctrl_off = ((flags >> 10) & 1)?
|
||||
PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
|
||||
|
||||
do {
|
||||
ctrl = pci_read_config16(devx, pos + ctrl_off);
|
||||
/* Is this the end of the hypertransport chain? */
|
||||
if (ctrl & (1 << 6)) {
|
||||
goto out;
|
||||
}
|
||||
|
||||
if (ctrl & ((1 << 4) | (1 << 8))) {
|
||||
/*
|
||||
* Either the link has failed, or we have
|
||||
* a CRC error.
|
||||
* Sometimes this can happen due to link
|
||||
* retrain, so lets knock it down and see
|
||||
* if its transient
|
||||
*/
|
||||
ctrl |= ((1 << 4) | (1 <<8)); // Link fail + Crc
|
||||
pci_write_config16(devx, pos + ctrl_off, ctrl);
|
||||
ctrl = pci_read_config16(devx, pos + ctrl_off);
|
||||
if (ctrl & ((1 << 4) | (1 << 8))) {
|
||||
// can not clear the error
|
||||
break;
|
||||
}
|
||||
}
|
||||
} while((ctrl & (1 << 5)) == 0);
|
||||
|
||||
break;
|
||||
}
|
||||
}
|
||||
pos = pci_io_read_config8(PCI_DEV(0, 0, 0), pos + PCI_CAP_LIST_NEXT);
|
||||
}
|
||||
} while(last_unitid != next_unitid);
|
||||
|
||||
out: ;
|
||||
#if HT_CHAIN_END_UNITID_BASE != 0x20
|
||||
if((ht_dev_num>1) && (real_last_unitid != HT_CHAIN_END_UNITID_BASE) && !end_used) {
|
||||
u16 flags;
|
||||
flags = pci_io_read_config16(PCI_DEV(0,real_last_unitid,0), real_last_pos + PCI_CAP_FLAGS);
|
||||
flags &= ~0x1f;
|
||||
flags |= HT_CHAIN_END_UNITID_BASE & 0x1f;
|
||||
pci_io_write_config16(PCI_DEV(0, real_last_unitid, 0), real_last_pos + PCI_CAP_FLAGS, flags);
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
}
|
||||
118
src/northbridge/amd/amdfam10/get_pci1234.c
Normal file
118
src/northbridge/amd/amdfam10/get_pci1234.c
Normal file
@ -0,0 +1,118 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include <cpu/amd/amdfam10_sysconf.h>
|
||||
|
||||
|
||||
/* Need pci1234 array
|
||||
* pci1234[0] will record sblink and bus range
|
||||
* pci1234[i] will record ht chain i.
|
||||
* It will keep the sequence when some ht io card is not installed.
|
||||
*
|
||||
* 1n: 8
|
||||
* 2n: 7x2
|
||||
* 3n: 6x3
|
||||
* 4n: 5x4
|
||||
* 5n: 4x5
|
||||
* 6n: 3x6
|
||||
* 7n: 2x7
|
||||
* 8n: 1x8
|
||||
*
|
||||
* 8n(4x2): 8x4
|
||||
* 16n(4x4): 16*2
|
||||
* 20n(4x5): 20x1
|
||||
* 32n(4x4+4x4): 16x1
|
||||
*
|
||||
* Total: xxx: I just want to use 32 instead, If you have more, you may need to
|
||||
* reset HC_POSSIBLE_NUM and update ssdt.dsl (hcdn, hclk)
|
||||
*
|
||||
* Put all the possible ht node/link to the list tp pci1234[] in get_bus_conf.c
|
||||
* on MB dir. Also, don't forget to increase the ACPI_SSDTX_NUM etc if you have
|
||||
* too much SSDT. How about co-processor on socket 1 on 2 way system.
|
||||
* or socket 2, and socket3 on 4 way system? treat that as one hc too!
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
void get_pci1234(void)
|
||||
{
|
||||
|
||||
int i,j;
|
||||
u32 dword;
|
||||
|
||||
dword = sysconf.sblk<<8;
|
||||
dword |= 1;
|
||||
sysconf.pci1234[0] = dword; // sblink
|
||||
sysconf.hcid[0] = 0;
|
||||
|
||||
/* about hardcode numbering for HT_IO support
|
||||
set the node_id and link_id that could have ht chain in the one array,
|
||||
then check if is enabled.... then update final value
|
||||
*/
|
||||
|
||||
//here we need to set hcdn
|
||||
//1. hypertransport.c need to record hcdn_reg together with 0xe0, 0xe4, 0xe8, 0xec when are set
|
||||
//2. so at the same time we need update hsdn with hcdn_reg here
|
||||
// printk_debug("sysconf.ht_c_num = %02d\n", sysconf.ht_c_num);
|
||||
|
||||
for(j=0;j<sysconf.ht_c_num;j++) {
|
||||
u32 dwordx;
|
||||
dwordx = sysconf.ht_c_conf_bus[j];
|
||||
// printk_debug("sysconf.ht_c_conf_bus[%02d] = %08x\n", j, sysconf.ht_c_conf_bus[j]);
|
||||
dwordx &=0xfffffffd; //keep bus num, node_id, link_num, enable bits
|
||||
if((dwordx & 0x7fd) == dword) { //SBLINK
|
||||
sysconf.pci1234[0] = dwordx;
|
||||
sysconf.hcdn[0] = sysconf.hcdn_reg[j];
|
||||
continue;
|
||||
}
|
||||
if((dwordx & 1)) {
|
||||
// We need to find out the number of HC
|
||||
// for exact match
|
||||
for(i=1;i<sysconf.hc_possible_num;i++) {
|
||||
if((dwordx & 0x7fc) == (sysconf.pci1234[i] & 0x7fc)) { // same node and same linkn
|
||||
sysconf.pci1234[i] = dwordx;
|
||||
sysconf.hcdn[i] = sysconf.hcdn_reg[j];
|
||||
break;
|
||||
}
|
||||
}
|
||||
// for 0xffc match or same node
|
||||
for(i=1;i<sysconf.hc_possible_num;i++) {
|
||||
if((dwordx & 0x7fc) == (dwordx & sysconf.pci1234[i] & 0x7fc)) {
|
||||
sysconf.pci1234[i] = dwordx;
|
||||
sysconf.hcdn[i] = sysconf.hcdn_reg[j];
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
for(i=1;i<sysconf.hc_possible_num;i++) {
|
||||
if(!(sysconf.pci1234[i] & 1)) {
|
||||
sysconf.pci1234[i] = 0;
|
||||
sysconf.hcdn[i] = 0x20202020;
|
||||
}
|
||||
sysconf.hcid[i] = 0;
|
||||
}
|
||||
}
|
||||
155
src/northbridge/amd/amdfam10/misc_control.c
Normal file
155
src/northbridge/amd/amdfam10/misc_control.c
Normal file
@ -0,0 +1,155 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2003 by Eric Biederman
|
||||
* Copyright (C) Stefan Reinauer
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/* Turn off machine check triggers when reading
|
||||
* pci space where there are no devices.
|
||||
* This is necessary when scaning the bus for
|
||||
* devices which is done by the kernel
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <part/hard_reset.h>
|
||||
#include <pc80/mc146818rtc.h>
|
||||
#include <bitops.h>
|
||||
#include <cpu/amd/model_10xxx_rev.h>
|
||||
|
||||
#include "amdfam10.h"
|
||||
|
||||
/**
|
||||
* @brief Read resources for AGP aperture
|
||||
*
|
||||
* @param
|
||||
*
|
||||
* There is only one AGP aperture resource needed. The resoruce is added to
|
||||
* the northbridge of BSP.
|
||||
*
|
||||
* The same trick can be used to augment legacy VGA resources which can
|
||||
* be detect by generic pci reousrce allocator for VGA devices.
|
||||
* BAD: it is more tricky than I think, the resource allocation code is
|
||||
* implemented in a way to NOT DOING legacy VGA resource allcation on
|
||||
* purpose :-(.
|
||||
*/
|
||||
static void mcf3_read_resources(device_t dev)
|
||||
{
|
||||
struct resource *resource;
|
||||
unsigned char iommu;
|
||||
/* Read the generic PCI resources */
|
||||
pci_dev_read_resources(dev);
|
||||
|
||||
/* If we are not the first processor don't allocate the gart apeture */
|
||||
if (dev->path.u.pci.devfn != PCI_DEVFN(CDB, 3)) {
|
||||
return;
|
||||
}
|
||||
|
||||
iommu = 1;
|
||||
get_option(&iommu, "iommu");
|
||||
|
||||
if (iommu) {
|
||||
/* Add a Gart apeture resource */
|
||||
resource = new_resource(dev, 0x94);
|
||||
resource->size = iommu?AGP_APERTURE_SIZE:1;
|
||||
resource->align = log2(resource->size);
|
||||
resource->gran = log2(resource->size);
|
||||
resource->limit = 0xffffffff; /* 4G */
|
||||
resource->flags = IORESOURCE_MEM;
|
||||
}
|
||||
}
|
||||
|
||||
static void set_agp_aperture(device_t dev)
|
||||
{
|
||||
struct resource *resource;
|
||||
|
||||
resource = probe_resource(dev, 0x94);
|
||||
if (resource) {
|
||||
device_t pdev;
|
||||
u32 gart_base, gart_acr;
|
||||
|
||||
/* Remember this resource has been stored */
|
||||
resource->flags |= IORESOURCE_STORED;
|
||||
|
||||
/* Find the size of the GART aperture */
|
||||
gart_acr = (0<<6)|(0<<5)|(0<<4)|((resource->gran - 25) << 1)|(0<<0);
|
||||
|
||||
/* Get the base address */
|
||||
gart_base = ((resource->base) >> 25) & 0x00007fff;
|
||||
|
||||
/* Update the other northbriges */
|
||||
pdev = 0;
|
||||
while((pdev = dev_find_device(PCI_VENDOR_ID_AMD, 0x1203, pdev))) {
|
||||
/* Store the GART size but don't enable it */
|
||||
pci_write_config32(pdev, 0x90, gart_acr);
|
||||
|
||||
/* Store the GART base address */
|
||||
pci_write_config32(pdev, 0x94, gart_base);
|
||||
|
||||
/* Don't set the GART Table base address */
|
||||
pci_write_config32(pdev, 0x98, 0);
|
||||
|
||||
/* Report the resource has been stored... */
|
||||
report_resource_stored(pdev, resource, " <gart>");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void mcf3_set_resources(device_t dev)
|
||||
{
|
||||
/* Set the gart apeture */
|
||||
set_agp_aperture(dev);
|
||||
|
||||
/* Set the generic PCI resources */
|
||||
pci_dev_set_resources(dev);
|
||||
}
|
||||
|
||||
static void misc_control_init(struct device *dev)
|
||||
{
|
||||
u32 cmd;
|
||||
|
||||
printk_debug("NB: Function 3 Misc Control.. ");
|
||||
|
||||
/* Disable Machine checks from Invalid Locations.
|
||||
* This is needed for PC backwards compatibility.
|
||||
*/
|
||||
cmd = pci_read_config32(dev, 0x44);
|
||||
cmd |= (1<<6) | (1<<25);
|
||||
pci_write_config32(dev, 0x44, cmd );
|
||||
|
||||
printk_debug("done.\n");
|
||||
}
|
||||
|
||||
|
||||
static struct device_operations mcf3_ops = {
|
||||
.read_resources = mcf3_read_resources,
|
||||
.set_resources = mcf3_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.init = misc_control_init,
|
||||
.scan_bus = 0,
|
||||
.ops_pci = 0,
|
||||
};
|
||||
|
||||
static struct pci_driver mcf3_driver __pci_driver = {
|
||||
.ops = &mcf3_ops,
|
||||
.vendor = PCI_VENDOR_ID_AMD,
|
||||
.device = 0x1203,
|
||||
};
|
||||
1477
src/northbridge/amd/amdfam10/northbridge.c
Normal file
1477
src/northbridge/amd/amdfam10/northbridge.c
Normal file
File diff suppressed because it is too large
Load Diff
25
src/northbridge/amd/amdfam10/northbridge.h
Normal file
25
src/northbridge/amd/amdfam10/northbridge.h
Normal file
@ -0,0 +1,25 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef NORTHBRIDGE_AMD_AMDFAM10_H
|
||||
#define NORTHBRIDGE_AMD_AMDFAM10_H
|
||||
|
||||
extern u32 amdfam10_scan_root_bus(device_t root, u32 max);
|
||||
|
||||
#endif /* NORTHBRIDGE_AMD_AMDFAM10_H */
|
||||
73
src/northbridge/amd/amdfam10/raminit.h
Normal file
73
src/northbridge/amd/amdfam10/raminit.h
Normal file
@ -0,0 +1,73 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef RAMINIT_H
|
||||
#define RAMINIT_H
|
||||
|
||||
#if 0
|
||||
#if DIMM_SUPPORT==0x0110
|
||||
//FBDIMM REG
|
||||
/* each channel can have 8 fbdimm */
|
||||
#define DIMM_SOCKETS 8
|
||||
struct mem_controller {
|
||||
u32 node_id;
|
||||
device_t f0, f1, f2, f3, f4, f5;
|
||||
/* channelA, channelB belong to DCT0,
|
||||
* channelC, channelD belong to DCT1
|
||||
* Each DCT may support one ganged logical FBDIMM ---> 128 bit
|
||||
* or a single unganged channel --->64 bit
|
||||
* a DCT can not support 2 unganged channels
|
||||
* two DCTs can not be ganged
|
||||
*/
|
||||
u8 spd_switch_addr;
|
||||
u8 spd_addr[DIMM_SOCKETS*4];
|
||||
};
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
//#if (DIMM_SUPPORT & 0x00ff)==0x0004
|
||||
//DDR2 REG and unbuffered : Socket F 1027 and AM3
|
||||
/* every channel have 4 DDR2 DIMM for socket F
|
||||
* 2 for socket M2/M3
|
||||
* 1 for socket s1g1
|
||||
*/
|
||||
#define DIMM_SOCKETS 4
|
||||
struct mem_controller {
|
||||
u32 node_id;
|
||||
device_t f0, f1, f2, f3, f4, f5;
|
||||
/* channel0 is DCT0 --- channelA
|
||||
* channel1 is DCT1 --- channelB
|
||||
* can be ganged, a single dual-channel DCT ---> 128 bit
|
||||
* or unganged a two single-channel DCTs ---> 64bit
|
||||
* When the DCTs are ganged, the writes to DCT1 set of registers
|
||||
* (F2x1XX) are ignored and reads return all 0's
|
||||
* The exception is the DCT phy registers, F2x[1,0]98, F2x[1,0]9C,
|
||||
* and all the associated indexed registers, are still
|
||||
* independently accessiable
|
||||
*/
|
||||
/* FIXME: I will only support ganged mode for easy support */
|
||||
u8 spd_switch_addr;
|
||||
u8 spd_addr[DIMM_SOCKETS*2];
|
||||
};
|
||||
|
||||
//#endif
|
||||
|
||||
|
||||
#endif
|
||||
155
src/northbridge/amd/amdfam10/raminit_amdmct.c
Normal file
155
src/northbridge/amd/amdfam10/raminit_amdmct.c
Normal file
@ -0,0 +1,155 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
|
||||
static void print_raminit(const char *strval, u32 val)
|
||||
{
|
||||
printk_debug("%s%08x\n", strval, val);
|
||||
}
|
||||
|
||||
|
||||
#define RAMINIT_DEBUG 1
|
||||
|
||||
|
||||
static void print_tx(const char *strval, u32 val)
|
||||
{
|
||||
#if RAMINIT_DEBUG == 1
|
||||
print_raminit(strval, val);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
static void print_t(const char *strval)
|
||||
{
|
||||
#if RAMINIT_DEBUG == 1
|
||||
print_debug(strval);
|
||||
#endif
|
||||
}
|
||||
#include "amdfam10.h"
|
||||
#include "../amdmct/wrappers/mcti.h"
|
||||
#include "../amdmct/amddefs.h"
|
||||
#include "../amdmct/mct/mct_d.h"
|
||||
#include "../amdmct/mct/mct_d_gcc.h"
|
||||
|
||||
#include "../amdmct/wrappers/mcti_d.c"
|
||||
#include "../amdmct/mct/mct_d.c"
|
||||
|
||||
|
||||
#include "../amdmct/mct/mctmtr_d.c"
|
||||
#include "../amdmct/mct/mctcsi_d.c"
|
||||
#include "../amdmct/mct/mctecc_d.c"
|
||||
#include "../amdmct/mct/mctpro_d.c"
|
||||
#include "../amdmct/mct/mctdqs_d.c"
|
||||
#include "../amdmct/mct/mctsrc.c"
|
||||
#include "../amdmct/mct/mctsrc1p.c"
|
||||
#include "../amdmct/mct/mcttmrl.c"
|
||||
#include "../amdmct/mct/mcthdi.c"
|
||||
#include "../amdmct/mct/mctndi_d.c"
|
||||
#include "../amdmct/mct/mctchi_d.c"
|
||||
|
||||
#if SYSTEM_TYPE == SERVER
|
||||
//L1
|
||||
#include "../amdmct/mct/mctardk3.c"
|
||||
#elif SYSTEM_TYPE == DESKTOP
|
||||
//AM2
|
||||
#include "../amdmct/mct/mctardk4.c"
|
||||
//#elif SYSTEM_TYPE == MOBILE
|
||||
//s1g1
|
||||
//#include "../amdmct/mct/mctardk5.c"
|
||||
#endif
|
||||
|
||||
#include "../amdmct/mct/mct_fd.c"
|
||||
|
||||
int mctRead_SPD(u32 smaddr, u32 reg)
|
||||
{
|
||||
return spd_read_byte(smaddr, reg);
|
||||
}
|
||||
|
||||
|
||||
void mctSMBhub_Init(u32 node)
|
||||
{
|
||||
struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
|
||||
struct mem_controller *ctrl = &( sysinfo->ctrl[node] );
|
||||
activate_spd_rom(ctrl);
|
||||
}
|
||||
|
||||
|
||||
void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node)
|
||||
{
|
||||
int j;
|
||||
struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
|
||||
struct mem_controller *ctrl = &( sysinfo->ctrl[node] );
|
||||
|
||||
for(j=0;j<DIMM_SOCKETS;j++) {
|
||||
pDCTstat->DIMMAddr[j*2] = ctrl->spd_addr[j] & 0xff;
|
||||
pDCTstat->DIMMAddr[j*2+1] = ctrl->spd_addr[DIMM_SOCKETS + j] & 0xff;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
u32 mctGetLogicalCPUID(u32 Node)
|
||||
{
|
||||
u32 dev;
|
||||
u32 val, valx;
|
||||
u32 family, model, stepping;
|
||||
u32 ret;
|
||||
dev = PA_NBMISC(Node);
|
||||
val = Get_NB32(dev, 0xfc);
|
||||
print_debug("Family_Model:"); print_debug_hex32(val); print_debug("\n");
|
||||
|
||||
family = ((val >> 8) & 0x0f) + ((val>>20) & 0xff);
|
||||
model = ((val>>4) & 0x0f) | ((val>>(16-4)) & 0xf0);
|
||||
stepping = val & 0xff;
|
||||
print_debug("Family:"); print_debug_hex8(family); print_debug("\t");
|
||||
print_debug("Model:"); print_debug_hex8(model); print_debug("\t");
|
||||
print_debug("Stepping:"); print_debug_hex8(stepping); print_debug("\n");
|
||||
|
||||
valx = (family<<12) | (model<<4) | (stepping);
|
||||
print_debug("converted:"); print_debug_hex32(valx); print_debug("\n");
|
||||
|
||||
switch (valx) {
|
||||
case 0x10000:
|
||||
ret = AMD_DR_A0A;
|
||||
break;
|
||||
case 0x10001:
|
||||
ret = AMD_DR_A1B;
|
||||
break;
|
||||
case 0x10002:
|
||||
ret = AMD_DR_A2;
|
||||
break;
|
||||
default:
|
||||
ret = 0;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
void raminit_amdmct(struct sys_info *sysinfo)
|
||||
{
|
||||
struct MCTStatStruc *pMCTstat = &(sysinfo->MCTstat);
|
||||
struct DCTStatStruc *pDCTstatA = sysinfo->DCTstatA;
|
||||
|
||||
print_debug("raminit_amdmct begin:\n");
|
||||
|
||||
mctAutoInitMCT_D(pMCTstat, pDCTstatA);
|
||||
|
||||
print_debug("raminit_amdmct end:\n");
|
||||
}
|
||||
81
src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c
Normal file
81
src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c
Normal file
@ -0,0 +1,81 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
|
||||
static void set_htic_bit(u8 i, u32 val, u8 bit)
|
||||
{
|
||||
u32 dword;
|
||||
dword = pci_read_config32(NODE_PCI(i, 0), HT_INIT_CONTROL);
|
||||
dword &= ~(1<<bit);
|
||||
dword |= ((val & 1) <<bit);
|
||||
pci_write_config32(NODE_PCI(i, 0), HT_INIT_CONTROL, dword);
|
||||
}
|
||||
|
||||
|
||||
static u32 get_htic_bit(u8 i, u8 bit)
|
||||
{
|
||||
u32 dword;
|
||||
dword = pci_read_config32(NODE_PCI(i, 0), HT_INIT_CONTROL);
|
||||
dword &= (1<<bit);
|
||||
return dword;
|
||||
}
|
||||
|
||||
static void wait_till_sysinfo_in_ram(void)
|
||||
{
|
||||
while(1) {
|
||||
/* give the NB a break, many CPUs spinning on one bit makes a
|
||||
* lot of traffic and time is not too important to APs.
|
||||
*/
|
||||
udelay_tsc(1000);
|
||||
if(get_htic_bit(0, 9)) return;
|
||||
}
|
||||
}
|
||||
|
||||
static void set_sysinfo_in_ram(u32 val)
|
||||
{
|
||||
set_htic_bit(0, val, 9);
|
||||
}
|
||||
|
||||
static void fill_mem_ctrl(u32 controllers, struct mem_controller *ctrl_a, const u8 *spd_addr)
|
||||
{
|
||||
int i;
|
||||
int j;
|
||||
int index = 0;
|
||||
struct mem_controller *ctrl;
|
||||
for(i=0;i<controllers; i++) {
|
||||
ctrl = &ctrl_a[i];
|
||||
ctrl->node_id = i;
|
||||
ctrl->f0 = NODE_PCI(i, 0);
|
||||
ctrl->f1 = NODE_PCI(i, 1);
|
||||
ctrl->f2 = NODE_PCI(i, 2);
|
||||
ctrl->f3 = NODE_PCI(i, 3);
|
||||
ctrl->f4 = NODE_PCI(i, 4);
|
||||
ctrl->f5 = NODE_PCI(i, 5);
|
||||
|
||||
if(spd_addr == (void *)0) continue;
|
||||
|
||||
ctrl->spd_switch_addr = spd_addr[index++];
|
||||
|
||||
for(j=0; j < 8; j++) {
|
||||
ctrl->spd_addr[j] = spd_addr[index++];
|
||||
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
169
src/northbridge/amd/amdfam10/reset_test.c
Normal file
169
src/northbridge/amd/amdfam10/reset_test.c
Normal file
@ -0,0 +1,169 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
|
||||
#define NODE_ID 0x60
|
||||
#define HT_INIT_CONTROL 0x6c
|
||||
#define HTIC_ColdR_Detect (1<<4)
|
||||
#define HTIC_BIOSR_Detect (1<<5)
|
||||
#define HTIC_INIT_Detect (1<<6)
|
||||
|
||||
/* mmconf is not ready */
|
||||
/* io_ext is not ready */
|
||||
static u32 cpu_init_detected(u8 nodeid)
|
||||
{
|
||||
u32 htic;
|
||||
device_t dev;
|
||||
|
||||
dev = NODE_PCI(nodeid, 0);
|
||||
htic = pci_io_read_config32(dev, HT_INIT_CONTROL);
|
||||
|
||||
return !!(htic & HTIC_INIT_Detect);
|
||||
}
|
||||
|
||||
static u32 bios_reset_detected(void)
|
||||
{
|
||||
u32 htic;
|
||||
htic = pci_io_read_config32(PCI_DEV(CBB, CDB, 0), HT_INIT_CONTROL);
|
||||
|
||||
return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect);
|
||||
}
|
||||
|
||||
static u32 cold_reset_detected(void)
|
||||
{
|
||||
u32 htic;
|
||||
htic = pci_io_read_config32(PCI_DEV(CBB, CDB, 0), HT_INIT_CONTROL);
|
||||
|
||||
return !(htic & HTIC_ColdR_Detect);
|
||||
}
|
||||
|
||||
static u32 other_reset_detected(void) // other warm reset not started by BIOS
|
||||
{
|
||||
u32 htic;
|
||||
htic = pci_io_read_config32(PCI_DEV(CBB, CDB, 0), HT_INIT_CONTROL);
|
||||
|
||||
return (htic & HTIC_ColdR_Detect) && (htic & HTIC_BIOSR_Detect);
|
||||
}
|
||||
|
||||
static void distinguish_cpu_resets(u8 nodeid)
|
||||
{
|
||||
u32 htic;
|
||||
device_t device;
|
||||
device = NODE_PCI(nodeid, 0);
|
||||
htic = pci_io_read_config32(device, HT_INIT_CONTROL);
|
||||
htic |= HTIC_ColdR_Detect | HTIC_BIOSR_Detect | HTIC_INIT_Detect;
|
||||
pci_io_write_config32(device, HT_INIT_CONTROL, htic);
|
||||
}
|
||||
|
||||
static u32 warm_reset_detect(u8 nodeid)
|
||||
{
|
||||
u32 htic;
|
||||
device_t device;
|
||||
device = NODE_PCI(nodeid, 0);
|
||||
htic = pci_io_read_config32(device, HT_INIT_CONTROL);
|
||||
return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect);
|
||||
}
|
||||
|
||||
static void set_bios_reset(void)
|
||||
{
|
||||
|
||||
u32 nodes;
|
||||
u32 htic;
|
||||
device_t dev;
|
||||
int i;
|
||||
|
||||
nodes = ((pci_read_config32(PCI_DEV(CBB, CDB, 0), 0x60) >> 4) & 7) + 1;
|
||||
|
||||
for(i = 0; i < nodes; i++) {
|
||||
dev = NODE_PCI(i,0);
|
||||
htic = pci_read_config32(dev, HT_INIT_CONTROL);
|
||||
htic &= ~HTIC_BIOSR_Detect;
|
||||
pci_write_config32(dev, HT_INIT_CONTROL, htic);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* Look up a which bus a given node/link combination is on.
|
||||
* return 0 when we can't find the answer.
|
||||
*/
|
||||
static u8 node_link_to_bus(u8 node, u8 link) // node are 6 bit, and link three bit
|
||||
{
|
||||
u32 reg;
|
||||
u32 val;
|
||||
|
||||
// put node and link in correct bit
|
||||
val = ((node & 0x0f)<<4) | ((node & 0x30)<< (12-4)) | ((link & 0x07)<<8) ;
|
||||
|
||||
for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
|
||||
u32 config_map;
|
||||
config_map = pci_io_read_config32(PCI_DEV(CBB, CDB, 1), reg);
|
||||
if ((config_map & 3) != 3) {
|
||||
continue;
|
||||
}
|
||||
if ((config_map & (((63 & 0x0f)<<4) | ((63 & 0x30)<< (12-4)) | ((7 & 0x07)<<8) )
|
||||
) == val )
|
||||
{
|
||||
return (config_map >> 16) & 0xff;
|
||||
}
|
||||
}
|
||||
|
||||
#if EXT_CONF_SUPPORT == 1
|
||||
// let's check that in extend space
|
||||
// use the nodeid extend space to find out the bus for the linkn
|
||||
u32 tempreg;
|
||||
int i;
|
||||
int j;
|
||||
u32 cfg_map_dest;
|
||||
device_t dev;
|
||||
|
||||
cfg_map_dest = (1<<7)|(1<<6)|link;
|
||||
|
||||
// three case: index_min==index_max, index_min+1=index_max; index_min+1<index_max
|
||||
dev = NODE_PCI(node, 1);
|
||||
for(j=0; j<64; j++) {
|
||||
pci_io_write_config32(dev, 0x110, j | (6<<28));
|
||||
tempreg = pci_io_read_config32(dev, 0x114);
|
||||
for(i=0; i<=3; i++) {
|
||||
tempreg >>= (i*8);
|
||||
if((tempreg & ((1<<7)|(1<<6)|0x3f)) == cfg_map_dest) {
|
||||
return (i+(j<<2)); //busn_min
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static u32 get_sblk(void)
|
||||
{
|
||||
u32 reg;
|
||||
/* read PCI_DEV(CBB,CDB,0) 0x64 bit [8:9] to find out SbLink m */
|
||||
reg = pci_io_read_config32(PCI_DEV(CBB, CDB, 0), 0x64);
|
||||
return ((reg>>8) & 3) ;
|
||||
}
|
||||
|
||||
|
||||
static u8 get_sbbusn(u8 sblk)
|
||||
{
|
||||
return node_link_to_bus(0, sblk);
|
||||
}
|
||||
|
||||
287
src/northbridge/amd/amdfam10/resourcemap.c
Normal file
287
src/northbridge/amd/amdfam10/resourcemap.c
Normal file
@ -0,0 +1,287 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
static void setup_default_resource_map(void)
|
||||
{
|
||||
static const u32 register_values[] = {
|
||||
/* Careful set limit registers before base registers which contain
|
||||
the enables */
|
||||
/* DRAM Limit i Registers
|
||||
* F1:0x44 i = 0
|
||||
* F1:0x4C i = 1
|
||||
* F1:0x54 i = 2
|
||||
* F1:0x5C i = 3
|
||||
* F1:0x64 i = 4
|
||||
* F1:0x6C i = 5
|
||||
* F1:0x74 i = 6
|
||||
* F1:0x7C i = 7
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 7: 3] Reserved
|
||||
* [10: 8] Interleave select
|
||||
* specifies the values of A[14:12] to use with
|
||||
* interleave enable.
|
||||
* [15:11] Reserved
|
||||
* [31:16] DRAM Limit Address i Bits 39-24
|
||||
* This field defines the upper address bits of a 40 bit
|
||||
* address that define the end of the DRAM region.
|
||||
*/
|
||||
PCI_ADDR(CBB, CDB, 1, 0x44), 0x0000f8f8, 0x00000000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0x4C), 0x0000f8f8, 0x00000001,
|
||||
PCI_ADDR(CBB, CDB, 1, 0x54), 0x0000f8f8, 0x00000002,
|
||||
PCI_ADDR(CBB, CDB, 1, 0x5C), 0x0000f8f8, 0x00000003,
|
||||
PCI_ADDR(CBB, CDB, 1, 0x64), 0x0000f8f8, 0x00000004,
|
||||
PCI_ADDR(CBB, CDB, 1, 0x6C), 0x0000f8f8, 0x00000005,
|
||||
PCI_ADDR(CBB, CDB, 1, 0x74), 0x0000f8f8, 0x00000006,
|
||||
PCI_ADDR(CBB, CDB, 1, 0x7C), 0x0000f8f8, 0x00000007,
|
||||
/* DRAM Base i Registers
|
||||
* F1:0x40 i = 0
|
||||
* F1:0x48 i = 1
|
||||
* F1:0x50 i = 2
|
||||
* F1:0x58 i = 3
|
||||
* F1:0x60 i = 4
|
||||
* F1:0x68 i = 5
|
||||
* F1:0x70 i = 6
|
||||
* F1:0x78 i = 7
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 7: 2] Reserved
|
||||
* [10: 8] Interleave Enable
|
||||
* 000 = No interleave
|
||||
* 001 = Interleave on A[12] (2 nodes)
|
||||
* 010 = reserved
|
||||
* 011 = Interleave on A[12] and A[14] (4 nodes)
|
||||
* 100 = reserved
|
||||
* 101 = reserved
|
||||
* 110 = reserved
|
||||
* 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
|
||||
* [15:11] Reserved
|
||||
* [13:16] DRAM Base Address i Bits 39-24
|
||||
* This field defines the upper address bits of a 40-bit
|
||||
* address that define the start of the DRAM region.
|
||||
*/
|
||||
PCI_ADDR(CBB, CDB, 1, 0x40), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0x48), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0x50), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0x60), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0x68), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0x70), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0x78), 0x0000f8fc, 0x00000000,
|
||||
|
||||
/* Memory-Mapped I/O Limit i Registers
|
||||
* F1:0x84 i = 0
|
||||
* F1:0x8C i = 1
|
||||
* F1:0x94 i = 2
|
||||
* F1:0x9C i = 3
|
||||
* F1:0xA4 i = 4
|
||||
* F1:0xAC i = 5
|
||||
* F1:0xB4 i = 6
|
||||
* F1:0xBC i = 7
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 3: 3] Reserved
|
||||
* [ 5: 4] Destination Link ID
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 = Reserved
|
||||
* [ 6: 6] Reserved
|
||||
* [ 7: 7] Non-Posted
|
||||
* 0 = CPU writes may be posted
|
||||
* 1 = CPU writes must be non-posted
|
||||
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
|
||||
* This field defines the upp adddress bits of a 40-bit
|
||||
* address that defines the end of a memory-mapped
|
||||
* I/O region n
|
||||
*/
|
||||
PCI_ADDR(CBB, CDB, 1, 0x84), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0x8C), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0x94), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0x9C), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0xA4), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0xAC), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0xB4), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0xBC), 0x00000048, 0x00ffff00,
|
||||
|
||||
/* Memory-Mapped I/O Base i Registers
|
||||
* F1:0x80 i = 0
|
||||
* F1:0x88 i = 1
|
||||
* F1:0x90 i = 2
|
||||
* F1:0x98 i = 3
|
||||
* F1:0xA0 i = 4
|
||||
* F1:0xA8 i = 5
|
||||
* F1:0xB0 i = 6
|
||||
* F1:0xB8 i = 7
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 2: 2] Cpu Disable
|
||||
* 0 = Cpu can use this I/O range
|
||||
* 1 = Cpu requests do not use this I/O range
|
||||
* [ 3: 3] Lock
|
||||
* 0 = base/limit registers i are read/write
|
||||
* 1 = base/limit registers i are read-only
|
||||
* [ 7: 4] Reserved
|
||||
* [31: 8] Memory-Mapped I/O Base Address i (39-16)
|
||||
* This field defines the upper address bits of a 40bit
|
||||
* address that defines the start of memory-mapped
|
||||
* I/O region i
|
||||
*/
|
||||
PCI_ADDR(CBB, CDB, 1, 0x80), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0x88), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0x90), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0x98), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0xA0), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0xA8), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0xB0), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0xB8), 0x000000f0, 0x00fc0003,
|
||||
|
||||
/* PCI I/O Limit i Registers
|
||||
* F1:0xC4 i = 0
|
||||
* F1:0xCC i = 1
|
||||
* F1:0xD4 i = 2
|
||||
* F1:0xDC i = 3
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 3: 3] Reserved
|
||||
* [ 5: 4] Destination Link ID
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 = reserved
|
||||
* [11: 6] Reserved
|
||||
* [24:12] PCI I/O Limit Address i
|
||||
* This field defines the end of PCI I/O region n
|
||||
* [31:25] Reserved
|
||||
*/
|
||||
PCI_ADDR(CBB, CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
|
||||
|
||||
/* PCI I/O Base i Registers
|
||||
* F1:0xC0 i = 0
|
||||
* F1:0xC8 i = 1
|
||||
* F1:0xD0 i = 2
|
||||
* F1:0xD8 i = 3
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 3: 2] Reserved
|
||||
* [ 4: 4] VGA Enable
|
||||
* 0 = VGA matches Disabled
|
||||
* 1 = matches all address < 64K and where A[9:0] is in
|
||||
* the range 3B0-3BB or 3C0-3DF independent of the
|
||||
* base & limit registers
|
||||
* [ 5: 5] ISA Enable
|
||||
* 0 = ISA matches Disabled
|
||||
* 1 = Blocks address < 64K and in the last 768 bytes of
|
||||
* eack 1K block from matching agains this base/limit
|
||||
* pair
|
||||
* [11: 6] Reserved
|
||||
* [24:12] PCI I/O Base i
|
||||
* This field defines the start of PCI I/O region n
|
||||
* [31:25] Reserved
|
||||
*/
|
||||
PCI_ADDR(CBB, CDB, 1, 0xC0), 0xFE000FCC, 0x00000003,
|
||||
PCI_ADDR(CBB, CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
|
||||
|
||||
/* Config Base and Limit i Registers
|
||||
* F1:0xE0 i = 0
|
||||
* F1:0xE4 i = 1
|
||||
* F1:0xE8 i = 2
|
||||
* F1:0xEC i = 3
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 2: 2] Device Number Compare Enable
|
||||
* 0 = The ranges are based on bus number
|
||||
* 1 = The ranges are ranges of devices on bus 0
|
||||
* [ 3: 3] Reserved
|
||||
* [ 6: 4] Destination Node
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 7: 7] Reserved
|
||||
* [ 9: 8] Destination Link
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 - Reserved
|
||||
* [15:10] Reserved
|
||||
* [23:16] Bus Number Base i
|
||||
* This field defines the lowest bus number in
|
||||
* configuration region i
|
||||
* [31:24] Bus Number Limit i
|
||||
* This field defines the highest bus number in
|
||||
* configuration regin i
|
||||
*/
|
||||
PCI_ADDR(CBB, CDB, 1, 0xE0), 0x0000FC88, 0xff000003,
|
||||
PCI_ADDR(CBB, CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
|
||||
};
|
||||
|
||||
u32 max;
|
||||
max = sizeof(register_values)/sizeof(register_values[0]);
|
||||
setup_resource_map(register_values, max);
|
||||
}
|
||||
|
||||
1
src/northbridge/amd/amdfam10/root_complex/Config.lb
Normal file
1
src/northbridge/amd/amdfam10/root_complex/Config.lb
Normal file
@ -0,0 +1 @@
|
||||
config chip.h
|
||||
24
src/northbridge/amd/amdfam10/root_complex/chip.h
Normal file
24
src/northbridge/amd/amdfam10/root_complex/chip.h
Normal file
@ -0,0 +1,24 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
struct northbridge_amd_amdfam10_root_complex_config
|
||||
{
|
||||
};
|
||||
|
||||
extern struct chip_operations northbridge_amd_amdfam10_root_complex_ops;
|
||||
231
src/northbridge/amd/amdfam10/setup_resource_map.c
Normal file
231
src/northbridge/amd/amdfam10/setup_resource_map.c
Normal file
@ -0,0 +1,231 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
|
||||
#define RES_DEBUG 0
|
||||
|
||||
static void setup_resource_map(const u32 *register_values, u32 max)
|
||||
{
|
||||
u32 i;
|
||||
// print_debug("setting up resource map....");
|
||||
|
||||
for(i = 0; i < max; i += 3) {
|
||||
device_t dev;
|
||||
u32 where;
|
||||
u32 reg;
|
||||
|
||||
dev = register_values[i] & ~0xff;
|
||||
where = register_values[i] & 0xff;
|
||||
reg = pci_read_config32(dev, where);
|
||||
reg &= register_values[i+1];
|
||||
reg |= register_values[i+2];
|
||||
pci_write_config32(dev, where, reg);
|
||||
}
|
||||
// print_debug("done.\n");
|
||||
}
|
||||
|
||||
|
||||
static void setup_resource_map_offset(const u32 *register_values,
|
||||
u32 max, u32 offset_pci_dev,
|
||||
u32 offset_io_base)
|
||||
{
|
||||
u32 i;
|
||||
// print_debug("setting up resource map offset....");
|
||||
for(i = 0; i < max; i += 3) {
|
||||
device_t dev;
|
||||
u32 where;
|
||||
unsigned long reg;
|
||||
dev = (register_values[i] & ~0xfff) + offset_pci_dev;
|
||||
where = register_values[i] & 0xfff;
|
||||
reg = pci_read_config32(dev, where);
|
||||
reg &= register_values[i+1];
|
||||
reg |= register_values[i+2] + offset_io_base;
|
||||
pci_write_config32(dev, where, reg);
|
||||
}
|
||||
// print_debug("done.\n");
|
||||
}
|
||||
|
||||
#define RES_PCI_IO 0x10
|
||||
#define RES_PORT_IO_8 0x22
|
||||
#define RES_PORT_IO_32 0x20
|
||||
#define RES_MEM_IO 0x40
|
||||
|
||||
static void setup_resource_map_x_offset(const u32 *register_values, u32 max,
|
||||
u32 offset_pci_dev, u32 offset_io_base)
|
||||
{
|
||||
u32 i;
|
||||
|
||||
#if RES_DEBUG
|
||||
print_debug("setting up resource map ex offset....");
|
||||
|
||||
#endif
|
||||
|
||||
#if RES_DEBUG
|
||||
print_debug("\n");
|
||||
#endif
|
||||
for(i = 0; i < max; i += 4) {
|
||||
#if RES_DEBUG
|
||||
printk_debug("%04x: %02x %08x <- & %08x | %08x\n",
|
||||
i/4, register_values[i],
|
||||
register_values[i+1] + ( (register_values[i]==RES_PCI_IO) ? offset_pci_dev : 0),
|
||||
register_values[i+2],
|
||||
register_values[i+3] + ( ( (register_values[i] & RES_PORT_IO_32) == RES_PORT_IO_32) ? offset_io_base : 0)
|
||||
);
|
||||
#endif
|
||||
switch (register_values[i]) {
|
||||
case RES_PCI_IO: //PCI
|
||||
{
|
||||
device_t dev;
|
||||
u32 where;
|
||||
u32 reg;
|
||||
dev = (register_values[i+1] & ~0xfff) + offset_pci_dev;
|
||||
where = register_values[i+1] & 0xfff;
|
||||
reg = pci_read_config32(dev, where);
|
||||
reg &= register_values[i+2];
|
||||
reg |= register_values[i+3];
|
||||
pci_write_config32(dev, where, reg);
|
||||
}
|
||||
break;
|
||||
case RES_PORT_IO_8: // io 8
|
||||
{
|
||||
u32 where;
|
||||
u32 reg;
|
||||
where = register_values[i+1] + offset_io_base;
|
||||
reg = inb(where);
|
||||
reg &= register_values[i+2];
|
||||
reg |= register_values[i+3];
|
||||
outb(reg, where);
|
||||
}
|
||||
break;
|
||||
case RES_PORT_IO_32: //io32
|
||||
{
|
||||
u32 where;
|
||||
u32 reg;
|
||||
where = register_values[i+1] + offset_io_base;
|
||||
reg = inl(where);
|
||||
reg &= register_values[i+2];
|
||||
reg |= register_values[i+3];
|
||||
outl(reg, where);
|
||||
}
|
||||
break;
|
||||
} // switch
|
||||
|
||||
|
||||
}
|
||||
|
||||
#if RES_DEBUG
|
||||
print_debug("done.\n");
|
||||
#endif
|
||||
}
|
||||
static void setup_resource_map_x(const u32 *register_values, u32 max)
|
||||
{
|
||||
u32 i;
|
||||
|
||||
#if RES_DEBUG
|
||||
print_debug("setting up resource map ex offset....");
|
||||
#endif
|
||||
|
||||
#if RES_DEBUG
|
||||
print_debug("\n");
|
||||
#endif
|
||||
for(i = 0; i < max; i += 4) {
|
||||
#if RES_DEBUG
|
||||
printk_debug("%04x: %02x %08x <- & %08x | %08x\n",
|
||||
i/4, register_values[i],register_values[i+1], register_values[i+2], register_values[i+3]);
|
||||
#endif
|
||||
switch (register_values[i]) {
|
||||
case RES_PCI_IO: //PCI
|
||||
{
|
||||
device_t dev;
|
||||
u32 where;
|
||||
u32 reg;
|
||||
dev = register_values[i+1] & ~0xff;
|
||||
where = register_values[i+1] & 0xff;
|
||||
reg = pci_read_config32(dev, where);
|
||||
reg &= register_values[i+2];
|
||||
reg |= register_values[i+3];
|
||||
pci_write_config32(dev, where, reg);
|
||||
}
|
||||
break;
|
||||
case RES_PORT_IO_8: // io 8
|
||||
{
|
||||
u32 where;
|
||||
u32 reg;
|
||||
where = register_values[i+1];
|
||||
reg = inb(where);
|
||||
reg &= register_values[i+2];
|
||||
reg |= register_values[i+3];
|
||||
outb(reg, where);
|
||||
}
|
||||
break;
|
||||
case RES_PORT_IO_32: //io32
|
||||
{
|
||||
u32 where;
|
||||
u32 reg;
|
||||
where = register_values[i+1];
|
||||
reg = inl(where);
|
||||
reg &= register_values[i+2];
|
||||
reg |= register_values[i+3];
|
||||
outl(reg, where);
|
||||
}
|
||||
break;
|
||||
} // switch
|
||||
|
||||
|
||||
}
|
||||
|
||||
#if RES_DEBUG
|
||||
print_debug("done.\n");
|
||||
#endif
|
||||
}
|
||||
|
||||
static void setup_iob_resource_map(const u32 *register_values, u32 max)
|
||||
{
|
||||
u32 i;
|
||||
|
||||
for(i = 0; i < max; i += 3) {
|
||||
u32 where;
|
||||
u32 reg;
|
||||
|
||||
where = register_values[i];
|
||||
reg = inb(where);
|
||||
reg &= register_values[i+1];
|
||||
reg |= register_values[i+2];
|
||||
outb(reg, where);
|
||||
}
|
||||
}
|
||||
|
||||
static void setup_io_resource_map(const u32 *register_values, u32 max)
|
||||
{
|
||||
u32 i;
|
||||
|
||||
for(i = 0; i < max; i += 3) {
|
||||
u32 where;
|
||||
u32 reg;
|
||||
|
||||
where = register_values[i];
|
||||
reg = inl(where);
|
||||
reg &= register_values[i+1];
|
||||
reg |= register_values[i+2];
|
||||
|
||||
outl(reg, where);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
88
src/northbridge/amd/amdfam10/spd_ddr2.h
Normal file
88
src/northbridge/amd/amdfam10/spd_ddr2.h
Normal file
@ -0,0 +1,88 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/* SPDs for DDR2 SDRAM */
|
||||
#define SPD_MEM_TYPE 2
|
||||
#define SPD_MEM_TYPE_SDRAM_DDR 0x07
|
||||
#define SPD_MEM_TYPE_SDRAM_DDR2 0x08
|
||||
|
||||
#define SPD_DIMM_TYPE 20 /* x bit0 or bit4 =1 mean registered*/
|
||||
#define SPD_DIMM_TYPE_RDIMM (1<<0)
|
||||
#define SPD_DIMM_TYPE_UDIMM (1<<1)
|
||||
#define SPD_DIMM_TYPE_SODIMM (1<<2)
|
||||
#define SPD_DIMM_TYPE_uDIMM (1<<3)
|
||||
#define SPD_DIMM_TYPE_mRDIMM (1<<4)
|
||||
#define SPD_DIMM_TYPE_mUDIMM (1<<5)
|
||||
#define SPD_MOD_ATTRIB 21
|
||||
#define SPD_MOD_ATTRIB_DIFCK 0x20
|
||||
#define SPD_MOD_ATTRIB_REGADC 0x11 /* x */
|
||||
#define SPD_MOD_ATTRIB_PROBE 0x40
|
||||
|
||||
#define SPD_DEV_ATTRIB 22 /* Device attributes --- general */
|
||||
#define SPD_DIMM_CONF_TYPE 11
|
||||
#define SPD_DIMM_CONF_TYPE_ECC 0x02
|
||||
#define SPD_DIMM_CONF_TYPE_ADDR_PARITY 0x04 /* ? */
|
||||
|
||||
#define SPD_ROW_NUM 3 /* Number of Row addresses */
|
||||
#define SPD_COL_NUM 4 /* Number of Column addresses */
|
||||
#define SPD_BANK_NUM 17 /* SDRAM Device attributes - Number of Banks on
|
||||
SDRAM device, it could be 0x4, 0x8, so address
|
||||
lines for that would be 2, and 3 */
|
||||
|
||||
/* Number of Ranks bit [2:0], Package (bit4, 1=stack, 0=planr), Height bit[7:5] */
|
||||
#define SPD_MOD_ATTRIB_RANK 5
|
||||
#define SPD_MOD_ATTRIB_RANK_NUM_SHIFT 0
|
||||
#define SPD_MOD_ATTRIB_RANK_NUM_MASK 0x07
|
||||
#define SPD_MOD_ATTRIB_RANK_NUM_BASE 1
|
||||
#define SPD_MOD_ATTRIB_RANK_NUM_MIN 1
|
||||
#define SPD_MOD_ATTRIB_RANK_NUM_MAX 8
|
||||
|
||||
#define SPD_RANK_SIZE 31 /* Only one bit is set */
|
||||
#define SPD_RANK_SIZE_1GB (1<<0)
|
||||
#define SPD_RANK_SIZE_2GB (1<<1)
|
||||
#define SPD_RANK_SIZE_4GB (1<<2)
|
||||
#define SPD_RANK_SIZE_8GB (1<<3)
|
||||
#define SPD_RANK_SIZE_16GB (1<<4)
|
||||
#define SPD_RANK_SIZE_128MB (1<<5)
|
||||
#define SPD_RANK_SIZE_256MB (1<<6)
|
||||
#define SPD_RANK_SIZE_512MB (1<<7)
|
||||
|
||||
#define SPD_DATA_WIDTH 6 /* valid value 0, 32, 33, 36, 64, 72, 80, 128, 144, 254, 255 */
|
||||
#define SPD_PRI_WIDTH 13 /* Primary SDRAM Width, it could be 0x08 or 0x10 */
|
||||
#define SPD_ERR_WIDTH 14 /* Error Checking SDRAM Width, it could be 0x08 or 0x10 */
|
||||
|
||||
#define SPD_CAS_LAT 18 /* SDRAM Device Attributes -- CAS Latency */
|
||||
#define SPD_CAS_LAT_2 (1<<2)
|
||||
#define SPD_CAS_LAT_3 (1<<3)
|
||||
#define SPD_CAS_LAT_4 (1<<4)
|
||||
#define SPD_CAS_LAT_5 (1<<5)
|
||||
#define SPD_CAS_LAT_6 (1<<6)
|
||||
|
||||
#define SPD_TRP 27 /* bit [7:2] = 1-63 ns, bit [1:0] 0.25ns+, final value ((val>>2) + (val & 3) * 0.25)ns */
|
||||
#define SPD_TRRD 28
|
||||
#define SPD_TRCD 29
|
||||
#define SPD_TRAS 30
|
||||
#define SPD_TWR 36 /* x */
|
||||
#define SPD_TWTR 37 /* x */
|
||||
#define SPD_TRTP 38 /* x */
|
||||
|
||||
#define SPD_TRC 41 /* add byte 0x40 bit [3:1] , so final val41+ table[((val40>>1) & 0x7)] ... table[]={0, 0.25, 0.33, 0.5, 0.75, 0, 0}*/
|
||||
#define SPD_TRFC 42 /* add byte 0x40 bit [6:4] , so final val42+ table[((val40>>4) & 0x7)] + (val40 & 1)*256*/
|
||||
|
||||
#define SPD_TREF 12
|
||||
346
src/northbridge/amd/amdfam10/ssdt.dsl
Normal file
346
src/northbridge/amd/amdfam10/ssdt.dsl
Normal file
@ -0,0 +1,346 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* Make sure HC_NUMS and HC_POSSIBLE_NUM setting is consistent to this file
|
||||
*/
|
||||
|
||||
DefinitionBlock ("SSDT.aml", "SSDT", 1, "AMD-FAM10", "AMD-ACPI", 100925440)
|
||||
{
|
||||
/*
|
||||
* These objects were referenced but not defined in this table
|
||||
*/
|
||||
External (\_SB_.PCI0, DeviceObj)
|
||||
|
||||
Scope (\_SB.PCI0)
|
||||
{
|
||||
Name (BUSN, Package (0x20) /* HC_NUMS */
|
||||
{
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x33333333,
|
||||
0x44444444,
|
||||
0x55555555,
|
||||
0x66666666,
|
||||
0x77777777,
|
||||
0x88888888,
|
||||
0x99999999,
|
||||
0xaaaaaaaa,
|
||||
0xbbbbbbbb,
|
||||
0xcccccccc,
|
||||
0xdddddddd,
|
||||
0xeeeeeeee,
|
||||
0x10101010,
|
||||
0x11111111,
|
||||
0x12121212,
|
||||
0x13131313,
|
||||
0x14141414,
|
||||
0x15151515,
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x33333333,
|
||||
0x44444444,
|
||||
0x55555555,
|
||||
0x66666666,
|
||||
0x77777777,
|
||||
0x88888888,
|
||||
0x99999999,
|
||||
0xaaaaaaaa,
|
||||
0xbbbbbbbb,
|
||||
0xcccccccc
|
||||
})
|
||||
Name (MMIO, Package (0x80) /* HC_NUMS * 4 */
|
||||
{
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x33333333,
|
||||
0x44444444,
|
||||
0x55555555,
|
||||
0x66666666,
|
||||
0x77777777,
|
||||
0x88888888,
|
||||
0x99999999,
|
||||
0xaaaaaaaa,
|
||||
0xbbbbbbbb,
|
||||
0xcccccccc,
|
||||
0xdddddddd,
|
||||
0xeeeeeeee,
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x33333333,
|
||||
0x44444444,
|
||||
0x55555555,
|
||||
0x66666666,
|
||||
0x77777777,
|
||||
0x88888888,
|
||||
0x99999999,
|
||||
0xaaaaaaaa,
|
||||
0xbbbbbbbb,
|
||||
0xcccccccc,
|
||||
0xdddddddd,
|
||||
0xeeeeeeee,
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x33333333,
|
||||
0x44444444,
|
||||
0x55555555,
|
||||
0x66666666,
|
||||
0x77777777,
|
||||
0x88888888,
|
||||
0x99999999,
|
||||
0xaaaaaaaa,
|
||||
0xbbbbbbbb,
|
||||
0xcccccccc,
|
||||
0xdddddddd,
|
||||
0xeeeeeeee,
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x33333333,
|
||||
0x44444444,
|
||||
0x55555555,
|
||||
0x66666666,
|
||||
0x77777777,
|
||||
0x88888888,
|
||||
0x99999999,
|
||||
0xaaaaaaaa,
|
||||
0xbbbbbbbb,
|
||||
0xcccccccc,
|
||||
0xdddddddd,
|
||||
0xeeeeeeee,
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x33333333,
|
||||
0x44444444,
|
||||
0x55555555,
|
||||
0x66666666,
|
||||
0x77777777,
|
||||
0x88888888,
|
||||
0x99999999,
|
||||
0xaaaaaaaa,
|
||||
0xbbbbbbbb,
|
||||
0xcccccccc,
|
||||
0xdddddddd,
|
||||
0xeeeeeeee,
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x33333333,
|
||||
0x44444444,
|
||||
0x55555555,
|
||||
0x66666666,
|
||||
0x77777777,
|
||||
0x88888888,
|
||||
0x99999999,
|
||||
0xaaaaaaaa,
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x33333333,
|
||||
0x44444444,
|
||||
0x55555555,
|
||||
0x66666666,
|
||||
0x77777777,
|
||||
0x88888888,
|
||||
0x99999999,
|
||||
0xaaaaaaaa,
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x33333333,
|
||||
0x44444444,
|
||||
0x55555555,
|
||||
0x66666666,
|
||||
0x77777777,
|
||||
0x88888888,
|
||||
0x99999999,
|
||||
0xaaaaaaaa,
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x33333333,
|
||||
0x44444444,
|
||||
0x55555555,
|
||||
0x66666666,
|
||||
0x77777777,
|
||||
0x88888888,
|
||||
0x99999999,
|
||||
0xaaaaaaaa,
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x33333333,
|
||||
0x44444444,
|
||||
0x55555555,
|
||||
0x66666666,
|
||||
0x77777777,
|
||||
0x88888888
|
||||
})
|
||||
Name (PCIO, Package (0x40) /* HC_NUMS * 2 */
|
||||
{
|
||||
0x77777777,
|
||||
0x88888888,
|
||||
0x99999999,
|
||||
0xaaaaaaaa,
|
||||
0xbbbbbbbb,
|
||||
0xcccccccc,
|
||||
0xdddddddd,
|
||||
0xeeeeeeee,
|
||||
0x77777777,
|
||||
0x88888888,
|
||||
0x99999999,
|
||||
0xaaaaaaaa,
|
||||
0xbbbbbbbb,
|
||||
0xcccccccc,
|
||||
0xdddddddd,
|
||||
0xeeeeeeee,
|
||||
0x77777777,
|
||||
0x88888888,
|
||||
0x99999999,
|
||||
0xaaaaaaaa,
|
||||
0xbbbbbbbb,
|
||||
0xcccccccc,
|
||||
0xdddddddd,
|
||||
0xeeeeeeee,
|
||||
0x77777777,
|
||||
0x88888888,
|
||||
0x99999999,
|
||||
0xaaaaaaaa,
|
||||
0xbbbbbbbb,
|
||||
0xcccccccc,
|
||||
0xdddddddd,
|
||||
0xeeeeeeee,
|
||||
0xaaaaaaaa,
|
||||
0xbbbbbbbb,
|
||||
0xcccccccc,
|
||||
0xdddddddd,
|
||||
0xeeeeeeee,
|
||||
0x77777777,
|
||||
0x88888888,
|
||||
0x99999999,
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x33333333,
|
||||
0x44444444,
|
||||
0x55555555,
|
||||
0x66666666,
|
||||
0x77777777,
|
||||
0x88888888,
|
||||
0x99999999,
|
||||
0xaaaaaaaa,
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x33333333,
|
||||
0x44444444,
|
||||
0x55555555,
|
||||
0x66666666,
|
||||
0x77777777,
|
||||
0x88888888,
|
||||
0x99999999,
|
||||
0xaaaaaaaa,
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x33333333,
|
||||
0x44444444
|
||||
})
|
||||
Name (SBLK, 0x11)
|
||||
Name (TOM1, 0xaaaaaaaa)
|
||||
Name (SBDN, 0xbbbbbbbb)
|
||||
Name (HCLK, Package (0x20) /* HC_POSSIBLE_NUM */
|
||||
{
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x33333333,
|
||||
0x44444444,
|
||||
0x55555555,
|
||||
0x66666666,
|
||||
0x77777777,
|
||||
0x88888888,
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x33333333,
|
||||
0x44444444,
|
||||
0x55555555,
|
||||
0x66666666,
|
||||
0x77777777,
|
||||
0x88888888,
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x33333333,
|
||||
0x44444444,
|
||||
0x55555555,
|
||||
0x66666666,
|
||||
0x77777777,
|
||||
0x88888888,
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x33333333,
|
||||
0x44444444,
|
||||
0x55555555,
|
||||
0x66666666,
|
||||
0x77777777,
|
||||
0x88888888
|
||||
})
|
||||
Name (HCDN, Package (0x20) /* HC_POSSIBLE_NUM */
|
||||
{
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x33333333,
|
||||
0x44444444,
|
||||
0x55555555,
|
||||
0x66666666,
|
||||
0x77777777,
|
||||
0x88888888,
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x33333333,
|
||||
0x44444444,
|
||||
0x55555555,
|
||||
0x66666666,
|
||||
0x77777777,
|
||||
0x88888888,
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x33333333,
|
||||
0x44444444,
|
||||
0x55555555,
|
||||
0x66666666,
|
||||
0x77777777,
|
||||
0x88888888,
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x33333333,
|
||||
0x44444444,
|
||||
0x55555555,
|
||||
0x66666666,
|
||||
0x77777777,
|
||||
0x88888888
|
||||
})
|
||||
Name (CBB, 0x99)
|
||||
Name (CBST, 0x88)
|
||||
Name (CBB2, 0x77)
|
||||
Name (CBS2, 0x66)
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
39
src/northbridge/amd/amdfam10/sspr1.dsl
Normal file
39
src/northbridge/amd/amdfam10/sspr1.dsl
Normal file
@ -0,0 +1,39 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
DefinitionBlock ("SSPR.aml", "SSDT", 1, "AMD-FAM10", "AMD-ACPI", 100925441)
|
||||
{
|
||||
Scope (\_SB)
|
||||
{
|
||||
Processor (\_SB.CPAA, 0xbb, 0x120, 6) // CPU0 and 0x01 need to be updated
|
||||
{
|
||||
Name(_PCT, Package ()
|
||||
{
|
||||
ResourceTemplate() {Register (FFixedHW, 0, 0, 0)}, //PERF_CTRL
|
||||
ResourceTemplate() {Register (FFixedHW, 0, 0, 0)}, //PERF_STATUS
|
||||
})
|
||||
|
||||
Name(_PSS, Package()
|
||||
{
|
||||
Package(0x06) {0x1111, 0x222222, 0x3333, 0x4444, 0x55, 0x66 },
|
||||
})
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
40
src/northbridge/amd/amdfam10/sspr2.dsl
Normal file
40
src/northbridge/amd/amdfam10/sspr2.dsl
Normal file
@ -0,0 +1,40 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
DefinitionBlock ("SSPR.aml", "SSDT", 1, "AMD-FAM10", "AMD-ACPI", 100925441)
|
||||
{
|
||||
Scope (\_SB)
|
||||
{
|
||||
Processor (\_SB.CPAA, 0xbb, 0x120, 6) // CPU0 and 0x01 need to be updated
|
||||
{
|
||||
Name(_PCT, Package ()
|
||||
{
|
||||
ResourceTemplate() {Register (FFixedHW, 0, 0, 0)}, //PERF_CTRL
|
||||
ResourceTemplate() {Register (FFixedHW, 0, 0, 0)}, //PERF_STATUS
|
||||
})
|
||||
|
||||
Name(_PSS, Package()
|
||||
{
|
||||
Package(0x06) {0x1111, 0x222222, 0x3333, 0x4444, 0x55, 0x66 },
|
||||
Package(0x06) {0x7777, 0x222222, 0x3333, 0x4444, 0x55, 0x66 },
|
||||
})
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
41
src/northbridge/amd/amdfam10/sspr3.dsl
Normal file
41
src/northbridge/amd/amdfam10/sspr3.dsl
Normal file
@ -0,0 +1,41 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
DefinitionBlock ("SSPR.aml", "SSDT", 1, "AMD-FAM10", "AMD-ACPI", 100925441)
|
||||
{
|
||||
Scope (\_SB)
|
||||
{
|
||||
Processor (\_SB.CPAA, 0xbb, 0x120, 6) // CPU0 and 0x01 need to be updated
|
||||
{
|
||||
Name(_PCT, Package ()
|
||||
{
|
||||
ResourceTemplate() {Register (FFixedHW, 0, 0, 0)}, //PERF_CTRL
|
||||
ResourceTemplate() {Register (FFixedHW, 0, 0, 0)}, //PERF_STATUS
|
||||
})
|
||||
|
||||
Name(_PSS, Package()
|
||||
{
|
||||
Package(0x06) {0x1111, 0x222222, 0x3333, 0x4444, 0x55, 0x66 },
|
||||
Package(0x06) {0x7777, 0x222222, 0x3333, 0x4444, 0x55, 0x66 },
|
||||
Package(0x06) {0x8888, 0x222222, 0x3333, 0x4444, 0x55, 0x66 },
|
||||
})
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
42
src/northbridge/amd/amdfam10/sspr4.dsl
Normal file
42
src/northbridge/amd/amdfam10/sspr4.dsl
Normal file
@ -0,0 +1,42 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
DefinitionBlock ("SSPR.aml", "SSDT", 1, "AMD-FAM10", "AMD-ACPI", 100925441)
|
||||
{
|
||||
Scope (\_SB)
|
||||
{
|
||||
Processor (\_SB.CPAA, 0xbb, 0x120, 6) // CPU0 and 0x01 need to be updated
|
||||
{
|
||||
Name(_PCT, Package ()
|
||||
{
|
||||
ResourceTemplate() {Register (FFixedHW, 0, 0, 0)}, //PERF_CTRL
|
||||
ResourceTemplate() {Register (FFixedHW, 0, 0, 0)}, //PERF_STATUS
|
||||
})
|
||||
|
||||
Name(_PSS, Package()
|
||||
{
|
||||
Package(0x06) {0x1111, 0x222222, 0x3333, 0x4444, 0x55, 0x66 },
|
||||
Package(0x06) {0x7777, 0x222222, 0x3333, 0x4444, 0x55, 0x66 },
|
||||
Package(0x06) {0x8888, 0x222222, 0x3333, 0x4444, 0x55, 0x66 },
|
||||
Package(0x06) {0x9999, 0x222222, 0x3333, 0x4444, 0x55, 0x66 },
|
||||
})
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
43
src/northbridge/amd/amdfam10/sspr5.dsl
Normal file
43
src/northbridge/amd/amdfam10/sspr5.dsl
Normal file
@ -0,0 +1,43 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
DefinitionBlock ("SSPR.aml", "SSDT", 1, "AMD-FAM10", "AMD-ACPI", 100925441)
|
||||
{
|
||||
Scope (\_SB)
|
||||
{
|
||||
Processor (\_SB.CPAA, 0xbb, 0x120, 6) // CPU0 and 0x01 need to be updated
|
||||
{
|
||||
Name(_PCT, Package ()
|
||||
{
|
||||
ResourceTemplate() {Register (FFixedHW, 0, 0, 0)}, //PERF_CTRL
|
||||
ResourceTemplate() {Register (FFixedHW, 0, 0, 0)}, //PERF_STATUS
|
||||
})
|
||||
|
||||
Name(_PSS, Package()
|
||||
{
|
||||
Package(0x06) {0x1111, 0x222222, 0x3333, 0x4444, 0x55, 0x66 },
|
||||
Package(0x06) {0x7777, 0x222222, 0x3333, 0x4444, 0x55, 0x66 },
|
||||
Package(0x06) {0x8888, 0x222222, 0x3333, 0x4444, 0x55, 0x66 },
|
||||
Package(0x06) {0x9999, 0x222222, 0x3333, 0x4444, 0x55, 0x66 },
|
||||
Package(0x06) {0xaaaa, 0x222222, 0x3333, 0x4444, 0x55, 0x66 },
|
||||
})
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
252
src/northbridge/amd/amdht/AsPsDefs.h
Normal file
252
src/northbridge/amd/amdht/AsPsDefs.h
Normal file
@ -0,0 +1,252 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
|
||||
#ifndef ASPSDEFS_H
|
||||
#define ASPSDEFS_H
|
||||
|
||||
/* AMD Platform Types */
|
||||
#define AMD_PTYPE_DSK 1
|
||||
#define AMD_PTYPE_MOB 2
|
||||
#define AMD_PTYPE_SVR 4
|
||||
#define AMD_PTYPE_DC 8
|
||||
#define AMD_PTYPE_MC 0x10
|
||||
#define AMD_PTYPE_UMA 0x20
|
||||
|
||||
#define APIC_BAR 0x1b /* APIC_BAR register */
|
||||
#define APIC_BAR_BP 0x100 /* APIC_BAR BSP bit */
|
||||
|
||||
#define PS_LIM_REG 0xC0010061 /* P-state Current Limit Register */
|
||||
#define PS_CUR_LIM_SHFT 4 /* P-state Current Limit shift position */
|
||||
|
||||
#define PS_CTL_REG 0xC0010062 /* P-state Control Register */
|
||||
#define PS_CMD_MASK_OFF 0xfffffff8 /* P-state Control Register CMD Mask OFF */
|
||||
|
||||
#define PS_STS_REG 0xC0010063 /* P-state Status Register */
|
||||
#define PS_STS_MASK 0x7 /* P-state Status Mask */
|
||||
|
||||
#define PS_REG_BASE 0xC0010064 /* P-state Register base */
|
||||
#define PS_MAX_REG 0xC0010068 /* Maximum P-State Register */
|
||||
#define PS_MIN_REG 0xC0010064 /* Mimimum P-State Register */
|
||||
|
||||
/* P-state register offset */
|
||||
#define PS_REG0 0 /* offset for P0 */
|
||||
#define PS_REG1 1 /* offset for P1 */
|
||||
#define PS_REG2 2 /* offset for P2 */
|
||||
#define PS_REG3 3 /* offset for P3 */
|
||||
#define PS_REG4 4 /* offset for P4 */
|
||||
|
||||
#define PS_PSDIS_MASK 0x7fffffff /* disable P-state register */
|
||||
#define PS_EN_MASK 0x80000000 /* P-state register enable mask */
|
||||
#define PS_NB_DID_MASK 0x400000 /* P-state Reg[NbDid] Mask */
|
||||
#define PS_NB_VID_M_OFF 0x01ffffff /* P-state Reg[NbVid] Mask OFF */
|
||||
#define PS_CPU_VID_M_ON 0x0fe00 /* P-state Reg[CpuVid] Mask On */
|
||||
#define PS_NB_VID_M_ON 0x0fe000000 /* P-state Reg[NbVid] Mask On */
|
||||
#define PS_CPU_VID_SHFT 9 /* P-state bit shift for CpuVid */
|
||||
#define PS_NB_VID_SHFT 25 /* P-state bit shift for NbVid */
|
||||
#define PS_BOTH_VID_OFF 0x01ff01ff /* Mask NbVid & CpuVid */
|
||||
#define PS_CPU_NB_VID_SHFT 16 /* P-state bit shift from CpuVid to NbVid */
|
||||
#define PS_NB_VID_SHFT 25 /* P-state NBVID shift */
|
||||
#define PS_DIS 0x7fffffff /* disable P-state reg */
|
||||
#define PS_EN 0x80000000 /* enable P-state reg */
|
||||
#define PS_CURDIV_SHFT 8 /* P-state Current Divisor shift position */
|
||||
#define PS_CPUDID_SHIFT 6 /* P-state CPU DID shift position */
|
||||
|
||||
/* for unfused parts */
|
||||
#define PS_NB_VID_110V 0x48000000
|
||||
#define PS_NB_VID_1175V 0x3c000000
|
||||
/* NB VID 1.100V =0x12[PVI]=0x24[SVI] = 0100100b 7-bit code */
|
||||
|
||||
#define PS_NB_DID0 0 /* NB DID 0 */
|
||||
#define PS_NB_DID1 0x400000 /* NB DID 1 */
|
||||
#define PS_CPU_VID_110V 0x4800 /* CPU VID 1.100V */
|
||||
#define PS_CPU_VID_1175V 0x3c00 /* CPU VID 1.175V */
|
||||
#define PS_CPU_DID 0x40 /* CPU DID 1 = divisor of 2 */
|
||||
#define PS_CPU_DID0 0 /* CPU DID 0 = divisor of 1 */
|
||||
#define PS_CPU_FID_16G 0x00 /* CPU FID of 00 = 1.6GHz */
|
||||
#define PS_CPU_FID_16G1 0x10 /* CPU FId of 16 COF = 16+16/2 = 16 */
|
||||
#define PS_CPU_FID_18G 20 /* CPU FId of 20 COF = 20+16/2 = 18 */
|
||||
#define PS_CPU_FID_19G 22 /* CPU FId of 20 COF = 22+16/2 = 19 */
|
||||
#define PS_CPU_FID_20G 24 /* CPU FId of 20 COF = 24+16/2 = 20 */
|
||||
#define PS_CPU_FID_22G 28 /* CPU FId of 2C COF = 28+16/2 = 22 */
|
||||
#define PS_CPU_FID_30G 44 /* CPU FId of 2C COF = 44+16/2 = 30 */
|
||||
|
||||
|
||||
|
||||
#define PCI_DEV_BASE 24 /* System PCI device ID base */
|
||||
#define LOCAL_APIC_ID_SHIFT 24 /* Local APCI ID shift bit # */
|
||||
#define APIC_CID_SIZE_SHIFT 12 /* ApicCoreIdSize shift bit # */
|
||||
#define FN_0 0 /* Function 0 */
|
||||
#define FN_1 1 /* Function 1 */
|
||||
#define FN_2 2 /* Function 2 */
|
||||
#define FN_3 3 /* Function 3 */
|
||||
#define FN_4 4 /* Function 4 */
|
||||
#define FN_5 5 /* Function 5 */
|
||||
#define FN_80000000 0x80000000 /* Function 8000_0000 */
|
||||
#define FN_80000001 0x80000001 /* Function 8000_0001 */
|
||||
#define FN_80000008 0x80000008 /* Function 8000_0008 */
|
||||
|
||||
#define LNK_INIT_REG 0x6C /* F0x6C link initialization control register */
|
||||
#define WARM_RESET_BIT 0x10 /* bit 4 =1 : warm reset */
|
||||
|
||||
#define HTC_REG 0x64 /* hardware thermal control reg */
|
||||
#define HTC_PS_LMT_MASK 0x8fffffff /* HtcPstateLimit mask off */
|
||||
#define PS_LIMIT_POS 28 /* PstateLimit position for HTC & STC */
|
||||
|
||||
#define STC_REG 0x68 /* software thermal control reg */
|
||||
#define STC_PS_LMT_MASK 0x8fffffff /* StcPstateLimit mask off */
|
||||
|
||||
#define CPTC0 0x0d4 /* Clock Power/Timing Control0 Register*/
|
||||
#define CPTC0_MASK 0x000c0fff /* Reset mask for this register */
|
||||
#define CPTC0_NBFID_MASK 0xffffffe0 /* NbFid mask off for this register */
|
||||
#define CPTC0_NBFID_MON 0x1f /* NbFid mask on for this register */
|
||||
#define NB_FID_EN 0x20 /* NbFidEn bit ON */
|
||||
#define NB_CLKDID_ALL 0x80000000 /* NbClkDidApplyAll bit ON */
|
||||
#define NB_CLKDID 0x40000000 /* NbClkDid value set by BIOS */
|
||||
#define PW_STP_UP50 0x08000000 /* PowerStepUp 50nS(1000b) */
|
||||
#define PW_STP_DN50 0x00800000 /* PowerStepDown 50nS (1000b)*/
|
||||
#define PW_STP_UP100 0x03000000 /* PowerStepUp 100nS(0011b) */
|
||||
#define PW_STP_DN100 0x00300000 /* PowerStepDown 100nS (0011b)*/
|
||||
#define PW_STP_UP200 0x02000000 /* PowerStepUp 200nS(0010b) */
|
||||
#define PW_STP_DN200 0x00200000 /* PowerStepDown 200nS (0010b)*/
|
||||
#define PW_STP_UP400 0x00000000 /* PowerStepUp 400nS(0000b) */
|
||||
#define PW_STP_DN400 0x00000000 /* PowerStepDown 400nS (0000b)*/
|
||||
|
||||
|
||||
#define LNK_PLL_LOCK 0x00010000 /* LnkPllLock value set (01b) by BIOS */
|
||||
|
||||
|
||||
|
||||
#define PSTATE_CTL 0xC0010070 /* P-state Control Register */
|
||||
#define NB_VID_POS 25 /* NbVid bit shift for position */
|
||||
#define NB_VID_MASK_OFF 0x01ffffff /* NbVid bits mask off */
|
||||
#define NB_VID_MASK_ON 0xfe000000 /* NbVid bits mask on */
|
||||
#define CPU_VID_POS 0x9 /* CpuVid bit shift for position */
|
||||
#define CPU_VID_MASK_OFF 0xffff01ff /* CpuVid bits mask off */
|
||||
#define CPU_VID_MASK_ON 0x0000fe00 /* CpuVid bits mask on */
|
||||
#define CPU_FID_DID_M_ON 0x000001ff /* CpuFid & CpuDid mask on */
|
||||
#define CPU_FID_DID_M_OFF 0xfffffe00 /* CpuFid & CpuDid mask off */
|
||||
#define NB_DID_VID_M_ON 0xfe400000 /* NbDid & NbVid mask on */
|
||||
#define NB_DID_M_ON 0x00400000 /* NbDid mask on */
|
||||
#define NB_DID_M_OFF 0xffbfffff /* NbDid mask off */
|
||||
#define NB_DID_POS 22 /* NbDid bit shift for position */
|
||||
#define PS_M_OFF 0xfff8ffff /* Cur Pstate mask off */
|
||||
#define PS_1 0x00010000 /* P-state 1 */
|
||||
#define PS_2 0x00020000 /* P-state 2 */
|
||||
#define PS_CPU_DID_1 0x40 /* Cpu Did 1 */
|
||||
|
||||
|
||||
|
||||
|
||||
#define PSTATE_STS 0xC0010071 /* P-state Status Register */
|
||||
#define STARTUP_PS_MASK 0x7 /* StartupPstate Mask */
|
||||
|
||||
/* define for NB VID & CPU VID transition functions */
|
||||
#define IS_NB 1
|
||||
#define IS_CPU 0
|
||||
|
||||
/* F3xD8 Clock Power/Timing Control 1 Register */
|
||||
#define CPTC1 0xd8 /* Clock Power/Timing Control1 Register*/
|
||||
#define VSRAMP_SLAM_MASK 0xffffff88 /* MaskOff [VSRampTime]&[VSSlamTime] */
|
||||
#define VSRAMP_SLAM_VALUE 0x16 /* [VSRampTime]=001b&[VSSlamTime]=110b */
|
||||
#define VS_RAMP_T 4 /* VSRampTime bit position */
|
||||
#define PWR_PLN_SHIFT 28 /* PwrPlanes bit shift */
|
||||
#define PWR_PLN_ON 0x10000000 /* PwrPlanes bit ON */
|
||||
#define PWR_PLN_OFF 0x0efffffff /* PwrPlanes bit OFF */
|
||||
|
||||
|
||||
|
||||
/* Northbridge Capability Register */
|
||||
#define NB_CAP 0xe8 /* Northbridge Cap Reg */
|
||||
#define CMP_CAP_SHFT 12 /* CMP CAP - number of enabled cores */
|
||||
|
||||
/* F3xDC Clock Power/Timing Control 2 Register */
|
||||
#define CPTC2 0xdc /* Clock Power/Timing Control2 Register*/
|
||||
#define PS_MAX_VAL_POS 8 /* PstateMaxValue bit shift */
|
||||
#define PS_MAX_VAL_MASK 0xfffff8ff /* PstateMaxValue Mask off */
|
||||
|
||||
#define PRCT_INFO 0x1fc /* Product Info Register */
|
||||
#define UNI_NB_FID_BIT 2 /* UniNbFid bit position */
|
||||
#define UNI_NB_VID_BIT 7 /* UniNbVid bit position */
|
||||
#define SPLT_NB_FID_OFFSET 14 /* SpltNbFidOffset value bit position */
|
||||
#define SPLT_NB_VID_OFFSET 17 /* SpltNbVidOffset value bit position */
|
||||
#define NB_CV_UPDATE 0x01 /* F3x1FC[NbCofVidUpdated] bit mask */
|
||||
#define NB_VID_UPDATE_ALL 0x02 /* F3x1FC[NbVidUpdatedAll] bit mask */
|
||||
#define C_FID_DID_M_OFF 0xfffffe00 /* mask off Core FID & DID */
|
||||
|
||||
#define PW_CTL_MISC 0x0a0 /* Power Control Miscellaneous Register */
|
||||
#define COF_VID_PROG_BIT 0x80000000 /* CofVidProg bit. 0= unfused part */
|
||||
#define DUAL_VDD_BIT 0x40000000 /* DualVdd bit. */
|
||||
#define NB_COFVID_UPDATE_BIT 0x01 /* NbCOFVIDUpdated bit */
|
||||
#define PVI_MODE 0x100 /* PviMode bit mask */
|
||||
#define VID_SLAM_OFF 0x0dfffffff /* set VidSlamMode OFF */
|
||||
#define VID_SLAM_ON 0x020000000 /* set VidSlamMode ON */
|
||||
#define PLLLOCK_OFF 0x0ffffc7ff /* PllLockTime Mask OFF */
|
||||
#define PLLLOCK_DFT 0x00001800 /* PllLockTime default value = 011b */
|
||||
#define PLLLOCK_DFT_L 0x00002800 /* PllLockTime long value = 101b */
|
||||
|
||||
/* P-state Specification register base in PCI sapce */
|
||||
#define PS_SPEC_REG 0x1e0 /* PS Spec register base address */
|
||||
#define PCI_REG_LEN 4 /* PCI register length */
|
||||
#define NB_DID_MASK 0x10000 /* NbDid bit mask */
|
||||
#define NB_DID_2 2 /* NbDid = 2 */
|
||||
#define NB_DID_1 1 /* NbDid = 1 */
|
||||
#define SPEC_PWRDIV_M_ON 0x06000000 /* PwrDiv mask on */
|
||||
#define SPEC_PWRVAL_M_ON 0x01e00000 /* PwrValue mask on */
|
||||
#define SPEC_PWRDIV_SHFT 25 /* PwrDiv shift */
|
||||
#define SPEC_PWRVAL_SHFT 17 /* PwrValue shift */
|
||||
|
||||
/* F4x1F4 Northbridge P-state spec register */
|
||||
#define NB_PS_SPEC_REG 0x1f4 /* Nb PS spec reg */
|
||||
|
||||
#define NM_PS_REG 5 /* number of P-state MSR registers */
|
||||
|
||||
/* sFidVidInit.outFlags defines */
|
||||
#define PWR_CK_OK 0 /* System board check OK */
|
||||
#define PWR_CK_NO_PS 1 /* All P-state registers are over
|
||||
the limit */
|
||||
|
||||
/* bit mask */
|
||||
#define BIT_MASK_1 0x1
|
||||
#define BIT_MASK_2 0x3
|
||||
#define BIT_MASK_3 0x7
|
||||
#define BIT_MASK_4 0x0f
|
||||
#define BIT_MASK_5 0x1f
|
||||
#define BIT_MASK_6 0x3f
|
||||
#define BIT_MASK_7 0x7f
|
||||
#define BIT_MASK_8 0x0ff
|
||||
|
||||
/* VID Code */
|
||||
#define VID_1_100V 0x12 /* 1.100V */
|
||||
#define VID_1_175V 0x1E /* 1.175V */
|
||||
|
||||
|
||||
/* Nb Fid Code */
|
||||
#define NB_FID_800M 0x00 /* 800MHz */
|
||||
|
||||
/* Nb DID Code */
|
||||
#define NB_DID_0 0
|
||||
#define NB_DID_1 1
|
||||
|
||||
/* GH Logical ID */
|
||||
|
||||
#define GH_REV_A2 0x4 /* GH Rev A2 logical ID, Upper half */
|
||||
|
||||
|
||||
#endif
|
||||
145
src/northbridge/amd/amdht/AsPsNb.c
Normal file
145
src/northbridge/amd/amdht/AsPsNb.c
Normal file
@ -0,0 +1,145 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
*----------------------------------------------------------------------------
|
||||
* MODULES USED
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
#undef FILECODE
|
||||
#define FILECODE 0xCCCC
|
||||
#include "comlib.h"
|
||||
#include "AsPsDefs.h"
|
||||
#include "AsPsNb.h"
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* PROTOTYPES OF LOCAL FUNCTIONS
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
u8 getNumOfNodeNb(void);
|
||||
u8 translateNodeIdToDeviceIdNb(u8 nodeId);
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* FUNCTION: getMinNbCOF
|
||||
* INPUT: None
|
||||
* OUTPUT: minNbCOF (in multiple of half of CLKIN, 100MHz)
|
||||
* DESCRIPTION:
|
||||
* This function returns the minimum possible NbCOF (in 100MHz)
|
||||
* for the system .
|
||||
* This function can be run on any core and is used by the HT & Memory init code
|
||||
* in Phase 1.
|
||||
* ----------------------------------------------------------------------------
|
||||
*/
|
||||
u8 getMinNbCOF(void)
|
||||
{
|
||||
u8 numOfNode, i, j, deviceId, nbDid, nbFid, nextNbFid;
|
||||
u32 dtemp;
|
||||
|
||||
nbDid = 0;
|
||||
nbFid = 0;
|
||||
|
||||
/* get number of node in the system */
|
||||
numOfNode = getNumOfNodeNb();
|
||||
|
||||
/* go through each node for the minimum NbCOF (in multiple of CLKIN/2) */
|
||||
for(i=0; i < numOfNode; i++)
|
||||
{
|
||||
/* stub function for APIC ID virtualization for large MP system later */
|
||||
deviceId = translateNodeIdToDeviceIdNb(i);
|
||||
|
||||
/* read all P-state spec registers for NbDid=1 */
|
||||
for(j=0; j < 5; j++)
|
||||
{
|
||||
AmdPCIRead(MAKE_SBDFO(0,0,deviceId,FN_4,PS_SPEC_REG+(j*PCI_REG_LEN)), &dtemp); /*F4x1E0 + j*4 */
|
||||
/* get NbDid */
|
||||
if(dtemp & NB_DID_MASK)
|
||||
nbDid = 1;
|
||||
}
|
||||
/* if F3x1FC[NbCofVidUpdate]=0, NbFid = default value */
|
||||
AmdPCIRead(MAKE_SBDFO(0,0,deviceId,FN_3,PRCT_INFO), &dtemp); /*F3x1FC*/
|
||||
if(!(dtemp & NB_CV_UPDATE)) /* F3x1FC[NbCofVidUpdated]=0, use default VID */
|
||||
{
|
||||
AmdPCIRead(MAKE_SBDFO(0,0,deviceId,FN_3,CPTC0), &dtemp); /*F3xD4*/
|
||||
nextNbFid = (u8) (dtemp & BIT_MASK_5);
|
||||
if(nbDid)
|
||||
nextNbFid = (u8) (nextNbFid >> 1);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* check PVI/SPI */
|
||||
AmdPCIRead(MAKE_SBDFO(0,0,deviceId,FN_3,PW_CTL_MISC), &dtemp); /*F3xA0*/
|
||||
if(dtemp & PVI_MODE) /* PVI */
|
||||
{
|
||||
AmdPCIRead(MAKE_SBDFO(0,0,deviceId,FN_3,PRCT_INFO), &dtemp); /*F3x1FC*/
|
||||
nextNbFid = (u8) (dtemp >> UNI_NB_FID_BIT);
|
||||
nextNbFid &= BIT_MASK_5;
|
||||
/* if(nbDid)
|
||||
nextNbFid = nextNbFid >> 1; */
|
||||
}
|
||||
else /* SVI */
|
||||
{
|
||||
AmdPCIRead(MAKE_SBDFO(0,0,deviceId,FN_3,PRCT_INFO), &dtemp); /*F3x1FC*/
|
||||
nextNbFid = (u8) ((dtemp >> UNI_NB_FID_BIT) & BIT_MASK_5);
|
||||
nextNbFid = (u8) (nextNbFid + ((dtemp >> SPLT_NB_FID_OFFSET) & BIT_MASK_3));
|
||||
/* if(nbDid)
|
||||
nextNbFid = nextNbFid >> 1; */
|
||||
}
|
||||
}
|
||||
if( i == 0)
|
||||
nbFid = nextNbFid;
|
||||
else if( nbFid > nextNbFid )
|
||||
nbFid = nextNbFid;
|
||||
}
|
||||
|
||||
/* add the base and convert to 100MHz divide by 2 if DID=1 */
|
||||
if(nbDid)
|
||||
nbFid = (u8) (nbFid + 4);
|
||||
else
|
||||
nbFid = (u8) ((nbFid + 4) << 1);
|
||||
return nbFid;
|
||||
}
|
||||
|
||||
u8 getNumOfNodeNb(void)
|
||||
{
|
||||
u32 dtemp;
|
||||
|
||||
AmdPCIRead(MAKE_SBDFO(0,0,24,0,0x60), &dtemp);
|
||||
dtemp = (dtemp >> 4) & BIT_MASK_3;
|
||||
dtemp++;
|
||||
return (u8)dtemp;
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* FUNCTION: translateNodeIdToDeviceId
|
||||
* INPUT: u8 nodeId - node ID of the node
|
||||
* OUTPUT: u8 - PCI device ID of the node
|
||||
* DESCRIPTION:
|
||||
* This function return the PCI device ID for PCI access using node ID.
|
||||
* This function may need to chnage node ID to device ID in big MP systems.
|
||||
* ----------------------------------------------------------------------------
|
||||
*/
|
||||
u8 translateNodeIdToDeviceIdNb(u8 nodeId)
|
||||
{
|
||||
return (u8) (nodeId+PCI_DEV_BASE);
|
||||
}
|
||||
26
src/northbridge/amd/amdht/AsPsNb.h
Normal file
26
src/northbridge/amd/amdht/AsPsNb.h
Normal file
@ -0,0 +1,26 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
|
||||
#ifndef ASPSNB_H
|
||||
#define ASPSNB_H
|
||||
|
||||
u8 getMinNbCOF(void);
|
||||
|
||||
#endif
|
||||
290
src/northbridge/amd/amdht/comlib.c
Normal file
290
src/northbridge/amd/amdht/comlib.c
Normal file
@ -0,0 +1,290 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#undef FILECODE
|
||||
#define FILECODE 0xCCCC
|
||||
#include "comlib.h"
|
||||
|
||||
/*
|
||||
*---------------------------------------------------------------------------
|
||||
* EXPORTED FUNCTIONS
|
||||
*
|
||||
*---------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
void CALLCONV AmdPCIReadBits(SBDFO loc, u8 highbit, u8 lowbit, u32 *pValue)
|
||||
{
|
||||
ASSERT(highbit < 32 && lowbit < 32 && highbit >= lowbit && (loc & 3) == 0);
|
||||
|
||||
AmdPCIRead(loc, pValue);
|
||||
*pValue = *pValue >> lowbit; /* Shift */
|
||||
|
||||
/* A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case */
|
||||
if ((highbit-lowbit) != 31)
|
||||
*pValue &= (((u32)1 << (highbit-lowbit+1))-1);
|
||||
}
|
||||
|
||||
|
||||
void CALLCONV AmdPCIWriteBits(SBDFO loc, u8 highbit, u8 lowbit, u32 *pValue)
|
||||
{
|
||||
u32 temp, mask;
|
||||
|
||||
ASSERT(highbit < 32 && lowbit < 32 && highbit >= lowbit && (loc & 3) == 0);
|
||||
|
||||
/* A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case */
|
||||
if ((highbit-lowbit) != 31)
|
||||
mask = (((u32)1 << (highbit-lowbit+1))-1);
|
||||
else
|
||||
mask = (u32)0xFFFFFFFF;
|
||||
|
||||
AmdPCIRead(loc, &temp);
|
||||
temp &= ~(mask << lowbit);
|
||||
temp |= (*pValue & mask) << lowbit;
|
||||
AmdPCIWrite(loc, &temp);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Given a SBDFO this routine will find the next PCI capabilities list entry.
|
||||
* If the end of the list of reached, or if a problem is detected, then
|
||||
* ILLEGAL_SBDFO is returned.
|
||||
*
|
||||
* To start a new search from the beginning of head of the list, specify a
|
||||
* SBDFO with a offset of zero.
|
||||
*/
|
||||
void CALLCONV AmdPCIFindNextCap(SBDFO *pCurrent)
|
||||
{
|
||||
SBDFO base;
|
||||
u32 offset;
|
||||
u32 temp;
|
||||
|
||||
if (*pCurrent == ILLEGAL_SBDFO)
|
||||
return;
|
||||
|
||||
offset = SBDFO_OFF(*pCurrent);
|
||||
base = *pCurrent - offset;
|
||||
*pCurrent = ILLEGAL_SBDFO;
|
||||
|
||||
/* Verify that the SBDFO points to a valid PCI device SANITY CHECK */
|
||||
AmdPCIRead(base, &temp);
|
||||
if (temp == 0xFFFFFFFF)
|
||||
return; /* There is no device at this address */
|
||||
|
||||
/* Verify that the device supports a capability list */
|
||||
AmdPCIReadBits(base + 0x04, 20, 20, &temp);
|
||||
if (temp == 0)
|
||||
return; /* This PCI device does not support capability lists */
|
||||
|
||||
if (offset != 0)
|
||||
{
|
||||
/* If we are continuing on an existing list */
|
||||
AmdPCIReadBits(base + offset, 15, 8, &temp);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* We are starting on a new list */
|
||||
AmdPCIReadBits(base + 0x34, 7, 0, &temp);
|
||||
}
|
||||
|
||||
if (temp == 0)
|
||||
return; /* We have reached the end of the capabilties list */
|
||||
|
||||
/* Error detection and recovery- The statement below protects against
|
||||
PCI devices with broken PCI capabilities lists. Detect a pointer
|
||||
that is not u32 aligned, points into the first 64 reserved DWORDs
|
||||
or points back to itself.
|
||||
*/
|
||||
if (((temp & 3) != 0) || (temp == offset) || (temp < 0x40))
|
||||
return;
|
||||
|
||||
*pCurrent = base + temp;
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
void CALLCONV Amdmemcpy(void *pDst, const void *pSrc, u32 length)
|
||||
{
|
||||
ASSERT(length <= 32768);
|
||||
ASSERT(pDst != NULL);
|
||||
ASSERT(pSrc != NULL);
|
||||
|
||||
while (length--){
|
||||
// *(((u8*)pDst)++) = *(((u8*)pSrc)++);
|
||||
*((u8*)pDst) = *((u8*)pSrc);
|
||||
pDst++;
|
||||
pSrc++;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void CALLCONV Amdmemset(void *pBuf, u8 val, u32 length)
|
||||
{
|
||||
ASSERT(length <= 32768);
|
||||
ASSERT(pBuf != NULL);
|
||||
|
||||
while (length--){
|
||||
//*(((u8*)pBuf)++) = val;
|
||||
*(((u8*)pBuf)) = val;
|
||||
pBuf++;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
u8 CALLCONV AmdBitScanReverse(u32 value)
|
||||
{
|
||||
u8 i;
|
||||
|
||||
for (i = 31; i != 0xFF; i--)
|
||||
{
|
||||
if (value & ((u32)1 << i))
|
||||
break;
|
||||
}
|
||||
|
||||
return i;
|
||||
}
|
||||
|
||||
|
||||
u32 CALLCONV AmdRotateRight(u32 value, u8 size, u32 count)
|
||||
{
|
||||
u32 msb, mask;
|
||||
ASSERT(size > 0 && size <= 32);
|
||||
|
||||
msb = (u32)1 << (size-1);
|
||||
mask = ((msb-1) << 1) + 1;
|
||||
|
||||
value = value & mask;
|
||||
|
||||
while (count--)
|
||||
{
|
||||
if (value & 1)
|
||||
value = (value >> 1) | msb;
|
||||
else
|
||||
value = value >> 1;
|
||||
}
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
|
||||
u32 CALLCONV AmdRotateLeft(u32 value, u8 size, u32 count)
|
||||
{
|
||||
u32 msb, mask;
|
||||
ASSERT(size > 0 && size <= 32);
|
||||
|
||||
msb = (u32)1 << (size-1);
|
||||
mask = ((msb-1) << 1) + 1;
|
||||
|
||||
value = value & mask;
|
||||
|
||||
while (count--)
|
||||
{
|
||||
if (value & msb)
|
||||
value = ((value << 1) & mask) | (u32)1;
|
||||
else
|
||||
value = ((value << 1) & mask);
|
||||
}
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
|
||||
void CALLCONV AmdPCIRead(SBDFO loc, u32 *Value)
|
||||
{
|
||||
/* Use LinuxBIOS PCI functions */
|
||||
*Value = pci_read_config32((loc & 0xFFFFF000), SBDFO_OFF(loc));
|
||||
}
|
||||
|
||||
|
||||
void CALLCONV AmdPCIWrite(SBDFO loc, u32 *Value)
|
||||
{
|
||||
/* Use LinuxBIOS PCI functions */
|
||||
pci_write_config32((loc & 0xFFFFF000), SBDFO_OFF(loc), *Value);
|
||||
}
|
||||
|
||||
|
||||
void CALLCONV AmdMSRRead(uint32 Address, uint64 *Value)
|
||||
{
|
||||
msr_t msr;
|
||||
|
||||
msr = rdmsr(Address);
|
||||
Value->lo = msr.lo;
|
||||
Value->hi = msr.hi;
|
||||
}
|
||||
|
||||
|
||||
void CALLCONV AmdMSRWrite(uint32 Address, uint64 *Value)
|
||||
{
|
||||
msr_t msr;
|
||||
|
||||
msr.lo = Value->lo;
|
||||
msr.hi = Value->hi;
|
||||
wrmsr(Address, msr);
|
||||
}
|
||||
|
||||
|
||||
void ErrorStop(u32 value)
|
||||
{
|
||||
printk_debug("Error: %08x ", value);
|
||||
|
||||
}
|
||||
|
||||
/*;----------------------------------------------------------------------------
|
||||
; void __pascal ErrorStop(DWORD Value);
|
||||
;
|
||||
; This implementation provides a rotating display of the error code on the
|
||||
; a port 80h POST display card. The rotation is used to make it easier to
|
||||
; view the error on both a 16-bit as well as a 32-bit display card.
|
||||
;
|
||||
; For use with SimNow the unrotated error code is also written to port 84h
|
||||
ErrorStop PROC FAR PASCAL PUBLIC Value:DWORD
|
||||
pushad
|
||||
mov eax, Value
|
||||
mov bx, 0DEADh
|
||||
out 84h, eax
|
||||
|
||||
ErrorStopTop:
|
||||
out 80h, eax
|
||||
|
||||
mov cx, 4 ; Rotate the display by one nibble
|
||||
@@:
|
||||
bt bx, 15
|
||||
rcl eax, 1
|
||||
rcl bx, 1
|
||||
loop @B
|
||||
|
||||
|
||||
push eax ; Delay a few hundred milliseconds
|
||||
push ebx
|
||||
mov ecx, 10h ; TSC
|
||||
db 00Fh, 032h ; RDMSR
|
||||
mov ebx, eax
|
||||
@@:
|
||||
db 00Fh, 032h ; RDMSR
|
||||
sub eax, ebx
|
||||
cmp eax, 500000000
|
||||
jb @B
|
||||
pop ebx
|
||||
pop eax
|
||||
|
||||
jmp ErrorStopTop
|
||||
|
||||
popad
|
||||
ret
|
||||
ErrorStop ENDP
|
||||
*/
|
||||
59
src/northbridge/amd/amdht/comlib.h
Normal file
59
src/northbridge/amd/amdht/comlib.h
Normal file
@ -0,0 +1,59 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef COMLIB_H
|
||||
#define COMLIB_H
|
||||
|
||||
#ifndef FILECODE
|
||||
#error "FILECODE was not defined, should be #define'd to 0xFxxx"
|
||||
#endif
|
||||
|
||||
#include "porting.h"
|
||||
|
||||
/* include LinuxBIOS pci functions */
|
||||
#include <device/pci_def.h>
|
||||
#include <device/pci_ids.h>
|
||||
|
||||
#ifdef AMD_DEBUG
|
||||
#define ASSERT(x) ((x) ? 0 : ErrorStop(((uint32)FILECODE)*0x10000 + ((__LINE__)%10) + (((__LINE__/10)%10)*0x10) + (((__LINE__/100)%10)*0x100) +(((__LINE__/1000)%10)*0x1000)))
|
||||
#else
|
||||
#define ASSERT(x)
|
||||
#endif
|
||||
|
||||
#ifdef AMD_DEBUG_ERROR_STOP
|
||||
/* Macro to aid debugging, causes program to halt and display the line number of the halt in decimal */
|
||||
#define STOP_HERE ErrorStop(((uint32)FILECODE)*0x10000 + ((__LINE__)%10) + (((__LINE__/10)%10)*0x10) + (((__LINE__/100)%10)*0x100) +(((__LINE__/1000)%10)*0x1000))
|
||||
#else
|
||||
/* Macro to aid debugging, causes program to halt and display the line number of the halt in decimal */
|
||||
/* #define STOP_HERE STOP_HERE_OnlyForDebugUse */
|
||||
#define STOP_HERE
|
||||
#endif
|
||||
|
||||
void CALLCONV AmdPCIReadBits(SBDFO loc, uint8 highbit, uint8 lowbit, uint32 *value);
|
||||
void CALLCONV AmdPCIWriteBits(SBDFO loc, uint8 highbit, uint8 lowbit, uint32 *value);
|
||||
void CALLCONV AmdPCIFindNextCap(SBDFO *current);
|
||||
|
||||
void CALLCONV Amdmemcpy(void *dst, const void *src, uint32 length);
|
||||
void CALLCONV Amdmemset(void *buf, uint8 val, uint32 length);
|
||||
|
||||
uint8 CALLCONV AmdBitScanReverse(uint32 value);
|
||||
uint32 CALLCONV AmdRotateRight(uint32 value, uint8 size, uint32 count);
|
||||
uint32 CALLCONV AmdRotateLeft(uint32 value, uint8 size, uint32 count);
|
||||
|
||||
#endif
|
||||
177
src/northbridge/amd/amdht/h3ffeat.h
Normal file
177
src/northbridge/amd/amdht/h3ffeat.h
Normal file
@ -0,0 +1,177 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
|
||||
#ifndef H3FFEAT_H
|
||||
#define H3FFEAT_H
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* DEFINITIONS AND MACROS
|
||||
*
|
||||
*-----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#define MAX_NODES 8
|
||||
#define MAX_LINKS 8
|
||||
#define MAX_PLATFORM_LINKS 64 /* 8x8 fully connected (28) + 4 chains with two HT devices */
|
||||
|
||||
/* These following are internal definitions */
|
||||
#define ROUTETOSELF 0x0F
|
||||
#define INVALID_LINK 0xCC /* Used in port list data structure to mark unused data entries.
|
||||
Can also be used for no link found in a port list search */
|
||||
|
||||
/* definitions for working with the port list structure */
|
||||
#define PORTLIST_TYPE_CPU 0
|
||||
#define PORTLIST_TYPE_IO 1
|
||||
|
||||
/*
|
||||
* Hypertransport Capability definitions and macros
|
||||
*
|
||||
*/
|
||||
|
||||
/* HT Host Capability */
|
||||
/* bool isHTHostCapability(u32 reg) */
|
||||
#define IS_HT_HOST_CAPABILITY(reg) \
|
||||
((reg & (u32)0xE00000FF) == (u32)0x20000008)
|
||||
|
||||
#define HT_HOST_CAP_SIZE 0x20
|
||||
|
||||
/* Host CapabilityRegisters */
|
||||
#define HTHOST_LINK_CAPABILITY_REG 0x00
|
||||
#define HTHOST_LINK_CONTROL_REG 0x04
|
||||
#define HTHOST_FREQ_REV_REG 0x08
|
||||
#define HT_HOST_REV_REV3 0x60
|
||||
#define HTHOST_FEATURE_CAP_REG 0x0C
|
||||
#define HTHOST_BUFFER_COUNT_REG 0x10
|
||||
#define HTHOST_ISOC_REG 0x14
|
||||
#define HTHOST_LINK_TYPE_REG 0x18
|
||||
#define HTHOST_TYPE_COHERENT 3
|
||||
#define HTHOST_TYPE_NONCOHERENT 7
|
||||
#define HTHOST_TYPE_MASK 0x1F
|
||||
|
||||
/* HT Slave Capability (HT1 compat) */
|
||||
#define IS_HT_SLAVE_CAPABILITY(reg) \
|
||||
((reg & (u32)0xE00000FF) == (u32)0x00000008)
|
||||
#define HTSLAVE_LINK01_OFFSET 4
|
||||
#define HTSLAVE_LINK_CONTROL_0_REG 4
|
||||
#define HTSLAVE_FREQ_REV_0_REG 0xC
|
||||
|
||||
/* HT3 gen Capability */
|
||||
#define IS_HT_GEN3_CAPABILITY(reg) \
|
||||
((reg & (u32)0xF80000FF) == (u32)0xD0000008)
|
||||
#define HTGEN3_LINK01_OFFSET 0x10
|
||||
#define HTGEN3_LINK_TRAINING_0_REG 0x10
|
||||
|
||||
/* HT3 Retry Capability */
|
||||
#define IS_HT_RETRY_CAPABILITY(reg) \
|
||||
((reg & (u32)0xF80000FF) == (u32)0xC0000008)
|
||||
|
||||
#define HTRETRY_CONTROL_REG 4
|
||||
|
||||
/* Unit ID Clumping Capability */
|
||||
#define IS_HT_UNITID_CAPABILITY(reg) \
|
||||
((reg & (u32)0xF80000FF) == (u32)0x90000008)
|
||||
|
||||
#define HTUNIT_SUPPORT_REG 4
|
||||
#define HTUNIT_ENABLE_REG 8
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* TYPEDEFS, STRUCTURES, ENUMS
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
typedef struct cNorthBridge cNorthBridge;
|
||||
|
||||
/* A pair consists of a source node, a link to the destination node, the
|
||||
* destination node, and its link back to source node. The even indices are
|
||||
* the source nodes and links, and the odd indices are for the destination
|
||||
* nodes and links.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/* This section is where the link is in the system and how to find it */
|
||||
u8 Type; /* 0 = CPU, 1 = Device, all others reserved */
|
||||
u8 Link; /* 0-1 for devices, 0-7 for CPUs */
|
||||
u8 NodeID; /* The node, or a pointer to the devices parent node */
|
||||
u8 HostLink, HostDepth; /* Link of parent node + depth in chain. Only used by devices */
|
||||
SBDFO Pointer; /* A pointer to the device's slave HT capability, so we don't have to keep searching */
|
||||
|
||||
/* This section is for the final settings, which are written to hardware */
|
||||
BOOL SelRegang; /* Only used for CPU->CPU links */
|
||||
u8 SelWidthIn;
|
||||
u8 SelWidthOut;
|
||||
u8 SelFrequency;
|
||||
|
||||
/* This section is for keeping track of capabilities and possible configurations */
|
||||
BOOL RegangCap;
|
||||
u16 PrvFrequencyCap;
|
||||
u8 PrvWidthInCap;
|
||||
u8 PrvWidthOutCap;
|
||||
u16 CompositeFrequencyCap;
|
||||
|
||||
} sPortDescriptor;
|
||||
|
||||
|
||||
/*
|
||||
* Our global state data structure
|
||||
*/
|
||||
typedef struct {
|
||||
AMD_HTBLOCK *HtBlock;
|
||||
|
||||
u8 NodesDiscovered; /* One less than the number of nodes found in the system */
|
||||
u8 TotalLinks;
|
||||
u8 sysMpCap; /* The maximum number of nodes that all processors are capable of */
|
||||
|
||||
/* Two ports for each link
|
||||
* Note: The Port pair 2*N and 2*N+1 are connected together to form a link
|
||||
* (e.g. 0,1 and 8,9 are ports on either end of an HT link) The lower number
|
||||
* port (2*N) is the source port. The device that owns the source port is
|
||||
* always the device closer to the BSP. (i.e. nearer the CPU in a
|
||||
* non-coherent chain, or the CPU with the lower NodeID).
|
||||
*/
|
||||
sPortDescriptor PortList[MAX_PLATFORM_LINKS*2];
|
||||
|
||||
/* The number of coherent links comming off of each node (i.e. the 'Degree' of the node) */
|
||||
u8 sysDegree[MAX_NODES];
|
||||
/* The systems adjency (sysMatrix[i][j] is true if Node_i has a link to Node_j) */
|
||||
BOOL sysMatrix[MAX_NODES][MAX_NODES];
|
||||
|
||||
/* Same as above, but for the currently selected database entry */
|
||||
u8 dbDegree[MAX_NODES];
|
||||
BOOL dbMatrix[MAX_NODES][MAX_NODES];
|
||||
|
||||
u8 Perm[MAX_NODES]; /* The node mapping from the database to the system */
|
||||
u8 ReversePerm[MAX_NODES]; /* The node mapping from the system to the database */
|
||||
|
||||
/* Data for non-coherent initilization */
|
||||
u8 AutoBusCurrent;
|
||||
u8 UsedCfgMapEntires;
|
||||
|
||||
/* 'This' pointer for northbridge */
|
||||
cNorthBridge *nb;
|
||||
} sMainData;
|
||||
|
||||
#endif /* H3FFEAT_H */
|
||||
1678
src/northbridge/amd/amdht/h3finit.c
Normal file
1678
src/northbridge/amd/amdht/h3finit.c
Normal file
File diff suppressed because it is too large
Load Diff
613
src/northbridge/amd/amdht/h3finit.h
Normal file
613
src/northbridge/amd/amdht/h3finit.h
Normal file
@ -0,0 +1,613 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef H3FINIT_H
|
||||
#define H3FINIT_H
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* DEFINITIONS AND MACROS
|
||||
*
|
||||
*-----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/* Width equates for call backs */
|
||||
#define HT_WIDTH_8_BITS 8
|
||||
#define HT_WIDTH_16_BITS 16
|
||||
#define HT_WIDTH_4_BITS 4
|
||||
#define HT_WIDTH_2_BITS 2
|
||||
|
||||
/* Frequency equates for call backs which take an actual frequency setting */
|
||||
#define HT_FREQUENCY_200M 0
|
||||
#define HT_FREQUENCY_400M 2
|
||||
#define HT_FREQUENCY_600M 4
|
||||
#define HT_FREQUENCY_800M 5
|
||||
#define HT_FREQUENCY_1000M 6
|
||||
#define HT_FREQUENCY_1200M 7
|
||||
#define HT_FREQUENCY_1400M 8
|
||||
#define HT_FREQUENCY_1600M 9
|
||||
#define HT_FREQUENCY_1800M 10
|
||||
#define HT_FREQUENCY_2000M 11
|
||||
#define HT_FREQUENCY_2200M 12
|
||||
#define HT_FREQUENCY_2400M 13
|
||||
#define HT_FREQUENCY_2600M 14
|
||||
|
||||
/* Frequency Limit equates for call backs which take a frequency supported mask. */
|
||||
#define HT_FREQUENCY_LIMIT_200M 1
|
||||
#define HT_FREQUENCY_LIMIT_400M 7
|
||||
#define HT_FREQUENCY_LIMIT_600M 0x1F
|
||||
#define HT_FREQUENCY_LIMIT_800M 0x3F
|
||||
#define HT_FREQUENCY_LIMIT_1000M 0x7F
|
||||
#define HT_FREQUENCY_LIMIT_HT1_ONLY 0x7F
|
||||
#define HT_FREQUENCY_LIMIT_1200M 0xFF
|
||||
#define HT_FREQUENCY_LIMIT_1400M 0x1FF
|
||||
#define HT_FREQUENCY_LIMIT_1600M 0x3FF
|
||||
#define HT_FREQUENCY_LIMIT_1800M 0x7FF
|
||||
#define HT_FREQUENCY_LIMIT_2000M 0xFFF
|
||||
#define HT_FREQUENCY_LIMIT_2200M 0x1FFF
|
||||
#define HT_FREQUENCY_LIMIT_2400M 0x3FFF
|
||||
#define HT_FREQUENCY_LIMIT_2600M 0x7FFF
|
||||
|
||||
/*
|
||||
* Event Notify definitions
|
||||
*/
|
||||
|
||||
/* Event Class definitions */
|
||||
#define HT_EVENT_CLASS_CRITICAL 1
|
||||
#define HT_EVENT_CLASS_ERROR 2
|
||||
#define HT_EVENT_CLASS_HW_FAULT 3
|
||||
#define HT_EVENT_CLASS_WARNING 4
|
||||
#define HT_EVENT_CLASS_INFO 5
|
||||
|
||||
/* Event definitions. */
|
||||
|
||||
/* Coherent subfunction events */
|
||||
#define HT_EVENT_COH_EVENTS 0x1000
|
||||
#define HT_EVENT_COH_NO_TOPOLOGY 0x1001
|
||||
#define HT_EVENT_COH_LINK_EXCEED 0x1002
|
||||
#define HT_EVENT_COH_FAMILY_FEUD 0x1003
|
||||
#define HT_EVENT_COH_NODE_DISCOVERED 0x1004
|
||||
#define HT_EVENT_COH_MPCAP_MISMATCH 0x1005
|
||||
|
||||
/* Non-coherent subfunction events */
|
||||
#define HT_EVENT_NCOH_EVENTS 0x2000
|
||||
#define HT_EVENT_NCOH_BUID_EXCEED 0x2001
|
||||
#define HT_EVENT_NCOH_LINK_EXCEED 0x2002
|
||||
#define HT_EVENT_NCOH_BUS_MAX_EXCEED 0x2003
|
||||
#define HT_EVENT_NCOH_CFG_MAP_EXCEED 0x2004
|
||||
#define HT_EVENT_NCOH_DEVICE_FAILED 0x2005
|
||||
#define HT_EVENT_NCOH_AUTO_DEPTH 0x2006
|
||||
|
||||
/* Optimization subfunction events */
|
||||
#define HT_EVENT_OPT_EVENTS 0x3000
|
||||
#define HT_EVENT_OPT_REQUIRED_CAP_RETRY 0x3001
|
||||
#define HT_EVENT_OPT_REQUIRED_CAP_GEN3 0x3002
|
||||
|
||||
/* HW Fault events */
|
||||
#define HT_EVENT_HW_EVENTS 0x4000
|
||||
#define HT_EVENT_HW_SYNCHFLOOD 0x4001
|
||||
#define HT_EVENT_HW_HTCRC 0x4002
|
||||
|
||||
/* The bbHT component (hb*) uses 0x5000 for events.
|
||||
* For consistency, we avoid that range here.
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* TYPEDEFS, STRUCTURES, ENUMS
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
typedef struct {
|
||||
u8 **topolist;
|
||||
u8 AutoBusStart;
|
||||
/* Note: This should always be the form AutoBusCurrent+N*AutoBusIncrement, also bus 253-255 are reserved */
|
||||
u8 AutoBusMax;
|
||||
u8 AutoBusIncrement;
|
||||
|
||||
/**----------------------------------------------------------------------------------------
|
||||
*
|
||||
* BOOL
|
||||
* AMD_CB_IgnoreLink(u8 Node, u8 Link)
|
||||
*
|
||||
* Description:
|
||||
* This routine is called every time a coherent link is found and then every
|
||||
* time a non-coherent link from a CPU is found.
|
||||
* Any coherent or non-coherent link from a CPU can be ignored and not used
|
||||
* for discovery or initialization. Useful for connection based systems.
|
||||
* (Note: not called for IO device to IO Device links.)
|
||||
*
|
||||
* Parameters:
|
||||
* @param[in] u8 node = The node on which this link is located
|
||||
* @param[in] u8 link = The link about to be initialized
|
||||
* @param[out] BOOL result = true to ignore this link and skip it
|
||||
* false to initialize the link normally
|
||||
*
|
||||
* ---------------------------------------------------------------------------------------
|
||||
*/
|
||||
BOOL (*AMD_CB_IgnoreLink)(u8 Node, u8 Link);
|
||||
|
||||
/**----------------------------------------------------------------------------------------
|
||||
*
|
||||
* BOOL
|
||||
* AMD_CB_OverrideBusNumbers(u8 Node, u8 Link, u8 *SecBus, u8 *SubBus)
|
||||
*
|
||||
* Description:
|
||||
* This routine is called every time a non-coherent chain is processed.
|
||||
* If a system can not use the auto Bus numbering feature for non-coherent chain bus
|
||||
* assignments, this routine can provide explicit control. For each chain, provide
|
||||
* the bus number range to use.
|
||||
*
|
||||
* Parameters:
|
||||
* @param[in] u8 node = The node on which this chain is located
|
||||
* @param[in] u8 link = The link on the host for this chain
|
||||
* @param[out] u8 secBus = Secondary Bus number for this non-coherent chain
|
||||
* @param[out] u8* subBus = Subordinate Bus number
|
||||
* @param[out] BOOL result = true this routine is supplying the bus numbers
|
||||
* false use auto Bus numbering
|
||||
*
|
||||
* ---------------------------------------------------------------------------------------
|
||||
*/
|
||||
BOOL (*AMD_CB_OverrideBusNumbers)(u8 Node, u8 Link, u8 *SecBus, u8 *SubBus);
|
||||
|
||||
/**----------------------------------------------------------------------------------------
|
||||
*
|
||||
* BOOL
|
||||
* AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
|
||||
*
|
||||
* Description:
|
||||
* This routine is called every time a non-coherent chain is processed.
|
||||
* BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
|
||||
* swap list. The first part of the list controls the BUID assignment and the
|
||||
* second part of the list provides the device to device linking. Device orientation
|
||||
* can be detected automatically, or explicitly. See documentation for more details.
|
||||
*
|
||||
* Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
|
||||
* based on each device's unit count.
|
||||
*
|
||||
* Parameters:
|
||||
* @param[in] u8 node = The node on which this chain is located
|
||||
* @param[in] u8 link = The link on the host for this chain
|
||||
* @param[out] u8** list = supply a pointer to a list
|
||||
* @param[out] BOOL result = true to use a manual list
|
||||
* false to initialize the link automatically
|
||||
*
|
||||
* ---------------------------------------------------------------------------------------
|
||||
*/
|
||||
BOOL (*AMD_CB_ManualBUIDSwapList)(u8 Node, u8 Link, u8 **List);
|
||||
|
||||
/**----------------------------------------------------------------------------------------
|
||||
*
|
||||
* void
|
||||
* AMD_CB_DeviceCapOverride(u8 HostNode, u8 HostLink, u8 Depth, u8 Segment,
|
||||
* u8 Bus, u8 Dev, u32 DevVenID, u8 Link,
|
||||
* u8 *LinkWidthIn, u8 *LinkWidthOut, u16 *FreqCap)
|
||||
*
|
||||
* Description:
|
||||
* This routine is called once for every link on every IO device.
|
||||
* Update the width and frequency capability if needed for this device.
|
||||
* This is used along with device capabilities, the limit call backs, and northbridge
|
||||
* limits to compute the default settings. The components of the device's PCI config
|
||||
* address are provided, so its settings can be consulted if need be. The input width
|
||||
* and frequency are the reported device capabilities.
|
||||
*
|
||||
* Parameters:
|
||||
* @param[in] u8 hostNode = The node on which this chain is located
|
||||
* @param[in] u8 hostLink = The link on the host for this chain
|
||||
* @param[in] u8 Depth = The depth in the I/O chain from the Host
|
||||
* @param[in] u8 Segment = The Device's PCI Bus Segment number
|
||||
* @param[in] u8 Bus = The Device's PCI Bus number
|
||||
* @param[in] u8 Dev = The Device's PCI device Number
|
||||
* @param[in] u32 DevVenID = The Device's PCI Vendor + Device ID (offset 0x00)
|
||||
* @param[in] u8 Link = The Device's link number (0 or 1)
|
||||
* @param[in,out] u8* LinkWidthIn = modify to change the Link Witdh In
|
||||
* @param[in,out] u8* LinkWidthOut = modify to change the Link Witdh Out
|
||||
* @param[in,out] u16* FreqCap = modify to change the link's frequency capability
|
||||
*
|
||||
* ---------------------------------------------------------------------------------------
|
||||
*/
|
||||
void (*AMD_CB_DeviceCapOverride)(
|
||||
u8 HostNode,
|
||||
u8 HostLink,
|
||||
u8 Depth,
|
||||
u8 Segment,
|
||||
u8 Bus,
|
||||
u8 Dev,
|
||||
u32 DevVenID,
|
||||
u8 Link,
|
||||
u8 *LinkWidthIn,
|
||||
u8 *LinkWidthOut,
|
||||
u16 *FreqCap
|
||||
);
|
||||
|
||||
/**----------------------------------------------------------------------------------------
|
||||
*
|
||||
* void
|
||||
* AMD_CB_Cpu2CpuPCBLimits(u8 NodeA, u8 LinkA, u8 NodeB, u8 LinkB,
|
||||
* u8 *ABLinkWidthLimit, u8 *BALinkWidthLimit, u16 *PCBFreqCap)
|
||||
*
|
||||
* Description:
|
||||
* For each coherent connection this routine is called once.
|
||||
* Update the frequency and width if needed for this link (usually based on board
|
||||
* restriction). This is used with CPU device capabilities and northbridge limits
|
||||
* to compute the default settings. The input width and frequency are valid, but do
|
||||
* not necessarily reflect the minimum setting that will be chosen.
|
||||
*
|
||||
* Parameters:
|
||||
* @param[in] u8 nodeA = One node on which this link is located
|
||||
* @param[in] u8 linkA = The link on this node
|
||||
* @param[in] u8 nodeB = The other node on which this link is located
|
||||
* @param[in] u8 linkB = The link on that node
|
||||
* @param[in,out] u8* ABLinkWidthLimit = modify to change the Link Witdh In
|
||||
* @param[in,out] u8* BALinkWidthLimit = modify to change the Link Witdh Out
|
||||
* @param[in,out] u16* PCBFreqCap = modify to change the link's frequency capability
|
||||
*
|
||||
* ---------------------------------------------------------------------------------------
|
||||
*/
|
||||
void (*AMD_CB_Cpu2CpuPCBLimits)(
|
||||
u8 NodeA,
|
||||
u8 LinkA,
|
||||
u8 NodeB,
|
||||
u8 LinkB,
|
||||
u8 *ABLinkWidthLimit,
|
||||
u8 *BALinkWidthLimit,
|
||||
u16 *PCBFreqCap
|
||||
);
|
||||
|
||||
/**----------------------------------------------------------------------------------------
|
||||
*
|
||||
* void
|
||||
* AMD_CB_IOPCBLimits(u8 HostNode, u8 HostLink, u8 Depth, u8 *DownstreamLinkWidthLimit,
|
||||
* u8 *UpstreamLinkWidthLimit, u16 *PCBFreqCap)
|
||||
*
|
||||
* Description:
|
||||
* For each non-coherent connection this routine is called once.
|
||||
* Update the frequency and width if needed for this link (usually based on board
|
||||
* restriction). This is used with device capabilities, device overrides, and northbridge limits
|
||||
* to compute the default settings. The input width and frequency are valid, but do
|
||||
* not necessarily reflect the minimum setting that will be chosen.
|
||||
*
|
||||
* Parameters:
|
||||
* @param[in] u8 hostNode = The node on which this link is located
|
||||
* @param[in] u8 hostLink = The link about to be initialized
|
||||
* @param[in] u8 Depth = The depth in the I/O chain from the Host
|
||||
* @param[in,out] u8* DownstreamLinkWidthLimit = modify to change the Link Witdh In
|
||||
* @param[in,out] u8* UpstreamLinkWidthLimit = modify to change the Link Witdh Out
|
||||
* @param[in,out] u16* PCBFreqCap = modify to change the link's frequency capability
|
||||
*
|
||||
* ---------------------------------------------------------------------------------------
|
||||
*/
|
||||
void (*AMD_CB_IOPCBLimits)(
|
||||
u8 HostNode,
|
||||
u8 HostLink,
|
||||
u8 Depth,
|
||||
u8 *DownstreamLinkWidthLimit,
|
||||
u8 *UpstreamLinkWidthLimit,
|
||||
u16 *PCBFreqCap
|
||||
);
|
||||
|
||||
/**----------------------------------------------------------------------------------------
|
||||
*
|
||||
* BOOL
|
||||
* AMD_CB_SkipRegang(u8 NodeA, u8 LinkA, u8 NodeB, u8 LinkB)
|
||||
*
|
||||
* Description:
|
||||
* This routine is called whenever two sublinks are both connected to the same CPUs.
|
||||
* Normally, unganged subsinks between the same two CPUs are reganged.
|
||||
* Return true from this routine to leave the links unganged.
|
||||
*
|
||||
* Parameters:
|
||||
* @param[in] u8 nodeA = One node on which this link is located
|
||||
* @param[in] u8 linkA = The link on this node
|
||||
* @param[in] u8 nodeB = The other node on which this link is located
|
||||
* @param[in] u8 linkB = The link on that node
|
||||
* @param[out] BOOL result = true to leave link unganged
|
||||
* false to regang link automatically
|
||||
*
|
||||
* ---------------------------------------------------------------------------------------
|
||||
*/
|
||||
BOOL (*AMD_CB_SkipRegang)(
|
||||
u8 NodeA,
|
||||
u8 LinkA,
|
||||
u8 NodeB,
|
||||
u8 LinkB
|
||||
);
|
||||
|
||||
/**----------------------------------------------------------------------------------------
|
||||
*
|
||||
* BOOL
|
||||
* AMD_CB_CustomizeTrafficDistribution()
|
||||
*
|
||||
* Description:
|
||||
* Near the end of HT initialization, this routine is called once.
|
||||
* If this routine will handle traffic distribution in a proprietary way,
|
||||
* after detecting which links to distribute traffic on and configuring the system,
|
||||
* return true. Return false to let the HT code detect and do traffic distribution
|
||||
* This routine can also be used to simply turn this feature off, or to pre-process
|
||||
* the system before normal traffic distribution.
|
||||
*
|
||||
* Parameters:
|
||||
* @param[out] BOOL result = true skip traffic distribution
|
||||
* false do normal traffic distribution
|
||||
*
|
||||
* ---------------------------------------------------------------------------------------
|
||||
*/
|
||||
BOOL (*AMD_CB_CustomizeTrafficDistribution)();
|
||||
|
||||
|
||||
/**----------------------------------------------------------------------------------------
|
||||
*
|
||||
* BOOL
|
||||
* AMD_CB_CustomizeBuffers(u8 Node)
|
||||
*
|
||||
* Description:
|
||||
* Near the end of HT initialization, this routine is called once per CPU node.
|
||||
* Implement proprietary buffer tuning and return true, or return false for normal tuning.
|
||||
* This routine can also be used to simply turn this feature off, or to pre-process
|
||||
* the system before normal tuning.
|
||||
*
|
||||
* Parameters:
|
||||
* @param[in] u8 node = buffer allocation may apply to this node
|
||||
* @param[out] BOOL result = true skip buffer allocation on this node
|
||||
* false tune buffers normally
|
||||
*
|
||||
* ---------------------------------------------------------------------------------------
|
||||
*/
|
||||
BOOL (*AMD_CB_CustomizeBuffers)( u8 node );
|
||||
|
||||
/**----------------------------------------------------------------------------------------
|
||||
*
|
||||
* void
|
||||
* AMD_CB_OverrideDevicePort(u8 HostNode, u8 HostLink, u8 Depth, u8 *LinkWidthIn,
|
||||
* u8 *LinkWidthOut, u16 *LinkFrequency)
|
||||
*
|
||||
* Description:
|
||||
* Called once for each active link on each IO device.
|
||||
* Provides an opportunity to directly control the frequency and width,
|
||||
* intended for test and debug. The input frequency and width will be used
|
||||
* if not overridden.
|
||||
*
|
||||
* Parameters:
|
||||
* @param[in] u8 hostNode = The node on which this link is located
|
||||
* @param[in] u8 hostLink = The link about to be initialized
|
||||
* @param[in] u8 Depth = The depth in the I/O chain from the Host
|
||||
* @param[in] u8 Link = the link on the device (0 or 1)
|
||||
* @param[in,out] u8* LinkWidthIn = modify to change the Link Witdh In
|
||||
* @param[in,out] u8* LinkWidthOut = modify to change the Link Witdh Out
|
||||
* @param[in,out] u16* LinkFrequency = modify to change the link's frequency capability
|
||||
*
|
||||
* ---------------------------------------------------------------------------------------
|
||||
*/
|
||||
void (*AMD_CB_OverrideDevicePort)(
|
||||
u8 HostNode,
|
||||
u8 HostLink,
|
||||
u8 Depth,
|
||||
u8 Link,
|
||||
u8 *LinkWidthIn,
|
||||
u8 *LinkWidthOut,
|
||||
u8 *LinkFrequency
|
||||
);
|
||||
|
||||
/**----------------------------------------------------------------------------------------
|
||||
*
|
||||
* void
|
||||
* AMD_CB_OverrideCpuPort(u8 Node, u8 Link, u8 *LinkWidthIn, u8 *LinkWidthOut,
|
||||
* u16 *LinkFrequency)
|
||||
*
|
||||
* Description:
|
||||
* Called once for each active link on each CPU.
|
||||
* Provides an opportunity to directly control the frequency and width,
|
||||
* intended for test and debug. The input frequency and width will be used
|
||||
* if not overridden.
|
||||
*
|
||||
* Parameters:
|
||||
* @param[in] u8 node = One node on which this link is located
|
||||
* @param[in] u8 link = The link on this node
|
||||
* @param[in,out] u8* LinkWidthIn = modify to change the Link Witdh In
|
||||
* @param[in,out] u8* LinkWidthOut = modify to change the Link Witdh Out
|
||||
* @param[in,out] u16* LinkFrequency = modify to change the link's frequency capability
|
||||
*
|
||||
*---------------------------------------------------------------------------------------
|
||||
*/
|
||||
void (*AMD_CB_OverrideCpuPort)(
|
||||
u8 Node,
|
||||
u8 Link,
|
||||
u8 *LinkWidthIn,
|
||||
u8 *LinkWidthOut,
|
||||
u8 *LinkFrequency
|
||||
);
|
||||
|
||||
/**----------------------------------------------------------------------------------------
|
||||
*
|
||||
* void
|
||||
* AMD_CB_EventNotify(u8 evtClass, u16 event, const u8 *pEventData0)
|
||||
*
|
||||
* Description:
|
||||
* Errors, events, faults, warnings, and useful information are provided by
|
||||
* calling this routine as often as necessary, once for each notification.
|
||||
* See elsewhere in this file for class, event, and event data definitions.
|
||||
* See the documentation for more details.
|
||||
*
|
||||
* Parameters:
|
||||
* @param[in] u8 evtClass = What level event is this
|
||||
* @param[in] u16 event = A unique ID of this event
|
||||
* @param[in] u8* pEventData0 = useful data associated with the event.
|
||||
*
|
||||
* ---------------------------------------------------------------------------------------
|
||||
*/
|
||||
void (*AMD_CB_EventNotify) (
|
||||
u8 evtClass,
|
||||
u16 event,
|
||||
const u8 *pEventData0
|
||||
);
|
||||
|
||||
} AMD_HTBLOCK;
|
||||
|
||||
/*
|
||||
* Event Notification Structures
|
||||
* These structures are passed to AMD_CB_EventNotify as *pEventData0.
|
||||
*/
|
||||
|
||||
/* For event HT_EVENT_HW_SYNCHFLOOD */
|
||||
typedef struct
|
||||
{
|
||||
u8 eSize;
|
||||
u8 node;
|
||||
u8 link;
|
||||
} sHtEventHWSynchFlood;
|
||||
|
||||
/* For event HT_EVENT_HW_HTCRC */
|
||||
typedef struct
|
||||
{
|
||||
u8 eSize;
|
||||
u8 node;
|
||||
u8 link;
|
||||
u8 laneMask;
|
||||
} sHtEventHWHtCrc;
|
||||
|
||||
/* For event HT_EVENT_NCOH_BUS_MAX_EXCEED */
|
||||
typedef struct
|
||||
{
|
||||
u8 eSize;
|
||||
u8 node;
|
||||
u8 link;
|
||||
u8 bus;
|
||||
} sHTEventNcohBusMaxExceed;
|
||||
|
||||
/* For event HT_EVENT_NCOH_LINK_EXCEED */
|
||||
typedef struct
|
||||
{
|
||||
u8 eSize;
|
||||
u8 node;
|
||||
u8 link;
|
||||
u8 depth;
|
||||
u8 maxLinks;
|
||||
} sHtEventNcohLinkExceed;
|
||||
|
||||
/* For event HT_EVENT_NCOH_CFG_MAP_EXCEED */
|
||||
typedef struct
|
||||
{
|
||||
u8 eSize;
|
||||
u8 node;
|
||||
u8 link;
|
||||
} sHtEventNcohCfgMapExceed;
|
||||
|
||||
/* For event HT_EVENT_NCOH_BUID_EXCEED */
|
||||
typedef struct
|
||||
{
|
||||
u8 eSize;
|
||||
u8 node;
|
||||
u8 link;
|
||||
u8 depth;
|
||||
u8 currentBUID;
|
||||
u8 unitCount;
|
||||
} sHtEventNcohBuidExceed;
|
||||
|
||||
/* For event HT_EVENT_NCOH_DEVICE_FAILED */
|
||||
typedef struct
|
||||
{
|
||||
u8 eSize;
|
||||
u8 node;
|
||||
u8 link;
|
||||
u8 depth;
|
||||
u8 attemptedBUID;
|
||||
} sHtEventNcohDeviceFailed;
|
||||
|
||||
/* For event HT_EVENT_NCOH_AUTO_DEPTH */
|
||||
typedef struct
|
||||
{
|
||||
u8 eSize;
|
||||
u8 node;
|
||||
u8 link;
|
||||
u8 depth;
|
||||
} sHtEventNcohAutoDepth;
|
||||
|
||||
/* For event HT_EVENT_OPT_REQUIRED_CAP_RETRY,
|
||||
* HT_EVENT_OPT_REQUIRED_CAP_GEN3
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
u8 eSize;
|
||||
u8 node;
|
||||
u8 link;
|
||||
u8 depth;
|
||||
} sHtEventOptRequiredCap;
|
||||
|
||||
/* For event HT_EVENT_COH_NO_TOPOLOGY */
|
||||
typedef struct
|
||||
{
|
||||
u8 eSize;
|
||||
u8 totalNodes;
|
||||
} sHtEventCohNoTopology;
|
||||
|
||||
/* For event HT_EVENT_COH_LINK_EXCEED */
|
||||
typedef struct
|
||||
{
|
||||
u8 eSize;
|
||||
u8 node;
|
||||
u8 link;
|
||||
u8 targetNode;
|
||||
u8 totalNodes;
|
||||
u8 maxLinks;
|
||||
} sHtEventCohLinkExceed;
|
||||
|
||||
/* For event HT_EVENT_COH_FAMILY_FEUD */
|
||||
typedef struct
|
||||
{
|
||||
u8 eSize;
|
||||
u8 node;
|
||||
u8 link;
|
||||
u8 totalNodes;
|
||||
} sHtEventCohFamilyFeud;
|
||||
|
||||
/* For event HT_EVENT_COH_NODE_DISCOVERED */
|
||||
typedef struct
|
||||
{
|
||||
u8 eSize;
|
||||
u8 node;
|
||||
u8 link;
|
||||
u8 newNode;
|
||||
} sHtEventCohNodeDiscovered;
|
||||
|
||||
/* For event HT_EVENT_COH_MPCAP_MISMATCH */
|
||||
typedef struct
|
||||
{
|
||||
u8 eSize;
|
||||
u8 node;
|
||||
u8 link;
|
||||
u8 sysMpCap;
|
||||
u8 totalNodes;
|
||||
} sHtEventCohMpCapMismatch;
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* FUNCTIONS PROTOTYPE
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
void amdHtInitialize(AMD_HTBLOCK *pBlock);
|
||||
|
||||
|
||||
#endif /* H3FINIT_H */
|
||||
|
||||
|
||||
358
src/northbridge/amd/amdht/h3gtopo.h
Normal file
358
src/northbridge/amd/amdht/h3gtopo.h
Normal file
@ -0,0 +1,358 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software * you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation * version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY * without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program * if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef HTTOPO_H
|
||||
#define HTTOPO_H
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* DEFINITIONS AND MACROS
|
||||
*
|
||||
*-----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* TYPEDEFS, STRUCTURES, ENUMS
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*
|
||||
* 0
|
||||
*/
|
||||
static u8 const amdHtTopologySingleNode[] = {
|
||||
0x01,
|
||||
0x00, 0xFF // Node 0
|
||||
};
|
||||
|
||||
/*
|
||||
* 0---1
|
||||
*/
|
||||
static u8 const amdHtTopologyDualNode[] = {
|
||||
0x02,
|
||||
0x02, 0xFF, 0x00, 0x11, // Node 0
|
||||
0x00, 0x00, 0x01, 0xFF // Node 1
|
||||
};
|
||||
|
||||
/*
|
||||
* 2
|
||||
* |
|
||||
* |
|
||||
* 0---1
|
||||
*/
|
||||
static u8 const amdHtTopologyThreeLine[] = {
|
||||
0x03,
|
||||
0x06, 0xFF, 0x04, 0x11, 0x02, 0x22, // Node 0
|
||||
0x00, 0x00, 0x01, 0xFF, 0x00, 0x00, // Node 1
|
||||
0x00, 0x00, 0x00, 0x00, 0x01, 0xFF // Node 2
|
||||
};
|
||||
|
||||
/*
|
||||
* 2
|
||||
* |\
|
||||
* | \
|
||||
* 0---1
|
||||
*/
|
||||
static u8 const amdHtTopologyTriangle[] = {
|
||||
0x03,
|
||||
0x06, 0xFF, 0x00, 0x11, 0x00, 0x22, // Node 0
|
||||
0x00, 0x00, 0x05, 0xFF, 0x00, 0x22, // Node 1
|
||||
0x00, 0x00, 0x00, 0x11, 0x03, 0xFF // Node 2
|
||||
};
|
||||
|
||||
/*
|
||||
* 2 3
|
||||
* |\ |
|
||||
* | \|
|
||||
* 0---1
|
||||
*/
|
||||
static u8 const amdHtTopologyFourDegenerate[] = {
|
||||
0x04,
|
||||
0x06, 0xFF, 0x00, 0x11, 0x00, 0x22, 0x00, 0x11, // Node 0
|
||||
0x08, 0x00, 0x0D, 0xFF, 0x08, 0x22, 0x05, 0x33, // Node 1
|
||||
0x00, 0x00, 0x00, 0x11, 0x03, 0xFF, 0x00, 0x11, // Node 2
|
||||
0x00, 0x11, 0x00, 0x11, 0x00, 0x11, 0x02, 0xFF // Node 3
|
||||
};
|
||||
|
||||
/*
|
||||
* 2---3
|
||||
* |\ /|
|
||||
* |/ \|
|
||||
* 0---1
|
||||
*/
|
||||
static u8 const amdHtTopologyFourFully[] = {
|
||||
0x04,
|
||||
0x0E, 0xFF, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, // Node 0
|
||||
0x00, 0x00, 0x0D, 0xFF, 0x00, 0x22, 0x00, 0x33, // Node 1
|
||||
0x00, 0x00, 0x00, 0x11, 0x0B, 0xFF, 0x00, 0x33, // Node 2
|
||||
0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x07, 0xFF // Node 3
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* 2---3
|
||||
* |\ |
|
||||
* | \|
|
||||
* 0---1
|
||||
*/
|
||||
static u8 const amdHtTopologyFourKite[] = {
|
||||
0x04,
|
||||
0x06, 0xFF, 0x00, 0x11, 0x00, 0x22, 0x00, 0x11, // Node 0
|
||||
0x08, 0x00, 0x0D, 0xFF, 0x00, 0x22, 0x00, 0x33, // Node 1
|
||||
0x00, 0x00, 0x00, 0x11, 0x0B, 0xFF, 0x01, 0x33, // Node 2
|
||||
0x00, 0x22, 0x00, 0x11, 0x00, 0x22, 0x06, 0xFF // Node 3
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* 2 3
|
||||
* | |
|
||||
* | |
|
||||
* 0---1
|
||||
*/
|
||||
static u8 const amdHtTopologyFourLine[] = {
|
||||
0x04,
|
||||
0x06, 0xFF, 0x04, 0x11, 0x02, 0x22, 0x04, 0x11, // Node 0
|
||||
0x08, 0x00, 0x09, 0xFF, 0x08, 0x00, 0x01, 0x33, // Node 1
|
||||
0x00, 0x00, 0x00, 0x00, 0x01, 0xFF, 0x00, 0x00, // Node 2
|
||||
0x00, 0x11, 0x00, 0x11, 0x00, 0x11, 0x02, 0xFF // Node 3
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* 2---3
|
||||
* | |
|
||||
* | |
|
||||
* 0---1
|
||||
*/
|
||||
static u8 const amdHtTopologyFourSquare[] = {
|
||||
0x04,
|
||||
0x06, 0xFF, 0x00, 0x11, 0x02, 0x22, 0x00, 0x22, // Node 0
|
||||
0x00, 0x00, 0x09, 0xFF, 0x00, 0x33, 0x01, 0x33, // Node 1
|
||||
0x08, 0x00, 0x00, 0x00, 0x09, 0xFF, 0x00, 0x33, // Node 2
|
||||
0x00, 0x11, 0x04, 0x11, 0x00, 0x22, 0x06, 0xFF, // Node 3
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* 2---3
|
||||
* |\
|
||||
* | \
|
||||
* 0 1
|
||||
*/
|
||||
static u8 const amdHtTopologyFourStar[] = {
|
||||
0x04,
|
||||
0x04, 0xFF, 0x00, 0x22, 0x00, 0x22, 0x00, 0x22, // Node 0
|
||||
0x00, 0x22, 0x04, 0xFF, 0x00, 0x22, 0x00, 0x22, // Node 1
|
||||
0x0A, 0x00, 0x09, 0x11, 0x0B, 0xFF, 0x03, 0x33, // Node 2
|
||||
0x00, 0x22, 0x00, 0x22, 0x00, 0x22, 0x04, 0xFF, // Node 3
|
||||
};
|
||||
|
||||
|
||||
static u8 const amdHtTopologyFiveFully[] = {
|
||||
0x05,
|
||||
0x1E, 0xFF, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, // Node 0
|
||||
0x00, 0x00, 0x1D, 0xFF, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, // Node 1
|
||||
0x00, 0x00, 0x00, 0x11, 0x1B, 0xFF, 0x00, 0x33, 0x00, 0x44, // Node 2
|
||||
0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x17, 0xFF, 0x00, 0x44, // Node 3
|
||||
0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x0F, 0xFF // Node 4
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
*
|
||||
* 4
|
||||
* |\
|
||||
* | \
|
||||
* 2 3
|
||||
* | |
|
||||
* 0---1
|
||||
*/
|
||||
static u8 const amdHtTopologyFiveTwistedLadder[] = {
|
||||
0x05,
|
||||
0x06, 0xFF, 0x04, 0x11, 0x02, 0x22, 0x00, 0x11, 0x00, 0x22, // Node0
|
||||
0x08, 0x00, 0x09, 0xFF, 0x08, 0x00, 0x01, 0x33, 0x00, 0x30, // Node1
|
||||
0x10, 0x00, 0x10, 0x00, 0x11, 0xFF, 0x00, 0x40, 0x01, 0x44, // Node2
|
||||
0x00, 0x11, 0x00, 0x11, 0x00, 0x14, 0x12, 0xFF, 0x02, 0x44, // Node3
|
||||
0x00, 0x22, 0x00, 0x23, 0x00, 0x22, 0x04, 0x33, 0x0C, 0xFF // Node4
|
||||
};
|
||||
|
||||
|
||||
static u8 const amdHtTopologySixFully[] = {
|
||||
0x06,
|
||||
0x3E, 0xFF, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, // Node 0
|
||||
0x00, 0x00, 0x3D, 0xFF, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, // Node 1
|
||||
0x00, 0x00, 0x00, 0x11, 0x3B, 0xFF, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, // Node 2
|
||||
0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x37, 0xFF, 0x00, 0x44, 0x00, 0x55, // Node 3
|
||||
0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x2F, 0xFF, 0x00, 0x55, // Node 4
|
||||
0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x1F, 0xFF // Node 5
|
||||
};
|
||||
|
||||
/*
|
||||
*
|
||||
* 4 5
|
||||
* |\ /|
|
||||
* |/ \|
|
||||
* 2 3
|
||||
* | |
|
||||
* 0---1
|
||||
*/
|
||||
static u8 const amdHtTopologySixTwistedLadder[] = {
|
||||
0x06,
|
||||
0x06, 0xFF, 0x04, 0x11, 0x02, 0x22, 0x00, 0x11, 0x02, 0x22, 0x00, 0x12, // Node0
|
||||
0x08, 0x00, 0x09, 0xFF, 0x00, 0x00, 0x01, 0x33, 0x00, 0x03, 0x01, 0x33, // Node1
|
||||
0x30, 0x00, 0x00, 0x00, 0x31, 0xFF, 0x00, 0x54, 0x21, 0x44, 0x00, 0x55, // Node2
|
||||
0x00, 0x11, 0x30, 0x11, 0x00, 0x45, 0x32, 0xFF, 0x00, 0x44, 0x12, 0x55, // Node3
|
||||
0x00, 0x22, 0x00, 0x32, 0x08, 0x22, 0x00, 0x33, 0x0C, 0xFF, 0x00, 0x32, // Node4
|
||||
0x00, 0x23, 0x00, 0x33, 0x00, 0x22, 0x04, 0x33, 0x00, 0x23, 0x0C, 0xFF // Node5
|
||||
};
|
||||
|
||||
|
||||
static u8 const amdHtTopologySevenFully[] = {
|
||||
0x07,
|
||||
0x7E, 0xFF, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, // Node 0
|
||||
0x00, 0x00, 0x7D, 0xFF, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, // Node 1
|
||||
0x00, 0x00, 0x00, 0x11, 0x7B, 0xFF, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, // Node 2
|
||||
0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x77, 0xFF, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, // Node 3
|
||||
0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x6F, 0xFF, 0x00, 0x55, 0x00, 0x66, // Node 4
|
||||
0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x5F, 0xFF, 0x00, 0x66, // Node 5
|
||||
0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0x3F, 0xFF, // Node 6
|
||||
};
|
||||
|
||||
|
||||
/* 6
|
||||
* |
|
||||
* 4 5
|
||||
* |\ /|
|
||||
* |/ \|
|
||||
* 2 3
|
||||
* | |
|
||||
* 0---1
|
||||
*/
|
||||
static u8 const amdHtTopologySevenTwistedLadder[] = {
|
||||
0x07,
|
||||
0x06, 0xFF, 0x00, 0x11, 0x02, 0x22, 0x00, 0x12, 0x00, 0x22, 0x00, 0x22, 0x00, 0x22, // Node0
|
||||
0x00, 0x00, 0x09, 0xFF, 0x00, 0x03, 0x01, 0x33, 0x00, 0x33, 0x00, 0x33, 0x00, 0x33, // Node1
|
||||
0x30, 0x00, 0x00, 0x50, 0x31, 0xFF, 0x00, 0x54, 0x21, 0x44, 0x01, 0x55, 0x21, 0x44, // Node2
|
||||
0x00, 0x41, 0x30, 0x11, 0x00, 0x45, 0x32, 0xFF, 0x02, 0x44, 0x12, 0x55, 0x02, 0x44, // Node3
|
||||
0x48, 0x22, 0x40, 0x33, 0x48, 0x22, 0x40, 0x33, 0x4C, 0xFF, 0x40, 0x32, 0x0C, 0x66, // Node4
|
||||
0x00, 0x22, 0x04, 0x33, 0x00, 0x22, 0x04, 0x33, 0x00, 0x23, 0x0C, 0xFF, 0x00, 0x23, // Node5
|
||||
0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x10, 0xFF // Node6
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* 5--4
|
||||
* /####\
|
||||
* 6######3
|
||||
* |######|
|
||||
* 7######2
|
||||
* \####/
|
||||
* 0--1
|
||||
*/
|
||||
static u8 const amdHtTopologyEightFully [] = {
|
||||
0x08,
|
||||
0xFE, 0xFF, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, 0x00, 0x77, // Node 0
|
||||
0x00, 0x00, 0xFD, 0xFF, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, 0x00, 0x77, // Node 1
|
||||
0x00, 0x00, 0x00, 0x11, 0xFB, 0xFF, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, 0x00, 0x77, // Node 2
|
||||
0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0xF7, 0xFF, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, 0x00, 0x77, // Node 3
|
||||
0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0xEF, 0xFF, 0x00, 0x55, 0x00, 0x66, 0x00, 0x77, // Node 4
|
||||
0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0xDF, 0xFF, 0x00, 0x66, 0x00, 0x77, // Node 5
|
||||
0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0xBF, 0xFF, 0x00, 0x77, // Node 6
|
||||
0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, 0x7F, 0xFF // Node 7
|
||||
};
|
||||
|
||||
|
||||
/* 6---7
|
||||
* | |
|
||||
* 4---5
|
||||
* | |
|
||||
* 2---3
|
||||
* | |
|
||||
* 0---1
|
||||
*/
|
||||
static u8 const amdHtTopologyEightStraightLadder[] = {
|
||||
0x08,
|
||||
0x06, 0xFF, 0x00, 0x11, 0x02, 0x22, 0x00, 0x22, 0x02, 0x22, 0x00, 0x22, 0x02, 0x22, 0x00, 0x22, // Node0
|
||||
0x00, 0x00, 0x09, 0xFF, 0x00, 0x33, 0x01, 0x33, 0x00, 0x33, 0x01, 0x33, 0x00, 0x33, 0x01, 0x33, // Node1
|
||||
0x18, 0x00, 0x00, 0x00, 0x19, 0xFF, 0x00, 0x33, 0x09, 0x44, 0x00, 0x44, 0x09, 0x44, 0x00, 0x44, // Node2
|
||||
0x00, 0x11, 0x24, 0x11, 0x00, 0x22, 0x26, 0xFF, 0x00, 0x55, 0x06, 0x55, 0x00, 0x55, 0x06, 0x55, // Node3
|
||||
0x60, 0x22, 0x00, 0x22, 0x60, 0x22, 0x00, 0x22, 0x64, 0xFF, 0x00, 0x55, 0x24, 0x66, 0x00, 0x66, // Node4
|
||||
0x00, 0x33, 0x90, 0x33, 0x00, 0x33, 0x90, 0x33, 0x00, 0x44, 0x98, 0xFF, 0x00, 0x77, 0x18, 0x77, // Node5
|
||||
0x80, 0x44, 0x00, 0x44, 0x80, 0x44, 0x00, 0x44, 0x80, 0x44, 0x00, 0x44, 0x90, 0xFF, 0x00, 0x77, // Node6
|
||||
0x00, 0x55, 0x40, 0x55, 0x00, 0x55, 0x40, 0x55, 0x00, 0x55, 0x40, 0x55, 0x00, 0x66, 0x60, 0xFF // Node7
|
||||
};
|
||||
|
||||
|
||||
/* 6---7
|
||||
* | |
|
||||
* 4 5
|
||||
* |\ /|
|
||||
* |/ \|
|
||||
* 2 3
|
||||
* | |
|
||||
* 0---1
|
||||
*/
|
||||
static u8 const amdHtTopologyEightTwistedLadder[] = {
|
||||
0x08,
|
||||
0x06, 0xFF, 0x00, 0x11, 0x02, 0x22, 0x00, 0x12, 0x00, 0x22, 0x00, 0x22, 0x00, 0x22, 0x00, 0x22, // Node0
|
||||
0x00, 0x00, 0x09, 0xFF, 0x00, 0x03, 0x01, 0x33, 0x00, 0x33, 0x00, 0x33, 0x00, 0x33, 0x00, 0x33, // Node1
|
||||
0x30, 0x00, 0x00, 0x50, 0x31, 0xFF, 0x00, 0x54, 0x21, 0x44, 0x01, 0x55, 0x21, 0x44, 0x01, 0x55, // Node2
|
||||
0x00, 0x41, 0x30, 0x11, 0x00, 0x45, 0x32, 0xFF, 0x02, 0x44, 0x12, 0x55, 0x02, 0x44, 0x12, 0x55, // Node3
|
||||
0x48, 0x22, 0x40, 0x33, 0x48, 0x22, 0x40, 0x33, 0x4C, 0xFF, 0x00, 0x32, 0x0C, 0x66, 0x00, 0x36, // Node4
|
||||
0x80, 0x22, 0x84, 0x33, 0x80, 0x22, 0x84, 0x33, 0x00, 0x23, 0x8C, 0xFF, 0x00, 0x27, 0x0C, 0x77, // Node5
|
||||
0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x80, 0x44, 0x00, 0x74, 0x90, 0xFF, 0x00, 0x77, // Node6
|
||||
0x00, 0x55, 0x00, 0x55, 0x00, 0x55, 0x00, 0x55, 0x00, 0x65, 0x40, 0x55, 0x00, 0x66, 0x60, 0xFF // Node7
|
||||
};
|
||||
|
||||
static const u8 * const amd_topo_list[] = {
|
||||
amdHtTopologySingleNode,
|
||||
amdHtTopologyDualNode,
|
||||
amdHtTopologyThreeLine,
|
||||
amdHtTopologyTriangle,
|
||||
amdHtTopologyFourLine,
|
||||
amdHtTopologyFourStar,
|
||||
amdHtTopologyFourDegenerate,
|
||||
amdHtTopologyFourSquare,
|
||||
amdHtTopologyFourKite,
|
||||
amdHtTopologyFourFully,
|
||||
amdHtTopologyFiveFully,
|
||||
amdHtTopologySixFully,
|
||||
amdHtTopologySevenFully,
|
||||
amdHtTopologyEightFully,
|
||||
amdHtTopologyEightTwistedLadder,
|
||||
amdHtTopologyEightStraightLadder,
|
||||
NULL // NULL to mark end of list
|
||||
};
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* FUNCTIONS PROTOTYPE
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
void getAmdTopolist(u8 ***p);
|
||||
|
||||
|
||||
#endif /* HTTOPO_H */
|
||||
|
||||
2214
src/northbridge/amd/amdht/h3ncmn.c
Normal file
2214
src/northbridge/amd/amdht/h3ncmn.c
Normal file
File diff suppressed because it is too large
Load Diff
132
src/northbridge/amd/amdht/h3ncmn.h
Normal file
132
src/northbridge/amd/amdht/h3ncmn.h
Normal file
@ -0,0 +1,132 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef H3NCMN_H
|
||||
#define H3NCMN_H
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* DEFINITIONS AND MACROS
|
||||
*
|
||||
*-----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/* Use a macro to convert a node number to a PCI device. If some future port of
|
||||
* this code needs to, this can easily be replaced by a function call:
|
||||
* u8 makePCIDeviceFromNode(u8 node);
|
||||
*/
|
||||
#define makePCIDeviceFromNode(node) \
|
||||
((u8)(24 + node))
|
||||
|
||||
/* Use a macro to convert a node number to a PCI bus. If some future port of
|
||||
* this code needs to, this can easily be replaced by a function call:
|
||||
* u8 makePCIBusFromNode(u8 node);
|
||||
*/
|
||||
#define makePCIBusFromNode(node) \
|
||||
((u8)(0))
|
||||
|
||||
/* Use a macro to convert a node number to a PCI Segment. If some future port of
|
||||
* this code needs to, this can easily be replaced by a function call:
|
||||
* u8 makePCISegmentFromNode(u8 node);
|
||||
*/
|
||||
#define makePCISegmentFromNode(node) \
|
||||
((u8)(0))
|
||||
|
||||
/* Macros to fix support issues that come up with early sample processors, which
|
||||
* sometimes do things like report capabilities that are actually unsupported.
|
||||
* Use the build flag, HT_BUILD_EARLY_SAMPLE_CPU_SUPPORT, to enable this support.
|
||||
*
|
||||
* It's not envisioned this would be replaced by an external function, but the prototype is
|
||||
* u16 fixEarlySampleFreqCapability(u16 fc);
|
||||
*/
|
||||
#ifndef HT_BUILD_EARLY_SAMPLE_CPU_SUPPORT
|
||||
#define fixEarlySampleFreqCapability(fc) \
|
||||
((u16)fc)
|
||||
#else
|
||||
#define fixEarlySampleFreqCapability(fc) \
|
||||
((u16)fc & HT_FREQUENCY_LIMIT_HT1_ONLY)
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* TYPEDEFS, STRUCTURES, ENUMS
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
struct cNorthBridge
|
||||
{
|
||||
/* Public data, clients of northbridge can access */
|
||||
u8 maxLinks;
|
||||
u8 maxNodes;
|
||||
u8 maxPlatformLinks;
|
||||
|
||||
/* Public Interfaces for northbridge clients, coherent init*/
|
||||
void (*writeRoutingTable)(u8 node, u8 target, u8 link, cNorthBridge *nb);
|
||||
void (*writeNodeID)(u8 node, u8 nodeID, cNorthBridge *nb);
|
||||
u8 (*readDefLnk)(u8 node, cNorthBridge *nb);
|
||||
void (*enableRoutingTables)(u8 node, cNorthBridge *nb);
|
||||
BOOL (*verifyLinkIsCoherent)(u8 node, u8 link, cNorthBridge *nb);
|
||||
BOOL (*readTrueLinkFailStatus)(u8 node, u8 link, sMainData *pDat, cNorthBridge *nb);
|
||||
u8 (*readToken)(u8 node, cNorthBridge *nb);
|
||||
void (*writeToken)(u8 node, u8 value, cNorthBridge *nb);
|
||||
u8 (*getNumCoresOnNode)(u8 node, cNorthBridge *nb);
|
||||
void (*setTotalNodesAndCores)(u8 node, u8 totalNodes, u8 totalCores, cNorthBridge *nb);
|
||||
void (*limitNodes)(u8 node, cNorthBridge *nb);
|
||||
void (*writeFullRoutingTable)(u8 node, u8 target, u8 reqLink, u8 rspLink, u32 bClinks, cNorthBridge *nb);
|
||||
BOOL (*isCompatible)(u8 node, cNorthBridge *nb);
|
||||
BOOL (*isCapable)(u8 node, sMainData *pDat, cNorthBridge *nb);
|
||||
void (*stopLink)(u8 node, u8 link, cNorthBridge *nb);
|
||||
BOOL (*handleSpecialLinkCase)(u8 node, u8 link, sMainData *pDat, cNorthBridge *nb);
|
||||
|
||||
/* Public Interfaces for northbridge clients, noncoherent init */
|
||||
u8 (*readSbLink)(cNorthBridge *nb);
|
||||
BOOL (*verifyLinkIsNonCoherent)(u8 node, u8 link, cNorthBridge *nb);
|
||||
void (*setCFGAddrMap)(u8 cfgMapIndex, u8 secBus, u8 subBus, u8 targetNode, u8 targetLink, sMainData *pDat, cNorthBridge *nb);
|
||||
|
||||
/* Public Interfaces for northbridge clients, Optimization */
|
||||
u8 (*convertBitsToWidth)(u8 value, cNorthBridge *nb);
|
||||
u8 (*convertWidthToBits)(u8 value, cNorthBridge *nb);
|
||||
u16 (*northBridgeFreqMask)(u8 node, cNorthBridge *nb);
|
||||
void (*gatherLinkData)(sMainData *pDat, cNorthBridge *nb);
|
||||
void (*setLinkData)(sMainData *pDat, cNorthBridge *nb);
|
||||
|
||||
/* Public Interfaces for northbridge clients, System and performance Tuning. */
|
||||
void (*writeTrafficDistribution)(u32 links01, u32 links10, cNorthBridge *nb);
|
||||
void (*bufferOptimizations)(u8 node, sMainData *pDat, cNorthBridge *nb);
|
||||
|
||||
/* Private Data for northbridge implementation use only */
|
||||
u32 selfRouteRequestMask;
|
||||
u32 selfRouteResponseMask;
|
||||
u8 broadcastSelfBit;
|
||||
u32 compatibleKey;
|
||||
} ;
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* FUNCTIONS PROTOTYPE
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
void newNorthBridge(u8 node, cNorthBridge *nb);
|
||||
|
||||
#endif /* H3NCMN_H */
|
||||
160
src/northbridge/amd/amdht/ht_wrapper.c
Normal file
160
src/northbridge/amd/amdht/ht_wrapper.c
Normal file
@ -0,0 +1,160 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* TYPEDEFS, DEFINITIONS AND MACROS
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/* Single CPU system? */
|
||||
#if (CONFIG_MAX_PHYSICAL_CPUS == 1)
|
||||
#define HT_BUILD_NC_ONLY 1
|
||||
#endif
|
||||
|
||||
/* Debugging Options */
|
||||
#define AMD_DEBUG 1
|
||||
//#define AMD_DEBUG_ERROR_STOP 1
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* MODULES USED
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#undef FILECODE
|
||||
#define FILECODE 0xFF01
|
||||
#include "comlib.h"
|
||||
#include "h3gtopo.h"
|
||||
#include "h3finit.h"
|
||||
|
||||
/* include the main HT source file */
|
||||
#include "h3finit.c"
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* LOCAL FUNCTIONS
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/* FIXME: Find a better place for these pre-ram functions. */
|
||||
#define NODE_HT(x) NODE_PCI(x,0)
|
||||
#define NODE_MP(x) NODE_PCI(x,1)
|
||||
#define NODE_MC(x) NODE_PCI(x,3)
|
||||
#define NODE_LC(x) NODE_PCI(x,4)
|
||||
static u32 get_nodes(void)
|
||||
{
|
||||
device_t dev;
|
||||
u32 nodes;
|
||||
|
||||
dev = PCI_DEV(CBB, CDB, 0);
|
||||
nodes = ((pci_read_config32(dev, 0x60)>>4) & 7) ;
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 8
|
||||
nodes += (((pci_read_config32(dev, 0x160)>>4) & 7)<<3);
|
||||
#endif
|
||||
nodes++;
|
||||
|
||||
return nodes;
|
||||
}
|
||||
|
||||
static void enable_apic_ext_id(u32 node)
|
||||
{
|
||||
u32 val;
|
||||
val = pci_read_config32(NODE_HT(node), 0x68);
|
||||
val |= (HTTC_APIC_EXT_SPUR | HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST);
|
||||
pci_write_config32(NODE_HT(node), 0x68, val);
|
||||
}
|
||||
|
||||
|
||||
static void setup_link_trans_cntrl()
|
||||
{
|
||||
/* FIXME: Not sure that this belongs here but it is HT related */
|
||||
u32 val;
|
||||
val = pci_read_config32(NODE_HT(0), 0x68);
|
||||
val |= 0x00206800; // DSNpReqLimit, LimitCldtCfg, BufRefPri, RespPassPW per BKDG;
|
||||
pci_write_config32(NODE_HT(0), 0x68, val);
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* void AMD_CB_EventNotify (u8 evtClass, u16 event, const u8 *pEventData0)
|
||||
*
|
||||
* Needs to be fixed to output the debug structures.
|
||||
*
|
||||
*/
|
||||
void AMD_CB_EventNotify (u8 evtClass, u16 event, const u8 *pEventData0)
|
||||
{
|
||||
printk_debug("AMD_CB_EventNotify()\n");
|
||||
printk_debug("event class: %02x event: %04x\n", evtClass, event);
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* void getAmdTopolist(u8 ***p)
|
||||
*
|
||||
* point to the stock topo list array
|
||||
*
|
||||
*/
|
||||
void getAmdTopolist(u8 ***p)
|
||||
{
|
||||
*p = (u8 **)amd_topo_list;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* void amd_ht_init(struct sys_info *sysinfo)
|
||||
*
|
||||
* AMD HT init LinuxBIOS wrapper
|
||||
*
|
||||
*/
|
||||
void amd_ht_init(struct sys_info *sysinfo)
|
||||
{
|
||||
AMD_HTBLOCK ht_wrapper = {
|
||||
NULL, // u8 **topolist;
|
||||
0, // u8 AutoBusStart;
|
||||
32, // u8 AutoBusMax;
|
||||
6, // u8 AutoBusIncrement;
|
||||
NULL, // BOOL (*AMD_CB_IgnoreLink)();
|
||||
NULL, // BOOL (*AMD_CB_OverrideBusNumbers)();
|
||||
NULL, // BOOL (*AMD_CB_ManualBUIDSwapList)();
|
||||
NULL, // void (*AMD_CB_DeviceCapOverride)();
|
||||
NULL, // void (*AMD_CB_Cpu2CpuPCBLimits)();
|
||||
NULL, // void (*AMD_CB_IOPCBLimits)();
|
||||
NULL, // BOOL (*AMD_CB_SkipRegang)();
|
||||
NULL, // BOOL (*AMD_CB_CustomizeTrafficDistribution)();
|
||||
NULL, // BOOL (*AMD_CB_CustomizeBuffers)();
|
||||
NULL, // void (*AMD_CB_OverrideDevicePort)();
|
||||
NULL, // void (*AMD_CB_OverrideCpuPort)();
|
||||
AMD_CB_EventNotify // void (*AMD_CB_EventNotify) ();
|
||||
};
|
||||
|
||||
printk_debug("Enter amd_ht_init()\n");
|
||||
amdHtInitialize(&ht_wrapper);
|
||||
printk_debug("Exit amd_ht_init()\n");
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
88
src/northbridge/amd/amdht/porting.h
Normal file
88
src/northbridge/amd/amdht/porting.h
Normal file
@ -0,0 +1,88 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef PORTING_H
|
||||
#define PORTING_H
|
||||
|
||||
|
||||
/* For AMD64 or 32-bit GCC */
|
||||
typedef int int32;
|
||||
typedef unsigned int uint32;
|
||||
typedef short int16;
|
||||
typedef unsigned short uint16;
|
||||
typedef char int8;
|
||||
typedef unsigned char uint8;
|
||||
|
||||
/* Create the Boolean type */
|
||||
#define TRUE 1
|
||||
#define FALSE 0
|
||||
typedef unsigned char BOOL;
|
||||
|
||||
/* Force tight packing of structures */
|
||||
#pragma pack(1)
|
||||
|
||||
#define CALLCONV
|
||||
|
||||
|
||||
typedef struct _uint64
|
||||
{
|
||||
uint32 lo;
|
||||
uint32 hi;
|
||||
}uint64;
|
||||
|
||||
|
||||
/*
|
||||
* SBDFO - Segment Bus Device Function Offset
|
||||
* 31:28 Segment (4-bits)
|
||||
* 27:20 Bus (8-bits)
|
||||
* 19:15 Device (5-bits)
|
||||
* 14:12 Function(3-bits)
|
||||
* 11:00 Offset (12-bits)
|
||||
*/
|
||||
typedef uint32 SBDFO;
|
||||
|
||||
#define MAKE_SBDFO(seg,bus,dev,fun,off) ((((uint32)(seg))<<28) | (((uint32)(bus))<<20) | \
|
||||
(((uint32)(dev))<<15) | (((uint32)(fun))<<12) | ((uint32)(off)))
|
||||
#define SBDFO_SEG(x) (((uint32)(x)>>28) & 0x0F)
|
||||
#define SBDFO_BUS(x) (((uint32)(x)>>20) & 0xFF)
|
||||
#define SBDFO_DEV(x) (((uint32)(x)>>15) & 0x1F)
|
||||
#define SBDFO_FUN(x) (((uint32)(x)>>12) & 0x07)
|
||||
#define SBDFO_OFF(x) (((uint32)(x)) & 0xFFF)
|
||||
#define ILLEGAL_SBDFO 0xFFFFFFFF
|
||||
|
||||
void CALLCONV AmdMSRRead(uint32 Address, uint64 *Value);
|
||||
void CALLCONV AmdMSRWrite(uint32 Address, uint64 *Value);
|
||||
void CALLCONV AmdIORead(uint8 IOSize, uint16 Address, uint32 *Value);
|
||||
void CALLCONV AmdIOWrite(uint8 IOSize, uint16 Address, uint32 *Value);
|
||||
void CALLCONV AmdMemRead(uint8 MemSize, uint64 *Address, uint32 *Value);
|
||||
void CALLCONV AmdMemWrite(uint8 MemSize, uint64 *Address, uint32 *Value);
|
||||
void CALLCONV AmdPCIRead(SBDFO loc, uint32 *Value);
|
||||
void CALLCONV AmdPCIWrite(SBDFO loc, uint32 *Value);
|
||||
void CALLCONV AmdCPUIDRead(uint32 Address, uint32 Regs[4]);
|
||||
void CALLCONV ErrorStop(uint32 Value);
|
||||
|
||||
#ifndef NULL
|
||||
#define NULL ((void *) 0)
|
||||
#endif
|
||||
|
||||
#define BYTESIZE 1
|
||||
#define WORDSIZE 2
|
||||
#define DWORDSIZE 4
|
||||
|
||||
#endif /* PORTING_H */
|
||||
69
src/northbridge/amd/amdmct/amddefs.h
Normal file
69
src/northbridge/amd/amdmct/amddefs.h
Normal file
@ -0,0 +1,69 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/* Public Revisions - USE THESE VERSIONS TO MAKE COMPARE WITH CPULOGICALID RETURN VALUE*/
|
||||
#define AMD_SAFEMODE 0x80000000 /* Unknown future revision - SAFE MODE */
|
||||
#define AMD_NPT_F0 0x00000001 /* F0 stepping */
|
||||
#define AMD_NPT_F1 0x00000002 /* F1 stepping */
|
||||
#define AMD_NPT_F2C 0x00000004
|
||||
#define AMD_NPT_F2D 0x00000008
|
||||
#define AMD_NPT_F2E 0x00000010 /* F2 stepping E */
|
||||
#define AMD_NPT_F2G 0x00000020 /* F2 stepping G */
|
||||
#define AMD_NPT_F2J 0x00000040
|
||||
#define AMD_NPT_F2K 0x00000080
|
||||
#define AMD_NPT_F3L 0x00000100 /* F3 Stepping */
|
||||
#define AMD_NPT_G0A 0x00000200 /* G0 stepping */
|
||||
#define AMD_NPT_G1B 0x00000400 /* G1 stepping */
|
||||
#define AMD_DR_A0A 0x00010000 /* Barcelona A0 */
|
||||
#define AMD_DR_A1B 0x00020000 /* Barcelona A1 */
|
||||
#define AMD_DR_A2 0x00040000 /* Barcelona A2 */
|
||||
#define AMD_DR_B0 0x00080000 /* Barcelona B0 */
|
||||
#define AMD_DR_B1 0x00100000 /* Barcelona B1 */
|
||||
#define AMD_DR_B2 0x00200000 /* Barcelona B2 */
|
||||
#define AMD_DR_BA 0x00400000 /* Barcelona BA */
|
||||
|
||||
/*
|
||||
Groups - Create as many as you wish, from the above public values
|
||||
*/
|
||||
#define AMD_NPT_F2 (AMD_NPT_F2C + AMD_NPT_F2D + AMD_NPT_F2E + AMD_NPT_F2G + AMD_NPT_F2J + AMD_NPT_F2K)
|
||||
#define AMD_NPT_F3 (AMD_NPT_F3L)
|
||||
#define AMD_NPT_Fx (AMD_NPT_F0 + AMD_NPT_F1 + AMD_NPT_F2 + AMD_NPT_F3)
|
||||
#define AMD_NPT_Gx (AMD_NPT_G0A + AMD_NPT_G1B)
|
||||
#define AMD_NPT_ALL (AMD_NPT_Fx + AMD_NPT_Gx)
|
||||
#define AMD_DR_Ax (AMD_DR_A0A + AMD_DR_A1B + AMD_DR_A2)
|
||||
#define AMD_FINEDELAY (AMD_NPT_F0 + AMD_NPT_F1 + AMD_NPT_F2)
|
||||
#define AMD_GT_F0 (AMD_NPT_ALL AND NOT AMD_NPT_F0)
|
||||
|
||||
|
||||
#define CPUID_EXT_PM 0x80000007
|
||||
|
||||
#define CPUID_MODEL 1
|
||||
|
||||
|
||||
#define HWCR 0xC0010015
|
||||
|
||||
|
||||
#define FidVidStatus 0xC0010042
|
||||
|
||||
|
||||
#define FS_Base 0xC0000100
|
||||
|
||||
|
||||
#define BU_CFG 0xC0011023
|
||||
#define BU_CFG2 0xC001102A
|
||||
552
src/northbridge/amd/amdmct/mct/mct.h
Normal file
552
src/northbridge/amd/amdmct/mct/mct.h
Normal file
@ -0,0 +1,552 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef MCT_H
|
||||
#define MCT_H
|
||||
/*===========================================================================
|
||||
CPU - K8/FAM10
|
||||
===========================================================================*/
|
||||
#define PT_L1 0 /* CPU Package Type*/
|
||||
#define PT_M2 1
|
||||
#define PT_S1 2
|
||||
|
||||
#define J_MIN 0 /* j loop constraint. 1=CL 2.0 T*/
|
||||
#define J_MAX 4 /* j loop constraint. 4=CL 6.0 T*/
|
||||
#define K_MIN 1 /* k loop constraint. 1=200 Mhz*/
|
||||
#define K_MAX 4 /* k loop constraint. 9=400 Mhz*/
|
||||
#define CL_DEF 2 /* Default value for failsafe operation. 2=CL 4.0 T*/
|
||||
#define T_DEF 1 /* Default value for failsafe operation. 1=5ns (cycle time)*/
|
||||
|
||||
#define BSCRate 1 /* reg bit field=rate of dram scrubber for ecc*/
|
||||
/* memory initialization (ecc and check-bits).*/
|
||||
/* 1=40 ns/64 bytes.*/
|
||||
#define FirstPass 1 /* First pass through RcvEn training*/
|
||||
#define SecondPass 2 /* Second pass through Rcven training*/
|
||||
|
||||
#define RCVREN_MARGIN 6 /* number of DLL taps to delay beyond first passing position*/
|
||||
#define MAXASYNCLATCTL_3 60 /* Max Async Latency Control value (This value will be divided by 20)*/
|
||||
#define DQS_FAIL 1
|
||||
#define DQS_PASS 0
|
||||
#define DQS_WRITEDIR 0
|
||||
#define DQS_READDIR 1
|
||||
#define MIN_DQS_WNDW 3
|
||||
#define secPassOffset 6
|
||||
|
||||
#define PA_HOST (((24 << 3)+0) << 8) /* Node 0 Host Bus function PCI Address bits [15:0] */
|
||||
#define PA_MAP (((24 << 3)+1) << 8) /* Node 0 MAP function PCI Address bits [15:0] */
|
||||
#define PA_DCT (((24 << 3)+2) << 8) /* Node 0 DCT function PCI Address bits [15:0] */
|
||||
#define PA_DCTADDL (((00 << 3)+2) << 8) /* Node x DCT function, Additional Registers PCI Address bits [15:0] */
|
||||
#define PA_NBMISC (((24 << 3)+3) << 8) /* Node 0 Misc PCI Address bits [15:0] */
|
||||
#define PA_NBDEVOP (((00 << 3)+3) << 8) /* Node 0 Misc PCI Address bits [15:0] */
|
||||
|
||||
#define DCC_EN 1 /* X:2:0x94[19]*/
|
||||
#define ILD_Lmt 3 /* X:2:0x94[18:16]*/
|
||||
|
||||
#define EncodedTSPD 0x00191709 /* encodes which SPD byte to get T from*/
|
||||
/* versus CL X, CL X-.5, and CL X-1*/
|
||||
|
||||
#define Bias_TrpT 3 /* bias to convert bus clocks to bit field value*/
|
||||
#define Bias_TrrdT 2
|
||||
#define Bias_TrcdT 3
|
||||
#define Bias_TrasT 3
|
||||
#define Bias_TrcT 11
|
||||
#define Bias_TrtpT 4
|
||||
#define Bias_TwrT 3
|
||||
#define Bias_TwtrT 0
|
||||
|
||||
#define Min_TrpT 3 /* min programmable value in busclocks*/
|
||||
#define Max_TrpT 6 /* max programmable value in busclocks*/
|
||||
#define Min_TrrdT 2
|
||||
#define Max_TrrdT 5
|
||||
#define Min_TrcdT 3
|
||||
#define Max_TrcdT 6
|
||||
#define Min_TrasT 5
|
||||
#define Max_TrasT 18
|
||||
#define Min_TrcT 11
|
||||
#define Max_TrcT 26
|
||||
#define Min_TrtpT 4
|
||||
#define Max_TrtpT 5
|
||||
#define Min_TwrT 3
|
||||
#define Max_TwrT 6
|
||||
#define Min_TwtrT 1
|
||||
#define Max_TwtrT 3
|
||||
|
||||
/* common register bit names */
|
||||
#define DramHoleValid 0 /* func 1, offset F0h, bit 0 */
|
||||
#define CSEnable 0 /* func 2, offset 40h-5C, bit 0 */
|
||||
#define Spare 1 /* func 2, offset 40h-5C, bit 1 */
|
||||
#define TestFail 2 /* func 2, offset 40h-5C, bit 2 */
|
||||
#define DqsRcvEnTrain 18 /* func 2, offset 78h, bit 18 */
|
||||
#define EnDramInit 31 /* func 2, offset 7Ch, bit 31 */
|
||||
#define DisAutoRefresh 18 /* func 2, offset 8Ch, bit 18 */
|
||||
#define InitDram 0 /* func 2, offset 90h, bit 0 */
|
||||
#define BurstLength32 10 /* func 2, offset 90h, bit 10 */
|
||||
#define Width128 11 /* func 2, offset 90h, bit 11 */
|
||||
#define X4Dimm 12 /* func 2, offset 90h, bit 12 */
|
||||
#define UnBuffDimm 16 /* func 2, offset 90h, bit 16 */
|
||||
#define DimmEcEn 19 /* func 2, offset 90h, bit 19 */
|
||||
#define MemClkFreqVal 3 /* func 2, offset 94h, bit 3 */
|
||||
#define RDqsEn 12 /* func 2, offset 94h, bit 12 */
|
||||
#define DisDramInterface 14 /* func 2, offset 94h, bit 14 */
|
||||
#define DctAccessWrite 30 /* func 2, offset 98h, bit 30 */
|
||||
#define DctAccessDone 31 /* func 2, offset 98h, bit 31 */
|
||||
#define PwrSavingsEn 10 /* func 2, offset A0h, bit 10 */
|
||||
#define Mod64BitMux 4 /* func 2, offset A0h, bit 4 */
|
||||
#define DisableJitter 1 /* func 2, offset A0h, bit 1 */
|
||||
#define DramEnabled 9 /* func 2, offset A0h, bit 9 */
|
||||
#define SyncOnUcEccEn 2 /* fun 3, offset 44h, bit 2 */
|
||||
|
||||
/*=============================================================================
|
||||
Jedec DDR II
|
||||
=============================================================================*/
|
||||
#define SPD_TYPE 2 /* SPD byte read location*/
|
||||
#define JED_DDRSDRAM 0x07 /* Jedec defined bit field*/
|
||||
#define JED_DDR2SDRAM 0x08 /* Jedec defined bit field*/
|
||||
|
||||
#define SPD_DIMMTYPE 20
|
||||
#define SPD_ATTRIB 21
|
||||
#define JED_DIFCKMSK 0x20 /* Differential Clock Input*/
|
||||
#define JED_REGADCMSK 0x11 /* Registered Address/Control*/
|
||||
#define JED_PROBEMSK 0x40 /* Analysis Probe installed*/
|
||||
#define SPD_DEVATTRIB 22
|
||||
#define SPD_EDCTYPE 11
|
||||
#define JED_ECC 0x02
|
||||
#define JED_ADRCPAR 0x04
|
||||
#define SPD_ROWSZ 3
|
||||
#define SPD_COLSZ 4
|
||||
#define SPD_LBANKS 17 /* number of [logical] banks on each device*/
|
||||
#define SPD_DMBANKS 5 /* number of physical banks on dimm*/
|
||||
#define SPDPLBit 4 /* Dram package bit*/
|
||||
#define SPD_BANKSZ 31 /* capacity of physical bank*/
|
||||
#define SPD_DEVWIDTH 13
|
||||
#define SPD_CASLAT 18
|
||||
#define SPD_TRP 27
|
||||
#define SPD_TRRD 28
|
||||
#define SPD_TRCD 29
|
||||
#define SPD_TRAS 30
|
||||
#define SPD_TWR 36
|
||||
#define SPD_TWTR 37
|
||||
#define SPD_TRTP 38
|
||||
#define SPD_TRCRFC 40
|
||||
#define SPD_TRC 41
|
||||
#define SPD_TRFC 42
|
||||
|
||||
#define SPD_MANDATEYR 93 /* Module Manufacturing Year (BCD) */
|
||||
|
||||
#define SPD_MANDATEWK 94 /* Module Manufacturing Week (BCD) */
|
||||
|
||||
/*--------------------------------------
|
||||
Jedec DDR II related equates
|
||||
--------------------------------------*/
|
||||
#define MYEAR06 6 /* Manufacturing Year BCD encoding of 2006 - 06d*/
|
||||
#define MWEEK24 0x24 /* Manufacturing Week BCD encoding of June - 24d*/
|
||||
|
||||
/*=============================================================================
|
||||
Macros
|
||||
=============================================================================*/
|
||||
|
||||
#define _2GB_RJ8 (2<<(30-8))
|
||||
#define _4GB_RJ8 (4<<(30-8))
|
||||
#define _4GB_RJ4 (4<<(30-4))
|
||||
|
||||
#define BigPagex8_RJ8 (1<<(17+3-8)) /* 128KB * 8 >> 8 */
|
||||
|
||||
/*=============================================================================
|
||||
Global MCT Status Structure
|
||||
=============================================================================*/
|
||||
struct MCTStatStruc {
|
||||
u32 GStatus; /* Global Status bitfield*/
|
||||
u32 HoleBase; /* If not zero, BASE[39:8] (system address)
|
||||
of sub 4GB dram hole for HW remapping.*/
|
||||
u32 Sub4GCacheTop; /* If not zero, the 32-bit top of cacheable memory.*/
|
||||
u32 SysLimit; /* LIMIT[39:8] (system address)*/
|
||||
};
|
||||
/*=============================================================================
|
||||
Global MCT Configuration Status Word (GStatus)
|
||||
=============================================================================*/
|
||||
/*These should begin at bit 0 of GStatus[31:0]*/
|
||||
#define GSB_MTRRshort 0 /* Ran out of MTRRs while mapping memory*/
|
||||
#define GSB_ECCDIMMs 1 /* All banks of all Nodes are ECC capable*/
|
||||
#define GSB_DramECCDis 2 /* Dram ECC requested but not enabled.*/
|
||||
#define GSB_SoftHole 3 /* A Node Base gap was created*/
|
||||
#define GSB_HWHole 4 /* A HW dram remap was created*/
|
||||
#define GSB_NodeIntlv 5 /* Node Memory interleaving was enabled*/
|
||||
#define GSB_SpIntRemapHole 16 /* Special condition for Node Interleave and HW remapping*/
|
||||
|
||||
|
||||
/*===============================================================================
|
||||
Local DCT Status structure (a structure for each DCT)
|
||||
===============================================================================*/
|
||||
|
||||
struct DCTStatStruc { /* A per Node structure*/
|
||||
u8 Node_ID; /* Node ID of current controller*/
|
||||
u8 ErrCode; /* Current error condition of Node
|
||||
0= no error
|
||||
1= Variance Error, DCT is running but not in an optimal configuration.
|
||||
2= Stop Error, DCT is NOT running
|
||||
3= Fatal Error, DCT/MCT initialization has been halted.*/
|
||||
u32 ErrStatus; /* Error Status bit Field */
|
||||
u32 Status; /* Status bit Field*/
|
||||
u8 DIMMAddr[8]; /* SPD address of DIMM controlled by MA0_CS_L[0,1]*/
|
||||
/* SPD address of..MB0_CS_L[0,1]*/
|
||||
/* SPD address of..MA1_CS_L[0,1]*/
|
||||
/* SPD address of..MB1_CS_L[0,1]*/
|
||||
/* SPD address of..MA2_CS_L[0,1]*/
|
||||
/* SPD address of..MB2_CS_L[0,1]*/
|
||||
/* SPD address of..MA3_CS_L[0,1]*/
|
||||
/* SPD address of..MB3_CS_L[0,1]*/
|
||||
u16 DIMMPresent; /* For each bit n 0..7, 1=DIMM n is present.
|
||||
DIMM# Select Signal
|
||||
0 MA0_CS_L[0,1]
|
||||
1 MB0_CS_L[0,1]
|
||||
2 MA1_CS_L[0,1]
|
||||
3 MB1_CS_L[0,1]
|
||||
4 MA2_CS_L[0,1]
|
||||
5 MB2_CS_L[0,1]
|
||||
6 MA3_CS_L[0,1]
|
||||
7 MB3_CS_L[0,1]*/
|
||||
u16 DIMMValid; /* For each bit n 0..7, 1=DIMM n is valid and is/will be configured*/
|
||||
u16 DIMMSPDCSE; /* For each bit n 0..7, 1=DIMM n SPD checksum error*/
|
||||
u16 DimmECCPresent; /* For each bit n 0..7, 1=DIMM n is ECC capable.*/
|
||||
u16 DimmPARPresent; /* For each bit n 0..7, 1=DIMM n is ADR/CMD Parity capable.*/
|
||||
u16 Dimmx4Present; /* For each bit n 0..7, 1=DIMM n contains x4 data devices.*/
|
||||
u16 Dimmx8Present; /* For each bit n 0..7, 1=DIMM n contains x8 data devices.*/
|
||||
u16 Dimmx16Present; /* For each bit n 0..7, 1=DIMM n contains x16 data devices.*/
|
||||
u16 DIMM1Kpage; /* For each bit n 0..7, 1=DIMM n contains 1K page devices.*/
|
||||
u8 MAload[2]; /* Number of devices loading MAA bus*/
|
||||
/* Number of devices loading MAB bus*/
|
||||
u8 MAdimms[2]; /* Number of DIMMs loading CH A*/
|
||||
/* Number of DIMMs loading CH B*/
|
||||
u8 DATAload[2]; /* Number of ranks loading CH A DATA*/
|
||||
/* Number of ranks loading CH B DATA*/
|
||||
u8 DIMMAutoSpeed; /* Max valid Mfg. Speed of DIMMs
|
||||
1=200Mhz
|
||||
2=266Mhz
|
||||
3=333Mhz
|
||||
4=400Mhz */
|
||||
u8 DIMMCASL; /* Min valid Mfg. CL bitfield
|
||||
0=2.0
|
||||
1=3.0
|
||||
2=4.0
|
||||
3=5.0
|
||||
4=6.0 */
|
||||
u16 DIMMTrcd; /* Minimax Trcd*40 (ns) of DIMMs*/
|
||||
u16 DIMMTrp; /* Minimax Trp*40 (ns) of DIMMs*/
|
||||
u16 DIMMTrtp; /* Minimax Trtp*40 (ns) of DIMMs*/
|
||||
u16 DIMMTras; /* Minimax Tras*40 (ns) of DIMMs*/
|
||||
u16 DIMMTrc; /* Minimax Trc*40 (ns) of DIMMs*/
|
||||
u16 DIMMTwr; /* Minimax Twr*40 (ns) of DIMMs*/
|
||||
u16 DIMMTrrd; /* Minimax Trrd*40 (ns) of DIMMs*/
|
||||
u16 DIMMTwtr; /* Minimax Twtr*40 (ns) of DIMMs*/
|
||||
u8 Speed; /* Bus Speed (to set Controller)
|
||||
1=200Mhz
|
||||
2=266Mhz
|
||||
3=333Mhz
|
||||
4=400Mhz */
|
||||
u8 CASL; /* CAS latency DCT setting
|
||||
0=2.0
|
||||
1=3.0
|
||||
2=4.0
|
||||
3=5.0
|
||||
4=6.0 */
|
||||
u8 Trcd; /* DCT Trcd (busclocks) */
|
||||
u8 Trp; /* DCT Trp (busclocks) */
|
||||
u8 Trtp; /* DCT Trtp (busclocks) */
|
||||
u8 Tras; /* DCT Tras (busclocks) */
|
||||
u8 Trc; /* DCT Trc (busclocks) */
|
||||
u8 Twr; /* DCT Twr (busclocks) */
|
||||
u8 Trrd; /* DCT Trrd (busclocks) */
|
||||
u8 Twtr; /* DCT Twtr (busclocks) */
|
||||
u8 Trfc[4]; /* DCT Logical DIMM0 Trfc
|
||||
0=75ns (for 256Mb devs)
|
||||
1=105ns (for 512Mb devs)
|
||||
2=127.5ns (for 1Gb devs)
|
||||
3=195ns (for 2Gb devs)
|
||||
4=327.5ns (for 4Gb devs) */
|
||||
/* DCT Logical DIMM1 Trfc (see Trfc0 for format) */
|
||||
/* DCT Logical DIMM2 Trfc (see Trfc0 for format) */
|
||||
/* DCT Logical DIMM3 Trfc (see Trfc0 for format) */
|
||||
u16 CSPresent; /* For each bit n 0..7, 1=Chip-select n is present */
|
||||
u16 CSTestFail; /* For each bit n 0..7, 1=Chip-select n is present but disabled */
|
||||
u32 DCTSysBase; /* BASE[39:8] (system address) of this Node's DCTs. */
|
||||
u32 DCTHoleBase; /* If not zero, BASE[39:8] (system address) of dram hole for HW remapping. Dram hole exists on this Node's DCTs. */
|
||||
u32 DCTSysLimit; /* LIMIT[39:8] (system address) of this Node's DCTs */
|
||||
u16 PresetmaxFreq; /* Maximum OEM defined DDR frequency
|
||||
200=200Mhz (DDR400)
|
||||
266=266Mhz (DDR533)
|
||||
333=333Mhz (DDR667)
|
||||
400=400Mhz (DDR800) */
|
||||
u8 _2Tmode; /* 1T or 2T CMD mode (slow access mode)
|
||||
1=1T
|
||||
2=2T */
|
||||
u8 TrwtTO; /* DCT TrwtTO (busclocks)*/
|
||||
u8 Twrrd; /* DCT Twrrd (busclocks)*/
|
||||
u8 Twrwr; /* DCT Twrwr (busclocks)*/
|
||||
u8 Trdrd; /* DCT Trdrd (busclocks)*/
|
||||
u32 CH_ODC_CTL[2]; /* Output Driver Strength (see BKDG FN2:Offset 9Ch, index 00h*/
|
||||
u32 CH_ADDR_TMG[2]; /* Address Bus Timing (see BKDG FN2:Offset 9Ch, index 04h*/
|
||||
/* Output Driver Strength (see BKDG FN2:Offset 9Ch, index 20h*/
|
||||
/* Address Bus Timing (see BKDG FN2:Offset 9Ch, index 24h*/
|
||||
u16 CH_EccDQSLike[2]; /* CHA DQS ECC byte like...*/
|
||||
u8 CH_EccDQSScale[2]; /* CHA DQS ECC byte scale*/
|
||||
// u8 reserved_b_1; /* Reserved*/
|
||||
/* CHB DQS ECC byte like...*/
|
||||
/* CHB DQS ECC byte scale*/
|
||||
// u8 reserved_b_2; /*Reserved*/
|
||||
u8 MaxAsyncLat; /* Max Asynchronous Latency (ns)*/
|
||||
u8 CH_B_DQS[2][2][9]; /* CHA Byte 0 - 7 and Check Write DQS Delay*/
|
||||
/* Reserved*/
|
||||
/* CHA Byte 0 - 7 and Check Read DQS Delay*/
|
||||
/* Reserved*/
|
||||
/* CHB Byte 0 - 7 and Check Write DQS Delay*/
|
||||
/* Reserved*/
|
||||
/* CHB Byte 0 - 7 and Check Read DQS Delay*/
|
||||
/* Reserved*/
|
||||
u8 CH_D_RCVRDLY[2][4]; /* CHA DIMM 0 - 3 Receiver Enable Delay*/
|
||||
/* CHB DIMM 0 - 3 Receiver Enable Delay*/
|
||||
u32 PtrPatternBufA; /* Ptr on stack to aligned DQS testing pattern*/
|
||||
u32 PtrPatternBufB; /*Ptr on stack to aligned DQS testing pattern*/
|
||||
u8 Channel; /* Current Channel (0= CH A, 1=CH B)*/
|
||||
u8 ByteLane; /* Current Byte Lane (0..7)*/
|
||||
u8 Direction; /* Current DQS-DQ training write direction (0=read, 1=write)*/
|
||||
u8 Pattern; /* Current pattern*/
|
||||
u8 DQSDelay; /* Current DQS delay value*/
|
||||
u32 TrainErrors; /* Current Training Errors*/
|
||||
// u8 reserved_b_3; /* RSVD */
|
||||
u32 AMC_TSC_DeltaLo; /* Time Stamp Counter measurement of AMC, Low dword*/
|
||||
u32 AMC_TSC_DeltaHi; /* Time Stamp Counter measurement of AMC, High dword*/
|
||||
u8 CH_B_Dly[2][2][2][8]; /* CH A byte lane 0 - 7 minimum filtered window passing DQS delay value*/
|
||||
/* CH A byte lane 0 - 7 maximum filtered window passing DQS delay value*/
|
||||
/* CH B byte lane 0 - 7 minimum filtered window passing DQS delay value*/
|
||||
/* CH B byte lane 0 - 7 maximum filtered window passing DQS delay value*/
|
||||
/* CH A byte lane 0 - 7 minimum filtered window passing DQS delay value*/
|
||||
/* CH A byte lane 0 - 7 maximum filtered window passing DQS delay value*/
|
||||
/* CH B byte lane 0 - 7 minimum filtered window passing DQS delay value*/
|
||||
/* CH B byte lane 0 - 7 maximum filtered window passing DQS delay value*/
|
||||
u32 LogicalCPUID; /* The logical CPUID of the node*/
|
||||
u16 HostBiosSrvc1; /* Word sized general purpose field for use by host BIOS. Scratch space.*/
|
||||
u32 HostBiosSrvc2; /* Dword sized general purpose field for use by host BIOS. Scratch space.*/
|
||||
u16 DimmQRPresent; /* QuadRank DIMM present?*/
|
||||
u16 DimmTrainFail; /* Bitmap showing which dimms failed training*/
|
||||
u16 CSTrainFail; /* Bitmap showing which chipselects failed training*/
|
||||
u16 DimmYr06; /* Bitmap indicating which Dimms have a manufactur's year code <= 2006*/
|
||||
u16 DimmWk2406; /* Bitmap indicating which Dimms have a manufactur's week code <= 24 of 2006 (June)*/
|
||||
u16 DimmDRPresent; /* Bitmap indicating that Dual Rank Dimms are present*/
|
||||
u16 DimmPlPresent; /* Bitmap indicating that Planar (1) or Stacked (0) Dimms are present.*/
|
||||
u16 ChannelTrainFail; /* Bitmap showing the chanel informaiton about failed Chip Selects*/
|
||||
/* 0 in any bit field indicates Channel 0*/
|
||||
/* 1 in any bit field indicates Channel 1*/
|
||||
};
|
||||
|
||||
/*===============================================================================
|
||||
Local Error Status Codes (DCTStatStruc.ErrCode)
|
||||
===============================================================================*/
|
||||
#define SC_RunningOK 0
|
||||
#define SC_VarianceErr 1 /* Running non-optimally*/
|
||||
#define SC_StopError 2 /* Not Running*/
|
||||
#define SC_FatalErr 3 /* Fatal Error, MCTB has exited immediately*/
|
||||
|
||||
/*===============================================================================
|
||||
Local Error Status (DCTStatStruc.ErrStatus[31:0])
|
||||
===============================================================================*/
|
||||
#define SB_NoDimms 0
|
||||
#define SB_DIMMChkSum 1
|
||||
#define SB_DimmMismatchM 2 /* dimm module type(buffer) mismatch*/
|
||||
#define SB_DimmMismatchT 3 /* dimm CL/T mismatch*/
|
||||
#define SB_DimmMismatchO 4 /* dimm organization mismatch (128-bit)*/
|
||||
#define SB_NoTrcTrfc 5 /* SPD missing Trc or Trfc info*/
|
||||
#define SB_NoCycTime 6 /* SPD missing byte 23 or 25*/
|
||||
#define SB_BkIntDis 7 /* Bank interleave requested but not enabled*/
|
||||
#define SB_DramECCDis 8 /* Dram ECC requested but not enabled*/
|
||||
#define SB_SpareDis 9 /* Online spare requested but not enabled*/
|
||||
#define SB_MinimumMode 10 /* Running in Minimum Mode*/
|
||||
#define SB_NORCVREN 11 /* No DQS Receiver Enable pass window found*/
|
||||
#define SB_CHA2BRCVREN 12 /* DQS Rcvr En pass window CHA to CH B too large*/
|
||||
#define SB_SmallRCVR 13 /* DQS Rcvr En pass window too small (far right of dynamic range)*/
|
||||
#define SB_NODQSPOS 14 /* No DQS-DQ passing positions*/
|
||||
#define SB_SMALLDQS 15 /* DQS-DQ passing window too small*/
|
||||
|
||||
/*===============================================================================
|
||||
Local Configuration Status (DCTStatStruc.Status[31:0])
|
||||
===============================================================================*/
|
||||
#define SB_Registered 0 /* All DIMMs are Registered*/
|
||||
#define SB_ECCDIMMs 1 /* All banks ECC capable*/
|
||||
#define SB_PARDIMMs 2 /* All banks Addr/CMD Parity capable*/
|
||||
#define SB_DiagClks 3 /* Jedec ALL slots clock enable diag mode*/
|
||||
#define SB_128bitmode 4 /* DCT in 128-bit mode operation*/
|
||||
#define SB_64MuxedMode 5 /* DCT in 64-bit mux'ed mode.*/
|
||||
#define SB_2TMode 6 /* 2T CMD timing mode is enabled.*/
|
||||
#define SB_SWNodeHole 7 /* Remapping of Node Base on this Node to create a gap.*/
|
||||
#define SB_HWHole 8 /* Memory Hole created on this Node using HW remapping.*/
|
||||
|
||||
|
||||
|
||||
/*===============================================================================
|
||||
NVRAM/run-time-configurable Items
|
||||
===============================================================================*/
|
||||
/* Platform Configuration */
|
||||
#define NV_PACK_TYPE 0 /* CPU Package Type (2-bits)
|
||||
0=NPT L1
|
||||
1=NPT M2
|
||||
2=NPT S1*/
|
||||
#define NV_MAX_NODES 1 /* Number of Nodes/Sockets (4-bits)*/
|
||||
#define NV_MAX_DIMMS 2 /* Number of DIMM slots for the specified Node ID (4-bits)*/
|
||||
#define NV_MAX_MEMCLK 3 /* Maximum platform demonstrated Memclock (10-bits)
|
||||
200=200Mhz (DDR400)
|
||||
266=266Mhz (DDR533)
|
||||
333=333Mhz (DDR667)
|
||||
400=400Mhz (DDR800)*/
|
||||
#define NV_ECC_CAP 4 /* Bus ECC capable (1-bits)
|
||||
0=Platform not capable
|
||||
1=Platform is capable*/
|
||||
#define NV_4RANKType 5 /* Quad Rank DIMM slot type (2-bits)
|
||||
0=Normal
|
||||
1=R4 (4-Rank Registered DIMMs in AMD server configuration)
|
||||
2=S4 (Unbuffered SO-DIMMs)*/
|
||||
#define NV_BYPMAX 6 /* Value to set DcqBypassMax field (See Function 2, Offset 94h, [27:24] of BKDG for field definition).
|
||||
4=4 times bypass (normal for non-UMA systems)
|
||||
7=7 times bypass (normal for UMA systems)*/
|
||||
#define NV_RDWRQBYP 7 /* Value to set RdWrQByp field (See Function 2, Offset A0h, [3:2] of BKDG for field definition).
|
||||
2=8 times (normal for non-UMA systems)
|
||||
3=16 times (normal for UMA systems)*/
|
||||
|
||||
|
||||
/* Dram Timing */
|
||||
#define NV_MCTUSRTMGMODE 10 /* User Memclock Mode (2-bits)
|
||||
0=Auto, no user limit
|
||||
1=Auto, user limit provided in NV_MemCkVal
|
||||
2=Manual, user value provided in NV_MemCkVal*/
|
||||
#define NV_MemCkVal 11 /* Memory Clock Value (2-bits)
|
||||
0=200Mhz
|
||||
1=266Mhz
|
||||
2=333Mhz
|
||||
3=400Mhz*/
|
||||
|
||||
/* Dram Configuration */
|
||||
#define NV_BankIntlv 20 /* Dram Bank (chip-select) Interleaving (1-bits)
|
||||
0=disable
|
||||
1=enable*/
|
||||
#define NV_AllMemClks 21 /* Turn on All DIMM clocks (1-bits)
|
||||
0=normal
|
||||
1=enable all memclocks*/
|
||||
#define NV_SPDCHK_RESTRT 22 /* SPD Check control bitmap (1-bits)
|
||||
0=Exit current node init if any DIMM has SPD checksum error
|
||||
1=Ignore faulty SPD checksums (Note: DIMM cannot be enabled)*/
|
||||
#define NV_DQSTrainCTL 23 /* DQS Signal Timing Training Control
|
||||
0=skip DQS training
|
||||
1=perform DQS training*/
|
||||
#define NV_NodeIntlv 24 /* Node Memory Interleaving (1-bits)
|
||||
0=disable
|
||||
1=enable*/
|
||||
#define NV_BurstLen32 25 /* burstLength32 for 64-bit mode (1-bits)
|
||||
0=disable (normal)
|
||||
1=enable (4 beat burst when width is 64-bits)*/
|
||||
|
||||
/* Dram Power */
|
||||
#define NV_CKE_PDEN 30 /* CKE based power down mode (1-bits)
|
||||
0=disable
|
||||
1=enable*/
|
||||
#define NV_CKE_CTL 31 /* CKE based power down control (1-bits)
|
||||
0=per Channel control
|
||||
1=per Chip select control*/
|
||||
#define NV_CLKHZAltVidC3 32 /* Memclock tri-stating during C3 and Alt VID (1-bits)
|
||||
0=disable
|
||||
1=enable*/
|
||||
|
||||
/* Memory Map/Mgt.*/
|
||||
#define NV_BottomIO 40 /* Bottom of 32-bit IO space (8-bits)
|
||||
NV_BottomIO[7:0]=Addr[31:24]*/
|
||||
#define NV_BottomUMA 41 /* Bottom of shared graphics dram (8-bits)
|
||||
NV_BottomUMA[7:0]=Addr[31:24]*/
|
||||
#define NV_MemHole 42 /* Memory Hole Remapping (1-bits)
|
||||
0=disable
|
||||
1=enable */
|
||||
|
||||
/* ECC */
|
||||
#define NV_ECC 50 /* Dram ECC enable*/
|
||||
#define NV_NBECC 52 /* ECC MCE enable*/
|
||||
#define NV_ChipKill 53 /* Chip-Kill ECC Mode enable*/
|
||||
#define NV_ECCRedir 54 /* Dram ECC Redirection enable*/
|
||||
#define NV_DramBKScrub 55 /* Dram ECC Background Scrubber CTL*/
|
||||
#define NV_L2BKScrub 56 /* L2 ECC Background Scrubber CTL*/
|
||||
#define NV_DCBKScrub 57 /* DCache ECC Background Scrubber CTL*/
|
||||
#define NV_CS_SpareCTL 58 /* Chip Select Spare Control bit 0:
|
||||
0=disable Spare
|
||||
1=enable Spare */
|
||||
/*Chip Select Spare Control bit 1-4:
|
||||
Reserved, must be zero*/
|
||||
#define NV_Parity 60 /* Parity Enable*/
|
||||
#define NV_SyncOnUnEccEn 61 /* SyncOnUnEccEn control
|
||||
0=disable
|
||||
1=enable*/
|
||||
|
||||
#ifndef MAX_NODES_SUPPORTED
|
||||
#define MAX_NODES_SUPPORTED 8
|
||||
#endif
|
||||
|
||||
#ifndef MAX_DIMMS_SUPPORTED
|
||||
#define MAX_DIMMS_SUPPORTED 8
|
||||
#endif
|
||||
|
||||
#ifndef MAX_CS_SUPPORTED
|
||||
#define MAX_CS_SUPPORTED 8
|
||||
#endif
|
||||
|
||||
|
||||
// global function
|
||||
u32 NodePresent(u32 Node);
|
||||
u32 Get_NB32n(struct DCTStatStruc *pDCTstat, u32 addrx);
|
||||
u32 Get_NB32(u32 addr); /* NOTE: extend addr to 32 bit for bus > 0 */
|
||||
u32 mctGetLogicalCPUID(u32 Node);
|
||||
|
||||
void K8FInterleaveBanks(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat);
|
||||
|
||||
void mctInitWithWritetoCS(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat);
|
||||
|
||||
void mctGet_PS_Cfg(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat);
|
||||
void Get_ChannelPS_Cfg0( unsigned MAAdimms, unsigned Speed, unsigned MAAload, unsigned DATAAload,
|
||||
unsigned *AddrTmgCTL, unsigned *ODC_CTL);
|
||||
void Get_ChannelPS_Cfg1( unsigned MAAdimms, unsigned Speed, unsigned MAAload,
|
||||
unsigned *AddrTmgCTL, unsigned *ODC_CTL, unsigned *val);
|
||||
void Get_ChannelPS_Cfg2( unsigned MAAdimms, unsigned Speed, unsigned MAAload,
|
||||
unsigned *AddrTmgCTL, unsigned *ODC_CTL, unsigned *val);
|
||||
|
||||
u8 MCTDefRet(void);
|
||||
|
||||
u32 Get_RcvrSysAddr(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 channel, u8 receiver, u8 *valid);
|
||||
u32 Get_MCTSysAddr(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 channel, u8 chipsel, u8 *valid);
|
||||
void K8FTrainReceiverEn(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA, u8 pass);
|
||||
void K8FTrainDQSPos(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA);
|
||||
u32 SetUpperFSbase(u32 addr_hi);
|
||||
|
||||
|
||||
void K8FECCInit(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA);
|
||||
|
||||
unsigned amd_FD_support(void);
|
||||
void amd_MCTInit(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA);
|
||||
|
||||
void K8FCPUMemTyping(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA);
|
||||
void K8FCPUMemTyping_clear(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA);
|
||||
|
||||
void K8FWaitMemClrDelay(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat);
|
||||
unsigned K8FCalcFinalDQSRcvValue(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, unsigned LeftRcvEn, unsigned RightRcvEn, unsigned *valid);
|
||||
|
||||
void K8FGetDeltaTSCPart1(struct DCTStatStruc *pDCTstat);
|
||||
void K8FGetDeltaTSCPart2(struct DCTStatStruc *pDCTstat);
|
||||
#endif
|
||||
3862
src/northbridge/amd/amdmct/mct/mct_d.c
Normal file
3862
src/northbridge/amd/amdmct/mct/mct_d.c
Normal file
File diff suppressed because it is too large
Load Diff
737
src/northbridge/amd/amdmct/mct/mct_d.h
Normal file
737
src/northbridge/amd/amdmct/mct/mct_d.h
Normal file
@ -0,0 +1,737 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* Description: Include file for all generic DDR 2 MCT files.
|
||||
*/
|
||||
#ifndef MCT_D_H
|
||||
#define MCT_D_H
|
||||
|
||||
|
||||
|
||||
/*===========================================================================
|
||||
CPU - K8/FAM10
|
||||
===========================================================================*/
|
||||
#define PT_L1 0 /* CPU Package Type */
|
||||
#define PT_M2 1
|
||||
#define PT_S1 2
|
||||
#define PT_GR 3
|
||||
|
||||
#define J_MIN 0 /* j loop constraint. 1=CL 2.0 T*/
|
||||
#define J_MAX 5 /* j loop constraint. 5=CL 7.0 T*/
|
||||
#define K_MIN 1 /* k loop constraint. 1=200 Mhz*/
|
||||
#define K_MAX 5 /* k loop constraint. 5=533 Mhz*/
|
||||
#define CL_DEF 2 /* Default value for failsafe operation. 2=CL 4.0 T*/
|
||||
#define T_DEF 1 /* Default value for failsafe operation. 1=5ns (cycle time)*/
|
||||
|
||||
#define BSCRate 1 /* reg bit field=rate of dram scrubber for ecc*/
|
||||
/* memory initialization (ecc and check-bits).*/
|
||||
/* 1=40 ns/64 bytes.*/
|
||||
#define FirstPass 1 /* First pass through RcvEn training*/
|
||||
#define SecondPass 2 /* Second pass through Rcven training*/
|
||||
|
||||
#define RCVREN_MARGIN 6 /* number of DLL taps to delay beyond first passing position*/
|
||||
#define MAXASYNCLATCTL_2 2 /* Max Async Latency Control value*/
|
||||
#define MAXASYNCLATCTL_3 3 /* Max Async Latency Control value*/
|
||||
|
||||
#define DQS_FAIL 1
|
||||
#define DQS_PASS 0
|
||||
#define DQS_WRITEDIR 1
|
||||
#define DQS_READDIR 0
|
||||
#define MIN_DQS_WNDW 3
|
||||
#define secPassOffset 6
|
||||
#define Pass1MemClkDly 0x20 /* Add 1/2 Memlock delay */
|
||||
#define MAX_RD_LAT 0x3FF
|
||||
#define MIN_FENCE 14
|
||||
#define MAX_FENCE 20
|
||||
#define MIN_DQS_WR_FENCE 14
|
||||
#define MAX_DQS_WR_FENCE 20
|
||||
#define FenceTrnFinDlySeed 19
|
||||
#define EarlyArbEn 19
|
||||
|
||||
#define PA_HOST(Node) ((((0x18+Node) << 3)+0) << 12) /* Node 0 Host Bus function PCI Address bits [15:0]*/
|
||||
#define PA_MAP(Node) ((((0x18+Node) << 3)+1) << 12) /* Node 0 MAP function PCI Address bits [15:0]*/
|
||||
#define PA_DCT(Node) ((((0x18+Node) << 3)+2) << 12) /* Node 0 DCT function PCI Address bits [15:0]*/
|
||||
//#define PA_EXT_DCT (((00 << 3)+4) << 8) /*Node 0 DCT extended configuration registers*/
|
||||
//#define PA_DCTADDL (((00 << 3)+2) << 8) /*Node x DCT function, Additional Registers PCI Address bits [15:0]*/
|
||||
//#define PA_EXT_DCTADDL (((00 << 3)+5) << 8) /*Node x DCT function, Additional Registers PCI Address bits [15:0]*/
|
||||
|
||||
#define PA_NBMISC(Node) ((((0x18+Node) << 3)+3) << 12) /*Node 0 Misc PCI Address bits [15:0]*/
|
||||
//#define PA_NBDEVOP (((00 << 3)+3) << 8) /*Node 0 Misc PCI Address bits [15:0]*/
|
||||
|
||||
#define DCC_EN 1 /* X:2:0x94[19]*/
|
||||
#define ILD_Lmt 3 /* X:2:0x94[18:16]*/
|
||||
|
||||
#define EncodedTSPD 0x00191709 /* encodes which SPD byte to get T from*/
|
||||
/* versus CL X, CL X-.5, and CL X-1*/
|
||||
|
||||
#define Bias_TrpT 3 /* bias to convert bus clocks to bit field value*/
|
||||
#define Bias_TrrdT 2
|
||||
#define Bias_TrcdT 3
|
||||
#define Bias_TrasT 3
|
||||
#define Bias_TrcT 11
|
||||
#define Bias_TrtpT 2
|
||||
#define Bias_TwrT 3
|
||||
#define Bias_TwtrT 0
|
||||
#define Bias_TfawT 7
|
||||
|
||||
#define Min_TrpT 3 /* min programmable value in busclocks*/
|
||||
#define Max_TrpT 6 /* max programmable value in busclocks*/
|
||||
#define Min_TrrdT 2
|
||||
#define Max_TrrdT 5
|
||||
#define Min_TrcdT 3
|
||||
#define Max_TrcdT 6
|
||||
#define Min_TrasT 5
|
||||
#define Max_TrasT 18
|
||||
#define Min_TrcT 11
|
||||
#define Max_TrcT 26
|
||||
#define Min_TrtpT 2
|
||||
#define Max_TrtpT 3
|
||||
#define Min_TwrT 3
|
||||
#define Max_TwrT 6
|
||||
#define Min_TwtrT 1
|
||||
#define Max_TwtrT 3
|
||||
|
||||
/*DDR2-1066 support*/
|
||||
#define Bias_TrcdT_1066 5
|
||||
#define Bias_TrasT_1066 15
|
||||
#define Bias_TrrdT_1066 4
|
||||
#define Bias_TwrT_1066 4
|
||||
#define Bias_TrpT_1066 5
|
||||
#define Bias_TwtrT_1066 4
|
||||
#define Bias_TfawT_1066 15
|
||||
|
||||
#define Min_TrcdT_1066 5
|
||||
#define Max_TrcdT_1066 12
|
||||
#define Min_TrasT_1066 15
|
||||
#define Max_TrasT_1066 30
|
||||
#define Min_TrcT_1066 11
|
||||
#define Max_TrcT_1066 42
|
||||
#define Min_TrrdT_1066 4
|
||||
#define Max_TrrdT_1066 7
|
||||
#define Min_TwrT_1066 5
|
||||
#define Max_TwrT_1066 8
|
||||
#define Min_TrpT_1066 5
|
||||
#define Max_TrpT_1066 12
|
||||
#define Min_TwtrT_1066 4
|
||||
#define Max_TwtrT_1066 7
|
||||
|
||||
/*common register bit names*/
|
||||
#define DramHoleValid 0 /* func 1, offset F0h, bit 0*/
|
||||
#define DramMemHoistValid 1 /* func 1, offset F0h, bit 1*/
|
||||
#define CSEnable 0 /* func 2, offset 40h-5C, bit 0*/
|
||||
#define Spare 1 /* func 2, offset 40h-5C, bit 1*/
|
||||
#define TestFail 2 /* func 2, offset 40h-5C, bit 2*/
|
||||
#define DqsRcvEnTrain 18 /* func 2, offset 78h, bit 18*/
|
||||
#define EnDramInit 31 /* func 2, offset 7Ch, bit 31*/
|
||||
#define DisAutoRefresh 18 /* func 2, offset 8Ch, bit 18*/
|
||||
#define InitDram 0 /* func 2, offset 90h, bit 0*/
|
||||
#define BurstLength32 10 /* func 2, offset 90h, bit 10*/
|
||||
#define Width128 11 /* func 2, offset 90h, bit 11*/
|
||||
#define X4Dimm 12 /* func 2, offset 90h, bit 12*/
|
||||
#define UnBuffDimm 16 /* func 2, offset 90h, bit 16*/
|
||||
#define DimmEcEn 19 /* func 2, offset 90h, bit 19*/
|
||||
#define MemClkFreqVal 3 /* func 2, offset 94h, bit 3*/
|
||||
#define RDqsEn 12 /* func 2, offset 94h, bit 12*/
|
||||
#define DisDramInterface 14 /* func 2, offset 94h, bit 14*/
|
||||
#define DctAccessWrite 30 /* func 2, offset 98h, bit 30*/
|
||||
#define DctAccessDone 31 /* func 2, offset 98h, bit 31*/
|
||||
#define MemClrStatus 0 /* func 2, offset A0h, bit 0*/
|
||||
#define PwrSavingsEn 10 /* func 2, offset A0h, bit 10*/
|
||||
#define Mod64BitMux 4 /* func 2, offset A0h, bit 4*/
|
||||
#define DisableJitter 1 /* func 2, offset A0h, bit 1*/
|
||||
#define MemClrDis 1 /* func 3, offset F8h, FNC 4, bit 1*/
|
||||
#define SyncOnUcEccEn 2 /* func 3, offset 44h, bit 2*/
|
||||
#define Dr_MemClrStatus 10 /* func 3, offset 110h, bit 10*/
|
||||
#define MemClrBusy 9 /* func 3, offset 110h, bit 9*/
|
||||
#define DctGangEn 4 /* func 3, offset 110h, bit 4*/
|
||||
#define MemClrInit 3 /* func 3, offset 110h, bit 3*/
|
||||
#define AssertCke 28 /* func 2, offset 7Ch, bit 28*/
|
||||
#define DeassertMemRstX 27 /* func 2, offset 7Ch, bit 27*/
|
||||
#define SendMrsCmd 26 /* func 2, offset 7Ch, bit 26*/
|
||||
#define SendAutoRefresh 25 /* func 2, offset 7Ch, bit 25*/
|
||||
#define SendPchgAll 24 /* func 2, offset 7Ch, bit 24*/
|
||||
#define DisDqsBar 6 /* func 2, offset 90h, bit 6*/
|
||||
#define DramEnabled 8 /* func 2, offset 110h, bit 8*/
|
||||
#define LegacyBiosMode 9 /* func 2, offset 94h, bit 9*/
|
||||
#define PrefDramTrainMode 28 /* func 2, offset 11Ch, bit 28*/
|
||||
#define FlushWr 30 /* func 2, offset 11Ch, bit 30*/
|
||||
#define DisAutoComp 30 /* func 2, offset 9Ch, Index 8, bit 30*/
|
||||
#define DqsRcvTrEn 13 /* func 2, offset 9Ch, Index 8, bit 13*/
|
||||
#define ForceAutoPchg 23 /* func 2, offset 90h, bit 23*/
|
||||
#define ClLinesToNbDis 15 /* Bu_CFG2, bit 15*/
|
||||
#define WbEnhWsbDis_D (48-32)
|
||||
#define PhyFenceTrEn 3 /* func 2, offset 9Ch, Index 8, bit 3 */
|
||||
#define ParEn 8 /* func 2, offset 90h, bit 8 */
|
||||
#define DcqArbBypassEn 19 /* func 2, offset 94h, bit 19 */
|
||||
#define ActiveCmdAtRst 1 /* func 2, offset A8H, bit 1 */
|
||||
#define FlushWrOnStpGnt 29 /* func 2, offset 11Ch, bit 29 */
|
||||
#define BankSwizzleMode 22 /* func 2, offset 94h, bit 22 */
|
||||
#define ChSetupSync 15 /* func 2, offset 78h, bit 15 */
|
||||
|
||||
|
||||
|
||||
/*=============================================================================
|
||||
SW Initialization
|
||||
============================================================================*/
|
||||
#define DLL_Enable 1
|
||||
#define OCD_Default 2
|
||||
#define OCD_Exit 3
|
||||
|
||||
|
||||
|
||||
/*=============================================================================
|
||||
Jedec DDR II
|
||||
=============================================================================*/
|
||||
#define SPD_TYPE 2 /*SPD byte read location*/
|
||||
#define JED_DDRSDRAM 0x07 /*Jedec defined bit field*/
|
||||
#define JED_DDR2SDRAM 0x08 /*Jedec defined bit field*/
|
||||
|
||||
#define SPD_DIMMTYPE 20
|
||||
#define SPD_ATTRIB 21
|
||||
#define JED_DIFCKMSK 0x20 /*Differential Clock Input*/
|
||||
#define JED_REGADCMSK 0x11 /*Registered Address/Control*/
|
||||
#define JED_PROBEMSK 0x40 /*Analysis Probe installed*/
|
||||
#define SPD_DEVATTRIB 22
|
||||
#define SPD_EDCTYPE 11
|
||||
#define JED_ECC 0x02
|
||||
#define JED_ADRCPAR 0x04
|
||||
#define SPD_ROWSZ 3
|
||||
#define SPD_COLSZ 4
|
||||
#define SPD_LBANKS 17 /*number of [logical] banks on each device*/
|
||||
#define SPD_DMBANKS 5 /*number of physical banks on dimm*/
|
||||
#define SPDPLBit 4 /* Dram package bit*/
|
||||
#define SPD_BANKSZ 31 /*capacity of physical bank*/
|
||||
#define SPD_DEVWIDTH 13
|
||||
#define SPD_CASLAT 18
|
||||
#define SPD_TRP 27
|
||||
#define SPD_TRRD 28
|
||||
#define SPD_TRCD 29
|
||||
#define SPD_TRAS 30
|
||||
#define SPD_TWR 36
|
||||
#define SPD_TWTR 37
|
||||
#define SPD_TRTP 38
|
||||
#define SPD_TRCRFC 40
|
||||
#define SPD_TRC 41
|
||||
#define SPD_TRFC 42
|
||||
|
||||
#define SPD_MANDATEYR 93 /*Module Manufacturing Year (BCD)*/
|
||||
|
||||
#define SPD_MANDATEWK 94 /*Module Manufacturing Week (BCD)*/
|
||||
|
||||
/*-----------------------------
|
||||
Jdec DDR II related equates
|
||||
-----------------------------*/
|
||||
#define MYEAR06 6 /* Manufacturing Year BCD encoding of 2006 - 06d*/
|
||||
#define MWEEK24 0x24 /* Manufacturing Week BCD encoding of June - 24d*/
|
||||
|
||||
/*=============================================================================
|
||||
Macros
|
||||
=============================================================================*/
|
||||
|
||||
#define _2GB_RJ8 (2<<(30-8))
|
||||
#define _4GB_RJ8 (4<<(30-8))
|
||||
#define _4GB_RJ4 (4<<(30-4))
|
||||
|
||||
#define BigPagex8_RJ8 (1<<(17+3-8)) /*128KB * 8 >> 8 */
|
||||
|
||||
/*=============================================================================
|
||||
Global MCT Status Structure
|
||||
=============================================================================*/
|
||||
struct MCTStatStruc {
|
||||
u32 GStatus; /* Global Status bitfield*/
|
||||
u32 HoleBase; /* If not zero, BASE[39:8] (system address)
|
||||
of sub 4GB dram hole for HW remapping.*/
|
||||
u32 Sub4GCacheTop; /* If not zero, the 32-bit top of cacheable memory.*/
|
||||
u32 SysLimit; /* LIMIT[39:8] (system address)*/
|
||||
};
|
||||
|
||||
/*=============================================================================
|
||||
Global MCT Configuration Status Word (GStatus)
|
||||
=============================================================================*/
|
||||
/*These should begin at bit 0 of GStatus[31:0]*/
|
||||
#define GSB_MTRRshort 0 /* Ran out of MTRRs while mapping memory*/
|
||||
#define GSB_ECCDIMMs 1 /* All banks of all Nodes are ECC capable*/
|
||||
#define GSB_DramECCDis 2 /* Dram ECC requested but not enabled.*/
|
||||
#define GSB_SoftHole 3 /* A Node Base gap was created*/
|
||||
#define GSB_HWHole 4 /* A HW dram remap was created*/
|
||||
#define GSB_NodeIntlv 5 /* Node Memory interleaving was enabled*/
|
||||
#define GSB_SpIntRemapHole 16 /* Special condition for Node Interleave and HW remapping*/
|
||||
#define GSB_EnDIMMSpareNW 17 /* Indicates that DIMM Spare can be used without a warm reset */
|
||||
/* NOTE: This is a local bit used by memory code */
|
||||
|
||||
|
||||
/*===============================================================================
|
||||
Local DCT Status structure (a structure for each DCT)
|
||||
===============================================================================*/
|
||||
|
||||
struct DCTStatStruc { /* A per Node structure*/
|
||||
/* DCTStatStruct_F - start */
|
||||
u8 Node_ID; /* Node ID of current controller*/
|
||||
u8 ErrCode; /* Current error condition of Node
|
||||
0= no error
|
||||
1= Variance Error, DCT is running but not in an optimal configuration.
|
||||
2= Stop Error, DCT is NOT running
|
||||
3= Fatal Error, DCT/MCT initialization has been halted.*/
|
||||
u32 ErrStatus; /* Error Status bit Field */
|
||||
u32 Status; /* Status bit Field*/
|
||||
u8 DIMMAddr[8]; /* SPD address of DIMM controlled by MA0_CS_L[0,1]*/
|
||||
/* SPD address of..MB0_CS_L[0,1]*/
|
||||
/* SPD address of..MA1_CS_L[0,1]*/
|
||||
/* SPD address of..MB1_CS_L[0,1]*/
|
||||
/* SPD address of..MA2_CS_L[0,1]*/
|
||||
/* SPD address of..MB2_CS_L[0,1]*/
|
||||
/* SPD address of..MA3_CS_L[0,1]*/
|
||||
/* SPD address of..MB3_CS_L[0,1]*/
|
||||
u16 DIMMPresent; /*For each bit n 0..7, 1=DIMM n is present.
|
||||
DIMM# Select Signal
|
||||
0 MA0_CS_L[0,1]
|
||||
1 MB0_CS_L[0,1]
|
||||
2 MA1_CS_L[0,1]
|
||||
3 MB1_CS_L[0,1]
|
||||
4 MA2_CS_L[0,1]
|
||||
5 MB2_CS_L[0,1]
|
||||
6 MA3_CS_L[0,1]
|
||||
7 MB3_CS_L[0,1]*/
|
||||
u16 DIMMValid; /* For each bit n 0..7, 1=DIMM n is valid and is/will be configured*/
|
||||
u16 DIMMMismatch; /* For each bit n 0..7, 1=DIMM n is mismatched, channel B is always considered the mismatch */
|
||||
u16 DIMMSPDCSE; /* For each bit n 0..7, 1=DIMM n SPD checksum error*/
|
||||
u16 DimmECCPresent; /* For each bit n 0..7, 1=DIMM n is ECC capable.*/
|
||||
u16 DimmPARPresent; /* For each bit n 0..7, 1=DIMM n is ADR/CMD Parity capable.*/
|
||||
u16 Dimmx4Present; /* For each bit n 0..7, 1=DIMM n contains x4 data devices.*/
|
||||
u16 Dimmx8Present; /* For each bit n 0..7, 1=DIMM n contains x8 data devices.*/
|
||||
u16 Dimmx16Present; /* For each bit n 0..7, 1=DIMM n contains x16 data devices.*/
|
||||
u16 DIMM2Kpage; /* For each bit n 0..7, 1=DIMM n contains 1K page devices.*/
|
||||
u8 MAload[2]; /* Number of devices loading MAA bus*/
|
||||
/* Number of devices loading MAB bus*/
|
||||
u8 MAdimms[2]; /*Number of DIMMs loading CH A*/
|
||||
/* Number of DIMMs loading CH B*/
|
||||
u8 DATAload[2]; /*Number of ranks loading CH A DATA*/
|
||||
/* Number of ranks loading CH B DATA*/
|
||||
u8 DIMMAutoSpeed; /*Max valid Mfg. Speed of DIMMs
|
||||
1=200Mhz
|
||||
2=266Mhz
|
||||
3=333Mhz
|
||||
4=400Mhz
|
||||
5=533Mhz*/
|
||||
u8 DIMMCASL; /* Min valid Mfg. CL bitfield
|
||||
0=2.0
|
||||
1=3.0
|
||||
2=4.0
|
||||
3=5.0
|
||||
4=6.0 */
|
||||
u16 DIMMTrcd; /* Minimax Trcd*40 (ns) of DIMMs*/
|
||||
u16 DIMMTrp; /* Minimax Trp*40 (ns) of DIMMs*/
|
||||
u16 DIMMTrtp; /* Minimax Trtp*40 (ns) of DIMMs*/
|
||||
u16 DIMMTras; /* Minimax Tras*40 (ns) of DIMMs*/
|
||||
u16 DIMMTrc; /* Minimax Trc*40 (ns) of DIMMs*/
|
||||
u16 DIMMTwr; /* Minimax Twr*40 (ns) of DIMMs*/
|
||||
u16 DIMMTrrd; /* Minimax Trrd*40 (ns) of DIMMs*/
|
||||
u16 DIMMTwtr; /* Minimax Twtr*40 (ns) of DIMMs*/
|
||||
u8 Speed; /* Bus Speed (to set Controller)
|
||||
1=200Mhz
|
||||
2=266Mhz
|
||||
3=333Mhz
|
||||
4=400Mhz */
|
||||
u8 CASL; /* CAS latency DCT setting
|
||||
0=2.0
|
||||
1=3.0
|
||||
2=4.0
|
||||
3=5.0
|
||||
4=6.0 */
|
||||
u8 Trcd; /* DCT Trcd (busclocks) */
|
||||
u8 Trp; /* DCT Trp (busclocks) */
|
||||
u8 Trtp; /* DCT Trtp (busclocks) */
|
||||
u8 Tras; /* DCT Tras (busclocks) */
|
||||
u8 Trc; /* DCT Trc (busclocks) */
|
||||
u8 Twr; /* DCT Twr (busclocks) */
|
||||
u8 Trrd; /* DCT Trrd (busclocks) */
|
||||
u8 Twtr; /* DCT Twtr (busclocks) */
|
||||
u8 Trfc[4]; /* DCT Logical DIMM0 Trfc
|
||||
0=75ns (for 256Mb devs)
|
||||
1=105ns (for 512Mb devs)
|
||||
2=127.5ns (for 1Gb devs)
|
||||
3=195ns (for 2Gb devs)
|
||||
4=327.5ns (for 4Gb devs) */
|
||||
/* DCT Logical DIMM1 Trfc (see Trfc0 for format) */
|
||||
/* DCT Logical DIMM2 Trfc (see Trfc0 for format) */
|
||||
/* DCT Logical DIMM3 Trfc (see Trfc0 for format) */
|
||||
u16 CSPresent; /* For each bit n 0..7, 1=Chip-select n is present */
|
||||
u16 CSTestFail; /* For each bit n 0..7, 1=Chip-select n is present but disabled */
|
||||
u32 DCTSysBase; /* BASE[39:8] (system address) of this Node's DCTs. */
|
||||
u32 DCTHoleBase; /* If not zero, BASE[39:8] (system address) of dram hole for HW remapping. Dram hole exists on this Node's DCTs. */
|
||||
u32 DCTSysLimit; /* LIMIT[39:8] (system address) of this Node's DCTs */
|
||||
u16 PresetmaxFreq; /* Maximum OEM defined DDR frequency
|
||||
200=200Mhz (DDR400)
|
||||
266=266Mhz (DDR533)
|
||||
333=333Mhz (DDR667)
|
||||
400=400Mhz (DDR800) */
|
||||
u8 _2Tmode; /* 1T or 2T CMD mode (slow access mode)
|
||||
1=1T
|
||||
2=2T */
|
||||
u8 TrwtTO; /* DCT TrwtTO (busclocks)*/
|
||||
u8 Twrrd; /* DCT Twrrd (busclocks)*/
|
||||
u8 Twrwr; /* DCT Twrwr (busclocks)*/
|
||||
u8 Trdrd; /* DCT Trdrd (busclocks)*/
|
||||
u32 CH_ODC_CTL[2]; /* Output Driver Strength (see BKDG FN2:Offset 9Ch, index 00h*/
|
||||
u32 CH_ADDR_TMG[2]; /* Address Bus Timing (see BKDG FN2:Offset 9Ch, index 04h*/
|
||||
/* Output Driver Strength (see BKDG FN2:Offset 9Ch, index 20h*/
|
||||
/* Address Bus Timing (see BKDG FN2:Offset 9Ch, index 24h*/
|
||||
u16 CH_EccDQSLike[2]; /* CHA DQS ECC byte like...*/
|
||||
u8 CH_EccDQSScale[2]; /* CHA DQS ECC byte scale*/
|
||||
/* CHA DQS ECC byte like...*/
|
||||
/* CHA DQS ECC byte scale*/
|
||||
u8 MaxAsyncLat; /* Max Asynchronous Latency (ns)*/
|
||||
// NOTE: Not used in Barcelona - u8 CH_D_RCVRDLY[2][4];
|
||||
/* CHA DIMM 0 - 4 Receiver Enable Delay*/
|
||||
/* CHB DIMM 0 - 4 Receiver Enable Delay */
|
||||
// NOTE: Not used in Barcelona - u8 CH_D_B_DQS[2][2][8];
|
||||
/* CHA Byte 0-7 Write DQS Delay */
|
||||
/* CHA Byte 0-7 Read DQS Delay */
|
||||
/* CHB Byte 0-7 Write DQS Delay */
|
||||
/* CHB Byte 0-7 Read DQS Delay */
|
||||
u32 PtrPatternBufA; /* Ptr on stack to aligned DQS testing pattern*/
|
||||
u32 PtrPatternBufB; /* Ptr on stack to aligned DQS testing pattern*/
|
||||
u8 Channel; /* Current Channel (0= CH A, 1=CH B)*/
|
||||
u8 ByteLane; /* Current Byte Lane (0..7)*/
|
||||
u8 Direction; /* Current DQS-DQ training write direction (0=read, 1=write)*/
|
||||
u8 Pattern; /* Current pattern*/
|
||||
u8 DQSDelay; /* Current DQS delay value*/
|
||||
u32 TrainErrors; /* Current Training Errors*/
|
||||
|
||||
u32 AMC_TSC_DeltaLo; /* Time Stamp Counter measurement of AMC, Low dword*/
|
||||
u32 AMC_TSC_DeltaHi; /* Time Stamp Counter measurement of AMC, High dword*/
|
||||
// NOTE: Not used in Barcelona - u8 CH_D_DIR_MaxMin_B_Dly[2][4][2][2][8];
|
||||
/* CH A byte lane 0 - 7 minimum filtered window passing DQS delay value*/
|
||||
/* CH A byte lane 0 - 7 maximum filtered window passing DQS delay value*/
|
||||
/* CH B byte lane 0 - 7 minimum filtered window passing DQS delay value*/
|
||||
/* CH B byte lane 0 - 7 maximum filtered window passing DQS delay value*/
|
||||
/* CH A byte lane 0 - 7 minimum filtered window passing DQS delay value*/
|
||||
/* CH A byte lane 0 - 7 maximum filtered window passing DQS delay value*/
|
||||
/* CH B byte lane 0 - 7 minimum filtered window passing DQS delay value*/
|
||||
/* CH B byte lane 0 - 7 maximum filtered window passing DQS delay value*/
|
||||
u32 LogicalCPUID; /* The logical CPUID of the node*/
|
||||
u16 HostBiosSrvc1; /* Word sized general purpose field for use by host BIOS. Scratch space.*/
|
||||
u32 HostBiosSrvc2; /* Dword sized general purpose field for use by host BIOS. Scratch space.*/
|
||||
u16 DimmQRPresent; /* QuadRank DIMM present?*/
|
||||
u16 DimmTrainFail; /* Bitmap showing which dimms failed training*/
|
||||
u16 CSTrainFail; /* Bitmap showing which chipselects failed training*/
|
||||
u16 DimmYr06; /* Bitmap indicating which Dimms have a manufactur's year code <= 2006*/
|
||||
u16 DimmWk2406; /* Bitmap indicating which Dimms have a manufactur's week code <= 24 of 2006 (June)*/
|
||||
u16 DimmDRPresent; /* Bitmap indicating that Dual Rank Dimms are present*/
|
||||
u16 DimmPlPresent; /* Bitmap indicating that Planar (1) or Stacked (0) Dimms are present.*/
|
||||
u16 ChannelTrainFai; /* Bitmap showing the chanel informaiton about failed Chip Selects
|
||||
0 in any bit field indicates Channel 0
|
||||
1 in any bit field indicates Channel 1 */
|
||||
u16 CSUsrTestFail; /* Chip selects excluded by user */
|
||||
/* DCTStatStruct_F - end */
|
||||
|
||||
u16 CH_MaxRdLat[2]; /* Max Read Latency (ns) for DCT 0*/
|
||||
/* Max Read Latency (ns) for DCT 1*/
|
||||
u8 CH_D_DIR_B_DQS[2][4][2][9]; /* [A/B] [DIMM1-4] [R/W] [DQS] */
|
||||
/* CHA DIMM0 Byte 0 - 7 and Check Write DQS Delay*/
|
||||
/* CHA DIMM0 Byte 0 - 7 and Check Read DQS Delay*/
|
||||
/* CHA DIMM1 Byte 0 - 7 and Check Write DQS Delay*/
|
||||
/* CHA DIMM1 Byte 0 - 7 and Check Read DQS Delay*/
|
||||
/* CHB DIMM0 Byte 0 - 7 and Check Write DQS Delay*/
|
||||
/* CHB DIMM0 Byte 0 - 7 and Check Read DQS Delay*/
|
||||
/* CHB DIMM1 Byte 0 - 7 and Check Write DQS Delay*/
|
||||
/* CHB DIMM1 Byte 0 - 7 and Check Read DQS Delay*/
|
||||
u8 CH_D_B_RCVRDLY[2][4][8]; /* [A/B] [DIMM0-3] [DQS] */
|
||||
/* CHA DIMM 0 Receiver Enable Delay*/
|
||||
/* CHA DIMM 1 Receiver Enable Delay*/
|
||||
/* CHA DIMM 2 Receiver Enable Delay*/
|
||||
/* CHA DIMM 3 Receiver Enable Delay*/
|
||||
|
||||
/* CHB DIMM 0 Receiver Enable Delay*/
|
||||
/* CHB DIMM 1 Receiver Enable Delay*/
|
||||
/* CHB DIMM 2 Receiver Enable Delay*/
|
||||
/* CHB DIMM 3 Receiver Enable Delay*/
|
||||
u8 CH_D_BC_RCVRDLY[2][4];
|
||||
/* CHA DIMM 0 - 4 Check Byte Receiver Enable Delay*/
|
||||
/* CHB DIMM 0 - 4 Check Byte Receiver Enable Delay*/
|
||||
u8 DIMMValidDCT[2]; /* DIMM# in DCT0*/
|
||||
/* DIMM# in DCT1*/
|
||||
u8 MaxDCTs; /* Max number of DCTs in system*/
|
||||
// NOTE: removed u8 DCT. Use ->dev_ for pci R/W; /*DCT pointer*/
|
||||
u8 GangedMode; /* Ganged mode enabled, 0 = disabled, 1 = enabled*/
|
||||
u8 DRPresent; /* Family 10 present flag, 0 = n0t Fam10, 1 = Fam10*/
|
||||
u32 NodeSysLimit; /* BASE[39:8],for DCT0+DCT1 system address*/
|
||||
u8 WrDatGrossH;
|
||||
u8 DqsRcvEnGrossL;
|
||||
// NOTE: Not used - u8 NodeSpeed /* Bus Speed (to set Controller)
|
||||
/* 1=200Mhz */
|
||||
/* 2=266Mhz */
|
||||
/* 3=333Mhz */
|
||||
// NOTE: Not used - u8 NodeCASL /* CAS latency DCT setting
|
||||
/* 0=2.0 */
|
||||
/* 1=3.0 */
|
||||
/* 2=4.0 */
|
||||
/* 3=5.0 */
|
||||
/* 4=6.0 */
|
||||
u8 TrwtWB;
|
||||
u8 CurrRcvrCHADelay; /* for keep current RcvrEnDly of chA*/
|
||||
u16 T1000; /* get the T1000 figure (cycle time (ns)*1K)*/
|
||||
u8 DqsRcvEn_Pass; /* for TrainRcvrEn byte lane pass flag*/
|
||||
u8 DqsRcvEn_Saved; /* for TrainRcvrEn byte lane saved flag*/
|
||||
u8 SeedPass1Remainder; /* for Phy assisted DQS receiver enable training*/
|
||||
|
||||
/* for second pass - Second pass should never run for Fam10*/
|
||||
// NOTE: Not used for Barcelona - u8 CH_D_B_RCVRDLY_1[2][4][8]; /* CHA DIMM 0 Receiver Enable Delay*/
|
||||
/* CHA DIMM 1 Receiver Enable Delay*/
|
||||
/* CHA DIMM 2 Receiver Enable Delay*/
|
||||
/* CHA DIMM 3 Receiver Enable Delay*/
|
||||
|
||||
/* CHB DIMM 0 Receiver Enable Delay*/
|
||||
/* CHB DIMM 1 Receiver Enable Delay*/
|
||||
/* CHB DIMM 2 Receiver Enable Delay*/
|
||||
/* CHB DIMM 3 Receiver Enable Delay*/
|
||||
|
||||
u8 ClToNB_flag; /* is used to restore ClLinesToNbDis bit after memory */
|
||||
u32 NodeSysBase; /* for channel interleave usage */
|
||||
|
||||
/* New for LB Support */
|
||||
u8 NodePresent;
|
||||
u32 dev_host;
|
||||
u32 dev_map;
|
||||
u32 dev_dct;
|
||||
u32 dev_nbmisc;
|
||||
};
|
||||
|
||||
/*===============================================================================
|
||||
Local Error Status Codes (DCTStatStruc.ErrCode)
|
||||
===============================================================================*/
|
||||
#define SC_RunningOK 0
|
||||
#define SC_VarianceErr 1 /* Running non-optimally*/
|
||||
#define SC_StopError 2 /* Not Running*/
|
||||
#define SC_FatalErr 3 /* Fatal Error, MCTB has exited immediately*/
|
||||
|
||||
/*===============================================================================
|
||||
Local Error Status (DCTStatStruc.ErrStatus[31:0])
|
||||
===============================================================================*/
|
||||
#define SB_NoDimms 0
|
||||
#define SB_DIMMChkSum 1
|
||||
#define SB_DimmMismatchM 2 /* dimm module type(buffer) mismatch*/
|
||||
#define SB_DimmMismatchT 3 /* dimm CL/T mismatch*/
|
||||
#define SB_DimmMismatchO 4 /* dimm organization mismatch (128-bit)*/
|
||||
#define SB_NoTrcTrfc 5 /* SPD missing Trc or Trfc info*/
|
||||
#define SB_NoCycTime 6 /* SPD missing byte 23 or 25*/
|
||||
#define SB_BkIntDis 7 /* Bank interleave requested but not enabled*/
|
||||
#define SB_DramECCDis 8 /* Dram ECC requested but not enabled*/
|
||||
#define SB_SpareDis 9 /* Online spare requested but not enabled*/
|
||||
#define SB_MinimumMode 10 /* Running in Minimum Mode*/
|
||||
#define SB_NORCVREN 11 /* No DQS Receiver Enable pass window found*/
|
||||
#define SB_CHA2BRCVREN 12 /* DQS Rcvr En pass window CHA to CH B too large*/
|
||||
#define SB_SmallRCVR 13 /* DQS Rcvr En pass window too small (far right of dynamic range)*/
|
||||
#define SB_NODQSPOS 14 /* No DQS-DQ passing positions*/
|
||||
#define SB_SMALLDQS 15 /* DQS-DQ passing window too small*/
|
||||
#define SB_DCBKScrubDis 16 /* DCache scrub requested but not enabled */
|
||||
|
||||
/*===============================================================================
|
||||
Local Configuration Status (DCTStatStruc.Status[31:0])
|
||||
===============================================================================*/
|
||||
#define SB_Registered 0 /* All DIMMs are Registered*/
|
||||
#define SB_ECCDIMMs 1 /* All banks ECC capable*/
|
||||
#define SB_PARDIMMs 2 /* All banks Addr/CMD Parity capable*/
|
||||
#define SB_DiagClks 3 /* Jedec ALL slots clock enable diag mode*/
|
||||
#define SB_128bitmode 4 /* DCT in 128-bit mode operation*/
|
||||
#define SB_64MuxedMode 5 /* DCT in 64-bit mux'ed mode.*/
|
||||
#define SB_2TMode 6 /* 2T CMD timing mode is enabled.*/
|
||||
#define SB_SWNodeHole 7 /* Remapping of Node Base on this Node to create a gap.*/
|
||||
#define SB_HWHole 8 /* Memory Hole created on this Node using HW remapping.*/
|
||||
#define SB_Over400MHz 9 /* DCT freq >= 400MHz flag*/
|
||||
#define SB_DQSPos_Pass2 10 /* Using for TrainDQSPos DIMM0/1, when freq>=400MHz*/
|
||||
#define SB_DQSRcvLimit 11 /* Using for DQSRcvEnTrain to know we have reached to upper bound.*/
|
||||
#define SB_ExtConfig 12 /* Indicator the default setting for extend PCI configuration support*/
|
||||
|
||||
|
||||
|
||||
|
||||
/*===============================================================================
|
||||
NVRAM/run-time-configurable Items
|
||||
===============================================================================*/
|
||||
/*Platform Configuration*/
|
||||
#define NV_PACK_TYPE 0 /* CPU Package Type (2-bits)
|
||||
0=NPT L1
|
||||
1=NPT M2
|
||||
2=NPT S1*/
|
||||
#define NV_MAX_NODES 1 /* Number of Nodes/Sockets (4-bits)*/
|
||||
#define NV_MAX_DIMMS 2 /* Number of DIMM slots for the specified Node ID (4-bits)*/
|
||||
#define NV_MAX_MEMCLK 3 /* Maximum platform demonstrated Memclock (10-bits)
|
||||
200=200Mhz (DDR400)
|
||||
266=266Mhz (DDR533)
|
||||
333=333Mhz (DDR667)
|
||||
400=400Mhz (DDR800)*/
|
||||
#define NV_ECC_CAP 4 /* Bus ECC capable (1-bits)
|
||||
0=Platform not capable
|
||||
1=Platform is capable*/
|
||||
#define NV_4RANKType 5 /* Quad Rank DIMM slot type (2-bits)
|
||||
0=Normal
|
||||
1=R4 (4-Rank Registered DIMMs in AMD server configuration)
|
||||
2=S4 (Unbuffered SO-DIMMs)*/
|
||||
#define NV_BYPMAX 6 /* Value to set DcqBypassMax field (See Function 2, Offset 94h, [27:24] of BKDG for field definition).
|
||||
4=4 times bypass (normal for non-UMA systems)
|
||||
7=7 times bypass (normal for UMA systems)*/
|
||||
#define NV_RDWRQBYP 7 /* Value to set RdWrQByp field (See Function 2, Offset A0h, [3:2] of BKDG for field definition).
|
||||
2=8 times (normal for non-UMA systems)
|
||||
3=16 times (normal for UMA systems)*/
|
||||
|
||||
|
||||
/*Dram Timing*/
|
||||
#define NV_MCTUSRTMGMODE 10 /* User Memclock Mode (2-bits)
|
||||
0=Auto, no user limit
|
||||
1=Auto, user limit provided in NV_MemCkVal
|
||||
2=Manual, user value provided in NV_MemCkVal*/
|
||||
#define NV_MemCkVal 11 /* Memory Clock Value (2-bits)
|
||||
0=200Mhz
|
||||
1=266Mhz
|
||||
2=333Mhz
|
||||
3=400Mhz*/
|
||||
|
||||
/*Dram Configuration*/
|
||||
#define NV_BankIntlv 20 /* Dram Bank (chip-select) Interleaving (1-bits)
|
||||
0=disable
|
||||
1=enable*/
|
||||
#define NV_AllMemClks 21 /* Turn on All DIMM clocks (1-bits)
|
||||
0=normal
|
||||
1=enable all memclocks*/
|
||||
#define NV_SPDCHK_RESTRT 22 /* SPD Check control bitmap (1-bits)
|
||||
0=Exit current node init if any DIMM has SPD checksum error
|
||||
1=Ignore faulty SPD checksums (Note: DIMM cannot be enabled)*/
|
||||
#define NV_DQSTrainCTL 23 /* DQS Signal Timing Training Control
|
||||
0=skip DQS training
|
||||
1=perform DQS training*/
|
||||
#define NV_NodeIntlv 24 /* Node Memory Interleaving (1-bits)
|
||||
0=disable
|
||||
1=enable*/
|
||||
#define NV_BurstLen32 25 /* BurstLength32 for 64-bit mode (1-bits)
|
||||
0=disable (normal)
|
||||
1=enable (4 beat burst when width is 64-bits)*/
|
||||
|
||||
/*Dram Power*/
|
||||
#define NV_CKE_PDEN 30 /* CKE based power down mode (1-bits)
|
||||
0=disable
|
||||
1=enable*/
|
||||
#define NV_CKE_CTL 31 /* CKE based power down control (1-bits)
|
||||
0=per Channel control
|
||||
1=per Chip select control*/
|
||||
#define NV_CLKHZAltVidC3 32 /* Memclock tri-stating during C3 and Alt VID (1-bits)
|
||||
0=disable
|
||||
1=enable*/
|
||||
|
||||
/*Memory Map/Mgt.*/
|
||||
#define NV_BottomIO 40 /* Bottom of 32-bit IO space (8-bits)
|
||||
NV_BottomIO[7:0]=Addr[31:24]*/
|
||||
#define NV_BottomUMA 41 /* Bottom of shared graphics dram (8-bits)
|
||||
NV_BottomUMA[7:0]=Addr[31:24]*/
|
||||
#define NV_MemHole 42 /* Memory Hole Remapping (1-bits)
|
||||
0=disable
|
||||
1=enable */
|
||||
|
||||
/*ECC*/
|
||||
#define NV_ECC 50 /* Dram ECC enable*/
|
||||
#define NV_NBECC 52 /* ECC MCE enable*/
|
||||
#define NV_ChipKill 53 /* Chip-Kill ECC Mode enable*/
|
||||
#define NV_ECCRedir 54 /* Dram ECC Redirection enable*/
|
||||
#define NV_DramBKScrub 55 /* Dram ECC Background Scrubber CTL*/
|
||||
#define NV_L2BKScrub 56 /* L2 ECC Background Scrubber CTL*/
|
||||
#define NV_DCBKScrub 57 /* DCache ECC Background Scrubber CTL*/
|
||||
#define NV_CS_SpareCTL 58 /* Chip Select Spare Control bit 0:
|
||||
0=disable Spare
|
||||
1=enable Spare */
|
||||
/* Chip Select Spare Control bit 1-4:
|
||||
Reserved, must be zero*/
|
||||
#define NV_SyncOnUnEccEn 61 /* SyncOnUnEccEn control
|
||||
0=disable
|
||||
1=enable*/
|
||||
#define NV_Unganged 62
|
||||
|
||||
#define NV_ChannelIntlv 63 /* Channel Interleaving (3-bits)
|
||||
xx0b = disable
|
||||
yy1b = enable with DctSelIntLvAddr set to yyb */
|
||||
|
||||
|
||||
#ifndef MAX_NODES_SUPPORTED
|
||||
#define MAX_NODES_SUPPORTED 8
|
||||
#endif
|
||||
|
||||
#ifndef MAX_DIMMS_SUPPORTED
|
||||
#define MAX_DIMMS_SUPPORTED 8
|
||||
#endif
|
||||
|
||||
#ifndef MAX_CS_SUPPORTED
|
||||
#define MAX_CS_SUPPORTED 8
|
||||
#endif
|
||||
|
||||
#ifndef MCT_DIMM_SPARE_NO_WARM
|
||||
#define MCT_DIMM_SPARE_NO_WARM 0
|
||||
#endif
|
||||
|
||||
|
||||
u32 Get_NB32(u32 dev, u32 reg);
|
||||
void Set_NB32(u32 dev, u32 reg, u32 val);
|
||||
u32 Get_NB32_index(u32 dev, u32 index_reg, u32 index);
|
||||
void Set_NB32_index(u32 dev, u32 index_reg, u32 index, u32 data);
|
||||
u32 Get_NB32_index_wait(u32 dev, u32 index_reg, u32 index);
|
||||
void Set_NB32_index_wait(u32 dev, u32 index_reg, u32 index, u32 data);
|
||||
u32 OtherTiming_A_D(struct DCTStatStruc *pDCTstat, u32 val);
|
||||
void mct_ForceAutoPrecharge_D(struct DCTStatStruc *pDCTstat, u32 dct);
|
||||
u32 Modify_D3CMP(struct DCTStatStruc *pDCTstat, u32 dct, u32 value);
|
||||
u8 mct_checkNumberOfDqsRcvEn_1Pass(u8 pass);
|
||||
u32 SetupDqsPattern_1PassA(u8 Pass);
|
||||
u32 SetupDqsPattern_1PassB(u8 Pass);
|
||||
u8 mct_Get_Start_RcvrEnDly_1Pass(u8 Pass);
|
||||
u8 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, u8 RcvrEnDly, u8 RcvrEnDlyLimit, u8 Channel, u8 Receiver, u8 Pass);
|
||||
void CPUMemTyping_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA);
|
||||
u32 mctGetLogicalCPUID(u32 Node);
|
||||
u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA);
|
||||
void TrainReceiverEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA, u8 Pass);
|
||||
void mct_TrainDQSPos_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA);
|
||||
void mctSetEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA);
|
||||
void TrainMaxReadLatency_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA);
|
||||
void mct_EndDQSTraining_D(struct MCTStatStruc *pMCTstat,struct DCTStatStruc *pDCTstatA);
|
||||
void mct_SetRcvrEnDly_D(struct DCTStatStruc *pDCTstat, u8 RcvrEnDly, u8 FinalValue, u8 Channel, u8 Receiver, u32 dev, u32 index_reg, u8 Addl_Index, u8 Pass);
|
||||
void SetEccDQSRcvrEn_D(struct DCTStatStruc *pDCTstat, u8 Channel);
|
||||
void mctGet_PS_Cfg_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u32 dct);
|
||||
void InterleaveBanks_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct);
|
||||
void mct_SetDramConfigHi_D(struct DCTStatStruc *pDCTstat, u32 dct, u32 DramConfigHi);
|
||||
void mct_DramInit_Hw_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct);
|
||||
void SyncSetting(struct DCTStatStruc *pDCTstat);
|
||||
void mct_SetClToNB_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat);
|
||||
void mct_SetWbEnhWsbDis_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat);
|
||||
void mct_TrainRcvrEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 Pass);
|
||||
void mct_EnableDimmEccEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 _DisableDramECC);
|
||||
u32 procOdtWorkaround(struct DCTStatStruc *pDCTstat, u32 dct, u32 val);
|
||||
void mct_BeforeDramInit_D(struct DCTStatStruc *pDCTstat, u32 dct);
|
||||
void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node);
|
||||
void mctSMBhub_Init(u32 node);
|
||||
int mctRead_SPD(u32 smaddr, u32 reg);
|
||||
void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA);
|
||||
void InterleaveChannels_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA);
|
||||
void mct_BeforeDQSTrain_Samp_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat);
|
||||
static void StoreDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 ChipSel);
|
||||
void phyAssistedMemFnceTraining(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA);
|
||||
u8 mct_SaveRcvEnDly_D_1Pass(struct DCTStatStruc *pDCTstat, u8 pass);
|
||||
static void mct_AdjustScrub_D(struct DCTStatStruc *pDCTstat, u16 *scrub_request);
|
||||
static u8 mct_InitReceiver_D(struct DCTStatStruc *pDCTstat, u8 dct);
|
||||
static void mct_Wait_10ns (u32 cycles);
|
||||
u8 mct_RcvrRankEnabled_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 Channel, u8 ChipSel);
|
||||
u32 mct_GetRcvrSysAddr_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 channel, u8 receiver, u8 *valid);
|
||||
void mct_Read1LTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u32 addr);
|
||||
#endif
|
||||
388
src/northbridge/amd/amdmct/mct/mct_d_gcc.h
Normal file
388
src/northbridge/amd/amdmct/mct/mct_d_gcc.h
Normal file
@ -0,0 +1,388 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
|
||||
static inline void _WRMSR(u32 addr, u32 lo, u32 hi)
|
||||
{
|
||||
__asm__ volatile (
|
||||
"wrmsr"
|
||||
:
|
||||
:"c"(addr),"a"(lo), "d" (hi)
|
||||
);
|
||||
}
|
||||
|
||||
|
||||
static inline void _RDMSR(u32 addr, u32 *lo, u32 *hi)
|
||||
{
|
||||
__asm__ volatile (
|
||||
"rdmsr"
|
||||
:"=a"(*lo), "=d" (*hi)
|
||||
:"c"(addr)
|
||||
);
|
||||
}
|
||||
|
||||
|
||||
static inline void _RDTSC(u32 *lo, u32 *hi)
|
||||
{
|
||||
__asm__ volatile (
|
||||
"rdtsc"
|
||||
: "=a" (*lo), "=d"(*hi)
|
||||
);
|
||||
}
|
||||
|
||||
|
||||
static inline void _cpu_id(u32 addr, u32 *val)
|
||||
{
|
||||
__asm__ volatile(
|
||||
"cpuid"
|
||||
: "=a" (val[0]),
|
||||
"=b" (val[1]),
|
||||
"=c" (val[2]),
|
||||
"=d" (val[3])
|
||||
: "0" (addr));
|
||||
|
||||
}
|
||||
|
||||
|
||||
static inline u32 bsr(u32 x)
|
||||
{
|
||||
u8 i;
|
||||
u32 ret = 0;
|
||||
|
||||
for(i=31; i>0; i--) {
|
||||
if(x & (1<<i)) {
|
||||
ret = i;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
|
||||
}
|
||||
|
||||
|
||||
static inline u32 bsf(u32 x)
|
||||
{
|
||||
u8 i;
|
||||
u32 ret = 32;
|
||||
|
||||
for(i=0; i<32; i++) {
|
||||
if(x & (1<<i)) {
|
||||
ret = i;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#define _MFENCE asm volatile ( "mfence")
|
||||
|
||||
#define _SFENCE asm volatile ( "sfence" )
|
||||
|
||||
/* prevent speculative execution of following instructions */
|
||||
#define _EXECFENCE asm volatile ("outb %al, $0xed")
|
||||
|
||||
static inline u32 read_cr4(void)
|
||||
{
|
||||
u32 cr4;
|
||||
__asm__ volatile ("movl %%cr4, %0" : "=r" (cr4));
|
||||
return cr4;
|
||||
}
|
||||
|
||||
|
||||
static inline void write_cr4(u32 cr4)
|
||||
{
|
||||
__asm__ volatile ("movl %0, %%cr4" : : "r" (cr4));
|
||||
}
|
||||
|
||||
|
||||
u32 SetUpperFSbase(u32 addr_hi);
|
||||
|
||||
|
||||
static void proc_CLFLUSH(u32 addr_hi)
|
||||
{
|
||||
SetUpperFSbase(addr_hi);
|
||||
|
||||
__asm__ volatile (
|
||||
/* clflush fs:[eax] */
|
||||
"outb %%al, $0xed\n\t" /* _EXECFENCE */
|
||||
"clflush %%fs:(%0)\n\t"
|
||||
"mfence\n\t"
|
||||
::"a" (addr_hi<<8)
|
||||
);
|
||||
}
|
||||
|
||||
|
||||
static void WriteLNTestPattern(u32 addr_lo, u8 *buf_a, u32 line_num)
|
||||
{
|
||||
__asm__ volatile (
|
||||
/*prevent speculative execution of following instructions*/
|
||||
/* FIXME: needed ? */
|
||||
"outb %%al, $0xed\n\t" /* _EXECFENCE */
|
||||
"1:\n\t"
|
||||
"movdqa (%3), %%xmm0\n\t"
|
||||
"movntdq %%xmm0, %%fs:(%0)\n\t" /* xmm0 is 128 bit */
|
||||
"addl %1, %0\n\t"
|
||||
"addl %1, %3\n\t"
|
||||
"loop 1b\n\t"
|
||||
"mfence\n\t"
|
||||
|
||||
:: "a" (addr_lo), "d" (16), "c" (line_num * 4), "b"(buf_a)
|
||||
);
|
||||
|
||||
}
|
||||
|
||||
|
||||
u32 read32_fs(u32 addr_lo)
|
||||
{
|
||||
u32 value;
|
||||
__asm__ volatile (
|
||||
"outb %%al, $0xed\n\t" /* _EXECFENCE */
|
||||
"movl %%fs:(%1), %0\n\t"
|
||||
:"=b"(value): "a" (addr_lo)
|
||||
);
|
||||
return value;
|
||||
}
|
||||
|
||||
|
||||
u8 read8_fs(u32 addr_lo)
|
||||
{
|
||||
u8 byte;
|
||||
__asm__ volatile (
|
||||
"outb %%al, $0xed\n\t" /* _EXECFENCE */
|
||||
"movb %%fs:(%1), %b0\n\t"
|
||||
"mfence\n\t"
|
||||
:"=b"(byte): "a" (addr_lo)
|
||||
);
|
||||
return byte;
|
||||
}
|
||||
|
||||
|
||||
static void FlushDQSTestPattern_L9(u32 addr_lo)
|
||||
{
|
||||
__asm__ volatile (
|
||||
"outb %%al, $0xed\n\t" /* _EXECFENCE */
|
||||
"clflush %%fs:-128(%%ecx)\n\t"
|
||||
"clflush %%fs:-64(%%ecx)\n\t"
|
||||
"clflush %%fs:(%%ecx)\n\t"
|
||||
"clflush %%fs:64(%%ecx)\n\t"
|
||||
|
||||
"clflush %%fs:-128(%%eax)\n\t"
|
||||
"clflush %%fs:-64(%%eax)\n\t"
|
||||
"clflush %%fs:(%%eax)\n\t"
|
||||
"clflush %%fs:64(%%eax)\n\t"
|
||||
|
||||
"clflush %%fs:-128(%%ebx)\n\t"
|
||||
|
||||
:: "b" (addr_lo+128+8*64), "c"(addr_lo+128),
|
||||
"a"(addr_lo+128+4*64)
|
||||
);
|
||||
|
||||
}
|
||||
|
||||
|
||||
static __attribute__((noinline)) void FlushDQSTestPattern_L18(u32 addr_lo)
|
||||
{
|
||||
__asm__ volatile (
|
||||
"outb %%al, $0xed\n\t" /* _EXECFENCE */
|
||||
"clflush %%fs:-128(%%eax)\n\t"
|
||||
"clflush %%fs:-64(%%eax)\n\t"
|
||||
"clflush %%fs:(%%eax)\n\t"
|
||||
"clflush %%fs:64(%%eax)\n\t"
|
||||
|
||||
"clflush %%fs:-128(%%edi)\n\t"
|
||||
"clflush %%fs:-64(%%edi)\n\t"
|
||||
"clflush %%fs:(%%edi)\n\t"
|
||||
"clflush %%fs:64(%%edi)\n\t"
|
||||
|
||||
"clflush %%fs:-128(%%ebx)\n\t"
|
||||
"clflush %%fs:-64(%%ebx)\n\t"
|
||||
"clflush %%fs:(%%ebx)\n\t"
|
||||
"clflush %%fs:64(%%ebx)\n\t"
|
||||
|
||||
"clflush %%fs:-128(%%ecx)\n\t"
|
||||
"clflush %%fs:-64(%%ecx)\n\t"
|
||||
"clflush %%fs:(%%ecx)\n\t"
|
||||
"clflush %%fs:64(%%ecx)\n\t"
|
||||
|
||||
"clflush %%fs:-128(%%edx)\n\t"
|
||||
"clflush %%fs:-64(%%edx)\n\t"
|
||||
|
||||
:: "b" (addr_lo+128+8*64), "c" (addr_lo+128+12*64),
|
||||
"d" (addr_lo +128+16*64), "a"(addr_lo+128),
|
||||
"D"(addr_lo+128+4*64)
|
||||
);
|
||||
}
|
||||
|
||||
|
||||
static void ReadL18TestPattern(u32 addr_lo)
|
||||
{
|
||||
// set fs and use fs prefix to access the mem
|
||||
__asm__ volatile (
|
||||
"outb %%al, $0xed\n\t" /* _EXECFENCE */
|
||||
"movl %%fs:-128(%%esi), %%eax\n\t" //TestAddr cache line
|
||||
"movl %%fs:-64(%%esi), %%eax\n\t" //+1
|
||||
"movl %%fs:(%%esi), %%eax\n\t" //+2
|
||||
"movl %%fs:64(%%esi), %%eax\n\t" //+3
|
||||
|
||||
"movl %%fs:-128(%%edi), %%eax\n\t" //+4
|
||||
"movl %%fs:-64(%%edi), %%eax\n\t" //+5
|
||||
"movl %%fs:(%%edi), %%eax\n\t" //+6
|
||||
"movl %%fs:64(%%edi), %%eax\n\t" //+7
|
||||
|
||||
"movl %%fs:-128(%%ebx), %%eax\n\t" //+8
|
||||
"movl %%fs:-64(%%ebx), %%eax\n\t" //+9
|
||||
"movl %%fs:(%%ebx), %%eax\n\t" //+10
|
||||
"movl %%fs:64(%%ebx), %%eax\n\t" //+11
|
||||
|
||||
"movl %%fs:-128(%%ecx), %%eax\n\t" //+12
|
||||
"movl %%fs:-64(%%ecx), %%eax\n\t" //+13
|
||||
"movl %%fs:(%%ecx), %%eax\n\t" //+14
|
||||
"movl %%fs:64(%%ecx), %%eax\n\t" //+15
|
||||
|
||||
"movl %%fs:-128(%%edx), %%eax\n\t" //+16
|
||||
"movl %%fs:-64(%%edx), %%eax\n\t" //+17
|
||||
"mfence\n\t"
|
||||
|
||||
:: "a"(0), "b" (addr_lo+128+8*64), "c" (addr_lo+128+12*64),
|
||||
"d" (addr_lo +128+16*64), "S"(addr_lo+128),
|
||||
"D"(addr_lo+128+4*64)
|
||||
);
|
||||
|
||||
}
|
||||
|
||||
|
||||
static void ReadL9TestPattern(u32 addr_lo)
|
||||
{
|
||||
|
||||
// set fs and use fs prefix to access the mem
|
||||
__asm__ volatile (
|
||||
"outb %%al, $0xed\n\t" /* _EXECFENCE */
|
||||
|
||||
"movl %%fs:-128(%%ecx), %%eax\n\t" //TestAddr cache line
|
||||
"movl %%fs:-64(%%ecx), %%eax\n\t" //+1
|
||||
"movl %%fs:(%%ecx), %%eax\n\t" //+2
|
||||
"movl %%fs:64(%%ecx), %%eax\n\t" //+3
|
||||
|
||||
"movl %%fs:-128(%%edx), %%eax\n\t" //+4
|
||||
"movl %%fs:-64(%%edx), %%eax\n\t" //+5
|
||||
"movl %%fs:(%%edx), %%eax\n\t" //+6
|
||||
"movl %%fs:64(%%edx), %%eax\n\t" //+7
|
||||
|
||||
"movl %%fs:-128(%%ebx), %%eax\n\t" //+8
|
||||
"mfence\n\t"
|
||||
|
||||
:: "a"(0), "b" (addr_lo+128+8*64), "c"(addr_lo+128),
|
||||
"d"(addr_lo+128+4*64)
|
||||
);
|
||||
|
||||
}
|
||||
|
||||
|
||||
static void ReadMaxRdLat1CLTestPattern_D(u32 addr)
|
||||
{
|
||||
SetUpperFSbase(addr);
|
||||
|
||||
__asm__ volatile (
|
||||
"outb %%al, $0xed\n\t" /* _EXECFENCE */
|
||||
"movl %%fs:-128(%%esi), %%eax\n\t" //TestAddr cache line
|
||||
"movl %%fs:-64(%%esi), %%eax\n\t" //+1
|
||||
"movl %%fs:(%%esi), %%eax\n\t" //+2
|
||||
"mfence\n\t"
|
||||
:: "a"(0), "S"((addr<<8)+128)
|
||||
);
|
||||
|
||||
}
|
||||
|
||||
|
||||
void WriteMaxRdLat1CLTestPattern_D(u32 buf, u32 addr)
|
||||
{
|
||||
SetUpperFSbase(addr);
|
||||
|
||||
__asm__ volatile (
|
||||
"outb %%al, $0xed\n\t" /* _EXECFENCE */
|
||||
"1:\n\t"
|
||||
"movdqa (%3), %%xmm0\n\t"
|
||||
"movntdq %%xmm0, %%fs:(%0)\n\t" /* xmm0 is 128 bit */
|
||||
"addl %1, %0\n\t"
|
||||
"addl %1, %3\n\t"
|
||||
"loop 1b\n\t"
|
||||
"mfence\n\t"
|
||||
|
||||
:: "a" (addr<<8), "d" (16), "c" (3 * 4), "b"(buf)
|
||||
);
|
||||
}
|
||||
|
||||
|
||||
static void FlushMaxRdLatTestPattern_D(u32 addr)
|
||||
{
|
||||
/* Flush a pattern of 72 bit times (per DQ) from cache.
|
||||
* This procedure is used to ensure cache miss on the next read training.
|
||||
*/
|
||||
|
||||
SetUpperFSbase(addr);
|
||||
|
||||
__asm__ volatile (
|
||||
"outb %%al, $0xed\n\t" /* _EXECFENCE */
|
||||
"clflush %%fs:-128(%%esi)\n\t" //TestAddr cache line
|
||||
"clflush %%fs:-64(%%esi)\n\t" //+1
|
||||
"clflush %%fs:(%%esi)\n\t" //+2
|
||||
"mfence\n\t"
|
||||
|
||||
:: "S"((addr<<8)+128)
|
||||
);
|
||||
}
|
||||
|
||||
|
||||
u32 stream_to_int(u8 *p)
|
||||
{
|
||||
int i;
|
||||
u32 val;
|
||||
u32 valx;
|
||||
|
||||
val = 0;
|
||||
|
||||
for(i=3; i>=0; i--) {
|
||||
val <<= 8;
|
||||
valx = *(p+i);
|
||||
val |= valx;
|
||||
}
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
|
||||
void oemSet_NB32(u32 addr, u32 val, u8 *valid)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
u32 oemGet_NB32(u32 addr, u8 *valid)
|
||||
{
|
||||
*valid = 0;
|
||||
return 0xffffffff;
|
||||
}
|
||||
|
||||
|
||||
u8 oemNodePresent_D(u8 Node, u8 *ret)
|
||||
{
|
||||
*ret = 0;
|
||||
return 0;
|
||||
}
|
||||
25
src/northbridge/amd/amdmct/mct/mct_fd.c
Normal file
25
src/northbridge/amd/amdmct/mct/mct_fd.c
Normal file
@ -0,0 +1,25 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
|
||||
|
||||
u8 amd_FD_support(void)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
206
src/northbridge/amd/amdmct/mct/mctardk3.c
Normal file
206
src/northbridge/amd/amdmct/mct/mctardk3.c
Normal file
@ -0,0 +1,206 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 021100xFF301 USA
|
||||
*/
|
||||
|
||||
|
||||
static void Get_ChannelPS_Cfg0_D( u8 MAAdimms, u8 Speed, u8 MAAload,
|
||||
u8 DATAAload, u32 *AddrTmgCTL, u32 *ODC_CTL);
|
||||
|
||||
|
||||
void mctGet_PS_Cfg_D(struct MCTStatStruc *pMCTstat,
|
||||
struct DCTStatStruc *pDCTstat, u32 dct)
|
||||
{
|
||||
u16 val, valx;
|
||||
|
||||
print_tx("dct: ", dct);
|
||||
print_tx("Speed: ", pDCTstat->Speed);
|
||||
|
||||
Get_ChannelPS_Cfg0_D(pDCTstat->MAdimms[dct], pDCTstat->Speed,
|
||||
pDCTstat->MAload[dct], pDCTstat->DATAload[dct],
|
||||
&(pDCTstat->CH_ADDR_TMG[dct]), &(pDCTstat->CH_ODC_CTL[dct]));
|
||||
|
||||
|
||||
if(pDCTstat->MAdimms[dct] == 1)
|
||||
pDCTstat->CH_ODC_CTL[dct] |= 0x20000000; /* 75ohms */
|
||||
else
|
||||
pDCTstat->CH_ODC_CTL[dct] |= 0x10000000; /* 150ohms */
|
||||
|
||||
pDCTstat->_2Tmode = 1;
|
||||
|
||||
/* use byte lane 4 delay for ECC lane */
|
||||
pDCTstat->CH_EccDQSLike[0] = 0x0504;
|
||||
pDCTstat->CH_EccDQSScale[0] = 0; /* 100% byte lane 4 */
|
||||
pDCTstat->CH_EccDQSLike[1] = 0x0504;
|
||||
pDCTstat->CH_EccDQSScale[1] = 0; /* 100% byte lane 4 */
|
||||
|
||||
|
||||
/*
|
||||
Overrides and/or exceptions
|
||||
*/
|
||||
|
||||
/* 1) QRx4 needs to adjust CS/ODT setup time */
|
||||
// FIXME: Add Ax support?
|
||||
if (mctGet_NVbits(NV_MAX_DIMMS) == 4) {
|
||||
if (pDCTstat->DimmQRPresent != 0) {
|
||||
pDCTstat->CH_ADDR_TMG[dct] &= 0xFF00FFFF;
|
||||
pDCTstat->CH_ADDR_TMG[dct] |= 0x00000000;
|
||||
if (pDCTstat->MAdimms[dct] == 4) {
|
||||
pDCTstat->CH_ADDR_TMG[dct] &= 0xFF00FFFF;
|
||||
pDCTstat->CH_ADDR_TMG[dct] |= 0x002F0000;
|
||||
if (pDCTstat->Speed == 3 || pDCTstat->Speed == 4) {
|
||||
pDCTstat->CH_ADDR_TMG[dct] &= 0xFF00FFFF;
|
||||
pDCTstat->CH_ADDR_TMG[dct] |= 0x00002F00;
|
||||
if (pDCTstat->MAdimms[dct] == 4)
|
||||
pDCTstat->CH_ODC_CTL[dct] = 0x00331222;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* 2) DRx4 (R/C-J) @ DDR667 needs to adjust CS/ODT setup time */
|
||||
if (pDCTstat->Speed == 3 || pDCTstat->Speed == 4) {
|
||||
val = pDCTstat->Dimmx4Present;
|
||||
if (dct == 0) {
|
||||
val &= 0x55;
|
||||
} else {
|
||||
val &= 0xAA;
|
||||
val >>= 1;
|
||||
}
|
||||
val &= pDCTstat->DIMMValid;
|
||||
if (val) {
|
||||
//FIXME: skip for Ax
|
||||
valx = pDCTstat->DimmDRPresent;
|
||||
if (dct == 0) {
|
||||
valx &= 0x55;
|
||||
} else {
|
||||
valx &= 0xAA;
|
||||
valx >>= 1;
|
||||
}
|
||||
if (mctGet_NVbits(NV_MAX_DIMMS) == 8) {
|
||||
val &= valx;
|
||||
if (val != 0) {
|
||||
pDCTstat->CH_ADDR_TMG[dct] &= 0xFFFF00FF;
|
||||
pDCTstat->CH_ADDR_TMG[dct] |= 0x00002F00;
|
||||
}
|
||||
} else {
|
||||
val &= valx;
|
||||
if (val != 0) {
|
||||
if (pDCTstat->Speed == 3 || pDCTstat->Speed == 3) {
|
||||
pDCTstat->CH_ADDR_TMG[dct] &= 0xFFFF00FF;
|
||||
pDCTstat->CH_ADDR_TMG[dct] |= 0x00002F00;
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
pDCTstat->CH_ODC_CTL[dct] = procOdtWorkaround(pDCTstat, dct, pDCTstat->CH_ODC_CTL[dct]);
|
||||
|
||||
print_tx("CH_ODC_CTL: ", pDCTstat->CH_ODC_CTL[dct]);
|
||||
print_tx("CH_ADDR_TMG: ", pDCTstat->CH_ADDR_TMG[dct]);
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
/*===============================================================================
|
||||
* Vendor is responsible for correct settings.
|
||||
* M2/Unbuffered 4 Slot - AMD Design Guideline.
|
||||
*===============================================================================
|
||||
* #1, BYTE, Speed (DCTStatstruc.Speed) (Secondary Key)
|
||||
* #2, BYTE, number of Address bus loads on the Channel. (Tershery Key)
|
||||
* These must be listed in ascending order.
|
||||
* FFh (0xFE) has special meanying of 'any', and must be listed first for each speed grade.
|
||||
* #3, DWORD, Address Timing Control Register Value
|
||||
* #4, DWORD, Output Driver Compensation Control Register Value
|
||||
* #5, BYTE, Number of DIMMs (Primary Key)
|
||||
*/
|
||||
static const u8 Table_ATC_ODC_8D_D[] = {
|
||||
0xFE, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x22, 0x12, 0x11, 0x00, 1,
|
||||
0xFE, 0xFF, 0x00, 0x00, 0x37, 0x00, 0x22, 0x12, 0x11, 0x00, 2,
|
||||
1, 0xFF, 0x00, 0x00, 0x2F, 0x00, 0x22, 0x12, 0x11, 0x00, 3,
|
||||
2, 0xFF, 0x00, 0x00, 0x2F, 0x00, 0x22, 0x12, 0x11, 0x00, 3,
|
||||
3, 0xFF, 0x2F, 0x00, 0x2F, 0x00, 0x22, 0x12, 0x11, 0x00, 3,
|
||||
4, 0xFF, 0x2F, 0x00, 0x2F, 0x00, 0x22, 0x12, 0x33, 0x00, 3,
|
||||
1, 0xFF, 0x00, 0x00, 0x2F, 0x00, 0x22, 0x12, 0x11, 0x00, 4,
|
||||
2, 0xFF, 0x00, 0x00, 0x2F, 0x00, 0x22, 0x12, 0x11, 0x00, 4,
|
||||
3, 0xFF, 0x2F, 0x00, 0x2F, 0x00, 0x22, 0x12, 0x33, 0x00, 4,
|
||||
4, 0xFF, 0x2F, 0x00, 0x2F, 0x00, 0x22, 0x12, 0x33, 0x00, 4,
|
||||
0xFF
|
||||
};
|
||||
|
||||
static const u8 Table_ATC_ODC_4D_D[] = {
|
||||
0xFE, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x22, 0x12, 0x11, 0x00, 1,
|
||||
0xFE, 0xFF, 0x00, 0x00, 0x37, 0x00, 0x22, 0x12, 0x11, 0x00, 2,
|
||||
0xFE, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x22, 0x12, 0x11, 0x00, 3,
|
||||
0xFE, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x22, 0x12, 0x11, 0x00, 4,
|
||||
0xFF
|
||||
};
|
||||
|
||||
static const u8 Table_ATC_ODC_8D_D_Ax[] = {
|
||||
1,0xff,0x00,0x00,0x2F,0x0,0x22,0x12,0x11,0x00, 0xFE,
|
||||
2,0xff,0x00,0x00,0x2C,0x0,0x22,0x12,0x11,0x00, 0xFE,
|
||||
3,0xff,0x00,0x00,0x2C,0x0,0x22,0x12,0x11,0x00, 0xFE,
|
||||
4,0xff,0x00,0x33,0x2F,0x0,0x22,0x12,0x11,0x00, 0xFE,
|
||||
0xFF
|
||||
};
|
||||
|
||||
static const u8 Table_ATC_ODC_4D_D_Ax[] = {
|
||||
1,0xff,0x00,0x00,0x2F,0x00,0x22,0x12,0x11,0x00, 0xFE,
|
||||
2,0xff,0x00,0x2C,0x2C,0x00,0x22,0x12,0x11,0x00, 0xFE,
|
||||
3,0xff,0x00,0x00,0x2C,0x00,0x22,0x12,0x11,0x00, 0xFE,
|
||||
4,0xff,0x00,0x33,0x2F,0x00,0x22,0x12,0x11,0x00, 0xFE,
|
||||
0xFF
|
||||
};
|
||||
|
||||
|
||||
static void Get_ChannelPS_Cfg0_D(u8 MAAdimms, u8 Speed, u8 MAAload,
|
||||
u8 DATAAload, u32 *AddrTmgCTL, u32 *ODC_CTL)
|
||||
{
|
||||
const u8 *p;
|
||||
|
||||
*AddrTmgCTL = 0;
|
||||
*ODC_CTL = 0;
|
||||
|
||||
if(mctGet_NVbits(NV_MAX_DIMMS) == 8) {
|
||||
/* 8 DIMM Table */
|
||||
p = Table_ATC_ODC_8D_D;
|
||||
//FIXME Add Ax support
|
||||
} else {
|
||||
/* 4 DIMM Table*/
|
||||
p = Table_ATC_ODC_4D_D;
|
||||
//FIXME Add Ax support
|
||||
}
|
||||
|
||||
while (*p != 0xFF) {
|
||||
if ((MAAdimms == *(p+10)) || (*(p+10 ) == 0xFE)) {
|
||||
if((*p == Speed) || (*p == 0xFE)) {
|
||||
if(MAAload <= *(p+1)) {
|
||||
*AddrTmgCTL = stream_to_int((u8*)(p+2));
|
||||
*ODC_CTL = stream_to_int((u8*)(p+6));
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
p+=11;
|
||||
}
|
||||
}
|
||||
|
||||
172
src/northbridge/amd/amdmct/mct/mctardk4.c
Normal file
172
src/northbridge/amd/amdmct/mct/mctardk4.c
Normal file
@ -0,0 +1,172 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
|
||||
static void Get_ChannelPS_Cfg0_D( u8 MAAdimms, u8 Speed, u8 MAAload,
|
||||
u8 DATAAload, u32 *AddrTmgCTL, u32 *ODC_CTL,
|
||||
u32 *CMDmode);
|
||||
|
||||
|
||||
void mctGet_PS_Cfg_D(struct MCTStatStruc *pMCTstat,
|
||||
struct DCTStatStruc *pDCTstat, u32 dct)
|
||||
|
||||
print_tx("dct: ", dct);
|
||||
print_tx("Speed: ", pDCTstat->Speed);
|
||||
|
||||
Get_ChannelPS_Cfg0_D(pDCTstat->MAdimms[dct], pDCTstat->Speed,
|
||||
pDCTstat->MAload[dct], pDCTstat->DATAload[dct],
|
||||
&(pDCTstat->CH_ADDR_TMG[dct]), &(pDCTstat->CH_ODC_CTL[dct]),
|
||||
&pDCTstat->_2Tmode);
|
||||
|
||||
// print_tx("1 CH_ODC_CTL: ", pDCTstat->CH_ODC_CTL[dct]);
|
||||
// print_tx("1 CH_ADDR_TMG: ", pDCTstat->CH_ADDR_TMG[dct]);
|
||||
|
||||
if(pDCTstat->MAdimms[dct] == 1)
|
||||
pDCTstat->CH_ODC_CTL[dct] |= 0x20000000; /* 75ohms */
|
||||
else
|
||||
pDCTstat->CH_ODC_CTL[dct] |= 0x10000000; /* 150ohms */
|
||||
|
||||
|
||||
/*
|
||||
* Overrides and/or workarounds
|
||||
*/
|
||||
pDCTstat->CH_ODC_CTL[dct] = procOdtWorkaround(pDCTstat, dct, pDCTstat->CH_ODC_CTL[dct]);
|
||||
|
||||
print_tx("4 CH_ODC_CTL: ", pDCTstat->CH_ODC_CTL[dct]);
|
||||
print_tx("4 CH_ADDR_TMG: ", pDCTstat->CH_ADDR_TMG[dct]);
|
||||
}
|
||||
|
||||
/*=============================================================================
|
||||
* Vendor is responsible for correct settings.
|
||||
* M2/Unbuffered 4 Slot - AMD Design Guideline.
|
||||
*=============================================================================
|
||||
* #1, BYTE, Speed (DCTStatstruc.Speed)
|
||||
* #2, BYTE, number of Address bus loads on the Channel.
|
||||
* These must be listed in ascending order.
|
||||
* FFh (-1) has special meanying of 'any', and must be listed first for
|
||||
* each speed grade.
|
||||
* #3, DWORD, Address Timing Control Register Value
|
||||
* #4, DWORD, Output Driver Compensation Control Register Value
|
||||
*/
|
||||
|
||||
static const u8 Table_ATC_ODC_D_Bx[] = {
|
||||
1, 0xFF, 0x00, 0x2F, 0x2F, 0x0, 0x22, 0x13, 0x11, 0x0
|
||||
2, 12, 0x00, 0x2F, 0x2F, 0x0, 0x22, 0x13, 0x11, 0x0
|
||||
2, 16, 0x00, 0x2F, 0x00, 0x0, 0x22, 0x13, 0x11, 0x0
|
||||
2, 20, 0x00, 0x2F, 0x38, 0x0, 0x22, 0x13, 0x11, 0x0
|
||||
2, 24, 0x00, 0x2F, 0x37, 0x0, 0x22, 0x13, 0x11, 0x0
|
||||
2, 32, 0x00, 0x2F, 0x34, 0x0, 0x22, 0x13, 0x11, 0x0
|
||||
3, 12, 0x20, 0x22, 0x20, 0x0, 0x22, 0x13, 0x11, 0x0
|
||||
3, 16, 0x20, 0x22, 0x30, 0x0, 0x22, 0x13, 0x11, 0x0
|
||||
3, 20, 0x20, 0x22, 0x2C, 0x0, 0x22, 0x13, 0x11, 0x0
|
||||
3, 24, 0x20, 0x22, 0x2A, 0x0, 0x22, 0x13, 0x11, 0x0
|
||||
3, 32, 0x20, 0x22, 0x2B, 0x0, 0x22, 0x13, 0x11, 0x0
|
||||
4, 0xFF, 0x20, 0x25, 0x20, 0x0, 0x22, 0x33, 0x11, 0x0
|
||||
5, 0xFF, 0x20, 0x20, 0x2F, 0x0, 0x22, 0x32, 0x11, 0x0
|
||||
0FFh
|
||||
|
||||
static const u8 Table_ATC_ODC_D_Ax[] = {
|
||||
1, 0xFF, 0x00, 0x2F, 0x2F, 0x0, 0x22, 0x13, 0x11, 0x0
|
||||
2, 12, 0x00, 0x2F, 0x2F, 0x0, 0x22, 0x13, 0x11, 0x0
|
||||
2, 16, 0x00, 0x2F, 0x00, 0x0, 0x22, 0x13, 0x11, 0x0
|
||||
2, 20, 0x00, 0x2F, 0x38, 0x0, 0x22, 0x13, 0x11, 0x0
|
||||
2, 24, 0x00, 0x2F, 0x37, 0x0, 0x22, 0x13, 0x11, 0x0
|
||||
2, 32, 0x00, 0x2F, 0x34, 0x0, 0x22, 0x13, 0x11, 0x0
|
||||
3, 12, 0x20, 0x22, 0x20, 0x0, 0x22, 0x13, 0x11, 0x0
|
||||
3, 16, 0x20, 0x22, 0x30, 0x0, 0x22, 0x13, 0x11, 0x0
|
||||
3, 20, 0x20, 0x22, 0x2C, 0x0, 0x22, 0x13, 0x11, 0x0
|
||||
3, 24, 0x20, 0x22, 0x2A, 0x0, 0x22, 0x13, 0x11, 0x0
|
||||
3, 32, 0x20, 0x22, 0x2B, 0x0, 0x22, 0x13, 0x11, 0x0
|
||||
4, 0xFF, 0x20, 0x25, 0x20, 0x0, 0x22, 0x33, 0x11, 0x0
|
||||
5, 0xFF, 0x20, 0x20, 0x2F, 0x0, 0x22, 0x32, 0x11, 0x0
|
||||
0xFF
|
||||
};
|
||||
|
||||
|
||||
static void Get_ChannelPS_Cfg0_D( u8 MAAdimms, u8 Speed, u8 MAAload,
|
||||
u8 DATAAload, u32 *AddrTmgCTL, u32 *ODC_CTL,
|
||||
u32 *CMDmode);
|
||||
{
|
||||
u8 *p;
|
||||
|
||||
*AddrTmgCTL = 0;
|
||||
*ODC_CTL = 0;
|
||||
*CMDmode = 1;
|
||||
|
||||
// FIXME: add Ax support
|
||||
if(MAAdimms == 0) {
|
||||
*ODC_CTL = 0x00111222;
|
||||
if(Speed == 3)
|
||||
*AddrTmgCTL = 0x00202220;
|
||||
else if (Speed == 2)
|
||||
*AddrTmgCTL = 0x002F2F00;
|
||||
else if (Speed == 1)
|
||||
*AddrTmgCTL = 0x002F2F00;
|
||||
else if (Speed == 4)
|
||||
*AddrTmgCTL = 0x00202520;
|
||||
else if (Speed == 4)
|
||||
*AddrTmgCTL = 0x002F2020;
|
||||
else
|
||||
*AddrTmgCTL = 0x002F2F2F;
|
||||
} else if(MAAdimms == 1) {
|
||||
if(Speed == 4) {
|
||||
*CMDmode = 2;
|
||||
*AddrTmgCTL = 0x00202520;
|
||||
*ODC_CTL = 0x00113222;
|
||||
} else if(Speed == 4) {
|
||||
*CMDmode = 2;
|
||||
*AddrTmgCTL = 0x002F2020;
|
||||
*ODC_CTL = 0x00113222;
|
||||
} else {
|
||||
*CMDmode = 1;
|
||||
*ODC_CTL = 0x00111222;
|
||||
if(Speed == 3) {
|
||||
*AddrTmgCTL = 0x00202220;
|
||||
} else if(Speed == 2) {
|
||||
if (MAAload == 4)
|
||||
*AddrTmgCTL = 0x002B2F00;
|
||||
else if (MAAload == 16)
|
||||
*AddrTmgCTL = 0x002B2F00;
|
||||
else if (MAAload == 8)
|
||||
*AddrTmgCTL = 0x002F2F00;
|
||||
else
|
||||
*AddrTmgCTL = 0x002F2F00;
|
||||
} else if(Speed == 1) {
|
||||
*AddrTmgCTL = 0x002F2F00;
|
||||
} else if(Speed == 5) {
|
||||
*AddrTmgCTL = 0x002F2020;
|
||||
} else {
|
||||
*AddrTmgCTL = 0x002F2F2F;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
*CMDmode = 2;
|
||||
p = Table_ATC_ODC_D_Bx;
|
||||
do {
|
||||
if(Speed == *p) {
|
||||
if(MAAload <= *(p+1)) {
|
||||
*AddrTmgCTL = stream_to_int(p+2);
|
||||
*ODC_CTL = stream_to_int(p+6);
|
||||
break;
|
||||
}
|
||||
}
|
||||
p+=10;
|
||||
} while (0xFF == *p);
|
||||
|
||||
}
|
||||
130
src/northbridge/amd/amdmct/mct/mctchi_d.c
Normal file
130
src/northbridge/amd/amdmct/mct/mctchi_d.c
Normal file
@ -0,0 +1,130 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
|
||||
|
||||
void InterleaveChannels_D(struct MCTStatStruc *pMCTstat,
|
||||
struct DCTStatStruc *pDCTstatA)
|
||||
{
|
||||
|
||||
u8 Node;
|
||||
u32 DramBase, DctSelBase;
|
||||
u8 DctSelIntLvAddr, DctSelHi;
|
||||
u8 HoleValid = 0;
|
||||
u32 HoleSize, HoleBase = 0;
|
||||
u32 val, tmp;
|
||||
u32 dct0_size, dct1_size;
|
||||
u8 enabled;
|
||||
struct DCTStatStruc *pDCTstat;
|
||||
|
||||
/* HoleValid - indicates whether the current Node contains hole.
|
||||
* HoleSize - indicates whether there is IO hole in the whole system
|
||||
* memory.
|
||||
*/
|
||||
|
||||
/* call back to wrapper not needed ManualChannelInterleave_D(); */
|
||||
/* call back - DctSelIntLvAddr = mctGet_NVbits(NV_ChannelIntlv);*/ /* override interleave */
|
||||
// FIXME: Check for Cx
|
||||
DctSelIntLvAddr = 5; /* use default: Enable channel interleave */
|
||||
enabled = 1; /* with Hash*: exclusive OR of address bits[20:16, 6]. */
|
||||
beforeInterleaveChannels_D(pDCTstatA, &enabled);
|
||||
|
||||
if (enabled) {
|
||||
DctSelIntLvAddr >>= 1;
|
||||
HoleSize = 0;
|
||||
if ((pMCTstat->GStatus & (1 << GSB_SoftHole)) ||
|
||||
(pMCTstat->GStatus & (1 << GSB_HWHole))) {
|
||||
if (pMCTstat->HoleBase) {
|
||||
HoleBase = pMCTstat->HoleBase >> 8;
|
||||
HoleSize = HoleBase & 0xFFFF0000;
|
||||
HoleSize |= ((~HoleBase) + 1) & 0xFFFF;
|
||||
}
|
||||
}
|
||||
Node = 0;
|
||||
while (Node < MAX_NODES_SUPPORTED) {
|
||||
pDCTstat = pDCTstatA + Node;
|
||||
val = Get_NB32(pDCTstat->dev_map, 0xF0);
|
||||
if (val & (1 << DramHoleValid))
|
||||
HoleValid = 1;
|
||||
if (!pDCTstat->GangedMode && pDCTstat->DIMMValidDCT[0] && pDCTstat->DIMMValidDCT[1]) {
|
||||
DramBase = pDCTstat->NodeSysBase >> 8;
|
||||
dct1_size = ((pDCTstat->NodeSysLimit) + 2) >> 8;
|
||||
dct0_size = Get_NB32(pDCTstat->dev_dct, 0x114);
|
||||
if (dct0_size >= 0x10000) {
|
||||
dct0_size -= HoleSize;
|
||||
}
|
||||
|
||||
dct0_size -= DramBase;
|
||||
dct1_size -= dct0_size;
|
||||
DctSelHi = 0x05; /* DctSelHiRngEn = 1, DctSelHi = 0 */
|
||||
if (dct1_size == dct0_size) {
|
||||
dct1_size = 0;
|
||||
DctSelHi = 0x04; /* DctSelHiRngEn = 0 */
|
||||
} else if (dct1_size > dct0_size ) {
|
||||
dct1_size = dct0_size;
|
||||
DctSelHi = 0x07; /* DctSelHiRngEn = 1, DctSelHi = 1 */
|
||||
}
|
||||
dct0_size = dct1_size;
|
||||
dct0_size += DramBase;
|
||||
dct0_size += dct1_size;
|
||||
if (dct0_size >= HoleBase) /* if DctSelBaseAddr > HoleBase */
|
||||
dct0_size += HoleBase;
|
||||
DctSelBase = dct0_size;
|
||||
|
||||
if (dct1_size == 0)
|
||||
dct0_size = 0;
|
||||
dct0_size -= dct1_size; /* DctSelBaseOffset = DctSelBaseAddr - Interleaved region */
|
||||
Set_NB32(pDCTstat->dev_dct, 0x114, dct0_size);
|
||||
|
||||
if (dct1_size == 0)
|
||||
dct1_size = DctSelBase;
|
||||
val = Get_NB32(pDCTstat->dev_dct, 0x110);
|
||||
val &= 0x7F8;
|
||||
val |= dct1_size;
|
||||
val |= DctSelHi;
|
||||
val |= (DctSelIntLvAddr << 6) & 0xFF;
|
||||
Set_NB32(pDCTstat->dev_dct, 0x110, val);
|
||||
print_tx("InterleaveChannels: DRAM Controller Select Low Register = ", val);
|
||||
|
||||
if (HoleValid) {
|
||||
tmp = DramBase;
|
||||
val = DctSelBase;
|
||||
if (val < HoleBase) { /* DctSelBaseAddr < DramHoleBase */
|
||||
val -= DramBase;
|
||||
val >>= 1;
|
||||
tmp += val;
|
||||
}
|
||||
tmp += HoleSize;
|
||||
val = Get_NB32(pDCTstat->dev_map, 0xF0); /* DramHoleOffset */
|
||||
val &= 0x7F;
|
||||
val |= (tmp & 0xFF);
|
||||
Set_NB32(pDCTstat->dev_map, 0xF0, val);
|
||||
print_tx("InterleaveChannels:0xF0 = ", val);
|
||||
|
||||
}
|
||||
}
|
||||
print_tx("InterleaveChannels_D: Node ", Node);
|
||||
print_tx("InterleaveChannels_D: Status ", pDCTstat->Status);
|
||||
print_tx("InterleaveChannels_D: ErrStatus ", pDCTstat->ErrStatus);
|
||||
print_tx("InterleaveChannels_D: ErrCode ", pDCTstat->ErrCode);
|
||||
Node++;
|
||||
}
|
||||
}
|
||||
print_t("InterleaveChannels_D: Done\n");
|
||||
}
|
||||
147
src/northbridge/amd/amdmct/mct/mctcsi_d.c
Normal file
147
src/northbridge/amd/amdmct/mct/mctcsi_d.c
Normal file
@ -0,0 +1,147 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
|
||||
/* Low swap bit vs bank size encoding (physical, not logical address bit)
|
||||
* ;To calculate the number by hand, add the number of Bank address bits
|
||||
* ;(2 or 3) to the number of column address bits, plus 3 (the logical
|
||||
* ;page size), and subtract 8.
|
||||
*/
|
||||
static const u8 Tab_int_D[] = { 6,7,7,8,8,8,8,8,9,9,8,9 };
|
||||
|
||||
void InterleaveBanks_D(struct MCTStatStruc *pMCTstat,
|
||||
struct DCTStatStruc *pDCTstat, u8 dct)
|
||||
{
|
||||
u8 ChipSel, EnChipSels;
|
||||
u32 AddrLoMask, AddrHiMask;
|
||||
u32 AddrLoMaskN, AddrHiMaskN, MemSize = 0;
|
||||
u8 DoIntlv, _CsIntCap;
|
||||
u32 BitDelta, BankEncd = 0;
|
||||
|
||||
u32 dev;
|
||||
u32 reg;
|
||||
u32 reg_off;
|
||||
u32 val;
|
||||
u32 val_lo, val_hi;
|
||||
|
||||
DoIntlv = mctGet_NVbits(NV_BankIntlv);
|
||||
_CsIntCap = 0;
|
||||
EnChipSels = 0;
|
||||
|
||||
dev = pDCTstat->dev_dct;
|
||||
reg_off = 0x100 * dct;
|
||||
|
||||
ChipSel = 0; /* Find out if current configuration is capable */
|
||||
while (DoIntlv && (ChipSel < MAX_CS_SUPPORTED)) {
|
||||
reg = 0x40+(ChipSel<<2) + reg_off; /* Dram CS Base 0 */
|
||||
val = Get_NB32(dev, reg);
|
||||
if ( val & (1<<CSEnable)) {
|
||||
EnChipSels++;
|
||||
reg = 0x60+((ChipSel>>1)<<2)+reg_off; /*Dram CS Mask 0 */
|
||||
val = Get_NB32(dev, reg);
|
||||
val >>= 19;
|
||||
val &= 0x3ff;
|
||||
val++;
|
||||
if (EnChipSels == 1)
|
||||
MemSize = val;
|
||||
else
|
||||
/*If mask sizes not same then skip */
|
||||
if (val != MemSize)
|
||||
break;
|
||||
reg = 0x80 + reg_off; /*Dram Bank Addressing */
|
||||
val = Get_NB32(dev, reg);
|
||||
val >>= (ChipSel>>1)<<2;
|
||||
val &= 0x0f;
|
||||
if(EnChipSels == 1)
|
||||
BankEncd = val;
|
||||
else
|
||||
/*If number of Rows/Columns not equal, skip */
|
||||
if (val != BankEncd)
|
||||
break;
|
||||
}
|
||||
ChipSel++;
|
||||
}
|
||||
if (ChipSel == MAX_CS_SUPPORTED) {
|
||||
if ((EnChipSels == 2) || (EnChipSels == 4) || (EnChipSels == 8))
|
||||
_CsIntCap = 1;
|
||||
}
|
||||
|
||||
if (DoIntlv) {
|
||||
if(!_CsIntCap) {
|
||||
pDCTstat->ErrStatus |= 1<<SB_BkIntDis;
|
||||
DoIntlv = 0;
|
||||
}
|
||||
}
|
||||
|
||||
if(DoIntlv) {
|
||||
val = Tab_int_D[BankEncd];
|
||||
if (pDCTstat->Status & (1<<SB_128bitmode))
|
||||
val++;
|
||||
|
||||
AddrLoMask = (EnChipSels - 1) << val;
|
||||
AddrLoMaskN = ~AddrLoMask;
|
||||
|
||||
val = bsf(MemSize) + 19;
|
||||
AddrHiMask = (EnChipSels -1) << val;
|
||||
AddrHiMaskN = ~AddrHiMask;
|
||||
|
||||
BitDelta = bsf(AddrHiMask) - bsf(AddrLoMask);
|
||||
|
||||
for (ChipSel = 0; ChipSel < MAX_CS_SUPPORTED; ChipSel++) {
|
||||
reg = 0x40+(ChipSel<<2) + reg_off; /*Dram CS Base 0 */
|
||||
val = Get_NB32(dev, reg);
|
||||
if (val & 3) {
|
||||
val_lo = val & AddrLoMask;
|
||||
val_hi = val & AddrHiMask;
|
||||
val &= AddrLoMaskN;
|
||||
val &= AddrHiMaskN;
|
||||
val_lo <<= BitDelta;
|
||||
val_hi >>= BitDelta;
|
||||
val |= val_lo;
|
||||
val |= val_hi;
|
||||
Set_NB32(dev, reg, val);
|
||||
|
||||
if(ChipSel & 1)
|
||||
continue;
|
||||
|
||||
reg = 0x60 + ((ChipSel>>1)<<2) + reg_off; /*Dram CS Mask 0 */
|
||||
val = Get_NB32(dev, reg);
|
||||
val_lo = val & AddrLoMask;
|
||||
val_hi = val & AddrHiMask;
|
||||
val &= AddrLoMaskN;
|
||||
val &= AddrHiMaskN;
|
||||
val_lo <<= BitDelta;
|
||||
val_hi >>= BitDelta;
|
||||
val |= val_lo;
|
||||
val |= val_hi;
|
||||
Set_NB32(dev, reg, val);
|
||||
}
|
||||
}
|
||||
print_t("InterleaveBanks_D: Banks Interleaved ");
|
||||
} /* DoIntlv */
|
||||
|
||||
// dump_pci_device(PCI_DEV(0, 0x18+pDCTstat->Node_ID, 2));
|
||||
|
||||
print_tx("InterleaveBanks_D: Status ", pDCTstat->Status);
|
||||
print_tx("InterleaveBanks_D: ErrStatus ", pDCTstat->ErrStatus);
|
||||
print_tx("InterleaveBanks_D: ErrCode ", pDCTstat->ErrCode);
|
||||
print_t("InterleaveBanks_D: Done\n");
|
||||
}
|
||||
|
||||
|
||||
1216
src/northbridge/amd/amdmct/mct/mctdqs_d.c
Normal file
1216
src/northbridge/amd/amdmct/mct/mctdqs_d.c
Normal file
File diff suppressed because it is too large
Load Diff
296
src/northbridge/amd/amdmct/mct/mctecc_d.c
Normal file
296
src/northbridge/amd/amdmct/mct/mctecc_d.c
Normal file
@ -0,0 +1,296 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
|
||||
#include "mct_d.h"
|
||||
|
||||
static void setSyncOnUnEccEn_D(struct MCTStatStruc *pMCTstat,
|
||||
struct DCTStatStruc *pDCTstatA);
|
||||
static u32 GetScrubAddr_D(u32 Node);
|
||||
static u8 isDramECCEn_D(struct DCTStatStruc *pDCTstat);
|
||||
|
||||
|
||||
/* Initialize ECC modes of Integrated Dram+Memory Controllers of a network of
|
||||
* Hammer processors. Use Dram background scrubber to fast initialize ECC bits
|
||||
* of all dram.
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
* Order that items are set:
|
||||
* 1. eccen bit in NB
|
||||
* 2. Scrub Base
|
||||
* 3. Temp Node Base
|
||||
* 4. Temp Node Limit
|
||||
* 5. Redir bit in NB
|
||||
* 6. Scrub CTL
|
||||
*
|
||||
* Conditions for setting background scrubber.
|
||||
* 1. node is present
|
||||
* 2. node has dram functioning (WE=RE=1)
|
||||
* 3. all eccdimms (or bit 17 of offset 90,fn 2)
|
||||
* 4. no chip-select gap exists
|
||||
*
|
||||
* The dram background scrubber is used under very controlled circumstances to
|
||||
* initialize all the ECC bits on the DIMMs of the entire dram address map
|
||||
* (including hidden or lost dram and dram above 4GB). We will turn the scrub
|
||||
* rate up to maximum, which should clear 4GB of dram in about 2.7 seconds.
|
||||
* We will activate the scrubbers of all nodes with ecc dram and let them run in
|
||||
* parallel, thereby reducing even further the time required to condition dram.
|
||||
* Finally, we will go through each node and either disable background scrubber,
|
||||
* or set the scrub rate to the user setup specified rate.
|
||||
*
|
||||
* To allow the NB to scrub, we need to wait a time period long enough to
|
||||
* guarantee that the NB scrubs the entire dram on its node. Do do this, we
|
||||
* simply sample the scrub ADDR once, for an initial value, then we sample and poll until the polled value of scrub ADDR
|
||||
* has wrapped around at least once: Scrub ADDRi+1 < Scrub ADDRi. Since we let all
|
||||
* Nodes run in parallel, we need to gaurantee that all nodes have wrapped. To do
|
||||
* this efficiently, we need only to sample one of the nodes, the node with the
|
||||
* largest ammount of dram populated is the one which will take the longest amount
|
||||
* of time (the scrub rate is set to max, the same rate, on all nodes). So,
|
||||
* during setup of scrub Base, we determine how much memory and which node has
|
||||
* the largest memory installed.
|
||||
*
|
||||
* Scrubbing should not ordinarily be enabled on a Node with a chip-select gap
|
||||
* (aka SW memhole, cs hoisting, etc..).To init ECC memory on this node, the
|
||||
* scrubber is used in two steps. First, the Dram Limit for the node is adjusted
|
||||
* down to the bottom of the gap, and that ECC dram is initialized. Second, the
|
||||
* orignal Limit is restored, the Scrub base is set to 4GB, and scrubber is
|
||||
* allowed to run until the Scrub Addr wraps around to zero.
|
||||
*/
|
||||
u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
|
||||
{
|
||||
u8 Node;
|
||||
u8 AllECC;
|
||||
u16 OB_NBECC;
|
||||
u32 curBase;
|
||||
u16 OB_ECCRedir;
|
||||
u32 LDramECC;
|
||||
u32 OF_ScrubCTL;
|
||||
u16 OB_ChipKill;
|
||||
u8 MemClrECC;
|
||||
|
||||
u32 dev;
|
||||
u32 reg;
|
||||
u32 val;
|
||||
|
||||
mctHookBeforeECC();
|
||||
|
||||
/* Construct these booleans, based on setup options, for easy handling
|
||||
later in this procedure */
|
||||
OB_NBECC = mctGet_NVbits(NV_NBECC); /* MCA ECC (MCE) enable bit */
|
||||
|
||||
OB_ECCRedir = mctGet_NVbits(NV_ECCRedir); /* ECC Redirection */
|
||||
|
||||
OB_ChipKill = mctGet_NVbits(NV_ChipKill); /* ECC Chip-kill mode */
|
||||
|
||||
OF_ScrubCTL = 0; /* Scrub CTL for Dcache, L2, and dram */
|
||||
val = mctGet_NVbits(NV_DCBKScrub);
|
||||
mct_AdjustScrub_D(pDCTstatA, val);
|
||||
OF_ScrubCTL |= val << 16;
|
||||
val = mctGet_NVbits(NV_L2BKScrub);
|
||||
OF_ScrubCTL |= val << 8;
|
||||
|
||||
val = mctGet_NVbits(NV_DramBKScrub);
|
||||
OF_ScrubCTL |= val;
|
||||
|
||||
AllECC = 1;
|
||||
MemClrECC = 0;
|
||||
print_t(" ECCInit 0 \n");
|
||||
for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) {
|
||||
struct DCTStatStruc *pDCTstat;
|
||||
pDCTstat = pDCTstatA + Node;
|
||||
LDramECC = 0;
|
||||
if (NodePresent_D(Node)) { /*If Node is present */
|
||||
dev = pDCTstat->dev_map;
|
||||
reg = 0x40+(Node << 3); /* Dram Base Node 0 + index */
|
||||
val = Get_NB32(dev, reg);
|
||||
|
||||
/* WE/RE is checked */
|
||||
if((val & 3)==3) { /* Node has dram populated */
|
||||
/* Negate 'all nodes/dimms ECC' flag if non ecc
|
||||
memory populated */
|
||||
if( pDCTstat->Status & (1<<SB_ECCDIMMs)) {
|
||||
LDramECC = isDramECCEn_D(pDCTstat);
|
||||
if(pDCTstat->ErrCode != SC_RunningOK) {
|
||||
pDCTstat->Status &= ~(1 << SB_ECCDIMMs);
|
||||
if (OB_NBECC) {
|
||||
pDCTstat->ErrStatus |= (1 << SB_DramECCDis);
|
||||
}
|
||||
AllECC = 0;
|
||||
LDramECC =0;
|
||||
}
|
||||
} else {
|
||||
AllECC = 0;
|
||||
}
|
||||
if(LDramECC) { /* if ECC is enabled on this dram */
|
||||
if (OB_NBECC) {
|
||||
mct_EnableDatIntlv_D(pMCTstat, pDCTstat);
|
||||
dev = pDCTstat->dev_nbmisc;
|
||||
reg =0x44; /* MCA NB Configuration */
|
||||
val = Get_NB32(dev, reg);
|
||||
val |= 1 << 22; /* EccEn */
|
||||
Set_NB32(dev, reg, val);
|
||||
DCTMemClr_Init_D(pMCTstat, pDCTstat);
|
||||
MemClrECC = 1;
|
||||
print_tx(" ECC enabled on node: ", Node);
|
||||
}
|
||||
} /* this node has ECC enabled dram */
|
||||
} else {
|
||||
LDramECC = 0;
|
||||
} /* Node has Dram */
|
||||
|
||||
if (MemClrECC) {
|
||||
MCTMemClrSync_D(pMCTstat, pDCTstatA);
|
||||
}
|
||||
} /* if Node present */
|
||||
}
|
||||
print_t(" ECCInit 1 \n");
|
||||
|
||||
if(AllECC)
|
||||
pMCTstat->GStatus |= 1<<GSB_ECCDIMMs;
|
||||
else
|
||||
pMCTstat->GStatus &= ~(1<<GSB_ECCDIMMs);
|
||||
|
||||
print_t(" ECCInit 2 \n");
|
||||
|
||||
/* Program the Dram BKScrub CTL to the proper (user selected) value.*/
|
||||
/* Reset MC4_STS. */
|
||||
for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) {
|
||||
struct DCTStatStruc *pDCTstat;
|
||||
pDCTstat = pDCTstatA + Node;
|
||||
LDramECC = 0;
|
||||
if (NodePresent_D(Node)) { /* If Node is present */
|
||||
reg = 0x40+(Node<<3); /* Dram Base Node 0 + index */
|
||||
val = Get_NB32(pDCTstat->dev_map, reg);
|
||||
curBase = val & 0xffff0000;
|
||||
/*WE/RE is checked because memory config may have been */
|
||||
if((val & 3)==3) { /* Node has dram populated */
|
||||
if (isDramECCEn_D(pDCTstat)) { /* if ECC is enabled on this dram */
|
||||
dev = pDCTstat->dev_nbmisc;
|
||||
val = curBase << 8;
|
||||
if(OB_ECCRedir) {
|
||||
val |= (1<<0); /* enable redirection */
|
||||
}
|
||||
Set_NB32(dev, 0x5C, val); /* Dram Scrub Addr Low */
|
||||
val = curBase>>24;
|
||||
Set_NB32(dev, 0x60, val); /* Dram Scrub Addr High */
|
||||
Set_NB32(dev, 0x58, OF_ScrubCTL); /*Scrub Control */ /*set dram background scrubbing to setup value */
|
||||
} /* this node has ECC enabled dram */
|
||||
} /*Node has Dram */
|
||||
} /*if Node present */
|
||||
}
|
||||
print_t(" ECCInit 3 \n");
|
||||
|
||||
if(mctGet_NVbits(NV_SyncOnUnEccEn))
|
||||
setSyncOnUnEccEn_D(pMCTstat, pDCTstatA);
|
||||
|
||||
mctHookAfterECC();
|
||||
return MemClrECC;
|
||||
}
|
||||
|
||||
|
||||
static void setSyncOnUnEccEn_D(struct MCTStatStruc *pMCTstat,
|
||||
struct DCTStatStruc *pDCTstatA)
|
||||
{
|
||||
u32 Node;
|
||||
u32 reg;
|
||||
u32 dev;
|
||||
u32 val;
|
||||
|
||||
for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) {
|
||||
struct DCTStatStruc *pDCTstat;
|
||||
pDCTstat = pDCTstatA + Node;
|
||||
if (NodePresent_D(Node)) { /* If Node is present*/
|
||||
reg = 0x40+(Node<<3); /* Dram Base Node 0 + index*/
|
||||
val = Get_NB32(pDCTstat->dev_map, reg);
|
||||
/*WE/RE is checked because memory config may have been*/
|
||||
if((val & 3)==3) { /* Node has dram populated*/
|
||||
if( isDramECCEn_D(pDCTstat)) {
|
||||
/*if ECC is enabled on this dram*/
|
||||
dev = pDCTstat->dev_nbmisc;
|
||||
reg = 0x44; /* MCA NB Configuration*/
|
||||
val = Get_NB32(dev, reg);
|
||||
val |= (1<<SyncOnUcEccEn);
|
||||
Set_NB32(dev, reg, val);
|
||||
}
|
||||
} /* Node has Dram*/
|
||||
} /* if Node present*/
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static u32 GetScrubAddr_D(u32 Node)
|
||||
{
|
||||
/* Get the current 40-bit Scrub ADDR address, scaled to 32-bits,
|
||||
* of the specified Node.
|
||||
*/
|
||||
|
||||
u32 reg;
|
||||
u32 regx;
|
||||
u32 lo, hi;
|
||||
u32 val;
|
||||
u32 dev = PA_NBMISC(Node);
|
||||
|
||||
|
||||
reg = 0x60; /* Scrub Addr High */
|
||||
hi = Get_NB32(dev, reg);
|
||||
|
||||
regx = 0x5C; /* Scrub Addr Low */
|
||||
lo = Get_NB32(dev, regx);
|
||||
/* Scrub Addr High again, detect 32-bit wrap */
|
||||
val = Get_NB32(dev, reg);
|
||||
if(val != hi) {
|
||||
hi = val; /* Scrub Addr Low again, if wrap occured */
|
||||
lo = Get_NB32(dev, regx);
|
||||
}
|
||||
|
||||
val = hi << 24;
|
||||
val |= lo >> 8;
|
||||
|
||||
return val; /* ScrubAddr[39:8] */
|
||||
}
|
||||
|
||||
|
||||
static u8 isDramECCEn_D(struct DCTStatStruc *pDCTstat)
|
||||
{
|
||||
u32 reg;
|
||||
u32 val;
|
||||
u8 i;
|
||||
u32 dev = pDCTstat->dev_dct;
|
||||
u8 ch_end;
|
||||
u8 isDimmECCEn = 0;
|
||||
|
||||
if(pDCTstat->GangedMode) {
|
||||
ch_end = 1;
|
||||
} else {
|
||||
ch_end = 2;
|
||||
}
|
||||
for(i=0; i<ch_end; i++) {
|
||||
if(pDCTstat->DIMMValidDCT[i] > 0){
|
||||
reg = 0x90 + i * 0x100; /* Dram Config Low */
|
||||
val = Get_NB32(dev, reg);
|
||||
if(val & (1<<DimmEcEn)) {
|
||||
/* set local flag 'dram ecc capable' */
|
||||
isDimmECCEn = 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
return isDimmECCEn;
|
||||
}
|
||||
88
src/northbridge/amd/amdmct/mct/mctgr.c
Normal file
88
src/northbridge/amd/amdmct/mct/mctgr.c
Normal file
@ -0,0 +1,88 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
|
||||
static const u8 Tab_GRCLKDis[] = { 8,0,8,8,0,0,8,0 };
|
||||
|
||||
|
||||
u32 mct_AdjustMemClkDis_GR(struct DCTStatStruc *pDCTstat, u32 dct,
|
||||
u32 DramTimingLo)
|
||||
{
|
||||
/* Greayhound format -> Griffin format */
|
||||
u32 NewDramTimingLo;
|
||||
u32 dev = pDCTstat->dev_dct;
|
||||
u32 reg;
|
||||
u32 reg_off = 0x100 * dct;
|
||||
u32 val;
|
||||
int i;
|
||||
|
||||
DramTimingLo = val;
|
||||
/* Dram Timing Low (owns Clock Enable bits) */
|
||||
NewDramTimingLo = Get_NB32(dev, 0x88 + reg_off);
|
||||
if(mctGet_NVbits(NV_AllMemClks)==0) {
|
||||
/*Special Jedec SPD diagnostic bit - "enable all clocks"*/
|
||||
if(!(pDCTstat->Status & (1<<SB_DiagClks))) {
|
||||
for(i=0; i<MAX_DIMMS_SUPPORTED; i++) {
|
||||
val = Tab_GRCLKDis[i];
|
||||
if(val<8) {
|
||||
if(!(pDCTstat->DIMMValidDCT[dct] & (1<<val))) {
|
||||
/* disable memclk */
|
||||
NewDramTimingLo |= (1<<(i+1));
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
DramTimingLo &= ~(0xff<<24);
|
||||
DramTimingLo |= NewDramTimingLo & (0xff<<24);
|
||||
DramTimingLo &= (0x4d<<24); /* FIXME - enable all MemClks for now */
|
||||
|
||||
return DramTimingLo;
|
||||
}
|
||||
|
||||
|
||||
u32 mct_AdjustDramConfigLo_GR(struct DCTStatStruc *pDCTstat, u32 dct, u32 val)
|
||||
{
|
||||
/* Greayhound format -> Griffin format */
|
||||
/*FIXME - BurstLength32 must be 0 when F3x44[DramEccEn]=1. */
|
||||
/*
|
||||
; mov cx,PA_NBMISC+44h ;MCA NB Configuration
|
||||
; call Get_NB32n_D
|
||||
; bt eax,22 ;EccEn
|
||||
; .if(CARRY?)
|
||||
; btr eax,BurstLength32
|
||||
; .endif
|
||||
*/
|
||||
return val;
|
||||
}
|
||||
|
||||
|
||||
void mct_AdjustMemHoist_GR(struct DCTStatStruc *pDCTstat, u32 base, u32 HoleSize)
|
||||
{
|
||||
u32 val;
|
||||
if(base >= pDCTstat->DCTHoleBase) {
|
||||
u32 dev = pDCTstat->dev_dct;
|
||||
base += HoleSize;
|
||||
base >>= 27 - 8;
|
||||
val = Get_NB32(dev, 0x110);
|
||||
val &= ~(0xfff<<11);
|
||||
val |= (base & 0xfff)<<11;
|
||||
Set_NB32(dev, 0x110, val);
|
||||
}
|
||||
}
|
||||
33
src/northbridge/amd/amdmct/mct/mcthdi.c
Normal file
33
src/northbridge/amd/amdmct/mct/mcthdi.c
Normal file
@ -0,0 +1,33 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
|
||||
void mct_DramInit_Hw_D(struct MCTStatStruc *pMCTstat,
|
||||
struct DCTStatStruc *pDCTstat, u8 dct)
|
||||
{
|
||||
u32 val;
|
||||
u32 reg;
|
||||
u32 dev = pDCTstat->dev_dct;
|
||||
|
||||
/*flag for selecting HW/SW DRAM Init HW DRAM Init */
|
||||
reg = 0x90 + 0x100 * dct; /*DRAM Configuration Low */
|
||||
val = Get_NB32(dev, reg);
|
||||
val |= (1<<InitDram);
|
||||
Set_NB32(dev, reg, val);
|
||||
}
|
||||
213
src/northbridge/amd/amdmct/mct/mctmtr_d.c
Normal file
213
src/northbridge/amd/amdmct/mct/mctmtr_d.c
Normal file
@ -0,0 +1,213 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
|
||||
#include "mct_d.h"
|
||||
|
||||
static void SetMTRRrangeWB_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr);
|
||||
static void SetMTRRrange_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr, u16 MtrrType);
|
||||
|
||||
void CPUMemTyping_D(struct MCTStatStruc *pMCTstat,
|
||||
struct DCTStatStruc *pDCTstatA)
|
||||
{
|
||||
/* BSP only. Set the fixed MTRRs for common legacy ranges.
|
||||
* Set TOP_MEM and TOM2.
|
||||
* Set some variable MTRRs with WB Uncacheable type.
|
||||
*/
|
||||
|
||||
u32 Bottom32bIO, Bottom40bIO, Cache32bTOP;
|
||||
u32 val;
|
||||
u32 addr;
|
||||
u32 lo, hi;
|
||||
|
||||
/* Set temporary top of memory from Node structure data.
|
||||
* Adjust temp top of memory down to accomodate 32-bit IO space.
|
||||
* Bottom40bIO=top of memory, right justified 8 bits
|
||||
* (defines dram versus IO space type)
|
||||
* Bottom32bIO=sub 4GB top of memory, right justified 8 bits
|
||||
* (defines dram versus IO space type)
|
||||
* Cache32bTOP=sub 4GB top of WB cacheable memory,
|
||||
* right justified 8 bits
|
||||
*/
|
||||
|
||||
val = mctGet_NVbits(NV_BottomIO);
|
||||
if(val == 0)
|
||||
val++;
|
||||
|
||||
Bottom32bIO = val << (24-8);
|
||||
|
||||
val = pMCTstat->SysLimit + 1;
|
||||
if(val <= _4GB_RJ8) {
|
||||
Bottom40bIO = 0;
|
||||
if(Bottom32bIO >= val)
|
||||
Bottom32bIO = val;
|
||||
} else {
|
||||
Bottom40bIO = val;
|
||||
}
|
||||
|
||||
val = mctGet_NVbits(NV_BottomUMA);
|
||||
if(val == 0)
|
||||
val++;
|
||||
|
||||
val <<= (24-8);
|
||||
if(val > Bottom32bIO)
|
||||
val = Bottom32bIO;
|
||||
|
||||
Cache32bTOP = val;
|
||||
|
||||
/*======================================================================
|
||||
Set default values for CPU registers
|
||||
======================================================================*/
|
||||
|
||||
/* NOTE : For LinuxBIOS, we don't need to set mtrr enables here because
|
||||
they are still enable from cache_as_ram.inc */
|
||||
|
||||
addr = 0x250;
|
||||
lo = 0x1E1E1E1E;
|
||||
hi = lo;
|
||||
_WRMSR(addr, lo, hi); /* 0 - 512K = WB Mem */
|
||||
addr = 0x258;
|
||||
_WRMSR(addr, lo, hi); /* 512K - 640K = WB Mem */
|
||||
|
||||
/*======================================================================
|
||||
Set variable MTRR values
|
||||
======================================================================*/
|
||||
/* NOTE: for LinuxBIOS change from 0x200 to 0x204: LinuxBIOS is using
|
||||
0x200, 0x201 for [1M, CONFIG_TOP_MEM)
|
||||
0x202, 0x203 for ROM Caching
|
||||
*/
|
||||
addr = 0x204; /* MTRR phys base 2*/
|
||||
/* use TOP_MEM as limit*/
|
||||
/* Limit=TOP_MEM|TOM2*/
|
||||
/* Base=0*/
|
||||
print_tx("\t CPUMemTyping: Cache32bTOP:", Cache32bTOP);
|
||||
SetMTRRrangeWB_D(0, &Cache32bTOP, &addr);
|
||||
/* Base */
|
||||
/* Limit */
|
||||
/* MtrrAddr */
|
||||
if(addr == -1) /* ran out of MTRRs?*/
|
||||
pMCTstat->GStatus |= 1<<GSB_MTRRshort;
|
||||
|
||||
pMCTstat->Sub4GCacheTop = Cache32bTOP<<8;
|
||||
|
||||
/*======================================================================
|
||||
Set TOP_MEM and TOM2 CPU registers
|
||||
======================================================================*/
|
||||
addr = TOP_MEM;
|
||||
lo = Bottom32bIO<<8;
|
||||
hi = Bottom32bIO>>24;
|
||||
_WRMSR(addr, lo, hi);
|
||||
print_tx("\t CPUMemTyping: Bottom32bIO:", Bottom32bIO);
|
||||
print_tx("\t CPUMemTyping: Bottom40bIO:", Bottom40bIO);
|
||||
if(Bottom40bIO) {
|
||||
hi = Bottom40bIO >> 24;
|
||||
lo = Bottom40bIO << 8;
|
||||
addr += 3; /* TOM2 */
|
||||
_WRMSR(addr, lo, hi);
|
||||
}
|
||||
addr = 0xC0010010; /* SYS_CFG */
|
||||
_RDMSR(addr, &lo, &hi);
|
||||
if(Bottom40bIO) {
|
||||
lo |= (1<<21); /* MtrrTom2En=1 */
|
||||
lo |= (1<<22); /* Tom2ForceMemTypeWB */
|
||||
} else {
|
||||
lo &= ~(1<<21); /* MtrrTom2En=0 */
|
||||
lo &= ~(1<<22); /* Tom2ForceMemTypeWB */
|
||||
}
|
||||
_WRMSR(addr, lo, hi);
|
||||
}
|
||||
|
||||
|
||||
static void SetMTRRrangeWB_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr)
|
||||
{
|
||||
/*set WB type*/
|
||||
SetMTRRrange_D(Base, pLimit, pMtrrAddr, 6);
|
||||
}
|
||||
|
||||
|
||||
static void SetMTRRrange_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr, u16 MtrrType)
|
||||
{
|
||||
/* Program MTRRs to describe given range as given cache type.
|
||||
* Use MTRR pairs starting with the given MTRRphys Base address,
|
||||
* and use as many as is required up to (excluding) MSR 020C, which
|
||||
* is reserved for OS.
|
||||
*
|
||||
* "Limit" in the context of this procedure is not the numerically
|
||||
* correct limit, but rather the Last address+1, for purposes of coding
|
||||
* efficiency and readability. Size of a region is then Limit-Base.
|
||||
*
|
||||
* 1. Size of each range must be a power of two
|
||||
* 2. Each range must be naturally aligned (Base is same as size)
|
||||
*
|
||||
* There are two code paths: the ascending path and descending path
|
||||
* (analogous to bsf and bsr), where the next limit is a funtion of the
|
||||
* next set bit in a forward or backward sequence of bits (as a function
|
||||
* of the Limit). We start with the ascending path, to ensure that
|
||||
* regions are naturally aligned, then we switch to the descending path
|
||||
* to maximize MTRR usage efficiency. Base=0 is a special case where we
|
||||
* start with the descending path. Correct Mask for region is
|
||||
* 2comp(Size-1)-1, which is 2comp(Limit-Base-1)-1
|
||||
*/
|
||||
|
||||
u32 curBase, curLimit, curSize;
|
||||
u32 val, valx;
|
||||
u32 addr;
|
||||
|
||||
val = curBase = Base;
|
||||
curLimit = *pLimit;
|
||||
addr = *pMtrrAddr;
|
||||
while((addr >= 0x200) && (addr < 0x20C) && (val < *pLimit)) {
|
||||
/* start with "ascending" code path */
|
||||
/* alignment (largest block size)*/
|
||||
valx = 1 << bsf(curBase);
|
||||
curSize = valx;
|
||||
|
||||
/* largest legal limit, given current non-zero range Base*/
|
||||
valx += curBase;
|
||||
if((curBase == 0) || (*pLimit < valx)) {
|
||||
/* flop direction to "descending" code path*/
|
||||
valx = 1<<bsr(*pLimit - curBase);
|
||||
curSize = valx;
|
||||
valx += curBase;
|
||||
}
|
||||
curLimit = valx; /*eax=curBase, edx=curLimit*/
|
||||
valx = val>>24;
|
||||
val <<= 8;
|
||||
|
||||
/* now program the MTRR */
|
||||
val |= MtrrType; /* set cache type (UC or WB)*/
|
||||
_WRMSR(addr, val, valx); /* prog. MTRR with current region Base*/
|
||||
val = ((~(curSize - 1))+1) - 1; /* Size-1*/ /*Mask=2comp(Size-1)-1*/
|
||||
valx = (val >> 24) | (0xff00); /* GH have 48 bits addr */
|
||||
val <<= 8;
|
||||
val |= ( 1 << 11); /* set MTRR valid*/
|
||||
addr++;
|
||||
_WRMSR(addr, val, valx); /* prog. MTRR with current region Mask*/
|
||||
val = curLimit;
|
||||
curBase = val; /* next Base = current Limit (loop exit)*/
|
||||
addr++; /* next MTRR pair addr */
|
||||
}
|
||||
if(val < *pLimit) {
|
||||
*pLimit = val;
|
||||
addr = -1;
|
||||
}
|
||||
*pMtrrAddr = addr;
|
||||
}
|
||||
|
||||
|
||||
237
src/northbridge/amd/amdmct/mct/mctndi_d.c
Normal file
237
src/northbridge/amd/amdmct/mct/mctndi_d.c
Normal file
@ -0,0 +1,237 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
|
||||
|
||||
void InterleaveNodes_D(struct MCTStatStruc *pMCTstat,
|
||||
struct DCTStatStruc *pDCTstatA)
|
||||
{
|
||||
|
||||
/* Applies Node memory interleaving if enabled and if all criteria are met. */
|
||||
u8 Node;
|
||||
u32 Base;
|
||||
u32 MemSize, MemSize0 = 0;
|
||||
u32 Dct0MemSize = 0, DctSelBase, DctSelBaseOffset;
|
||||
u8 Nodes;
|
||||
u8 NodesWmem;
|
||||
u8 DoIntlv;
|
||||
u8 _NdIntCap;
|
||||
u8 _SWHole;
|
||||
u8 HWHoleSz;
|
||||
u32 DramHoleAddrReg;
|
||||
u32 HoleBase;
|
||||
u32 dev0;
|
||||
u32 reg0;
|
||||
u32 val;
|
||||
u8 i;
|
||||
struct DCTStatStruc *pDCTstat;
|
||||
|
||||
DoIntlv = mctGet_NVbits(NV_NodeIntlv);
|
||||
|
||||
_NdIntCap = 0;
|
||||
HWHoleSz = 0; /*For HW remapping, NOT Node hoisting. */
|
||||
|
||||
pDCTstat = pDCTstatA + 0;
|
||||
dev0 = pDCTstat->dev_host;
|
||||
Nodes = ((Get_NB32(dev0, 0x60) >> 4) & 0x7) + 1;
|
||||
|
||||
|
||||
dev0 = pDCTstat->dev_map;
|
||||
reg0 = 0x40;
|
||||
|
||||
NodesWmem = 0;
|
||||
Node = 0;
|
||||
|
||||
while (DoIntlv && (Node < Nodes)) {
|
||||
pDCTstat = pDCTstatA + Node;
|
||||
if (pMCTstat->GStatus & (1 << GSB_SpIntRemapHole)) {
|
||||
pMCTstat->GStatus |= 1 << GSB_HWHole;
|
||||
_SWHole = 0;
|
||||
} else if (pDCTstat->Status & (1 << SB_SWNodeHole)) {
|
||||
_SWHole = 1;
|
||||
} else {
|
||||
_SWHole = 0;
|
||||
}
|
||||
|
||||
if(!_SWHole) {
|
||||
Base = Get_NB32(dev0, reg0);
|
||||
if (Base & 1) {
|
||||
NodesWmem++;
|
||||
Base &= 0xFFFF0000; /* Base[39:8] */
|
||||
|
||||
if (pDCTstat->Status & (1 << SB_HWHole )) {
|
||||
|
||||
/* to get true amount of dram,
|
||||
* subtract out memory hole if HW dram remapping */
|
||||
DramHoleAddrReg = Get_NB32(pDCTstat->dev_map, 0xF0);
|
||||
HWHoleSz = DramHoleAddrReg >> 16;
|
||||
HWHoleSz = (((~HWHoleSz) + 1) & 0xFF);
|
||||
HWHoleSz <<= 24-8;
|
||||
}
|
||||
/* check to see if the amount of memory on each channel
|
||||
* are the same on all nodes */
|
||||
|
||||
DctSelBase = Get_NB32(pDCTstat->dev_dct, 0x114);
|
||||
if(DctSelBase) {
|
||||
DctSelBase <<= 8;
|
||||
if ( pDCTstat->Status & (1 << SB_HWHole)) {
|
||||
if (DctSelBase >= 0x1000000) {
|
||||
DctSelBase -= HWHoleSz;
|
||||
}
|
||||
}
|
||||
DctSelBaseOffset -= Base;
|
||||
if (Node == 0) {
|
||||
Dct0MemSize = DctSelBase;
|
||||
} else if (DctSelBase != Dct0MemSize) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
MemSize = Get_NB32(dev0, reg0 + 4);
|
||||
MemSize &= 0xFFFF0000;
|
||||
MemSize += 0x00010000;
|
||||
MemSize -= Base;
|
||||
if ( pDCTstat->Status & (1 << SB_HWHole)) {
|
||||
MemSize -= HWHoleSz;
|
||||
}
|
||||
if (Node == 0) {
|
||||
MemSize0 = MemSize;
|
||||
} else if (MemSize0 != MemSize) {
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
break;
|
||||
}
|
||||
Node++;
|
||||
reg0 += 8;
|
||||
}
|
||||
|
||||
if (Node == Nodes) {
|
||||
/* if all nodes have memory and no Node had SW memhole */
|
||||
if (Nodes == 2 || Nodes == 4 || Nodes == 8)
|
||||
_NdIntCap = 1;
|
||||
}
|
||||
|
||||
if (!_NdIntCap)
|
||||
DoIntlv = 0;
|
||||
|
||||
|
||||
if (pMCTstat->GStatus & 1 << (GSB_SpIntRemapHole)) {
|
||||
HWHoleSz = pMCTstat->HoleBase;
|
||||
if (HWHoleSz == 0) {
|
||||
HWHoleSz = mctGet_NVbits(NV_BottomIO) & 0xFF;
|
||||
HWHoleSz <<= 24-8;
|
||||
}
|
||||
HWHoleSz = ((~HWHoleSz) + 1) & 0x00FF0000;
|
||||
}
|
||||
|
||||
if (DoIntlv) {
|
||||
MCTMemClr_D(pMCTstat,pDCTstatA);
|
||||
/* Program Interleaving enabled on Node 0 map only.*/
|
||||
MemSize0 <<= bsf(Nodes); /* MemSize=MemSize*2 (or 4, or 8) */
|
||||
Dct0MemSize <<= bsf(Nodes);
|
||||
MemSize0 += HWHoleSz;
|
||||
Base = ((Nodes - 1) << 8) | 3;
|
||||
reg0 = 0x40;
|
||||
Node = 0;
|
||||
while(Node < Nodes) {
|
||||
Set_NB32(dev0, reg0, Base);
|
||||
MemSize = MemSize0;
|
||||
MemSize--;
|
||||
MemSize &= 0xFFFF0000;
|
||||
MemSize |= Node << 8; /* set IntlvSel[2:0] field */
|
||||
MemSize |= Node; /* set DstNode[2:0] field */
|
||||
Set_NB32(dev0, reg0 + 4, MemSize0);
|
||||
reg0 += 8;
|
||||
Node++;
|
||||
}
|
||||
|
||||
/* set base/limit to F1x120/124 per Node */
|
||||
Node = 0;
|
||||
while(Node < Nodes) {
|
||||
pDCTstat = pDCTstatA + Node;
|
||||
pDCTstat->NodeSysBase = 0;
|
||||
MemSize = MemSize0;
|
||||
MemSize -= HWHoleSz;
|
||||
MemSize--;
|
||||
pDCTstat->NodeSysLimit = MemSize;
|
||||
Set_NB32(pDCTstat->dev_map, 0x120, Node << 21);
|
||||
MemSize = MemSize0;
|
||||
MemSize--;
|
||||
MemSize >>= 19;
|
||||
val = Base;
|
||||
val &= 0x700;
|
||||
val <<= 13;
|
||||
val |= MemSize;
|
||||
Set_NB32(pDCTstat->dev_map, 0x124, val);
|
||||
|
||||
if (pMCTstat->GStatus & (1 << GSB_HWHole)) {
|
||||
HoleBase = pMCTstat->HoleBase;
|
||||
if (Dct0MemSize >= HoleBase) {
|
||||
val = HWHoleSz;
|
||||
if( Node == 0) {
|
||||
val += Dct0MemSize;
|
||||
}
|
||||
} else {
|
||||
val = HWHoleSz + Dct0MemSize;
|
||||
}
|
||||
|
||||
val >>= 8; /* DramHoleOffset */
|
||||
HoleBase <<= 8; /* DramHoleBase */
|
||||
val |= HoleBase;
|
||||
val |= 1 << DramMemHoistValid;
|
||||
val |= 1 << DramHoleValid;
|
||||
Set_NB32(pDCTstat->dev_map, 0xF0, val);
|
||||
}
|
||||
|
||||
|
||||
Set_NB32(pDCTstat->dev_dct, 0x114, Dct0MemSize >> 8); /* DctSelBaseOffset */
|
||||
val = Get_NB32(pDCTstat->dev_dct, 0x110);
|
||||
val &= 0x7FF;
|
||||
val |= Dct0MemSize >> 8;
|
||||
Set_NB32(pDCTstat->dev_dct, 0x110, val); /* DctSelBaseAddr */
|
||||
print_tx("InterleaveNodes: DRAM Controller Select Low Register = ", val);
|
||||
Node++;
|
||||
}
|
||||
|
||||
|
||||
/* Copy Node 0 into other Nodes' CSRs */
|
||||
Node = 1;
|
||||
while (Node < Nodes) {
|
||||
pDCTstat = pDCTstatA + Node;
|
||||
|
||||
for (i = 0x40; i <= 0x80; i++) {
|
||||
val = Get_NB32(dev0, i);
|
||||
Set_NB32(pDCTstat->dev_map, i, val);
|
||||
}
|
||||
|
||||
val = Get_NB32(dev0, 0xF0);
|
||||
Set_NB32(pDCTstat->dev_map, 0xF0, val);
|
||||
Node++;
|
||||
}
|
||||
pMCTstat->GStatus = (1 << GSB_NodeIntlv);
|
||||
}
|
||||
print_tx("InterleaveNodes_D: Status ", pDCTstat->Status);
|
||||
print_tx("InterleaveNodes_D: ErrStatus ", pDCTstat->ErrStatus);
|
||||
print_tx("InterleaveNodes_D: ErrCode ", pDCTstat->ErrCode);
|
||||
print_t("InterleaveNodes_D: Done\n");
|
||||
}
|
||||
406
src/northbridge/amd/amdmct/mct/mctpro_d.c
Normal file
406
src/northbridge/amd/amdmct/mct/mctpro_d.c
Normal file
@ -0,0 +1,406 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
|
||||
static u32 CheckNBCOFAutoPrechg(struct DCTStatStruc *pDCTstat, u32 dct);
|
||||
static u8 mct_AdjustDQSPosDelay_D(struct DCTStatStruc *pDCTstat, u8 dly);
|
||||
|
||||
void EarlySampleSupport_D(void)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
u32 procOdtWorkaround(struct DCTStatStruc *pDCTstat, u32 dct, u32 val)
|
||||
{
|
||||
u32 tmp;
|
||||
tmp = pDCTstat->LogicalCPUID;
|
||||
if ((tmp == AMD_DR_A0A) || (tmp == AMD_DR_A1B) || (tmp == AMD_DR_A2)) {
|
||||
val &= 0x0FFFFFFF;
|
||||
if(pDCTstat->MAdimms[dct] > 1)
|
||||
val |= 0x10000000;
|
||||
}
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
|
||||
u32 OtherTiming_A_D(struct DCTStatStruc *pDCTstat, u32 val)
|
||||
{
|
||||
/* Bug#10695:One MEMCLK Bubble Writes Don't Do X4 X8 Switching Correctly
|
||||
* Solution: BIOS should set DRAM Timing High[Twrwr] > 00b
|
||||
* ( F2x[1, 0]8C[1:0] > 00b). Silicon Status: Fixed in Rev B
|
||||
* FIXME: check if this is still required.
|
||||
*/
|
||||
u32 tmp;
|
||||
tmp = pDCTstat->LogicalCPUID;
|
||||
if ((tmp == AMD_DR_A0A) || (tmp == AMD_DR_A1B) || (tmp == AMD_DR_A2)) {
|
||||
if(!(val & (3<<12) ))
|
||||
val |= 1<<12;
|
||||
}
|
||||
return val;
|
||||
}
|
||||
|
||||
|
||||
void mct_ForceAutoPrecharge_D(struct DCTStatStruc *pDCTstat, u32 dct)
|
||||
{
|
||||
u32 tmp;
|
||||
u32 reg;
|
||||
u32 reg_off;
|
||||
u32 dev;
|
||||
u32 val;
|
||||
|
||||
tmp = pDCTstat->LogicalCPUID;
|
||||
if ((tmp == AMD_DR_A0A) || (tmp == AMD_DR_A1B) || (tmp == AMD_DR_A2)) {
|
||||
if(CheckNBCOFAutoPrechg(pDCTstat, dct)) {
|
||||
dev = pDCTstat->dev_dct;
|
||||
reg_off = 0x100 * dct;
|
||||
reg = 0x90 + reg_off; /* Dram Configuration Lo */
|
||||
val = Get_NB32(dev, reg);
|
||||
val |= 1<<ForceAutoPchg;
|
||||
if(!pDCTstat->GangedMode)
|
||||
val |= 1<<BurstLength32;
|
||||
Set_NB32(dev, reg, val);
|
||||
|
||||
reg = 0x88 + reg_off; /* cx=Dram Timing Lo */
|
||||
val = Get_NB32(dev, reg);
|
||||
val |= 0x000F0000; /* Trc = 0Fh */
|
||||
Set_NB32(dev, reg, val);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void mct_EndDQSTraining_D(struct MCTStatStruc *pMCTstat,
|
||||
struct DCTStatStruc *pDCTstatA)
|
||||
{
|
||||
/* Bug#13341: Prefetch is getting killed when the limit is reached in
|
||||
* PrefDramTrainMode
|
||||
* Solution: Explicitly clear the PrefDramTrainMode bit after training
|
||||
* sequence in order to ensure resumption of normal HW prefetch
|
||||
* behavior.
|
||||
* NOTE -- this has been documented with a note at the end of this
|
||||
* section in the BKDG (although, admittedly, the note does not really
|
||||
* stand out).
|
||||
* Silicon Status: Fixed in Rev B ( confirm)
|
||||
* FIXME: check this.
|
||||
*/
|
||||
|
||||
u32 tmp;
|
||||
u32 dev;
|
||||
u32 reg;
|
||||
u32 val;
|
||||
u32 Node;
|
||||
|
||||
for(Node = 0; Node < MAX_NODES_SUPPORTED; Node++) {
|
||||
struct DCTStatStruc *pDCTstat;
|
||||
pDCTstat = pDCTstatA + Node;
|
||||
|
||||
if(!pDCTstat->NodePresent) break;
|
||||
|
||||
tmp = pDCTstat->LogicalCPUID;
|
||||
if ((tmp == AMD_DR_A0A) || (tmp == AMD_DR_A1B) || (tmp == AMD_DR_A2)) {
|
||||
dev = pDCTstat->dev_dct;
|
||||
reg = 0x11c;
|
||||
val = Get_NB32(dev, reg);
|
||||
val &= ~(1<<PrefDramTrainMode);
|
||||
Set_NB32(dev, reg, val);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
void mct_BeforeDQSTrain_Samp_D(struct MCTStatStruc *pMCTstat,
|
||||
struct DCTStatStruc *pDCTstat)
|
||||
{
|
||||
/* Bug#15115: Uncertainty In The Sync Chain Leads To Setup Violations
|
||||
* In TX FIFO
|
||||
* Solution: BIOS should program DRAM Control Register[RdPtrInit] = 5h,
|
||||
* (F2x[1, 0]78[3:0] = 5h).
|
||||
* Silicon Status: Fixed In Rev B0
|
||||
*/
|
||||
|
||||
/* Bug#15880: Determine validity of reset settings for DDR PHY timing
|
||||
* regi..
|
||||
* Solutiuon: At least, set WrDqs fine delay to be 0 for DDR2 training.
|
||||
*/
|
||||
|
||||
u32 dev;
|
||||
u32 reg_off;
|
||||
u32 index_reg;
|
||||
u32 index;
|
||||
u32 reg;
|
||||
u32 val;
|
||||
u32 tmp;
|
||||
u32 Channel;
|
||||
|
||||
|
||||
tmp = pDCTstat->LogicalCPUID;
|
||||
if ((tmp == AMD_DR_A0A) || (tmp == AMD_DR_A1B) || (tmp == AMD_DR_A2)) {
|
||||
|
||||
dev = pDCTstat->dev_dct;
|
||||
index = 0;
|
||||
|
||||
for(Channel = 0; Channel<2; Channel++) {
|
||||
index_reg = 0x98 + 0x100 * Channel;
|
||||
val = Get_NB32_index_wait(dev, index_reg, 0x0d004007);
|
||||
val |= 0x3ff;
|
||||
Set_NB32_index_wait(dev, index_reg, 0x0d0f4f07, val);
|
||||
}
|
||||
|
||||
for(Channel = 0; Channel<2; Channel++) {
|
||||
if(pDCTstat->GangedMode && Channel)
|
||||
break;
|
||||
reg_off = 0x100 * Channel;
|
||||
reg = 0x78 + reg_off;
|
||||
val = Get_NB32(dev, reg);
|
||||
val &= ~(0x07);
|
||||
val |= 5;
|
||||
Set_NB32(dev, reg, val);
|
||||
}
|
||||
|
||||
for(Channel = 0; Channel<2; Channel++) {
|
||||
reg_off = 0x100 * Channel;
|
||||
val = 0;
|
||||
index_reg = 0x98 + reg_off;
|
||||
for( index = 0x30; index < (0x45 + 1); index++) {
|
||||
Set_NB32_index_wait(dev, index_reg, index, val);
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
u32 Modify_D3CMP(struct DCTStatStruc *pDCTstat, u32 dct, u32 value)
|
||||
{
|
||||
/* Errata#189: Reads To Phy Driver Calibration Register and Phy
|
||||
* Predriver Calibration Register Do Not Return Bit 27.
|
||||
* Solution: See #41322 for details.
|
||||
* BIOS can modify bit 27 of the Phy Driver Calibration register
|
||||
* as follows:
|
||||
* 1. Read F2x[1, 0]9C_x09
|
||||
* 2. Read F2x[1, 0]9C_x0D004201
|
||||
* 3. Set F2x[1, 0]9C_x09[27] = F2x[1, 0]9C_x0D004201[10]
|
||||
* BIOS can modify bit 27 of the Phy Predriver Calibration register
|
||||
* as follows:
|
||||
* 1. Read F2x[1, 0]9C_x0A
|
||||
* 2. Read F2x[1, 0]9C_x0D004209
|
||||
* 3. Set F2x[1, 0]9C_x0A[27] = F2x[1, 0]9C_x0D004209[10]
|
||||
* Silicon Status: Fixed planned for DR-B0
|
||||
*/
|
||||
|
||||
u32 dev;
|
||||
u32 index_reg;
|
||||
u32 index;
|
||||
u32 val;
|
||||
u32 tmp;
|
||||
|
||||
tmp = pDCTstat->LogicalCPUID;
|
||||
if ((tmp == AMD_DR_A0A) || (tmp == AMD_DR_A1B) || (tmp == AMD_DR_A2)) {
|
||||
dev = pDCTstat->dev_dct;
|
||||
index_reg = 0x98 + 0x100 * dct;
|
||||
index = 0x0D004201;
|
||||
val = Get_NB32_index_wait(dev, index_reg, index);
|
||||
value &= ~(1<<27);
|
||||
value |= ((val>>10) & 1) << 27;
|
||||
}
|
||||
return value;
|
||||
}
|
||||
|
||||
|
||||
void SyncSetting(struct DCTStatStruc *pDCTstat)
|
||||
{
|
||||
/* Errata#198: AddrCmdSetup, CsOdtSetup, and CkeSetup Require Identical
|
||||
* Programming For Both Channels in Ganged Mode
|
||||
* Solution: The BIOS must program the following DRAM timing parameters
|
||||
* the same for both channels:
|
||||
* 1. F2x[1, 0]9C_x04[21] (AddrCmdSetup)
|
||||
* 2. F2x[1, 0]9C_x04[15] (CsOdtSetup)
|
||||
* 3. F2x[1, 0]9C_x04[5]) (CkeSetup)
|
||||
* That is, if the AddrCmdSetup, CsOdtSetup, or CkeSetup is
|
||||
* set to 1'b1 for one of the controllers, then the corresponding
|
||||
* AddrCmdSetup, CsOdtSetup, or CkeSetup must be set to 1'b1 for the
|
||||
* other controller.
|
||||
* Silicon Status: Fix TBD
|
||||
*/
|
||||
|
||||
u32 tmp;
|
||||
tmp = pDCTstat->LogicalCPUID;
|
||||
if ((tmp == AMD_DR_A0A) || (tmp == AMD_DR_A1B) || (tmp == AMD_DR_A2)) {
|
||||
pDCTstat->CH_ODC_CTL[1] = pDCTstat->CH_ODC_CTL[0];
|
||||
pDCTstat->CH_ADDR_TMG[1] = pDCTstat->CH_ADDR_TMG[0];
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static u32 CheckNBCOFAutoPrechg(struct DCTStatStruc *pDCTstat, u32 dct)
|
||||
{
|
||||
u32 ret = 0;
|
||||
u32 lo, hi;
|
||||
u32 msr;
|
||||
u32 val;
|
||||
u32 valx, valy;
|
||||
u32 NbDid;
|
||||
|
||||
/* 3 * (Fn2xD4[NBFid]+4)/(2^NbDid)/(3+Fn2x94[MemClkFreq]) */
|
||||
msr = 0xC0010071;
|
||||
_RDMSR(msr, &lo, &hi);
|
||||
NbDid = (lo>>22) & 1;
|
||||
|
||||
val = Get_NB32(pDCTstat->dev_dct, 0x94 + 0x100 * dct);
|
||||
valx = ((val & 0x07) + 3)<<NbDid;
|
||||
print_tx("MemClk:", valx >> NbDid);
|
||||
|
||||
val = Get_NB32(pDCTstat->dev_nbmisc, 0xd4);
|
||||
valy = ((val & 0x1f) + 4) * 3;
|
||||
print_tx("NB COF:", valy >> NbDid);
|
||||
|
||||
val = valy/valx;
|
||||
if((val==3) && (valy%valx)) /* 3 < NClk/MemClk < 4 */
|
||||
ret = 1;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
void mct_BeforeDramInit_D(struct DCTStatStruc *pDCTstat, u32 dct)
|
||||
{
|
||||
u32 tmp;
|
||||
u32 Speed;
|
||||
u32 ch, ch_start, ch_end;
|
||||
u32 index_reg;
|
||||
u32 index;
|
||||
u32 dev;
|
||||
u32 val;
|
||||
|
||||
|
||||
tmp = pDCTstat->LogicalCPUID;
|
||||
if ((tmp == AMD_DR_A0A) || (tmp == AMD_DR_A1B) || (tmp == AMD_DR_A2)) {
|
||||
Speed = pDCTstat->Speed;
|
||||
/* MemClkFreq = 333MHz or 533Mhz */
|
||||
if((Speed == 3) || (Speed == 2)) {
|
||||
if(pDCTstat->GangedMode) {
|
||||
ch_start = 0;
|
||||
ch_end = 2;
|
||||
} else {
|
||||
ch_start = dct;
|
||||
ch_end = dct+1;
|
||||
}
|
||||
dev = pDCTstat->dev_dct;
|
||||
index = 0x0D00E001;
|
||||
for(ch=ch_start; ch<ch_end; ch++) {
|
||||
index_reg = 0x98 + 0x100 * ch;
|
||||
val = Get_NB32_index(dev, index_reg, 0x0D00E001);
|
||||
val &= ~(0xf0);
|
||||
val |= 0x80;
|
||||
Set_NB32_index(dev, index_reg, 0x0D01E001, val);
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static u8 mct_AdjustDelay_D(struct DCTStatStruc *pDCTstat, u8 dly)
|
||||
{
|
||||
u8 skip = 0;
|
||||
dly &= 0x1f;
|
||||
if ((dly >= MIN_FENCE) && (dly <= MAX_FENCE))
|
||||
skip = 1;
|
||||
|
||||
return skip;
|
||||
}
|
||||
|
||||
|
||||
static u8 mct_checkFenceHoleAdjust_D(struct MCTStatStruc *pMCTstat,
|
||||
struct DCTStatStruc *pDCTstat, u8 DQSDelay,
|
||||
u8 ChipSel, u8 *result)
|
||||
{
|
||||
u8 ByteLane;
|
||||
u32 tmp;
|
||||
|
||||
tmp = pDCTstat->LogicalCPUID;
|
||||
if ((tmp == AMD_DR_A0A) || (tmp == AMD_DR_A1B) || (tmp == AMD_DR_A2)) {
|
||||
if (pDCTstat->Direction == DQS_WRITEDIR) {
|
||||
if ((pDCTstat->Speed == 2) || (pDCTstat->Speed == 3)) {
|
||||
if(DQSDelay == 13) {
|
||||
if (*result == 0xFF) {
|
||||
for (ByteLane = 0; ByteLane < 8; ByteLane++) {
|
||||
pDCTstat->DQSDelay = 13;
|
||||
pDCTstat->ByteLane = ByteLane;
|
||||
/* store the value into the data structure */
|
||||
StoreDQSDatStrucVal_D(pMCTstat, pDCTstat, ChipSel);
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
if (mct_AdjustDQSPosDelay_D(pDCTstat, DQSDelay)) {
|
||||
*result = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static u8 mct_AdjustDQSPosDelay_D(struct DCTStatStruc *pDCTstat, u8 dly)
|
||||
{
|
||||
u8 skip = 0;
|
||||
|
||||
dly &= 0x1f;
|
||||
if ((dly >= MIN_DQS_WR_FENCE) && (dly <= MAX_DQS_WR_FENCE))
|
||||
skip = 1;
|
||||
|
||||
return skip;
|
||||
|
||||
}
|
||||
|
||||
static void beforeInterleaveChannels_D(struct DCTStatStruc *pDCTstatA, u8 *enabled) {
|
||||
|
||||
if (pDCTstatA->LogicalCPUID & (AMD_DR_Ax))
|
||||
*enabled = 0;
|
||||
}
|
||||
|
||||
|
||||
static u8 mctDoAxRdPtrInit_D(struct DCTStatStruc *pDCTstat, u8 *Rdtr)
|
||||
{
|
||||
u32 tmp;
|
||||
|
||||
tmp = pDCTstat->LogicalCPUID;
|
||||
if ((tmp == AMD_DR_A0A) || (tmp == AMD_DR_A1B) || (tmp == AMD_DR_A2)) {
|
||||
*Rdtr = 5;
|
||||
return 1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static void mct_AdjustScrub_D(struct DCTStatStruc *pDCTstat, u16 *scrub_request) {
|
||||
|
||||
/* Erratum #202: disable DCache scrubber for Ax parts */
|
||||
|
||||
if (pDCTstat->LogicalCPUID & (AMD_DR_Ax)) {
|
||||
*scrub_request = 0;
|
||||
pDCTstat->ErrStatus |= 1 << SB_DCBKScrubDis;
|
||||
}
|
||||
}
|
||||
|
||||
1121
src/northbridge/amd/amdmct/mct/mctsrc.c
Normal file
1121
src/northbridge/amd/amdmct/mct/mctsrc.c
Normal file
File diff suppressed because it is too large
Load Diff
96
src/northbridge/amd/amdmct/mct/mctsrc1p.c
Normal file
96
src/northbridge/amd/amdmct/mct/mctsrc1p.c
Normal file
@ -0,0 +1,96 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
|
||||
u8 mct_checkNumberOfDqsRcvEn_1Pass(u8 pass)
|
||||
{
|
||||
u8 ret = 1;
|
||||
if (pass == SecondPass)
|
||||
ret = 0;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
u32 SetupDqsPattern_1PassA(u8 pass)
|
||||
{
|
||||
return (u32) TestPattern1_D;
|
||||
}
|
||||
|
||||
|
||||
u32 SetupDqsPattern_1PassB(u8 pass)
|
||||
{
|
||||
return (u32) TestPattern0_D;
|
||||
}
|
||||
|
||||
u8 mct_Get_Start_RcvrEnDly_1Pass(u8 pass)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
u8 mct_Average_RcvrEnDly_1Pass(struct DCTStatStruc *pDCTstat, u8 Channel, u8 Receiver,
|
||||
u8 Pass)
|
||||
{
|
||||
u8 i, MaxValue;
|
||||
u8 *p;
|
||||
u8 val;
|
||||
|
||||
MaxValue = 0;
|
||||
p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1];
|
||||
|
||||
for(i=0; i < 8; i++) {
|
||||
/* get left value from DCTStatStruc.CHA_D0_B0_RCVRDLY*/
|
||||
val = p[i];
|
||||
/* get right value from DCTStatStruc.CHA_D0_B0_RCVRDLY_1*/
|
||||
val += Pass1MemClkDly;
|
||||
/* write back the value to stack */
|
||||
if (val > MaxValue)
|
||||
MaxValue = val;
|
||||
|
||||
p[i] = val;
|
||||
}
|
||||
// pDCTstat->DimmTrainFail &= ~(1<<Receiver+Channel);
|
||||
|
||||
return MaxValue;
|
||||
}
|
||||
|
||||
|
||||
|
||||
u8 mct_AdjustFinalDQSRcvValue_1Pass(u8 val_1p, u8 val_2p)
|
||||
{
|
||||
return (val_1p & 0xff) + ((val_2p & 0xff)<<8);
|
||||
}
|
||||
|
||||
|
||||
u8 mct_SaveRcvEnDly_D_1Pass(struct DCTStatStruc *pDCTstat, u8 pass)
|
||||
{
|
||||
u8 ret;
|
||||
ret = 0;
|
||||
if((pDCTstat->DqsRcvEn_Pass == 0xff) && (pass== FirstPass))
|
||||
ret = 2;
|
||||
return ret;
|
||||
}
|
||||
|
||||
u8 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat,
|
||||
u8 RcvrEnDly, u8 RcvrEnDlyLimit,
|
||||
u8 Channel, u8 Receiver, u8 Pass)
|
||||
|
||||
{
|
||||
return mct_Average_RcvrEnDly_1Pass(pDCTstat, Channel, Receiver, Pass);
|
||||
}
|
||||
139
src/northbridge/amd/amdmct/mct/mctsrc2p.c
Normal file
139
src/northbridge/amd/amdmct/mct/mctsrc2p.c
Normal file
@ -0,0 +1,139 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
|
||||
u8 mct_checkNumberOfDqsRcvEn_Pass(u8 pass)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
u32 SetupDqsPattern_PassA(u8 Pass)
|
||||
{
|
||||
u32 ret;
|
||||
if(Pass == FirstPass)
|
||||
ret = (u32) TestPattern1_D;
|
||||
else
|
||||
ret = (u32) TestPattern2_D;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
u32 SetupDqsPattern_PassB(u8 Pass)
|
||||
{
|
||||
u32 ret;
|
||||
if(Pass == FirstPass)
|
||||
ret = (u32) TestPattern0_D;
|
||||
else
|
||||
ret = (u32) TestPattern2_D;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
u8 mct_Get_Start_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat,
|
||||
u8 Channel, u8 Receiver,
|
||||
u8 Pass)
|
||||
{
|
||||
u8 RcvrEnDly;
|
||||
|
||||
if (Pass == FirstPass)
|
||||
RcvrEnDly = 0;
|
||||
else {
|
||||
u8 max = 0;
|
||||
u8 val;
|
||||
u8 i;
|
||||
u8 *p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver>>1];
|
||||
u8 bn;
|
||||
bn = 8;
|
||||
// print_tx("mct_Get_Start_RcvrEnDly_Pass: Channel:", Channel);
|
||||
// print_tx("mct_Get_Start_RcvrEnDly_Pass: Receiver:", Receiver);
|
||||
for ( i=0;i<bn; i++) {
|
||||
val = p[i];
|
||||
// print_tx("mct_Get_Start_RcvrEnDly_Pass: i:", i);
|
||||
// print_tx("mct_Get_Start_RcvrEnDly_Pass: val:", val);
|
||||
if(val > max) {
|
||||
max = val;
|
||||
}
|
||||
}
|
||||
RcvrEnDly = max;
|
||||
// while(1) {; }
|
||||
// RcvrEnDly += secPassOffset; //FIXME Why
|
||||
}
|
||||
|
||||
return RcvrEnDly;
|
||||
}
|
||||
|
||||
|
||||
|
||||
u8 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat,
|
||||
u8 RcvrEnDly, u8 RcvrEnDlyLimit,
|
||||
u8 Channel, u8 Receiver, u8 Pass)
|
||||
{
|
||||
u8 i;
|
||||
u8 *p;
|
||||
u8 *p_1;
|
||||
u8 val;
|
||||
u8 val_1;
|
||||
u8 valid = 1;
|
||||
u8 bn;
|
||||
|
||||
bn = 8;
|
||||
|
||||
p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver>>1];
|
||||
|
||||
if (Pass == SecondPass) { /* second pass must average values */
|
||||
//FIXME: which byte?
|
||||
p_1 = pDCTstat->B_RCVRDLY_1;
|
||||
// p_1 = pDCTstat->CH_D_B_RCVRDLY_1[Channel][Receiver>>1];
|
||||
for(i=0; i<bn; i++) {
|
||||
val = p[i];
|
||||
/* left edge */
|
||||
if (val != (RcvrEnDlyLimit - 1)) {
|
||||
val -= Pass1MemClkDly;
|
||||
val_1 = p_1[i];
|
||||
val += val_1;
|
||||
val >>= 1;
|
||||
p[i] = val;
|
||||
} else {
|
||||
valid = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (!valid) {
|
||||
pDCTstat->ErrStatus |= 1<<SB_NORCVREN;
|
||||
} else {
|
||||
pDCTstat->DimmTrainFail &= ~(1<<(Receiver + Channel));
|
||||
}
|
||||
} else {
|
||||
for(i=0; i < bn; i++) {
|
||||
val = p[i];
|
||||
/* Add 1/2 Memlock delay */
|
||||
//val += Pass1MemClkDly;
|
||||
val += 0x5; // NOTE: middle value with DQSRCVEN_SAVED_GOOD_TIMES
|
||||
//val += 0x02;
|
||||
p[i] = val;
|
||||
pDCTstat->DimmTrainFail &= ~(1<<(Receiver + Channel));
|
||||
}
|
||||
}
|
||||
|
||||
return RcvrEnDly;
|
||||
}
|
||||
413
src/northbridge/amd/amdmct/mct/mcttmrl.c
Normal file
413
src/northbridge/amd/amdmct/mct/mcttmrl.c
Normal file
@ -0,0 +1,413 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
* Description: Max Read Latency Training feature for DDR 2 MCT
|
||||
*/
|
||||
|
||||
static u8 CompareMaxRdLatTestPattern_D(u32 pattern_buf, u32 addr);
|
||||
static u32 GetMaxRdLatTestAddr_D(struct MCTStatStruc *pMCTstat,
|
||||
struct DCTStatStruc *pDCTstat, u8 Channel,
|
||||
u8 *MaxRcvrEnDly, u8 *valid);
|
||||
u8 mct_GetStartMaxRdLat_D(struct MCTStatStruc *pMCTstat,
|
||||
struct DCTStatStruc *pDCTstat, u8 Channel,
|
||||
u8 DQSRcvEnDly, u32 *Margin);
|
||||
static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat,
|
||||
struct DCTStatStruc *pDCTstat);
|
||||
static void mct_setMaxRdLatTrnVal_D(struct DCTStatStruc *pDCTstat, u8 Channel,
|
||||
u16 MaxRdLatVal);
|
||||
|
||||
/*Warning: These must be located so they do not cross a logical 16-bit
|
||||
segment boundary!*/
|
||||
static const u32 TestMaxRdLAtPattern_D[] = {
|
||||
0x6E0E3FAC, 0x0C3CFF52,
|
||||
0x4A688181, 0x49C5B613,
|
||||
0x7C780BA6, 0x5C1650E3,
|
||||
0x0C4F9D76, 0x0C6753E6,
|
||||
0x205535A5, 0xBABFB6CA,
|
||||
0x610E6E5F, 0x0C5F1C87,
|
||||
0x488493CE, 0x14C9C383,
|
||||
0xF5B9A5CD, 0x9CE8F615,
|
||||
|
||||
0xAAD714B5, 0xC38F1B4C,
|
||||
0x72ED647C, 0x669F7562,
|
||||
0x5233F802, 0x4A898B30,
|
||||
0x10A40617, 0x3326B465,
|
||||
0x55386E04, 0xC807E3D3,
|
||||
0xAB49E193, 0x14B4E63A,
|
||||
0x67DF2495, 0xEA517C45,
|
||||
0x7624CE51, 0xF8140C51,
|
||||
|
||||
0x4824BD23, 0xB61DD0C9,
|
||||
0x072BCFBE, 0xE8F3807D,
|
||||
0x919EA373, 0x25E30C47,
|
||||
0xFEB12958, 0x4DA80A5A,
|
||||
0xE9A0DDF8, 0x792B0076,
|
||||
0xE81C73DC, 0xF025B496,
|
||||
0x1DB7E627, 0x808594FE,
|
||||
0x82668268, 0x655C7783,
|
||||
};
|
||||
|
||||
|
||||
static u32 SetupMaxRdPattern(struct MCTStatStruc *pMCTstat,
|
||||
struct DCTStatStruc *pDCTstat,
|
||||
u32 *buffer)
|
||||
{
|
||||
/* 1. Copy the alpha and Beta patterns from ROM to Cache,
|
||||
* aligning on 16 byte boundary
|
||||
* 2. Set the ptr to Cacheable copy in DCTStatstruc.PtrPatternBufA
|
||||
* for Alpha
|
||||
* 3. Set the ptr to Cacheable copy in DCTStatstruc.PtrPatternBufB
|
||||
* for Beta
|
||||
*/
|
||||
|
||||
u32 *buf;
|
||||
u8 i;
|
||||
|
||||
buf = (u32 *)(((u32)buffer + 0x10) & (0xfffffff0));
|
||||
|
||||
for(i = 0; i < (16 * 3); i++) {
|
||||
buf[i] = TestMaxRdLAtPattern_D[i];
|
||||
}
|
||||
|
||||
return (u32)buf;
|
||||
|
||||
}
|
||||
|
||||
|
||||
void TrainMaxReadLatency_D(struct MCTStatStruc *pMCTstat,
|
||||
struct DCTStatStruc *pDCTstatA)
|
||||
{
|
||||
u8 Node;
|
||||
|
||||
for(Node = 0; Node < MAX_NODES_SUPPORTED; Node++) {
|
||||
struct DCTStatStruc *pDCTstat;
|
||||
pDCTstat = pDCTstatA + Node;
|
||||
|
||||
if(!pDCTstat->NodePresent)
|
||||
break;
|
||||
|
||||
if(pDCTstat->DCTSysLimit)
|
||||
maxRdLatencyTrain_D(pMCTstat, pDCTstat);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat,
|
||||
struct DCTStatStruc *pDCTstat)
|
||||
{
|
||||
u8 Channel;
|
||||
u32 TestAddr0;
|
||||
u8 _DisableDramECC = 0, _Wrap32Dis = 0, _SSE2 = 0;
|
||||
u16 MaxRdLatDly;
|
||||
u8 RcvrEnDly = 0;
|
||||
u32 PatternBuffer[60]; // FIXME: why not 48 + 4
|
||||
u32 Margin;
|
||||
u32 addr;
|
||||
u32 cr4;
|
||||
u32 lo, hi;
|
||||
|
||||
u8 valid;
|
||||
u32 pattern_buf;
|
||||
|
||||
cr4 = read_cr4();
|
||||
if(cr4 & (1<<9)) { /* save the old value */
|
||||
_SSE2 = 1;
|
||||
}
|
||||
cr4 |= (1<<9); /* OSFXSR enable SSE2 */
|
||||
write_cr4(cr4);
|
||||
|
||||
addr = HWCR;
|
||||
_RDMSR(addr, &lo, &hi);
|
||||
if(lo & (1<<17)) { /* save the old value */
|
||||
_Wrap32Dis = 1;
|
||||
}
|
||||
lo |= (1<<17); /* HWCR.wrap32dis */
|
||||
lo &= ~(1<<15); /* SSEDIS */
|
||||
/* Setting wrap32dis allows 64-bit memory references in
|
||||
real mode */
|
||||
_WRMSR(addr, lo, hi);
|
||||
|
||||
_DisableDramECC = mct_DisableDimmEccEn_D(pMCTstat, pDCTstat);
|
||||
|
||||
pattern_buf = SetupMaxRdPattern(pMCTstat, pDCTstat, PatternBuffer);
|
||||
|
||||
for (Channel = 0; Channel < 2; Channel++) {
|
||||
print_debug_dqs("\tMaxRdLatencyTrain51: Channel ",Channel, 1);
|
||||
pDCTstat->Channel = Channel;
|
||||
|
||||
if( (pDCTstat->Status & (1 << SB_128bitmode)) && Channel)
|
||||
break; /*if ganged mode, skip DCT 1 */
|
||||
|
||||
TestAddr0 = GetMaxRdLatTestAddr_D(pMCTstat, pDCTstat, Channel, &RcvrEnDly, &valid);
|
||||
if(!valid) /* Address not supported on current CS */
|
||||
continue;
|
||||
/* rank 1 of DIMM, testpattern 0 */
|
||||
WriteMaxRdLat1CLTestPattern_D(pattern_buf, TestAddr0);
|
||||
|
||||
MaxRdLatDly = mct_GetStartMaxRdLat_D(pMCTstat, pDCTstat, Channel, RcvrEnDly, &Margin);
|
||||
print_debug_dqs("\tMaxRdLatencyTrain52: MaxRdLatDly start ", MaxRdLatDly, 2);
|
||||
print_debug_dqs("\tMaxRdLatencyTrain52: MaxRdLatDly Margin ", Margin, 2);
|
||||
while(MaxRdLatDly < MAX_RD_LAT) { /* sweep Delay value here */
|
||||
mct_setMaxRdLatTrnVal_D(pDCTstat, Channel, MaxRdLatDly);
|
||||
ReadMaxRdLat1CLTestPattern_D(TestAddr0);
|
||||
if( CompareMaxRdLatTestPattern_D(pattern_buf, TestAddr0) == DQS_PASS)
|
||||
break;
|
||||
SetTargetWTIO_D(TestAddr0);
|
||||
FlushMaxRdLatTestPattern_D(TestAddr0);
|
||||
ResetTargetWTIO_D();
|
||||
MaxRdLatDly++;
|
||||
}
|
||||
print_debug_dqs("\tMaxRdLatencyTrain53: MaxRdLatDly end ", MaxRdLatDly, 2);
|
||||
mct_setMaxRdLatTrnVal_D(pDCTstat, Channel, MaxRdLatDly + Margin);
|
||||
}
|
||||
|
||||
if(_DisableDramECC) {
|
||||
mct_EnableDimmEccEn_D(pMCTstat, pDCTstat, _DisableDramECC);
|
||||
}
|
||||
|
||||
if(!_Wrap32Dis) {
|
||||
addr = HWCR;
|
||||
_RDMSR(addr, &lo, &hi);
|
||||
lo &= ~(1<<17); /* restore HWCR.wrap32dis */
|
||||
_WRMSR(addr, lo, hi);
|
||||
}
|
||||
if(!_SSE2){
|
||||
cr4 = read_cr4();
|
||||
cr4 &= ~(1<<9); /* restore cr4.OSFXSR */
|
||||
write_cr4(cr4);
|
||||
}
|
||||
|
||||
#if DQS_TRAIN_DEBUG > 0
|
||||
{
|
||||
u8 Channel;
|
||||
print_debug("maxRdLatencyTrain: CH_MaxRdLat:\n");
|
||||
for(Channel = 0; Channel<2; Channel++) {
|
||||
print_debug("Channel:"); print_debug_hex8(Channel);
|
||||
print_debug(": ");
|
||||
print_debug_hex8( pDCTstat->CH_MaxRdLat[Channel] );
|
||||
print_debug("\n");
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
static void mct_setMaxRdLatTrnVal_D(struct DCTStatStruc *pDCTstat,
|
||||
u8 Channel, u16 MaxRdLatVal)
|
||||
{
|
||||
u8 i;
|
||||
u32 reg;
|
||||
u32 dev;
|
||||
u32 val;
|
||||
|
||||
if (pDCTstat->GangedMode) {
|
||||
Channel = 0; // for safe
|
||||
for (i=0; i<2; i++)
|
||||
pDCTstat->CH_MaxRdLat[i] = MaxRdLatVal;
|
||||
} else {
|
||||
pDCTstat->CH_MaxRdLat[Channel] = MaxRdLatVal;
|
||||
}
|
||||
|
||||
dev = pDCTstat->dev_dct;
|
||||
reg = 0x78 + Channel * 0x100;
|
||||
val = Get_NB32(dev, reg);
|
||||
val &= ~(0x3ff<<22);
|
||||
val |= MaxRdLatVal<<22;
|
||||
/* program MaxRdLatency to correspond with current delay */
|
||||
Set_NB32(dev, reg, val);
|
||||
|
||||
}
|
||||
|
||||
|
||||
static u8 CompareMaxRdLatTestPattern_D(u32 pattern_buf, u32 addr)
|
||||
{
|
||||
/* Compare only the first beat of data. Since target addrs are cache
|
||||
* line aligned, the Channel parameter is used to determine which cache
|
||||
* QW to compare.
|
||||
*/
|
||||
|
||||
u32 *test_buf = (u32 *)pattern_buf;
|
||||
u32 addr_lo;
|
||||
u32 val, val_test;
|
||||
int i;
|
||||
u8 ret = DQS_PASS;
|
||||
|
||||
SetUpperFSbase(addr);
|
||||
addr_lo = addr<<8;
|
||||
|
||||
_EXECFENCE;
|
||||
for (i=0; i<(16*3); i++) {
|
||||
val = read32_fs(addr_lo);
|
||||
val_test = test_buf[i];
|
||||
|
||||
print_debug_dqs_pair("\t\t\t\t\t\ttest_buf = ", (u32)test_buf, " value = ", val_test, 5);
|
||||
print_debug_dqs_pair("\t\t\t\t\t\ttaddr_lo = ", addr_lo, " value = ", val, 5);
|
||||
if(val != val_test) {
|
||||
ret = DQS_FAIL;
|
||||
break;
|
||||
}
|
||||
addr_lo += 4;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static u32 GetMaxRdLatTestAddr_D(struct MCTStatStruc *pMCTstat,
|
||||
struct DCTStatStruc *pDCTstat,
|
||||
u8 Channel, u8 *MaxRcvrEnDly,
|
||||
u8 *valid)
|
||||
{
|
||||
u8 Max = 0;
|
||||
|
||||
u8 Channel_Max = 0;
|
||||
u8 d;
|
||||
u8 d_Max = 0;
|
||||
|
||||
u8 Byte;
|
||||
u32 TestAddr0 = 0;
|
||||
u8 ch, ch_start, ch_end;
|
||||
u8 bn;
|
||||
|
||||
bn = 8;
|
||||
|
||||
if(pDCTstat->Status & (1 << SB_128bitmode)) {
|
||||
ch_start = 0;
|
||||
ch_end = 2;
|
||||
} else {
|
||||
ch_start = Channel;
|
||||
ch_end = Channel + 1;
|
||||
}
|
||||
|
||||
*valid = 0;
|
||||
|
||||
for(ch = ch_start; ch < ch_end; ch++) {
|
||||
for(d=0; d<4; d++) {
|
||||
for(Byte = 0; Byte<bn; Byte++) {
|
||||
u8 tmp;
|
||||
tmp = pDCTstat->CH_D_B_RCVRDLY[ch][d][Byte];
|
||||
if(tmp>Max) {
|
||||
Max = tmp;
|
||||
Channel_Max = Channel;
|
||||
d_Max = d;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if(mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, Channel_Max, d_Max << 1)) {
|
||||
TestAddr0 = mct_GetMCTSysAddr_D(pMCTstat, pDCTstat, Channel_Max, d_Max << 1, valid);
|
||||
}
|
||||
|
||||
if(*valid)
|
||||
*MaxRcvrEnDly = Max;
|
||||
|
||||
return TestAddr0;
|
||||
|
||||
}
|
||||
|
||||
u8 mct_GetStartMaxRdLat_D(struct MCTStatStruc *pMCTstat,
|
||||
struct DCTStatStruc *pDCTstat,
|
||||
u8 Channel, u8 DQSRcvEnDly, u32 *Margin)
|
||||
{
|
||||
u32 SubTotal;
|
||||
u32 val;
|
||||
u32 valx;
|
||||
u32 valxx;
|
||||
u32 index_reg;
|
||||
u32 reg_off;
|
||||
u32 dev;
|
||||
|
||||
if(pDCTstat->GangedMode)
|
||||
Channel = 0;
|
||||
|
||||
index_reg = 0x98 + 0x100 * Channel;
|
||||
|
||||
reg_off = 0x100 * Channel;
|
||||
dev = pDCTstat->dev_dct;
|
||||
|
||||
/* Multiply the CAS Latency by two to get a number of 1/2 MEMCLKs units.*/
|
||||
val = Get_NB32(dev, 0x88 + reg_off);
|
||||
SubTotal = ((val & 0x0f) + 1) << 1; /* SubTotal is 1/2 Memclk unit */
|
||||
|
||||
/* If registered DIMMs are being used then add 1 MEMCLK to the sub-total*/
|
||||
val = Get_NB32(dev, 0x90 + reg_off);
|
||||
if(!(val & (1 << UnBuffDimm)))
|
||||
SubTotal += 2;
|
||||
|
||||
/*If the address prelaunch is setup for 1/2 MEMCLKs then add 1,
|
||||
* else add 2 to the sub-total. if (AddrCmdSetup || CsOdtSetup
|
||||
* || CkeSetup) then K := K + 2; */
|
||||
val = Get_NB32_index_wait(dev, index_reg, 0x04);
|
||||
if(!(val & 0x00202020))
|
||||
SubTotal += 1;
|
||||
else
|
||||
SubTotal += 2;
|
||||
|
||||
/* If the F2x[1, 0]78[RdPtrInit] field is 4, 5, 6 or 7 MEMCLKs,
|
||||
* then add 4, 3, 2, or 1 MEMCLKs, respectively to the sub-total. */
|
||||
val = Get_NB32(dev, 0x78 + reg_off);
|
||||
SubTotal += 8 - (val & 0x0f);
|
||||
|
||||
/* Convert bits 7-5 (also referred to as the course delay) of the current
|
||||
* (or worst case) DQS receiver enable delay to 1/2 MEMCLKs units,
|
||||
* rounding up, and add this to the sub-total. */
|
||||
SubTotal += DQSRcvEnDly >> 5; /*BOZO-no rounding up */
|
||||
|
||||
SubTotal <<= 1; /*scale 1/2 MemClk to 1/4 MemClk */
|
||||
|
||||
/* Convert the sub-total (in 1/2 MEMCLKs) to northbridge clocks (NCLKs)
|
||||
* as follows (assuming DDR400 and assuming that no P-state or link speed
|
||||
* changes have occurred). */
|
||||
|
||||
/*New formula:
|
||||
SubTotal *= 3*(Fn2xD4[NBFid]+4)/(3+Fn2x94[MemClkFreq])/2 */
|
||||
val = Get_NB32(dev, 0x94 + reg_off);
|
||||
/* SubTotal div 4 to scale 1/4 MemClk back to MemClk */
|
||||
val &= 7;
|
||||
if (val == 4) {
|
||||
val++; /* adjust for DDR2-1066 */
|
||||
}
|
||||
valx = (val + 3) << 2; /* SubTotal div 4 to scale 1/4 MemClk back to MemClk */
|
||||
|
||||
|
||||
val = Get_NB32(pDCTstat->dev_nbmisc, 0xD4);
|
||||
val = ((val & 0x1f) + 4 ) * 3;
|
||||
|
||||
/* Calculate 1 MemClk + 1 NCLK delay in NCLKs for margin */
|
||||
valxx = val << 2;
|
||||
valxx /= valx;
|
||||
if (valxx % valx)
|
||||
valxx++; /* round up */
|
||||
valxx++; /* add 1NCLK */
|
||||
*Margin = valxx; /* one MemClk delay in NCLKs and one additional NCLK */
|
||||
|
||||
val *= SubTotal;
|
||||
|
||||
val /= valx;
|
||||
if (val % valx)
|
||||
val++; /* round up */
|
||||
|
||||
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
|
||||
59
src/northbridge/amd/amdmct/wrappers/mcti.h
Normal file
59
src/northbridge/amd/amdmct/wrappers/mcti.h
Normal file
@ -0,0 +1,59 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
|
||||
#define SERVER 0
|
||||
#define DESKTOP 1
|
||||
//#define MOBILE 2
|
||||
#define REV_F 0
|
||||
#define REV_DR 1
|
||||
#define REV_FDR 2
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
COMMENT OUT ALL BUT 1
|
||||
----------------------------------------------------------------------------*/
|
||||
//#define BUILD_VERSION REV_F /*BIOS supports rev F only*/
|
||||
//#define BUILD_VERSION REV_DR /*BIOS supports rev 10 only*/
|
||||
//#define BUILD_VERSION REV_FDR /*BIOS supports both rev F and 10*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
COMMENT OUT ALL BUT 1
|
||||
----------------------------------------------------------------------------*/
|
||||
#ifndef SYSTEM_TYPE
|
||||
#define SYSTEM_TYPE SERVER
|
||||
//#define SYSTEM_TYPE DESKTOP
|
||||
//#define SYSTEM_TYPE MOBILE
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
COMMENT OUT ALL BUT 1
|
||||
----------------------------------------------------------------------------*/
|
||||
#define UMA_SUPPORT 0 /*Not supported */
|
||||
//#define UMA_SUPPORT 1 /*Supported */
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
UPDATE AS NEEDED
|
||||
----------------------------------------------------------------------------*/
|
||||
#define MAX_NODES_SUPPORTED 8
|
||||
#define MAX_DIMMS_SUPPORTED 8
|
||||
#define MAX_CS_SUPPORTED 8
|
||||
#define MCT_TRNG_KEEPOUT_START 0x00000C00
|
||||
#define MCT_TRNG_KEEPOUT_END 0x00000CFF
|
||||
|
||||
338
src/northbridge/amd/amdmct/wrappers/mcti_d.c
Normal file
338
src/northbridge/amd/amdmct/wrappers/mcti_d.c
Normal file
@ -0,0 +1,338 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/* Call-backs */
|
||||
|
||||
u16 mctGet_NVbits(u8 index)
|
||||
{
|
||||
u16 val = 0;
|
||||
|
||||
switch (index) {
|
||||
case NV_PACK_TYPE:
|
||||
#if SYSTEM_TYPE == SERVER
|
||||
val = 0;
|
||||
#elif SYSTEM_TYPE == DESKTOP
|
||||
val = 1;
|
||||
//#elif SYSTEM_TYPE == MOBILE
|
||||
// val = 2;
|
||||
#endif
|
||||
break;
|
||||
case NV_MAX_NODES:
|
||||
val = MAX_NODES_SUPPORTED;
|
||||
break;
|
||||
case NV_MAX_DIMMS:
|
||||
//val = MAX_DIMMS_SUPPORTED;
|
||||
val = 8;
|
||||
break;
|
||||
case NV_MAX_MEMCLK:
|
||||
/* Maximum platform supported memclk */
|
||||
//val = 200; /* 200MHz(DDR400) */
|
||||
//val = 266; /* 266MHz(DDR533) */
|
||||
//val = 333; /* 333MHz(DDR667) */
|
||||
val = 400; /* 400MHz(DDR800) */
|
||||
break;
|
||||
case NV_ECC_CAP:
|
||||
#if SYSTEM_TYPE == SERVER
|
||||
val = 1; /* memory bus ECC capable */
|
||||
#else
|
||||
val = 0; /* memory bus ECC not capable */
|
||||
#endif
|
||||
break;
|
||||
case NV_4RANKType:
|
||||
/* Quad Rank DIMM slot type */
|
||||
val = 0; /* normal */
|
||||
//val = 1; /* R4 (registered DIMMs in AMD server configuration) */
|
||||
//val = 2; /* S4 (Unbuffered SO-DIMMS) */
|
||||
break;
|
||||
case NV_BYPMAX:
|
||||
#if (UMA_SUPPORT == 0)
|
||||
val = 4;
|
||||
#elif (UMA_SUPPORT == 1)
|
||||
val = 7;
|
||||
#endif
|
||||
break;
|
||||
case NV_RDWRQBYP:
|
||||
#if (UMA_SUPPORT == 0)
|
||||
val = 2;
|
||||
#elif (UMA_SUPPORT == 1)
|
||||
val = 3;
|
||||
#endif
|
||||
break;
|
||||
case NV_MCTUSRTMGMODE:
|
||||
val = 0; /* Automatic (recommended) */
|
||||
//val = 1; /* Limited */
|
||||
//val = 2; /* Manual */
|
||||
break;
|
||||
case NV_MemCkVal:
|
||||
//val = 0; /* 200MHz */
|
||||
//val = 1; /* 266MHz */
|
||||
val = 2; /* 333MHz */
|
||||
break;
|
||||
case NV_BankIntlv:
|
||||
/* Bank (chip select) interleaving */
|
||||
//val = 0; /* disabled */
|
||||
val = 1; /* enabled (recommended) */
|
||||
break;
|
||||
case NV_MemHole:
|
||||
//val = 0; /* Disabled */
|
||||
val = 1; /* Enabled (recommended) */
|
||||
break;
|
||||
case NV_AllMemClks:
|
||||
val = 0; /* Normal (only to slots that have enabled DIMMs) */
|
||||
//val = 1; /* Enable all memclocks */
|
||||
break;
|
||||
case NV_SPDCHK_RESTRT:
|
||||
val = 0; /* Exit current node initialization if any DIMM has SPD checksum error */
|
||||
//val = 1; /* Ignore faulty SPD checksum (DIMM will still be disabled), continue current node intialization */
|
||||
break;
|
||||
case NV_DQSTrainCTL:
|
||||
//val = 0; /*Skip dqs training */
|
||||
val = 1; /* Perform dqs training */
|
||||
break;
|
||||
case NV_NodeIntlv:
|
||||
val = 0; /* Disabled (recommended) */
|
||||
//val = 1; /* Enable */
|
||||
break;
|
||||
case NV_BurstLen32:
|
||||
#if (UMA_SUPPORT == 0)
|
||||
val = 0; /* 64 byte mode */
|
||||
#elif (UMA_SUPPORT == 1)
|
||||
val = 1; /* 32 byte mode */
|
||||
#endif
|
||||
break;
|
||||
case NV_CKE_PDEN:
|
||||
//val = 0; /* Disable */
|
||||
val = 1; /* Enable */
|
||||
break;
|
||||
case NV_CKE_CTL:
|
||||
val = 0; /* per channel control */
|
||||
//val = 1; /* per chip select control */
|
||||
break;
|
||||
case NV_CLKHZAltVidC3:
|
||||
val = 0; /* disable */
|
||||
//val = 1; /* enable */
|
||||
break;
|
||||
case NV_BottomIO:
|
||||
val = 0xC0; /* address bits [31:24] */
|
||||
break;
|
||||
case NV_BottomUMA:
|
||||
#if (UMA_SUPPORT == 0)
|
||||
val = 0xC0; /* address bits [31:24] */
|
||||
#elif (UMA_SUPPORT == 1)
|
||||
val = 0xB0; /* address bits [31:24] */
|
||||
#endif
|
||||
break;
|
||||
case NV_ECC:
|
||||
#if (SYSTEM_TYPE == SERVER)
|
||||
val = 1; /* Enable */
|
||||
#else
|
||||
val = 0; /* Disable */
|
||||
#endif
|
||||
break;
|
||||
case NV_NBECC:
|
||||
#if (SYSTEM_TYPE == SERVER)
|
||||
val = 1; /* Enable */
|
||||
#else
|
||||
val = 0; /* Disable */
|
||||
#endif
|
||||
break;
|
||||
case NV_ChipKill:
|
||||
#if (SYSTEM_TYPE == SERVER)
|
||||
val = 1; /* Enable */
|
||||
#else
|
||||
val = 0; /* Disable */
|
||||
#endif
|
||||
break;
|
||||
case NV_ECCRedir:
|
||||
val = 0; /* Disable */
|
||||
//val = 1; /* Enable */
|
||||
break;
|
||||
case NV_DramBKScrub:
|
||||
val = 0x00; /* Disabled */
|
||||
//val = 0x01; /* 40ns */
|
||||
//val = 0x02; /* 80ns */
|
||||
//val = 0x03; /* 160ns */
|
||||
//val = 0x04; /* 320ns */
|
||||
//val = 0x05; /* 640ns */
|
||||
//val = 0x06; /* 1.28us */
|
||||
//val = 0x07; /* 2.56us */
|
||||
//val = 0x08; /* 5.12us */
|
||||
//val = 0x09; /* 10.2us */
|
||||
//val = 0x0a; /* 20.5us */
|
||||
//val = 0x0b; /* 41us */
|
||||
//val = 0x0c; /* 81.9us */
|
||||
//val = 0x0d; /* 163.8us */
|
||||
//val = 0x0e; /* 327.7us */
|
||||
//val = 0x0f; /* 655.4us */
|
||||
//val = 0x10; /* 1.31ms */
|
||||
//val = 0x11; /* 2.62ms */
|
||||
//val = 0x12; /* 5.24ms */
|
||||
//val = 0x13; /* 10.49ms */
|
||||
//val = 0x14; /* 20.97sms */
|
||||
//val = 0x15; /* 42ms */
|
||||
//val = 0x16; /* 84ms */
|
||||
break;
|
||||
case NV_L2BKScrub:
|
||||
val = 0; /* Disabled - See L2Scrub in BKDG */
|
||||
break;
|
||||
case NV_DCBKScrub:
|
||||
val = 0; /* Disabled - See DcacheScrub in BKDG */
|
||||
break;
|
||||
case NV_CS_SpareCTL:
|
||||
val = 0; /* Disabled */
|
||||
//val = 1; /* Enabled */
|
||||
case NV_SyncOnUnEccEn:
|
||||
val = 0; /* Disabled */
|
||||
//val = 1; /* Enabled */
|
||||
case NV_Unganged:
|
||||
/* channel interleave is better performance than ganged mode at this time */
|
||||
val = 1; /* Enabled */
|
||||
//val = 0; /* Disabled */
|
||||
case NV_ChannelIntlv:
|
||||
val = 5; /* Disabled */ /* Not currently checked in mctchi_d.c */
|
||||
/* Bit 0 = 0 - Disable
|
||||
* 1 - Enable
|
||||
* Bits[2:1] = 00b - Address bits 6
|
||||
* 01b - Address bits 1
|
||||
* 10b - Hash*, XOR of address bits [20:16, 6]
|
||||
* 11b - Hash*, XOR of address bits [20:16, 9]
|
||||
*/
|
||||
|
||||
}
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
|
||||
void mctHookAfterDIMMpre(void)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat)
|
||||
{
|
||||
pDCTstat->PresetmaxFreq = 400;
|
||||
}
|
||||
|
||||
|
||||
void mctAdjustAutoCycTmg(void)
|
||||
{
|
||||
}
|
||||
|
||||
void mctAdjustAutoCycTmg_D(void)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
void mctHookAfterAutoCycTmg(void)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
void mctGetCS_ExcludeMap(void)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
void mctHookAfterAutoCfg(void)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
void mctHookAfterPSCfg(void)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
void mctHookAfterHTMap(void)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
void mctHookAfterCPU(void)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
void mctSaveDQSSigTmg_D(void)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
void mctGetDQSSigTmg_D(void)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
void mctHookBeforeECC(void)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
void mctHookAfterECC(void)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
void mctInitMemGPIOs_A(void)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
void mctInitMemGPIOs_A_D(void)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
void mctNodeIDDebugPort_D(void)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
void mctWarmReset(void)
|
||||
{
|
||||
}
|
||||
|
||||
void mctWarmReset_D(void)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
void mctHookBeforeDramInit(void)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
void mctHookAfterDramInit(void)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
void mctHookBeforeAnyTraining(void)
|
||||
{
|
||||
}
|
||||
|
||||
void mctHookAfterAnyTraining(void)
|
||||
{
|
||||
}
|
||||
|
||||
u32 mctGetLogicalCPUID_D(u8 node)
|
||||
{
|
||||
return mctGetLogicalCPUID(node);
|
||||
}
|
||||
Reference in New Issue
Block a user