tgl mainboards: Move SATA related settings into SATA device scope

Change-Id: I03508c50fe56fd85f8bf89f724863e546d4140e9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
Felix Singer 2024-06-27 23:25:32 +02:00
parent df141f61cc
commit 8c1daf9751
2 changed files with 11 additions and 12 deletions

View File

@ -141,12 +141,6 @@ chip soc/intel/tigerlake
register "PcieClkSrcUsage[5]" = "PCIE_CLK_NOTUSED"
register "PcieClkSrcUsage[6]" = "PCIE_CLK_NOTUSED"
# Enable SATA
register "SataSalpSupport" = "1"
register "SataPortsEnable[1]" = "1"
register "SataPortsDevSlp[1]" = "1"
register "SataPortsEnableDitoConfig[1]" = "1"
register "SerialIoI2cMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C1] = PchSerialIoPci,
@ -462,7 +456,12 @@ chip soc/intel/tigerlake
device ref i2c2 on end
device ref i2c3 on end
device ref heci1 on end
device ref sata on end
device ref sata on
register "SataSalpSupport" = "1"
register "SataPortsEnable[1]" = "1"
register "SataPortsDevSlp[1]" = "1"
register "SataPortsEnableDitoConfig[1]" = "1"
end
device ref pcie_rp7 on end
device ref pcie_rp8 on
probe DB_SD SD_GL9755S

View File

@ -59,10 +59,6 @@ chip soc/intel/tigerlake
register "PcieClkSrcUsage[2]" = "0x3"
register "PcieClkSrcUsage[3]" = "0x8"
register "SataSalpSupport" = "1"
register "SataPortsEnable[0]" = "1"
register "SataPortsEnable[1]" = "1"
# enabling EDP in PortA
register "DdiPortAConfig" = "DDI_PORT_CFG_EDP"
@ -267,7 +263,11 @@ chip soc/intel/tigerlake
device ref csme2 off end
device ref heci3 off end
device ref heci4 off end
device ref sata on end
device ref sata on
register "SataSalpSupport" = "1"
register "SataPortsEnable[0]" = "1"
register "SataPortsEnable[1]" = "1"
end
device ref i2c4 off end
device ref i2c5 on end
device ref uart2 on end