soc/mediatek/mt8195: Enable SCP SRAM
Enable SCP SRAM to allow module in SCPSYS to access DRAM. TEST=AFE acess DRAM successfully Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I40862f8d74e5aa17361f1c91ea31a10b0a4ffb31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54014 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@@ -6,6 +6,7 @@
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#include <soc/mt6359p.h>
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#include <soc/pmif.h>
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#include <soc/rtc.h>
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#include <soc/scp.h>
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void platform_romstage_main(void)
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{
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@@ -14,4 +15,5 @@ void platform_romstage_main(void)
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mt6315_init();
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clk_buf_init();
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rtc_boot();
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scp_rsi_enable();
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}
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@@ -27,6 +27,7 @@ romstage-y += ../common/flash_controller.c
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romstage-y += ../common/gpio.c gpio.c
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romstage-y += ../common/i2c.c i2c.c
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romstage-y += ../common/pll.c pll.c
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romstage-y += scp.c
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romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
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romstage-y += ../common/timer.c timer.c
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romstage-y += ../common/uart.c
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14
src/soc/mediatek/mt8195/include/soc/scp.h
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src/soc/mediatek/mt8195/include/soc/scp.h
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@@ -0,0 +1,14 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef SOC_MEDIATEK_MT8195_SCP_H
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#define SOC_MEDIATEK_MT8195_SCP_H
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#include <soc/addressmap.h>
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#define SCP_SRAM_PDN_DISABLE_VAL 0xFFFFFFFF
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#define REG_L1TCM_SRAM_PDN (void *)(SCP_CFG_BASE + 0x2102C)
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void scp_rsi_enable(void);
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void scp_rsi_disable(void);
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#endif
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src/soc/mediatek/mt8195/scp.c
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src/soc/mediatek/mt8195/scp.c
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@@ -0,0 +1,19 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/mmio.h>
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#include <soc/scp.h>
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void scp_rsi_enable(void)
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{
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u32 val;
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for (val = SCP_SRAM_PDN_DISABLE_VAL; val != 0U;) {
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val = val >> 1;
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write32(REG_L1TCM_SRAM_PDN, val);
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}
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}
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void scp_rsi_disable(void)
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{
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write32(REG_L1TCM_SRAM_PDN, SCP_SRAM_PDN_DISABLE_VAL);
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}
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