soc/mediatek/mt8195: Enable SCP SRAM

Enable SCP SRAM to allow module in SCPSYS to access DRAM.

TEST=AFE acess DRAM successfully

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I40862f8d74e5aa17361f1c91ea31a10b0a4ffb31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54014
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/cherry/romstage.c

@@ -6,6 +6,7 @@
 #include <soc/mt6359p.h>
 #include <soc/pmif.h>
 #include <soc/rtc.h>
+#include <soc/scp.h>
 
 void platform_romstage_main(void)
 {
@@ -14,4 +15,5 @@ void platform_romstage_main(void)
 	mt6315_init();
 	clk_buf_init();
 	rtc_boot();
+	scp_rsi_enable();
 }

src/soc/mediatek/mt8195/Makefile.inc

@@ -27,6 +27,7 @@ romstage-y += ../common/flash_controller.c
 romstage-y += ../common/gpio.c gpio.c
 romstage-y += ../common/i2c.c i2c.c
 romstage-y += ../common/pll.c pll.c
+romstage-y += scp.c
 romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
 romstage-y += ../common/timer.c timer.c
 romstage-y += ../common/uart.c

src/soc/mediatek/mt8195/include/soc/scp.h

@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_MEDIATEK_MT8195_SCP_H
+#define SOC_MEDIATEK_MT8195_SCP_H
+
+#include <soc/addressmap.h>
+
+#define SCP_SRAM_PDN_DISABLE_VAL	0xFFFFFFFF
+
+#define REG_L1TCM_SRAM_PDN		(void *)(SCP_CFG_BASE + 0x2102C)
+
+void scp_rsi_enable(void);
+void scp_rsi_disable(void);
+#endif

src/soc/mediatek/mt8195/scp.c

@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/mmio.h>
+#include <soc/scp.h>
+
+void scp_rsi_enable(void)
+{
+	u32 val;
+
+	for (val = SCP_SRAM_PDN_DISABLE_VAL; val != 0U;) {
+		val = val >> 1;
+		write32(REG_L1TCM_SRAM_PDN, val);
+	}
+}
+
+void scp_rsi_disable(void)
+{
+	write32(REG_L1TCM_SRAM_PDN, SCP_SRAM_PDN_DISABLE_VAL);
+}