soc/amd/glinda: drop code for non-existing eMMC controller

Glinda doesn't have an eMMC controller and also doesn't have GPIO pins
that eMMC signals can be multiplexed on, so drop the eMMC related code
from Glinda.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I49ead01075780ea97dae99a36632f7659fd00587
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74662
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/amd/glinda/Kconfig

@@ -46,7 +46,6 @@ config SOC_AMD_GLINDA
 	select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS	# TODO: Check if this is still correct
 	select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH
 	select SOC_AMD_COMMON_BLOCK_DATA_FABRIC
-	select SOC_AMD_COMMON_BLOCK_EMMC		# TODO: Check if this is still correct
 	select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES # TODO: Check if this is still correct
 	select SOC_AMD_COMMON_BLOCK_GRAPHICS		# TODO: Check if this is still correct
 	select SOC_AMD_COMMON_BLOCK_HAS_ESPI		# TODO: Check if this is still correct

src/soc/amd/glinda/acpi/pci_int_defs.asl

@@ -22,9 +22,6 @@ IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
 	PIRG, 0x00000008,	/* Index 6: INTG */
 	PIRH, 0x00000008,	/* Index 7: INTH */
 
-	Offset (0x43),
-	PMMC, 0x00000008,	/* Index 0x43: eMMC */
-
 	Offset (0x62),
 	PGPI, 0x00000008,	/* Index 0x62: GPIO */
 
@@ -51,9 +48,6 @@ IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
 	IORG, 0x00000008,	/* Index 0x86: INTG */
 	IORH, 0x00000008,	/* Index 0x87: INTH */
 
-	Offset (0xC3),
-	IMMC, 0x00000008,	/* Index 0xC3: eMMC */
-
 	Offset (0xE2),
 	IGPI, 0x00000008,	/* Index 0xE2: GPIO */
 

src/soc/amd/glinda/chipset.cb

@@ -95,5 +95,4 @@ chip soc/amd/glinda
 	device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end
 	device mmio 0xfedcf000 alias uart_3 off ops amd_uart_mmio_ops end
 	device mmio 0xfedd1000 alias uart_4 off ops amd_uart_mmio_ops end
-	device mmio 0xfedd5000 alias emmc off ops amd_emmc_mmio_ops end
 end

src/soc/amd/glinda/fch.c

@@ -53,7 +53,6 @@ static const struct irq_idx_name irq_association[] = {
 	{ PIRQ_GPIOA,	"GPIOa" },
 	{ PIRQ_GPIOB,	"GPIOb" },
 	{ PIRQ_GPIOC,	"GPIOc" },
-	{ PIRQ_EMMC,	"eMMC" },
 	{ PIRQ_GPP0,	"GPP0" },
 	{ PIRQ_GPP1,	"GPP1" },
 	{ PIRQ_GPP2,	"GPP2" },

src/soc/amd/glinda/include/soc/amd_pci_int_defs.h

@@ -40,9 +40,7 @@
 #define PIRQ_GPIOA	0x21	/* GPIOa from PAD_FANIN0 */
 #define PIRQ_GPIOB	0x22	/* GPIOb from PAD_FANOUT0 */
 #define PIRQ_GPIOC	0x23	/* GPIOc no IRQ connected */
-/* 0x24-0x42 reserved */
-#define PIRQ_EMMC	0x43	/* eMMC */
-/* 0x44-0x4f reserved */
+/* 0x24-0x4f reserved */
 #define PIRQ_GPP0	0x50	/* GPPInt0 */
 #define PIRQ_GPP1	0x51	/* GPPInt1 */
 #define PIRQ_GPP2	0x52	/* GPPInt2 */

src/soc/amd/glinda/include/soc/aoac_defs.h

@@ -20,6 +20,5 @@
 #define FCH_AOAC_DEV_UART4		20
 #define FCH_AOAC_DEV_UART3		26
 #define FCH_AOAC_DEV_ESPI		27
-#define FCH_AOAC_DEV_EMMC		28
 
 #endif /* AMD_GLINDA_AOAC_DEFS_H */

src/soc/amd/glinda/include/soc/iomap.h

@@ -36,9 +36,6 @@
 #define APU_DMAC4_BASE			0xfedd0000
 #define APU_UART4_BASE			0xfedd1000
 
-#define APU_EMMC_BASE			0xfedd5000
-#define APU_EMMC_CONFIG_BASE		0xfedd5800
-
 #endif /* ENV_X86 */
 
 #define FLASH_BASE_ADDR			((0xffffffff - CONFIG_ROM_SIZE) + 1)