sb/intel/i82801dx: Improve LPC device early init
Make the implementation more similar to i82801gx, enabling ACPI PM and GPIO register spaces already in bootblock. Change-Id: I41ad8622801dbbadafdc37359d521eed42256e63 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
@@ -8,10 +8,9 @@
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void mainboard_romstage_entry(void)
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{
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/* Perform some early chipset initialization required
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* before RAM initialization can work
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*/
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/* FIXME: Keep until flashed bootblock has these. */
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i82801dx_early_init();
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i82801dx_lpc_setup();
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sdram_initialize();
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@@ -2,6 +2,11 @@
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ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801DX),y)
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bootblock-y += bootblock.c
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bootblock-y += early_init.c
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romstage-y += early_init.c
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ramstage-y += i82801dx.c
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ramstage-y += ac97.c
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ramstage-y += fadt.c
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@@ -10,8 +15,4 @@ ramstage-y += lpc.c
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ramstage-y += usb.c
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ramstage-y += usb2.c
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romstage-y += early_smbus.c
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bootblock-y += bootblock.c
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endif
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@@ -8,4 +8,9 @@ void bootblock_early_southbridge_init(void)
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/* Set FWH IDs for 2 MB flash part. */
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if (CONFIG_ROM_SIZE == 0x200000)
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pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xe8, 0x00001111);
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/* Setup decode ports and LPC I/F enables. */
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i82801dx_early_init();
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i82801dx_lpc_setup();
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}
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33
src/southbridge/intel/i82801dx/early_init.c
Normal file
33
src/southbridge/intel/i82801dx/early_init.c
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@@ -0,0 +1,33 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/smbus_host.h>
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#include <device/pci_ops.h>
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#include "i82801dx.h"
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void i82801dx_early_init(void)
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{
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const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
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/* Enable ACPI I/O range decode and ACPI power management. */
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pci_write_config32(dev, PMBASE, DEFAULT_PMBASE | 1);
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pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
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pci_write_config32(dev, GPIO_BASE, GPIOBASE_ADDR | 1);
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pci_write_config8(dev, GPIO_CNTL, 0x10);
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if (ENV_RAMINIT)
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enable_smbus();
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}
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void i82801dx_lpc_setup(void)
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{
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const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
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/* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB.
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* LPT decode defaults to 0x378-0x37F and 0x778-0x77F.
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* Floppy decode defaults to 0x3F0-0x3F5, 0x3F7.
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* We also need to set the value for LPC I/F Enables Register.
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*/
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pci_write_config8(dev, COM_DEC, 0x10);
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pci_write_config16(dev, LPC_EN, 0x300F);
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}
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@@ -1,9 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/smbus_host.h>
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#include "i82801dx.h"
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void i82801dx_early_init(void)
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{
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enable_smbus();
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}
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@@ -1,26 +1,14 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* the problem: we have 82801dbm support in fb1, and 82801er in fb2.
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* fb1 code is what we want, fb2 structure is needed however.
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* so we need to get fb1 code for 82801dbm into fb2 structure.
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*/
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/* What I did: took the 80801er stuff from fb2, verify it against the
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* db stuff in fb1, and made sure it was right.
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*/
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#ifndef I82801DX_H
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#define I82801DX_H
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#include <acpi/acpi.h>
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#if !defined(__ASSEMBLER__)
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#include <device/device.h>
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void i82801dx_enable(struct device *dev);
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void i82801dx_early_init(void);
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#endif
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void i82801dx_lpc_setup(void);
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#define DEBUG_PERIODIC_SMIS 0
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@@ -54,8 +42,7 @@ void i82801dx_early_init(void);
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#define PCICMD 0x04
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#define PMBASE 0x40
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#define PMBASE_ADDR 0x0400
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#define DEFAULT_PMBASE PMBASE_ADDR
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#define DEFAULT_PMBASE 0x0400
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#define ACPI_CNTL 0x44
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#define ACPI_EN (1 << 4)
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#define BIOS_CNTL 0x4E
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@@ -21,20 +21,6 @@
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typedef struct southbridge_intel_i82801dx_config config_t;
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/**
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* Enable ACPI I/O range.
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*
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* @param dev PCI device with ACPI and PM BAR's
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*/
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static void i82801dx_enable_acpi(struct device *dev)
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{
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/* Set ACPI base address (I/O space). */
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pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1));
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/* Enable ACPI I/O range decode and ACPI power management. */
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pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
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}
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/**
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* Set miscellaneous static southbridge features.
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*
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@@ -155,12 +141,6 @@ static void i82801dx_power_options(struct device *dev)
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outl(reg32, pmbase + 0x04);
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}
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static void gpio_init(struct device *dev)
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{
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/* This should be done in romstage.c already */
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pci_write_config32(dev, GPIO_BASE, (GPIOBASE_ADDR | 1));
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pci_write_config8(dev, GPIO_CNTL, 0x10);
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}
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static void i82801dx_rtc_init(struct device *dev)
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{
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@@ -197,17 +177,6 @@ static void i82801dx_lpc_route_dma(struct device *dev, u8 mask)
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pci_write_config16(dev, PCI_DMA_CFG, reg16);
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}
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static void i82801dx_lpc_decode_en(struct device *dev)
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{
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/* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB.
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* LPT decode defaults to 0x378-0x37F and 0x778-0x77F.
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* Floppy decode defaults to 0x3F0-0x3F5, 0x3F7.
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* We also need to set the value for LPC I/F Enables Register.
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*/
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pci_write_config8(dev, COM_DEC, 0x10);
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pci_write_config16(dev, LPC_EN, 0x300F);
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}
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/* ICH4 does not mention HPET in the docs, but
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* all ICH3 and ICH4 do have HPETs built in.
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*/
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@@ -247,7 +216,6 @@ static void enable_hpet(struct device *dev)
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static void lpc_init(struct device *dev)
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{
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i82801dx_enable_acpi(dev);
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/* IO APIC initialization. */
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i82801dx_enable_ioapic(dev);
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@@ -259,9 +227,6 @@ static void lpc_init(struct device *dev)
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/* Setup power options. */
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i82801dx_power_options(dev);
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/* Set the state of the GPIO lines. */
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gpio_init(dev);
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/* Initialize the real time clock. */
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i82801dx_rtc_init(dev);
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@@ -271,9 +236,6 @@ static void lpc_init(struct device *dev)
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/* Initialize ISA DMA. */
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isa_dma_init();
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/* Setup decode ports and LPC I/F enables. */
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i82801dx_lpc_decode_en(dev);
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/* Initialize the High Precision Event Timers */
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enable_hpet(dev);
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