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Refactor DGPU implementation, fix hybrid suspend

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Change-Id: Ia7873a016e003532346170a3d27469bf085a47c4
This commit is contained in:
Jeremy Soller
2020-06-25 14:38:15 -06:00
committed by Jeremy Soller
parent 3b8e9fa539
commit 8e7ffe4952
12 changed files with 28 additions and 158 deletions
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2
src/mainboard/system76/addw2/acpi/dgpu.asl
View File

@@ -24,7 +24,7 @@
#define DGPU_RST_N GPP_F22
#define DGPU_PWR_EN GPP_F23
#define DGPU_GC6 GPP_C12
#define DGPU_GC6 GPP_K21
Device (\_SB.PCI0.PEGP.DEV0)
{

44
src/mainboard/system76/addw2/acpi/pegp.asl
View File

@@ -4,7 +4,6 @@
Device (PEGP)
{
Name (_ADR, 0x00010000)
Name (_STA, 0xF)
PowerResource (PWRR, 0, 0)
{
@@ -14,7 +13,7 @@ Device (PEGP)
{
Debug = "PEGP.PWRR._ON"
If (_STA != 1) {
\_SB.PCI0.PEGP._ON ()
\_SB.PCI0.PEGP.DEV0._ON ()
_STA = 1
}
}
@@ -23,50 +22,13 @@ Device (PEGP)
{
Debug = "PEGP.PWRR._OFF"
If (_STA != 0) {
\_SB.PCI0.PEGP._OFF ()
\_SB.PCI0.PEGP.DEV0._OFF ()
_STA = 0
}
}
}
/* Depend on the CLK to be active. _PR3 is also searched by nouveau to
* detect "Windows 8 compatible Optimus _DSM handler".
*/
Name (_PRE, Package () { \_SB.PCI0.PEGP.PWRR })
Name (_PR0, Package () { \_SB.PCI0.PEGP.PWRR })
Name (_PR2, Package () { \_SB.PCI0.PEGP.PWRR })
Name (_PR3, Package () { \_SB.PCI0.PEGP.PWRR })
Name (_PSC, 0)
Method (_PS0)
{
Debug = "PEGP._PS0"
_PSC = 0
}
Method (_PS3)
{
Debug = "PEGP._PS3"
_PSC = 3
}
Method (_ON)
{
Debug = "PEGP._ON"
If (_STA != 0xF)
{
^DEV0._ON ()
_STA = 0xF
}
}
Method (_OFF)
{
Debug = "PEGP._OFF"
If (_STA != 0x5)
{
^DEV0._OFF ()
_STA = 0x5
}
}
}

3
src/mainboard/system76/addw2/acpi/sleep.asl
View File

@@ -3,6 +3,9 @@
/* Method called from _PTS prior to enter sleep state */
Method (MPTS, 1) {
\_SB.PCI0.LPCB.EC0.PTS (Arg0)
// Turn DGPU on before sleeping
\_SB.PCI0.PEGP.DEV0._ON()
}
/* Method called from _WAK prior to wakeup */

3
src/mainboard/system76/addw2/bootblock.c
View File

@@ -1,13 +1,16 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootblock_common.h>
#include <console/console.h>
#include <delay.h>
#include <gpio.h>
#include "gpio.h"
static void dgpu_power_enable(int onoff) {
printk(BIOS_DEBUG, "system76: DGPU power %d\n", onoff);
if (onoff) {
gpio_set(DGPU_RST_N, 0);
mdelay(4);
gpio_set(DGPU_PWR_EN, 1);
mdelay(4);
gpio_set(DGPU_RST_N, 1);

17
src/mainboard/system76/addw2/hda_verb.c
View File

@@ -22,23 +22,6 @@ const u32 cim_verb_data[] = {
AZALIA_PIN_CFG(0, 0x1b, 0x90170110),
AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d),
AZALIA_PIN_CFG(0, 0x1e, 0x04451150),
/* Intel, KabylakeHDMI */
0x8086280b, /* Vendor ID */
0x80860101, /* Subsystem ID */
4, /* Number of entries */
AZALIA_SUBVENDOR(2, 0x80860101),
AZALIA_PIN_CFG(2, 0x05, 0x18560010),
AZALIA_PIN_CFG(2, 0x06, 0x18560010),
AZALIA_PIN_CFG(2, 0x07, 0x18560010),
/* Nvidia, GPU92HDMI/DP */
0x10de0092, /* Vendor ID */
0x155865e1, /* Subsystem ID */
5, /* Number of entries */
AZALIA_SUBVENDOR(0, 0x155865e1),
AZALIA_PIN_CFG(0, 0x04, 0x185600f0),
AZALIA_PIN_CFG(0, 0x05, 0x185600f0),
AZALIA_PIN_CFG(0, 0x06, 0x185600f0),
AZALIA_PIN_CFG(0, 0x07, 0x185600f0),
};
const u32 pc_beep_verbs[] = {};

44
src/mainboard/system76/gaze15/acpi/pegp.asl
View File

@@ -4,7 +4,6 @@
Device (PEGP)
{
Name (_ADR, 0x00010000)
Name (_STA, 0xF)
PowerResource (PWRR, 0, 0)
{
@@ -14,7 +13,7 @@ Device (PEGP)
{
Debug = "PEGP.PWRR._ON"
If (_STA != 1) {
\_SB.PCI0.PEGP._ON ()
\_SB.PCI0.PEGP.DEV0._ON ()
_STA = 1
}
}
@@ -23,50 +22,13 @@ Device (PEGP)
{
Debug = "PEGP.PWRR._OFF"
If (_STA != 0) {
\_SB.PCI0.PEGP._OFF ()
\_SB.PCI0.PEGP.DEV0._OFF ()
_STA = 0
}
}
}
/* Depend on the CLK to be active. _PR3 is also searched by nouveau to
* detect "Windows 8 compatible Optimus _DSM handler".
*/
Name (_PRE, Package () { \_SB.PCI0.PEGP.PWRR })
Name (_PR0, Package () { \_SB.PCI0.PEGP.PWRR })
Name (_PR2, Package () { \_SB.PCI0.PEGP.PWRR })
Name (_PR3, Package () { \_SB.PCI0.PEGP.PWRR })
Name (_PSC, 0)
Method (_PS0)
{
Debug = "PEGP._PS0"
_PSC = 0
}
Method (_PS3)
{
Debug = "PEGP._PS3"
_PSC = 3
}
Method (_ON)
{
Debug = "PEGP._ON"
If (_STA != 0xF)
{
^DEV0._ON ()
_STA = 0xF
}
}
Method (_OFF)
{
Debug = "PEGP._OFF"
If (_STA != 0x5)
{
^DEV0._OFF ()
_STA = 0x5
}
}
}

3
src/mainboard/system76/gaze15/acpi/sleep.asl
View File

@@ -3,6 +3,9 @@
/* Method called from _PTS prior to enter sleep state */
Method (MPTS, 1) {
\_SB.PCI0.LPCB.EC0.PTS (Arg0)
// Turn DGPU on before sleeping
\_SB.PCI0.PEGP.DEV0._ON()
}
/* Method called from _WAK prior to wakeup */

3
src/mainboard/system76/gaze15/bootblock.c
View File

@@ -1,13 +1,16 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootblock_common.h>
#include <console/console.h>
#include <delay.h>
#include <gpio.h>
#include "gpio.h"
static void dgpu_power_enable(int onoff) {
printk(BIOS_DEBUG, "system76: DGPU power %d\n", onoff);
if (onoff) {
gpio_set(DGPU_RST_N, 0);
mdelay(4);
gpio_set(DGPU_PWR_EN, 1);
mdelay(4);
gpio_set(DGPU_RST_N, 1);

17
src/mainboard/system76/gaze15/hda_verb.c
View File

@@ -22,23 +22,6 @@ const u32 cim_verb_data[] = {
AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
AZALIA_PIN_CFG(0, 0x1d, 0x41738205),
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
/* Intel, KabylakeHDMI */
0x8086280b, /* Vendor ID */
0x80860101, /* Subsystem ID */
4, /* Number of entries */
AZALIA_SUBVENDOR(2, 0x80860101),
AZALIA_PIN_CFG(2, 0x05, 0x18560010),
AZALIA_PIN_CFG(2, 0x06, 0x18560010),
AZALIA_PIN_CFG(2, 0x07, 0x18560010),
/* Nvidia, GPU99HDMI/DP */
0x10de0099, /* Vendor ID */
0x10de0000, /* Subsystem ID */
5, /* Number of entries */
AZALIA_SUBVENDOR(0, 0x10de0000),
AZALIA_PIN_CFG(0, 0x04, 0x185600f0),
AZALIA_PIN_CFG(0, 0x05, 0x185600f0),
AZALIA_PIN_CFG(0, 0x06, 0x585600f0),
AZALIA_PIN_CFG(0, 0x07, 0x585600f0),
};
const u32 pc_beep_verbs[] = {};

44
src/mainboard/system76/oryp6/acpi/pegp.asl
View File

@@ -4,7 +4,6 @@
Device (PEGP)
{
Name (_ADR, 0x00010000)
Name (_STA, 0xF)
PowerResource (PWRR, 0, 0)
{
@@ -14,7 +13,7 @@ Device (PEGP)
{
Debug = "PEGP.PWRR._ON"
If (_STA != 1) {
\_SB.PCI0.PEGP._ON ()
\_SB.PCI0.PEGP.DEV0._ON ()
_STA = 1
}
}
@@ -23,50 +22,13 @@ Device (PEGP)
{
Debug = "PEGP.PWRR._OFF"
If (_STA != 0) {
\_SB.PCI0.PEGP._OFF ()
\_SB.PCI0.PEGP.DEV0._OFF ()
_STA = 0
}
}
}
/* Depend on the CLK to be active. _PR3 is also searched by nouveau to
* detect "Windows 8 compatible Optimus _DSM handler".
*/
Name (_PRE, Package () { \_SB.PCI0.PEGP.PWRR })
Name (_PR0, Package () { \_SB.PCI0.PEGP.PWRR })
Name (_PR2, Package () { \_SB.PCI0.PEGP.PWRR })
Name (_PR3, Package () { \_SB.PCI0.PEGP.PWRR })
Name (_PSC, 0)
Method (_PS0)
{
Debug = "PEGP._PS0"
_PSC = 0
}
Method (_PS3)
{
Debug = "PEGP._PS3"
_PSC = 3
}
Method (_ON)
{
Debug = "PEGP._ON"
If (_STA != 0xF)
{
^DEV0._ON ()
_STA = 0xF
}
}
Method (_OFF)
{
Debug = "PEGP._OFF"
If (_STA != 0x5)
{
^DEV0._OFF ()
_STA = 0x5
}
}
}

3
src/mainboard/system76/oryp6/acpi/sleep.asl
View File

@@ -3,6 +3,9 @@
/* Method called from _PTS prior to enter sleep state */
Method (MPTS, 1) {
\_SB.PCI0.LPCB.EC0.PTS (Arg0)
// Turn DGPU on before sleeping
\_SB.PCI0.PEGP.DEV0._ON()
}
/* Method called from _WAK prior to wakeup */

3
src/mainboard/system76/oryp6/bootblock.c
View File

@@ -1,13 +1,16 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootblock_common.h>
#include <console/console.h>
#include <delay.h>
#include <gpio.h>
#include "gpio.h"
static void dgpu_power_enable(int onoff) {
printk(BIOS_DEBUG, "system76: DGPU power %d\n", onoff);
if (onoff) {
gpio_set(DGPU_RST_N, 0);
mdelay(4);
gpio_set(DGPU_PWR_EN, 1);
mdelay(4);
gpio_set(DGPU_RST_N, 1);