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intel/broadwell: Use smm_subregion()

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Change-Id: I95f1685f9b74f68fd6cb681a614e52b8e0748216
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34738
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki
2019-08-15 11:29:15 +03:00
parent 540151f115
commit 8f09688d23
5 changed files with 22 additions and 60 deletions
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17
src/soc/intel/broadwell/memmap.c
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@@ -16,12 +16,12 @@
#define __SIMPLE_DEVICE__
#include <cbmem.h>
#include <cpu/x86/smm.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <soc/pci_devs.h>
#include <soc/systemagent.h>
#include <soc/smm.h>
#include <stage_cache.h>
#include <stdint.h>
static uintptr_t dpr_region_start(void)
@@ -46,14 +46,13 @@ void *cbmem_top(void)
return (void *) dpr_region_start();
}
void stage_cache_external_region(void **base, size_t *size)
void smm_region(uintptr_t *start, size_t *size)
{
/* The ramstage cache lives in the TSEG region.
* The top of RAM is defined to be the TSEG base address. */
u32 offset = smm_region_size();
offset -= CONFIG_IED_REGION_SIZE;
offset -= CONFIG_SMM_RESERVED_SIZE;
uintptr_t tseg = pci_read_config32(PCI_DEV(0, 0, 0), TSEG);
uintptr_t bgsm = pci_read_config32(PCI_DEV(0, 0, 0), BGSM);
*base = (void *)(cbmem_top() + offset);
*size = CONFIG_SMM_RESERVED_SIZE;
tseg = ALIGN_DOWN(tseg, 1 * MiB);
bgsm = ALIGN_DOWN(bgsm, 1 * MiB);
*start = tseg;
*size = bgsm - tseg;
}