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mb/google/puff/var/*: Clean up SerialIO/I2C config in overridetree

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Ensure that the SerialIoDevMode config and common_soc_config registers
for each variant are programmed consistently with the devices'
enabled status in that variant's overridetree; remove and disable
extraneous devices as appropriate.

TEST=build/boot several puff variants, verify all components working
as expected, nothing missing from cbmem, lspci, etc.

Change-Id: Ib9d0cf48e405be7c00c553646651fc6f28c4e3f0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80164
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Matt DeVillier
2024-01-21 20:48:26 -06:00
committed by Felix Singer
parent 3f4c830bf6
commit 8facfa84ac
11 changed files with 21 additions and 75 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
src/mainboard/google/puff/variants/ambassador/overridetree.cb
View File

@@ -15,9 +15,9 @@ chip soc/intel/cannonlake
[PchSerialIoIndexI2C2] = PchSerialIoPci,
[PchSerialIoIndexI2C3] = PchSerialIoPci,
[PchSerialIoIndexI2C4] = PchSerialIoPci,
[PchSerialIoIndexI2C5] = PchSerialIoPci,
[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
[PchSerialIoIndexSPI0] = PchSerialIoPci,
[PchSerialIoIndexSPI1] = PchSerialIoPci,
[PchSerialIoIndexSPI1] = PchSerialIoDisabled,
[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
[PchSerialIoIndexUART1] = PchSerialIoDisabled,
@@ -157,7 +157,6 @@ chip soc/intel/cannonlake
#| | required to set up a BAR |
#| | for TPM communication |
#| | before memory is up |
#| I2C0 | RFU |
#| I2C2 | PS175 |
#| I2C3 | MST |
#| I2C4 | Audio |
@@ -167,11 +166,6 @@ chip soc/intel/cannonlake
.speed_mhz = 1,
.early_init = 1,
},
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 0,
.fall_time_ns = 0,
},
.i2c[2] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 60,

4
src/mainboard/google/puff/variants/dooly/overridetree.cb
View File

@@ -22,9 +22,9 @@ chip soc/intel/cannonlake
[PchSerialIoIndexI2C2] = PchSerialIoPci,
[PchSerialIoIndexI2C3] = PchSerialIoPci,
[PchSerialIoIndexI2C4] = PchSerialIoPci,
[PchSerialIoIndexI2C5] = PchSerialIoPci,
[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
[PchSerialIoIndexSPI0] = PchSerialIoPci,
[PchSerialIoIndexSPI1] = PchSerialIoPci,
[PchSerialIoIndexSPI1] = PchSerialIoDisabled,
[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
[PchSerialIoIndexUART1] = PchSerialIoDisabled,

10
src/mainboard/google/puff/variants/duffy/overridetree.cb
View File

@@ -15,9 +15,9 @@ chip soc/intel/cannonlake
[PchSerialIoIndexI2C2] = PchSerialIoPci,
[PchSerialIoIndexI2C3] = PchSerialIoPci,
[PchSerialIoIndexI2C4] = PchSerialIoPci,
[PchSerialIoIndexI2C5] = PchSerialIoPci,
[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
[PchSerialIoIndexSPI0] = PchSerialIoPci,
[PchSerialIoIndexSPI1] = PchSerialIoPci,
[PchSerialIoIndexSPI1] = PchSerialIoDisabled,
[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
[PchSerialIoIndexUART1] = PchSerialIoDisabled,
@@ -218,7 +218,6 @@ chip soc/intel/cannonlake
#| | required to set up a BAR |
#| | for TPM communication |
#| | before memory is up |
#| I2C0 | RFU |
#| I2C2 | PS175 |
#| I2C3 | MST |
#| I2C4 | Audio |
@@ -228,11 +227,6 @@ chip soc/intel/cannonlake
.speed_mhz = 1,
.early_init = 1,
},
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 0,
.fall_time_ns = 0,
},
.i2c[2] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 60,

10
src/mainboard/google/puff/variants/faffy/overridetree.cb
View File

@@ -15,9 +15,9 @@ chip soc/intel/cannonlake
[PchSerialIoIndexI2C2] = PchSerialIoPci,
[PchSerialIoIndexI2C3] = PchSerialIoPci,
[PchSerialIoIndexI2C4] = PchSerialIoPci,
[PchSerialIoIndexI2C5] = PchSerialIoPci,
[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
[PchSerialIoIndexSPI0] = PchSerialIoPci,
[PchSerialIoIndexSPI1] = PchSerialIoPci,
[PchSerialIoIndexSPI1] = PchSerialIoDisabled,
[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
[PchSerialIoIndexUART1] = PchSerialIoDisabled,
@@ -226,7 +226,6 @@ chip soc/intel/cannonlake
#| | required to set up a BAR |
#| | for TPM communication |
#| | before memory is up |
#| I2C0 | RFU |
#| I2C2 | PS175 |
#| I2C3 | MST |
#| I2C4 | Audio |
@@ -236,11 +235,6 @@ chip soc/intel/cannonlake
.speed_mhz = 1,
.early_init = 1,
},
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 0,
.fall_time_ns = 0,
},
.i2c[2] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 60,

10
src/mainboard/google/puff/variants/genesis/overridetree.cb
View File

@@ -8,9 +8,9 @@ chip soc/intel/cannonlake
[PchSerialIoIndexI2C2] = PchSerialIoPci,
[PchSerialIoIndexI2C3] = PchSerialIoPci,
[PchSerialIoIndexI2C4] = PchSerialIoPci,
[PchSerialIoIndexI2C5] = PchSerialIoPci,
[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
[PchSerialIoIndexSPI0] = PchSerialIoPci,
[PchSerialIoIndexSPI1] = PchSerialIoPci,
[PchSerialIoIndexSPI1] = PchSerialIoDisabled,
[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
[PchSerialIoIndexUART1] = PchSerialIoDisabled,
@@ -150,7 +150,6 @@ chip soc/intel/cannonlake
#| | required to set up a BAR |
#| | for TPM communication |
#| | before memory is up |
#| I2C0 | RFU |
#| I2C2 | PS175 |
#| I2C3 | MST |
#| I2C4 | Audio |
@@ -160,11 +159,6 @@ chip soc/intel/cannonlake
.speed_mhz = 1,
.early_init = 1,
},
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 0,
.fall_time_ns = 0,
},
.i2c[2] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 60,

10
src/mainboard/google/puff/variants/kaisa/overridetree.cb
View File

@@ -15,9 +15,9 @@ chip soc/intel/cannonlake
[PchSerialIoIndexI2C2] = PchSerialIoPci,
[PchSerialIoIndexI2C3] = PchSerialIoPci,
[PchSerialIoIndexI2C4] = PchSerialIoPci,
[PchSerialIoIndexI2C5] = PchSerialIoPci,
[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
[PchSerialIoIndexSPI0] = PchSerialIoPci,
[PchSerialIoIndexSPI1] = PchSerialIoPci,
[PchSerialIoIndexSPI1] = PchSerialIoDisabled,
[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
[PchSerialIoIndexUART1] = PchSerialIoDisabled,
@@ -218,7 +218,6 @@ chip soc/intel/cannonlake
#| | required to set up a BAR |
#| | for TPM communication |
#| | before memory is up |
#| I2C0 | RFU |
#| I2C2 | PS175 |
#| I2C3 | MST |
#| I2C4 | Audio |
@@ -228,11 +227,6 @@ chip soc/intel/cannonlake
.speed_mhz = 1,
.early_init = 1,
},
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 0,
.fall_time_ns = 0,
},
.i2c[2] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 60,

10
src/mainboard/google/puff/variants/moonbuggy/overridetree.cb
View File

@@ -8,9 +8,9 @@ chip soc/intel/cannonlake
[PchSerialIoIndexI2C2] = PchSerialIoPci,
[PchSerialIoIndexI2C3] = PchSerialIoPci,
[PchSerialIoIndexI2C4] = PchSerialIoPci,
[PchSerialIoIndexI2C5] = PchSerialIoPci,
[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
[PchSerialIoIndexSPI0] = PchSerialIoPci,
[PchSerialIoIndexSPI1] = PchSerialIoPci,
[PchSerialIoIndexSPI1] = PchSerialIoDisabled,
[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
[PchSerialIoIndexUART1] = PchSerialIoPci,
@@ -150,7 +150,6 @@ chip soc/intel/cannonlake
#| | required to set up a BAR |
#| | for TPM communication |
#| | before memory is up |
#| I2C0 | RFU |
#| I2C2 | PS175 |
#| I2C3 | MST |
#| I2C4 | Audio |
@@ -160,11 +159,6 @@ chip soc/intel/cannonlake
.speed_mhz = 1,
.early_init = 1,
},
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 0,
.fall_time_ns = 0,
},
.i2c[2] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 60,

10
src/mainboard/google/puff/variants/noibat/overridetree.cb
View File

@@ -13,9 +13,9 @@ chip soc/intel/cannonlake
[PchSerialIoIndexI2C2] = PchSerialIoPci,
[PchSerialIoIndexI2C3] = PchSerialIoPci,
[PchSerialIoIndexI2C4] = PchSerialIoPci,
[PchSerialIoIndexI2C5] = PchSerialIoPci,
[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
[PchSerialIoIndexSPI0] = PchSerialIoPci,
[PchSerialIoIndexSPI1] = PchSerialIoPci,
[PchSerialIoIndexSPI1] = PchSerialIoDisabled,
[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
[PchSerialIoIndexUART1] = PchSerialIoDisabled,
@@ -141,7 +141,6 @@ chip soc/intel/cannonlake
#| | required to set up a BAR |
#| | for TPM communication |
#| | before memory is up |
#| I2C0 | RFU |
#| I2C2 | PS175 |
#| I2C3 | MST |
#| I2C4 | Audio |
@@ -151,11 +150,6 @@ chip soc/intel/cannonlake
.speed_mhz = 1,
.early_init = 1,
},
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 0,
.fall_time_ns = 0,
},
.i2c[2] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 60,

10
src/mainboard/google/puff/variants/puff/overridetree.cb
View File

@@ -9,9 +9,9 @@ chip soc/intel/cannonlake
[PchSerialIoIndexI2C2] = PchSerialIoPci,
[PchSerialIoIndexI2C3] = PchSerialIoPci,
[PchSerialIoIndexI2C4] = PchSerialIoPci,
[PchSerialIoIndexI2C5] = PchSerialIoPci,
[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
[PchSerialIoIndexSPI0] = PchSerialIoPci,
[PchSerialIoIndexSPI1] = PchSerialIoPci,
[PchSerialIoIndexSPI1] = PchSerialIoDisabled,
[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
[PchSerialIoIndexUART1] = PchSerialIoDisabled,
@@ -151,7 +151,6 @@ chip soc/intel/cannonlake
#| | required to set up a BAR |
#| | for TPM communication |
#| | before memory is up |
#| I2C0 | RFU |
#| I2C2 | PS175 |
#| I2C3 | MST |
#| I2C4 | Audio |
@@ -161,11 +160,6 @@ chip soc/intel/cannonlake
.speed_mhz = 1,
.early_init = 1,
},
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 0,
.fall_time_ns = 0,
},
.i2c[2] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 60,

2
src/mainboard/google/puff/variants/scout/overridetree.cb
View File

@@ -10,7 +10,7 @@ chip soc/intel/cannonlake
[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
[PchSerialIoIndexSPI0] = PchSerialIoPci,
[PchSerialIoIndexSPI1] = PchSerialIoPci,
[PchSerialIoIndexSPI1] = PchSerialIoDisabled,
[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
[PchSerialIoIndexUART1] = PchSerialIoPci,

10
src/mainboard/google/puff/variants/wyvern/overridetree.cb
View File

@@ -11,9 +11,9 @@ chip soc/intel/cannonlake
[PchSerialIoIndexI2C2] = PchSerialIoPci,
[PchSerialIoIndexI2C3] = PchSerialIoPci,
[PchSerialIoIndexI2C4] = PchSerialIoPci,
[PchSerialIoIndexI2C5] = PchSerialIoPci,
[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
[PchSerialIoIndexSPI0] = PchSerialIoPci,
[PchSerialIoIndexSPI1] = PchSerialIoPci,
[PchSerialIoIndexSPI1] = PchSerialIoDisabled,
[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
[PchSerialIoIndexUART1] = PchSerialIoDisabled,
@@ -152,7 +152,6 @@ chip soc/intel/cannonlake
#| | required to set up a BAR |
#| | for TPM communication |
#| | before memory is up |
#| I2C0 | RFU |
#| I2C2 | PS175 |
#| I2C3 | MST |
#| I2C4 | Audio |
@@ -162,11 +161,6 @@ chip soc/intel/cannonlake
.speed_mhz = 1,
.early_init = 1,
},
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 0,
.fall_time_ns = 0,
},
.i2c[2] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 60,