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mainboard/dell: Add new mainboard XPS 8300 (Sandy Bridge)

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Mainboard is identified as 0Y2MRG.
The version tested is with Nvidia dGPU (gfx 560ti).

The flash is a 4MiB Winbond W25Q32BVSIG.
It can be flashed internally with flashrom.
Add a strap on the service mode pin of the mainboard for internal flash.

Tested working:
- SeaBIOS
- All USB ports
- SATA
- dGPU
- Ethernet
- Environment control
- GPIOs
- S3 Sleep mode
- WakeOnLan

Change-Id: I7d394794fec580bc7aed3f6396ceb47d4a6fd059
Signed-off-by: Ronald Claveau <sousmangoosta@aliel.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
This commit is contained in:
Ronald Claveau
2024-05-29 23:21:33 +02:00
committed by Felix Singer
parent 30610597f2
commit 91d2f5d5e0
14 changed files with 457 additions and 0 deletions
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35
src/mainboard/dell/xps_8300/Kconfig Normal file
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## SPDX-License-Identifier: GPL-2.0-only
if BOARD_DELL_XPS_8300
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_4096
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select INTEL_INT15
select NORTHBRIDGE_INTEL_SANDYBRIDGE
select SERIRQ_CONTINUOUS_MODE
select SOUTHBRIDGE_INTEL_BD82X6X
select USE_NATIVE_RAMINIT
select SUPERIO_ITE_IT8772F
config MAINBOARD_DIR
default "dell/xps_8300"
config MAINBOARD_PART_NUMBER
default "XPS 8300"
config DRAM_RESET_GATE_GPIO # FIXME: check this
default 60
config USBDEBUG_HCD_INDEX
default 2
config VGA_BIOS_DGPU_ID
default "10de,1082"
config CBFS_SIZE
default 0x26F000
endif

4
src/mainboard/dell/xps_8300/Kconfig.name Normal file
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## SPDX-License-Identifier: GPL-2.0-only
config BOARD_DELL_XPS_8300
bool "XPS 8300"

6
src/mainboard/dell/xps_8300/Makefile.mk Normal file
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# SPDX-License-Identifier: GPL-2.0-only
bootblock-y += early_init.c
bootblock-y += gpio.c
romstage-y += early_init.c
romstage-y += gpio.c

3
src/mainboard/dell/xps_8300/acpi/ec.asl Normal file
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/* SPDX-License-Identifier: CC-PDDC */
/* Please update the license if adding licensable material. */

10
src/mainboard/dell/xps_8300/acpi/platform.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
Method(_WAK, 1)
{
Return(Package() {0, 0})
}
Method(_PTS, 1)
{
}

2
src/mainboard/dell/xps_8300/acpi/superio.asl Normal file
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/* SPDX-License-Identifier: CC-PDDC */
/* Please update the license if adding licensable material. */

6
src/mainboard/dell/xps_8300/board_info.txt Normal file
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Category: desktop
ROM protocol: SPI
ROM package: SOIC-8
ROM socketed: n
Flashrom support: y
Release year: 2011

48
src/mainboard/dell/xps_8300/devicetree.cb Normal file
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# SPDX-License-Identifier: GPL-2.0-only
chip northbridge/intel/sandybridge
register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}"
device domain 0x0 on
subsystemid 0x1028 0x04aa inherit
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "docking_supported" = "0"
register "pcie_port_coalesce" = "1"
register "usb_port_config" = "{
{ 1, 1, 0 },
{ 1, 1, 0 },
{ 1, 1, 1 },
{ 1, 1, 1 },
{ 1, 0, 2 }, // FIXME: Unknown current: RCBA(0x3510)=0x3510
{ 1, 0, 2 }, // FIXME: Unknown current: RCBA(0x3514)=0x3514
{ 1, 6, 3 },
{ 1, 6, 3 },
{ 1, 0, 5 }, // FIXME: Unknown current: RCBA(0x3520)=0x3520
{ 1, 6, 5 },
{ 1, 6, 5 },
{ 1, 0, 5 }, // FIXME: Unknown current: RCBA(0x352c)=0x352c
{ 1, 6, 6 },
{ 0, 6, 6 },
}"
device ref mei1 on end
device ref ehci2 on end
device ref pcie_rp1 on end
device ref pcie_rp4 on end
device ref pcie_rp5 on end
device ref ehci1 on end
device ref lpc on
register "gen1_dec" = "0x003c0a01"
register "spi_lvscc" = "0x2005"
register "spi_uvscc" = "0x2005"
end
device ref sata1 on
register "sata_interface_speed_support" = "0x3"
register "sata_port_map" = "0x1f"
end
device ref smbus on end
end
device ref host_bridge on end
device ref peg10 on end
end
end

29
src/mainboard/dell/xps_8300/dsdt.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
#include <acpi/acpi.h>
DefinitionBlock(
"dsdt.aml",
"DSDT",
ACPI_DSDT_REV_2,
OEM_ID,
ACPI_TABLE_CREATOR,
0x20141018
)
{
#include <acpi/dsdt_top.asl>
#include "acpi/platform.asl"
#include <cpu/intel/common/acpi/cpu.asl>
#include <southbridge/intel/common/acpi/platform.asl>
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
#include <southbridge/intel/common/acpi/sleepstates.asl>
Device (\_SB.PCI0)
{
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
}
}

63
src/mainboard/dell/xps_8300/early_init.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootblock_common.h>
#include <device/pci_ops.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8772f/it8772f.h>
#define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO)
#define MOUSE_DEV PNP_DEV(0x2e, IT8772F_KBCM)
#define EC_DEV PNP_DEV(0x2e, IT8772F_EC)
void bootblock_mainboard_early_init(void)
{
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0e);
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
/* Set up GPIOs on Super I/O. */
ite_ac_resume_southbridge(EC_DEV);
ite_reg_write(MOUSE_DEV, 0x30, 0x00); // PS/2 Mouse disable
ite_reg_write(EC_DEV, 0x30, 0x01); // Environment controller activate
ite_reg_write(EC_DEV, 0x60, 0x0a); // Environment controller MSB Register Base Address
ite_reg_write(EC_DEV, 0x61, 0x30); // Environment controller LSB Register Base Address
ite_reg_write(EC_DEV, 0x62, 0x0a); // PME Direct Access MSB Register Base Address
ite_reg_write(EC_DEV, 0x63, 0x20); // PME Direct Access LSB Register Base Address
ite_reg_write(GPIO_DEV, 0x25, 0x00); // GPIO Set 1
ite_reg_write(GPIO_DEV, 0x26, 0xfc); // GPIO Set 2, Enable pin 7 and 8 to GPIO
ite_reg_write(GPIO_DEV, 0x27, 0x00); // GPIO Set 3
ite_reg_write(GPIO_DEV, 0x28, 0x00); // GPIO Set 4
ite_reg_write(GPIO_DEV, 0x29, 0x00); // GPIO Set 5 and 6
ite_reg_write(GPIO_DEV, 0x2a, 0x00); // Special function 1
ite_reg_write(GPIO_DEV, 0x2b, 0x00); // Special function 2
ite_reg_write(GPIO_DEV, 0x2c, 0x03); // Special function 3
ite_reg_write(GPIO_DEV, 0x60, 0x0a); // SMI MSB Register Base Address
ite_reg_write(GPIO_DEV, 0x62, 0x0a); // Simple I/O MSB Register Base Address
ite_reg_write(GPIO_DEV, 0xb0, 0x00); // Pin set 1 polarity registers
ite_reg_write(GPIO_DEV, 0xb1, 0x00); // Pin set 2 polarity registers
ite_reg_write(GPIO_DEV, 0xb2, 0x00); // Pin set 3 polarity registers
ite_reg_write(GPIO_DEV, 0xb3, 0x00); // Pin set 4 polarity registers
ite_reg_write(GPIO_DEV, 0xb4, 0x00); // Pin set 5 polarity registers
ite_reg_write(GPIO_DEV, 0xb8, 0x00); // Pin set 1 int pull-up disable
ite_reg_write(GPIO_DEV, 0xb9, 0x00); // Pin set 1 int pull-up disable
ite_reg_write(GPIO_DEV, 0xba, 0x00); // Pin set 1 int pull-up disable
ite_reg_write(GPIO_DEV, 0xbb, 0x00); // Pin set 1 int pull-up disable
ite_reg_write(GPIO_DEV, 0xbc, 0x00); // Pin set 1 int pull-up disable
ite_reg_write(GPIO_DEV, 0xbd, 0x00); // Pin set 1 int pull-up disable
ite_reg_write(GPIO_DEV, 0xc0, 0x01); // Set Simple I/O functions on SI/O Set 1
ite_reg_write(GPIO_DEV, 0xc1, 0x0c); // Set Simple I/O functions on SI/O Set 2
ite_reg_write(GPIO_DEV, 0xc2, 0x00); // Set Simple I/O functions on SI/O Set 3
ite_reg_write(GPIO_DEV, 0xc3, 0x40); // Set Simple I/O functions on SI/O Set 4
ite_reg_write(GPIO_DEV, 0xc4, 0x00); // Set Simple I/O functions on SI/O Set 5
ite_reg_write(GPIO_DEV, 0xc8, 0x01); // Set Simple I/O Output on SI/O Set 1
ite_reg_write(GPIO_DEV, 0xc9, 0x0c); // Set Simple I/O Output on SI/O Set 2
ite_reg_write(GPIO_DEV, 0xca, 0x00); // Set Simple I/O Output on SI/O Set 3
ite_reg_write(GPIO_DEV, 0xcb, 0x40); // Set Simple I/O Output on SI/O Set 4
ite_reg_write(GPIO_DEV, 0xcc, 0x00); // Set Simple I/O Output on SI/O Set 5
ite_reg_write(GPIO_DEV, 0xcd, 0x00); // Set Simple I/O Output on SI/O Set 6
ite_reg_write(GPIO_DEV, 0xe9, 0x07); // GPIO Bus Select Control Register
ite_reg_write(GPIO_DEV, 0xf6, 0x00); // Hardware Monitor Alert Beep Pin Mapping Register
}

195
src/mainboard/dell/xps_8300/gpio.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <southbridge/intel/common/gpio.h>
static const struct pch_gpio_set1 pch_gpio_set1_mode = {
.gpio0 = GPIO_MODE_GPIO,
.gpio1 = GPIO_MODE_GPIO,
.gpio2 = GPIO_MODE_GPIO,
.gpio3 = GPIO_MODE_GPIO,
.gpio4 = GPIO_MODE_GPIO,
.gpio5 = GPIO_MODE_GPIO,
.gpio6 = GPIO_MODE_GPIO,
.gpio7 = GPIO_MODE_GPIO,
.gpio8 = GPIO_MODE_GPIO,
.gpio9 = GPIO_MODE_NATIVE,
.gpio10 = GPIO_MODE_NATIVE,
.gpio11 = GPIO_MODE_GPIO,
.gpio12 = GPIO_MODE_GPIO,
.gpio13 = GPIO_MODE_GPIO,
.gpio14 = GPIO_MODE_NATIVE,
.gpio15 = GPIO_MODE_GPIO,
.gpio16 = GPIO_MODE_GPIO,
.gpio17 = GPIO_MODE_GPIO,
.gpio18 = GPIO_MODE_NATIVE,
.gpio19 = GPIO_MODE_NATIVE,
.gpio20 = GPIO_MODE_NATIVE,
.gpio21 = GPIO_MODE_GPIO,
.gpio22 = GPIO_MODE_NATIVE,
.gpio23 = GPIO_MODE_GPIO,
.gpio24 = GPIO_MODE_GPIO,
.gpio25 = GPIO_MODE_NATIVE,
.gpio26 = GPIO_MODE_NATIVE,
.gpio27 = GPIO_MODE_GPIO,
.gpio28 = GPIO_MODE_GPIO,
.gpio29 = GPIO_MODE_GPIO,
.gpio30 = GPIO_MODE_NATIVE,
.gpio31 = GPIO_MODE_GPIO,
};
static const struct pch_gpio_set1 pch_gpio_set1_direction = {
.gpio0 = GPIO_DIR_INPUT,
.gpio1 = GPIO_DIR_INPUT,
.gpio2 = GPIO_DIR_INPUT,
.gpio3 = GPIO_DIR_INPUT,
.gpio4 = GPIO_DIR_INPUT,
.gpio5 = GPIO_DIR_INPUT,
.gpio6 = GPIO_DIR_INPUT,
.gpio7 = GPIO_DIR_INPUT,
.gpio8 = GPIO_DIR_OUTPUT,
.gpio11 = GPIO_DIR_OUTPUT,
.gpio12 = GPIO_DIR_OUTPUT,
.gpio13 = GPIO_DIR_OUTPUT,
.gpio15 = GPIO_DIR_OUTPUT,
.gpio16 = GPIO_DIR_INPUT,
.gpio17 = GPIO_DIR_INPUT,
.gpio21 = GPIO_DIR_INPUT,
.gpio23 = GPIO_DIR_INPUT,
.gpio24 = GPIO_DIR_INPUT,
.gpio27 = GPIO_DIR_INPUT,
.gpio28 = GPIO_DIR_OUTPUT,
.gpio29 = GPIO_DIR_OUTPUT,
.gpio31 = GPIO_DIR_INPUT,
};
static const struct pch_gpio_set1 pch_gpio_set1_level = {
.gpio8 = GPIO_LEVEL_HIGH,
.gpio11 = GPIO_LEVEL_HIGH,
.gpio12 = GPIO_LEVEL_LOW,
.gpio13 = GPIO_LEVEL_HIGH,
.gpio15 = GPIO_LEVEL_LOW,
.gpio28 = GPIO_LEVEL_LOW,
.gpio29 = GPIO_LEVEL_HIGH,
};
static const struct pch_gpio_set1 pch_gpio_set1_reset = {
};
static const struct pch_gpio_set1 pch_gpio_set1_invert = {
};
static const struct pch_gpio_set1 pch_gpio_set1_blink = {
};
static const struct pch_gpio_set2 pch_gpio_set2_mode = {
.gpio32 = GPIO_MODE_GPIO,
.gpio33 = GPIO_MODE_GPIO,
.gpio34 = GPIO_MODE_GPIO,
.gpio35 = GPIO_MODE_GPIO,
.gpio36 = GPIO_MODE_NATIVE,
.gpio37 = GPIO_MODE_NATIVE,
.gpio38 = GPIO_MODE_GPIO,
.gpio39 = GPIO_MODE_GPIO,
.gpio40 = GPIO_MODE_NATIVE,
.gpio41 = GPIO_MODE_NATIVE,
.gpio42 = GPIO_MODE_NATIVE,
.gpio43 = GPIO_MODE_NATIVE,
.gpio44 = GPIO_MODE_GPIO,
.gpio45 = GPIO_MODE_GPIO,
.gpio46 = GPIO_MODE_GPIO,
.gpio47 = GPIO_MODE_NATIVE,
.gpio48 = GPIO_MODE_GPIO,
.gpio49 = GPIO_MODE_GPIO,
.gpio50 = GPIO_MODE_NATIVE,
.gpio51 = GPIO_MODE_NATIVE,
.gpio52 = GPIO_MODE_NATIVE,
.gpio53 = GPIO_MODE_NATIVE,
.gpio54 = GPIO_MODE_NATIVE,
.gpio55 = GPIO_MODE_NATIVE,
.gpio56 = GPIO_MODE_NATIVE,
.gpio57 = GPIO_MODE_GPIO,
.gpio58 = GPIO_MODE_NATIVE,
.gpio59 = GPIO_MODE_NATIVE,
.gpio60 = GPIO_MODE_GPIO,
.gpio61 = GPIO_MODE_NATIVE,
.gpio62 = GPIO_MODE_NATIVE,
.gpio63 = GPIO_MODE_NATIVE,
};
static const struct pch_gpio_set2 pch_gpio_set2_direction = {
.gpio32 = GPIO_DIR_INPUT,
.gpio33 = GPIO_DIR_OUTPUT,
.gpio34 = GPIO_DIR_INPUT,
.gpio35 = GPIO_DIR_INPUT,
.gpio38 = GPIO_DIR_INPUT,
.gpio39 = GPIO_DIR_INPUT,
.gpio44 = GPIO_DIR_INPUT,
.gpio45 = GPIO_DIR_INPUT,
.gpio46 = GPIO_DIR_OUTPUT,
.gpio48 = GPIO_DIR_INPUT,
.gpio49 = GPIO_DIR_INPUT,
.gpio57 = GPIO_DIR_INPUT,
.gpio60 = GPIO_DIR_INPUT,
};
static const struct pch_gpio_set2 pch_gpio_set2_level = {
.gpio33 = GPIO_LEVEL_HIGH,
.gpio46 = GPIO_LEVEL_LOW,
};
static const struct pch_gpio_set2 pch_gpio_set2_reset = {
};
static const struct pch_gpio_set3 pch_gpio_set3_mode = {
.gpio64 = GPIO_MODE_NATIVE,
.gpio65 = GPIO_MODE_NATIVE,
.gpio66 = GPIO_MODE_NATIVE,
.gpio67 = GPIO_MODE_NATIVE,
.gpio68 = GPIO_MODE_GPIO,
.gpio69 = GPIO_MODE_GPIO,
.gpio70 = GPIO_MODE_GPIO,
.gpio71 = GPIO_MODE_NATIVE,
.gpio72 = GPIO_MODE_GPIO,
.gpio73 = GPIO_MODE_NATIVE,
.gpio74 = GPIO_MODE_GPIO,
.gpio75 = GPIO_MODE_NATIVE,
};
static const struct pch_gpio_set3 pch_gpio_set3_direction = {
.gpio68 = GPIO_DIR_INPUT,
.gpio69 = GPIO_DIR_INPUT,
.gpio70 = GPIO_DIR_INPUT,
.gpio72 = GPIO_DIR_OUTPUT,
.gpio74 = GPIO_DIR_OUTPUT,
};
static const struct pch_gpio_set3 pch_gpio_set3_level = {
.gpio72 = GPIO_LEVEL_HIGH,
.gpio74 = GPIO_LEVEL_HIGH,
};
static const struct pch_gpio_set3 pch_gpio_set3_reset = {
};
const struct pch_gpio_map mainboard_gpio_map = {
.set1 = {
.mode = &pch_gpio_set1_mode,
.direction = &pch_gpio_set1_direction,
.level = &pch_gpio_set1_level,
.blink = &pch_gpio_set1_blink,
.invert = &pch_gpio_set1_invert,
.reset = &pch_gpio_set1_reset,
},
.set2 = {
.mode = &pch_gpio_set2_mode,
.direction = &pch_gpio_set2_direction,
.level = &pch_gpio_set2_level,
.reset = &pch_gpio_set2_reset,
},
.set3 = {
.mode = &pch_gpio_set3_mode,
.direction = &pch_gpio_set3_direction,
.level = &pch_gpio_set3_level,
.reset = &pch_gpio_set3_reset,
},
};

9
src/mainboard/dell/xps_8300/hda_verb.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/azalia_device.h>
const u32 cim_verb_data[0] = {};
const u32 pc_beep_verbs[0] = {};
AZALIA_ARRAY_SIZES;

16
src/mainboard/dell/xps_8300/mainboard.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/device.h>
#include <drivers/intel/gma/int15.h>
#include <southbridge/intel/bd82x6x/pch.h>
static void mainboard_enable(struct device *dev)
{
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE,
GMA_INT15_PANEL_FIT_DEFAULT,
GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
}
struct chip_operations mainboard_ops = {
.enable_dev = mainboard_enable,
};

31
src/mainboard/dell/xps_8300/smihandler.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <types.h>
#include <acpi/acpi.h>
#include <cpu/x86/smm.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8772f/it8772f.h>
#define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO)
void mainboard_smi_sleep(u8 slp_typ)
{
switch (slp_typ) {
case ACPI_S3:
ite_set_3vsbsw(GPIO_DEV, true);
ite_delay_pwrgd3(GPIO_DEV);
it8772f_gpio_led(
GPIO_DEV,
2 /* set */,
0x02 /* select */,
0x01 /* polarity */,
0x01 /* 1 = pullup */,
0x01 /* output */,
0x00 /* 1 = Simple IO function */,
SIO_GPIO_BLINK_GPIO22,
IT8772F_GPIO_BLINK_FREQUENCY_1_HZ);
break;
default:
break;
}
}