mainboards/amd/fam10: Add romstage timestamps
Example output: 1:start of rom stage 542 2:before ram initialization 193,989 (193,447) 3:after ram initialization 3,319,114 (3,125,124) 4:end of romstage 3,320,004 (889) Change-Id: Idcde7dc4c7a1d6c3118c82b67e8c2fcd4a07553b Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8776 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
committed by
Kyösti Mälkki
parent
a2a4bcf1a5
commit
91e9f676b7
@@ -34,6 +34,7 @@
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#include <device/pnp_def.h>
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#include <cpu/x86/lapic.h>
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#include <console/console.h>
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#include <timestamp.h>
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#include <cpu/amd/model_10xxx_rev.h>
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#include <northbridge/amd/amdfam10/raminit.h>
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#include <northbridge/amd/amdfam10/amdfam10.h>
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@@ -79,6 +80,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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u32 bsp_apicid = 0, val;
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msr_t msr;
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timestamp_init(timestamp_get());
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timestamp_add_now(TS_START_ROMSTAGE);
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if (!cpu_init_detectedx && boot_cpu()) {
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/* Nothing special needs to be done to find bus 0 */
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/* Allow the HT devices to be found */
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@@ -198,8 +202,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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// die("Die Before MCT init.");
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timestamp_add_now(TS_BEFORE_INITRAM);
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printk(BIOS_DEBUG, "raminit_amdmct()\n");
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raminit_amdmct(sysinfo);
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timestamp_add_now(TS_AFTER_INITRAM);
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cbmem_initialize_empty();
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post_code(0x41);
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@@ -217,6 +224,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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rs780_before_pci_init();
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timestamp_add_now(TS_END_ROMSTAGE);
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post_code(0x42);
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post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
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post_code(0x43); // Should never see this post code.
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@@ -33,6 +33,7 @@
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#include <device/pnp_def.h>
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#include <cpu/x86/lapic.h>
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#include <console/console.h>
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#include <timestamp.h>
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#include <cpu/amd/model_10xxx_rev.h>
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#include <northbridge/amd/amdfam10/raminit.h>
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#include <northbridge/amd/amdfam10/amdfam10.h>
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@@ -74,6 +75,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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u32 bsp_apicid = 0, val;
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msr_t msr;
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timestamp_init(timestamp_get());
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timestamp_add_now(TS_START_ROMSTAGE);
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if (!cpu_init_detectedx && boot_cpu()) {
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/* Nothing special needs to be done to find bus 0 */
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/* Allow the HT devices to be found */
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@@ -196,8 +200,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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// die("Die Before MCT init.");
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timestamp_add_now(TS_BEFORE_INITRAM);
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printk(BIOS_DEBUG, "raminit_amdmct()\n");
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raminit_amdmct(sysinfo);
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timestamp_add_now(TS_AFTER_INITRAM);
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cbmem_initialize_empty();
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post_code(0x41);
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@@ -216,6 +223,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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rs780_before_pci_init();
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sb800_before_pci_init();
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timestamp_add_now(TS_END_ROMSTAGE);
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post_code(0x42);
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post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
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post_code(0x43); // Should never see this post code.
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@@ -33,6 +33,7 @@
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#include <device/pnp_def.h>
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#include <cpu/x86/lapic.h>
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#include <console/console.h>
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#include <timestamp.h>
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#include <cpu/amd/model_10xxx_rev.h>
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#include <northbridge/amd/amdfam10/raminit.h>
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#include <northbridge/amd/amdfam10/amdfam10.h>
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@@ -77,6 +78,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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u32 bsp_apicid = 0, val;
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msr_t msr;
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timestamp_init(timestamp_get());
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timestamp_add_now(TS_START_ROMSTAGE);
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if (!cpu_init_detectedx && boot_cpu()) {
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/* Nothing special needs to be done to find bus 0 */
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/* Allow the HT devices to be found */
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@@ -198,8 +202,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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// die("Die Before MCT init.");
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timestamp_add_now(TS_BEFORE_INITRAM);
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printk(BIOS_DEBUG, "raminit_amdmct()\n");
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raminit_amdmct(sysinfo);
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timestamp_add_now(TS_AFTER_INITRAM);
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cbmem_initialize_empty();
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post_code(0x41);
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@@ -215,6 +222,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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rs780_before_pci_init();
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sb7xx_51xx_before_pci_init();
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timestamp_add_now(TS_END_ROMSTAGE);
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post_code(0x42);
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post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
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post_code(0x43); // Should never see this post code.
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@@ -33,6 +33,7 @@
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#include <device/pnp_def.h>
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#include <cpu/x86/lapic.h>
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#include <console/console.h>
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#include <timestamp.h>
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#include <cpu/amd/model_10xxx_rev.h>
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#include "southbridge/amd/amd8111/early_smbus.c"
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#include <northbridge/amd/amdfam10/raminit.h>
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@@ -188,6 +189,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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u32 bsp_apicid = 0, val;
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msr_t msr;
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timestamp_init(timestamp_get());
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timestamp_add_now(TS_START_ROMSTAGE);
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if (!cpu_init_detectedx && boot_cpu()) {
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/* Nothing special needs to be done to find bus 0 */
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/* Allow the HT devices to be found */
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@@ -310,8 +314,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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// die("Die Before MCT init.");
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timestamp_add_now(TS_BEFORE_INITRAM);
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printk(BIOS_DEBUG, "raminit_amdmct()\n");
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raminit_amdmct(sysinfo);
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timestamp_add_now(TS_AFTER_INITRAM);
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cbmem_initialize_empty();
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post_code(0x41);
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@@ -324,6 +331,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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// die("After MCT init before CAR disabled.");
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timestamp_add_now(TS_END_ROMSTAGE);
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post_code(0x42);
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post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
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post_code(0x43); // Should never see this post code.
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@@ -33,6 +33,7 @@
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#include <device/pnp_def.h>
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#include <cpu/x86/lapic.h>
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#include <console/console.h>
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#include <timestamp.h>
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#include <cpu/amd/model_10xxx_rev.h>
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#include <northbridge/amd/amdfam10/raminit.h>
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#include <northbridge/amd/amdfam10/amdfam10.h>
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@@ -77,6 +78,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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u32 bsp_apicid = 0, val;
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msr_t msr;
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timestamp_init(timestamp_get());
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timestamp_add_now(TS_START_ROMSTAGE);
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if (!cpu_init_detectedx && boot_cpu()) {
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/* Nothing special needs to be done to find bus 0 */
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/* Allow the HT devices to be found */
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@@ -198,8 +202,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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// die("Die Before MCT init.");
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timestamp_add_now(TS_BEFORE_INITRAM);
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printk(BIOS_DEBUG, "raminit_amdmct()\n");
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raminit_amdmct(sysinfo);
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timestamp_add_now(TS_AFTER_INITRAM);
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cbmem_initialize_empty();
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post_code(0x41);
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@@ -215,6 +222,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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rs780_before_pci_init();
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sb7xx_51xx_before_pci_init();
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timestamp_add_now(TS_END_ROMSTAGE);
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post_code(0x42);
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post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
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post_code(0x43); // Should never see this post code.
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@@ -35,6 +35,7 @@ unsigned int get_sbdn(unsigned bus);
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#include <device/pnp_def.h>
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#include <cpu/x86/lapic.h>
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#include <console/console.h>
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#include <timestamp.h>
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#include <lib.h>
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#include <spd.h>
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#include <cpu/amd/model_10xxx_rev.h>
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@@ -213,6 +214,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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u32 bsp_apicid = 0, val, wants_reset;
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msr_t msr;
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timestamp_init(timestamp_get());
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timestamp_add_now(TS_START_ROMSTAGE);
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if (!cpu_init_detectedx && boot_cpu()) {
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/* Nothing special needs to be done to find bus 0 */
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/* Allow the HT devices to be found */
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@@ -341,8 +345,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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post_code(0x40);
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timestamp_add_now(TS_BEFORE_INITRAM);
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printk(BIOS_DEBUG, "raminit_amdmct()\n");
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raminit_amdmct(sysinfo);
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timestamp_add_now(TS_AFTER_INITRAM);
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cbmem_initialize_empty();
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post_code(0x41);
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@@ -368,6 +375,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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/* Restore default SuperIO access */
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outb(0xaa, port);
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timestamp_add_now(TS_END_ROMSTAGE);
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post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
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post_code(0x43); // Should never see this post code.
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}
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@@ -33,6 +33,7 @@
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#include <device/pnp_def.h>
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#include <cpu/x86/lapic.h>
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#include <console/console.h>
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#include <timestamp.h>
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#include <cpu/amd/model_10xxx_rev.h>
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#include <northbridge/amd/amdfam10/raminit.h>
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#include <northbridge/amd/amdfam10/amdfam10.h>
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@@ -78,6 +79,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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u32 bsp_apicid = 0, val;
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msr_t msr;
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timestamp_init(timestamp_get());
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timestamp_add_now(TS_START_ROMSTAGE);
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if (!cpu_init_detectedx && boot_cpu()) {
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/* Nothing special needs to be done to find bus 0 */
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/* Allow the HT devices to be found */
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@@ -200,8 +204,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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// die("Die Before MCT init.");
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timestamp_add_now(TS_BEFORE_INITRAM);
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printk(BIOS_DEBUG, "raminit_amdmct()\n");
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raminit_amdmct(sysinfo);
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timestamp_add_now(TS_AFTER_INITRAM);
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cbmem_initialize_empty();
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post_code(0x41);
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@@ -217,6 +224,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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rs780_before_pci_init();
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sb7xx_51xx_before_pci_init();
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timestamp_add_now(TS_END_ROMSTAGE);
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post_code(0x42);
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post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
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post_code(0x43); // Should never see this post code.
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@@ -33,6 +33,7 @@
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#include <device/pnp_def.h>
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#include <cpu/x86/lapic.h>
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#include <console/console.h>
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#include <timestamp.h>
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#include <cpu/amd/model_10xxx_rev.h>
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#include <northbridge/amd/amdfam10/raminit.h>
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#include <northbridge/amd/amdfam10/amdfam10.h>
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@@ -78,6 +79,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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u32 bsp_apicid = 0, val;
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msr_t msr;
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timestamp_init(timestamp_get());
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timestamp_add_now(TS_START_ROMSTAGE);
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if (!cpu_init_detectedx && boot_cpu()) {
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/* Nothing special needs to be done to find bus 0 */
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/* Allow the HT devices to be found */
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@@ -200,8 +204,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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// die("Die Before MCT init.");
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timestamp_add_now(TS_BEFORE_INITRAM);
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printk(BIOS_DEBUG, "raminit_amdmct()\n");
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raminit_amdmct(sysinfo);
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timestamp_add_now(TS_AFTER_INITRAM);
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cbmem_initialize_empty();
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post_code(0x41);
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@@ -217,6 +224,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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rs780_before_pci_init();
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sb7xx_51xx_before_pci_init();
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timestamp_add_now(TS_END_ROMSTAGE);
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post_code(0x42);
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post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
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post_code(0x43); // Should never see this post code.
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@@ -34,6 +34,7 @@
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#include <device/pnp_def.h>
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#include <cpu/x86/lapic.h>
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#include <console/console.h>
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#include <timestamp.h>
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#include <cpu/amd/model_10xxx_rev.h>
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#include <northbridge/amd/amdfam10/raminit.h>
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#include <northbridge/amd/amdfam10/amdfam10.h>
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@@ -78,6 +79,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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u32 bsp_apicid = 0, val;
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msr_t msr;
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timestamp_init(timestamp_get());
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timestamp_add_now(TS_START_ROMSTAGE);
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if (!cpu_init_detectedx && boot_cpu()) {
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/* Nothing special needs to be done to find bus 0 */
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/* Allow the HT devices to be found */
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@@ -195,8 +199,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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// die("Die Before MCT init.");
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timestamp_add_now(TS_BEFORE_INITRAM);
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printk(BIOS_DEBUG, "raminit_amdmct()\n");
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raminit_amdmct(sysinfo);
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timestamp_add_now(TS_AFTER_INITRAM);
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cbmem_initialize_empty();
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post_code(0x41);
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@@ -214,6 +221,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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rs780_before_pci_init();
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timestamp_add_now(TS_END_ROMSTAGE);
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post_code(0x42);
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post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
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post_code(0x43); // Should never see this post code.
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@@ -34,6 +34,7 @@
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#include <device/pnp_def.h>
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#include <cpu/x86/lapic.h>
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#include <console/console.h>
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#include <timestamp.h>
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#include <cpu/amd/model_10xxx_rev.h>
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#include <northbridge/amd/amdfam10/raminit.h>
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#include <northbridge/amd/amdfam10/amdfam10.h>
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@@ -80,6 +81,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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u32 bsp_apicid = 0, val;
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msr_t msr;
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timestamp_init(timestamp_get());
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timestamp_add_now(TS_START_ROMSTAGE);
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if (!cpu_init_detectedx && boot_cpu()) {
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/* Nothing special needs to be done to find bus 0 */
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/* Allow the HT devices to be found */
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@@ -199,8 +203,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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// die("Die Before MCT init.");
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timestamp_add_now(TS_BEFORE_INITRAM);
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printk(BIOS_DEBUG, "raminit_amdmct()\n");
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raminit_amdmct(sysinfo);
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timestamp_add_now(TS_AFTER_INITRAM);
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cbmem_initialize_empty();
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post_code(0x41);
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@@ -218,6 +225,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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rs780_before_pci_init();
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timestamp_add_now(TS_END_ROMSTAGE);
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post_code(0x42);
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post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
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post_code(0x43); // Should never see this post code.
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@@ -29,6 +29,7 @@
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#include <device/pnp_def.h>
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#include <cpu/x86/lapic.h>
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#include <console/console.h>
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#include <timestamp.h>
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#include <cpu/amd/model_10xxx_rev.h>
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#include <northbridge/amd/amdfam10/raminit.h>
|
||||
#include <northbridge/amd/amdfam10/amdfam10.h>
|
||||
@@ -74,6 +75,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
u32 bsp_apicid = 0, val;
|
||||
msr_t msr;
|
||||
|
||||
timestamp_init(timestamp_get());
|
||||
timestamp_add_now(TS_START_ROMSTAGE);
|
||||
|
||||
if (!cpu_init_detectedx && boot_cpu()) {
|
||||
/* Nothing special needs to be done to find bus 0 */
|
||||
/* Allow the HT devices to be found */
|
||||
@@ -195,8 +199,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
|
||||
// die("Die Before MCT init.");
|
||||
|
||||
timestamp_add_now(TS_BEFORE_INITRAM);
|
||||
printk(BIOS_DEBUG, "raminit_amdmct()\n");
|
||||
raminit_amdmct(sysinfo);
|
||||
timestamp_add_now(TS_AFTER_INITRAM);
|
||||
|
||||
cbmem_initialize_empty();
|
||||
post_code(0x41);
|
||||
|
||||
@@ -212,6 +219,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
rs780_before_pci_init();
|
||||
sb7xx_51xx_before_pci_init();
|
||||
|
||||
timestamp_add_now(TS_END_ROMSTAGE);
|
||||
|
||||
post_code(0x42);
|
||||
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
|
||||
post_code(0x43); // Should never see this post code.
|
||||
|
@@ -29,6 +29,7 @@
|
||||
#include <device/pnp_def.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <console/console.h>
|
||||
#include <timestamp.h>
|
||||
#include <cpu/amd/model_10xxx_rev.h>
|
||||
#include <northbridge/amd/amdfam10/raminit.h>
|
||||
#include <northbridge/amd/amdfam10/amdfam10.h>
|
||||
@@ -74,6 +75,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
u32 bsp_apicid = 0, val;
|
||||
msr_t msr;
|
||||
|
||||
timestamp_init(timestamp_get());
|
||||
timestamp_add_now(TS_START_ROMSTAGE);
|
||||
|
||||
if (!cpu_init_detectedx && boot_cpu()) {
|
||||
/* Nothing special needs to be done to find bus 0 */
|
||||
/* Allow the HT devices to be found */
|
||||
@@ -195,8 +199,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
|
||||
// die("Die Before MCT init.");
|
||||
|
||||
timestamp_add_now(TS_BEFORE_INITRAM);
|
||||
printk(BIOS_DEBUG, "raminit_amdmct()\n");
|
||||
raminit_amdmct(sysinfo);
|
||||
timestamp_add_now(TS_AFTER_INITRAM);
|
||||
|
||||
cbmem_initialize_empty();
|
||||
post_code(0x41);
|
||||
|
||||
@@ -212,6 +219,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
rs780_before_pci_init();
|
||||
sb7xx_51xx_before_pci_init();
|
||||
|
||||
timestamp_add_now(TS_END_ROMSTAGE);
|
||||
|
||||
post_code(0x42);
|
||||
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
|
||||
post_code(0x43); // Should never see this post code.
|
||||
|
@@ -33,6 +33,7 @@
|
||||
#include <device/pnp_def.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <console/console.h>
|
||||
#include <timestamp.h>
|
||||
#include <cpu/amd/model_10xxx_rev.h>
|
||||
#include <northbridge/amd/amdfam10/raminit.h>
|
||||
#include <northbridge/amd/amdfam10/amdfam10.h>
|
||||
@@ -78,6 +79,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
u32 bsp_apicid = 0, val;
|
||||
msr_t msr;
|
||||
|
||||
timestamp_init(timestamp_get());
|
||||
timestamp_add_now(TS_START_ROMSTAGE);
|
||||
|
||||
if (!cpu_init_detectedx && boot_cpu()) {
|
||||
/* Nothing special needs to be done to find bus 0 */
|
||||
/* Allow the HT devices to be found */
|
||||
@@ -198,8 +202,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
|
||||
// die("Die Before MCT init.");
|
||||
|
||||
timestamp_add_now(TS_BEFORE_INITRAM);
|
||||
printk(BIOS_DEBUG, "raminit_amdmct()\n");
|
||||
raminit_amdmct(sysinfo);
|
||||
timestamp_add_now(TS_AFTER_INITRAM);
|
||||
|
||||
cbmem_initialize_empty();
|
||||
post_code(0x41);
|
||||
|
||||
@@ -215,6 +222,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
rs780_before_pci_init();
|
||||
sb7xx_51xx_before_pci_init();
|
||||
|
||||
timestamp_add_now(TS_END_ROMSTAGE);
|
||||
|
||||
post_code(0x42);
|
||||
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
|
||||
post_code(0x43); // Should never see this post code.
|
||||
|
@@ -37,6 +37,7 @@
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include "option_table.h"
|
||||
#include <console/console.h>
|
||||
#include <timestamp.h>
|
||||
#include <cpu/amd/model_10xxx_rev.h>
|
||||
#include "southbridge/broadcom/bcm5785/early_smbus.c"
|
||||
#include <northbridge/amd/amdfam10/raminit.h>
|
||||
@@ -96,6 +97,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
u32 bsp_apicid = 0, val;
|
||||
msr_t msr;
|
||||
|
||||
timestamp_init(timestamp_get());
|
||||
timestamp_add_now(TS_START_ROMSTAGE);
|
||||
|
||||
if (!cpu_init_detectedx && boot_cpu()) {
|
||||
/* Nothing special needs to be done to find bus 0 */
|
||||
/* Allow the HT devices to be found */
|
||||
@@ -202,13 +206,18 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
/* all ap stopped? */
|
||||
// init_timer(); // Need to use TMICT to synchronize FID/VID
|
||||
|
||||
timestamp_add_now(TS_BEFORE_INITRAM);
|
||||
printk(BIOS_DEBUG, "raminit_amdmct()\n");
|
||||
raminit_amdmct(sysinfo);
|
||||
timestamp_add_now(TS_AFTER_INITRAM);
|
||||
|
||||
cbmem_initialize_empty();
|
||||
post_code(0x41);
|
||||
|
||||
bcm5785_early_setup();
|
||||
|
||||
timestamp_add_now(TS_END_ROMSTAGE);
|
||||
|
||||
post_cache_as_ram();
|
||||
}
|
||||
|
||||
|
@@ -33,6 +33,7 @@
|
||||
#include <device/pnp_def.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <console/console.h>
|
||||
#include <timestamp.h>
|
||||
#include <cpu/amd/model_10xxx_rev.h>
|
||||
#include <northbridge/amd/amdfam10/raminit.h>
|
||||
#include <northbridge/amd/amdfam10/amdfam10.h>
|
||||
@@ -77,6 +78,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
u32 bsp_apicid = 0, val;
|
||||
msr_t msr;
|
||||
|
||||
timestamp_init(timestamp_get());
|
||||
timestamp_add_now(TS_START_ROMSTAGE);
|
||||
|
||||
if (!cpu_init_detectedx && boot_cpu()) {
|
||||
/* Nothing special needs to be done to find bus 0 */
|
||||
/* Allow the HT devices to be found */
|
||||
@@ -198,8 +202,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
|
||||
// die("Die Before MCT init.");
|
||||
|
||||
timestamp_add_now(TS_BEFORE_INITRAM);
|
||||
printk(BIOS_DEBUG, "raminit_amdmct()\n");
|
||||
raminit_amdmct(sysinfo);
|
||||
timestamp_add_now(TS_AFTER_INITRAM);
|
||||
|
||||
cbmem_initialize_empty();
|
||||
post_code(0x41);
|
||||
|
||||
@@ -215,6 +222,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
rs780_before_pci_init();
|
||||
sb7xx_51xx_before_pci_init();
|
||||
|
||||
timestamp_add_now(TS_END_ROMSTAGE);
|
||||
|
||||
post_code(0x42);
|
||||
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
|
||||
post_code(0x43); // Should never see this post code.
|
||||
|
@@ -34,6 +34,7 @@
|
||||
#include <device/pnp_def.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <console/console.h>
|
||||
#include <timestamp.h>
|
||||
#include <cpu/amd/model_10xxx_rev.h>
|
||||
#include <northbridge/amd/amdfam10/raminit.h>
|
||||
#include <northbridge/amd/amdfam10/amdfam10.h>
|
||||
@@ -82,6 +83,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
u32 bsp_apicid = 0, val;
|
||||
msr_t msr;
|
||||
|
||||
timestamp_init(timestamp_get());
|
||||
timestamp_add_now(TS_START_ROMSTAGE);
|
||||
|
||||
if (!cpu_init_detectedx && boot_cpu()) {
|
||||
/* Nothing special needs to be done to find bus 0 */
|
||||
/* Allow the HT devices to be found */
|
||||
@@ -203,8 +207,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
|
||||
// die("Die Before MCT init.");
|
||||
|
||||
timestamp_add_now(TS_BEFORE_INITRAM);
|
||||
printk(BIOS_DEBUG, "raminit_amdmct()\n");
|
||||
raminit_amdmct(sysinfo);
|
||||
timestamp_add_now(TS_AFTER_INITRAM);
|
||||
|
||||
cbmem_initialize_empty();
|
||||
post_code(0x41);
|
||||
|
||||
@@ -220,6 +227,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
rs780_before_pci_init();
|
||||
sb7xx_51xx_before_pci_init();
|
||||
|
||||
timestamp_add_now(TS_END_ROMSTAGE);
|
||||
|
||||
post_code(0x42);
|
||||
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
|
||||
post_code(0x43); // Should never see this post code.
|
||||
|
@@ -30,6 +30,7 @@
|
||||
#include <device/pnp_def.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <console/console.h>
|
||||
#include <timestamp.h>
|
||||
#include <lib.h>
|
||||
#include <spd.h>
|
||||
#include <cpu/amd/model_10xxx_rev.h>
|
||||
@@ -106,6 +107,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
u8 reg;
|
||||
msr_t msr;
|
||||
|
||||
timestamp_init(timestamp_get());
|
||||
timestamp_add_now(TS_START_ROMSTAGE);
|
||||
|
||||
if (!cpu_init_detectedx && boot_cpu()) {
|
||||
/* Nothing special needs to be done to find bus 0 */
|
||||
/* Allow the HT devices to be found */
|
||||
@@ -229,11 +233,16 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
|
||||
post_code(0x40);
|
||||
|
||||
timestamp_add_now(TS_BEFORE_INITRAM);
|
||||
printk(BIOS_DEBUG, "raminit_amdmct()\n");
|
||||
raminit_amdmct(sysinfo);
|
||||
timestamp_add_now(TS_AFTER_INITRAM);
|
||||
|
||||
cbmem_initialize_empty();
|
||||
post_code(0x41);
|
||||
|
||||
timestamp_add_now(TS_END_ROMSTAGE);
|
||||
|
||||
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
|
||||
post_code(0x43); // Should never see this post code.
|
||||
}
|
||||
|
@@ -30,6 +30,7 @@
|
||||
#include <device/pnp_def.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <console/console.h>
|
||||
#include <timestamp.h>
|
||||
#include <lib.h>
|
||||
#include <spd.h>
|
||||
#include <cpu/amd/model_10xxx_rev.h>
|
||||
@@ -106,6 +107,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
u32 bsp_apicid = 0, val, wants_reset;
|
||||
msr_t msr;
|
||||
|
||||
timestamp_init(timestamp_get());
|
||||
timestamp_add_now(TS_START_ROMSTAGE);
|
||||
|
||||
if (!cpu_init_detectedx && boot_cpu()) {
|
||||
/* Nothing special needs to be done to find bus 0 */
|
||||
/* Allow the HT devices to be found */
|
||||
@@ -226,11 +230,16 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
|
||||
post_code(0x40);
|
||||
|
||||
timestamp_add_now(TS_BEFORE_INITRAM);
|
||||
printk(BIOS_DEBUG, "raminit_amdmct()\n");
|
||||
raminit_amdmct(sysinfo);
|
||||
timestamp_add_now(TS_AFTER_INITRAM);
|
||||
|
||||
cbmem_initialize_empty();
|
||||
post_code(0x41);
|
||||
|
||||
timestamp_add_now(TS_END_ROMSTAGE);
|
||||
|
||||
post_cache_as_ram(); // BSP switch stack to ram, copy + execute stage 2
|
||||
post_code(0x42); // Should never see this post code.
|
||||
}
|
||||
|
@@ -30,6 +30,7 @@
|
||||
#include <device/pnp_def.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <console/console.h>
|
||||
#include <timestamp.h>
|
||||
#include <lib.h>
|
||||
#include <spd.h>
|
||||
#include <cpu/amd/model_10xxx_rev.h>
|
||||
@@ -171,6 +172,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
u32 bsp_apicid = 0, val, wants_reset;
|
||||
msr_t msr;
|
||||
|
||||
timestamp_init(timestamp_get());
|
||||
timestamp_add_now(TS_START_ROMSTAGE);
|
||||
|
||||
if (!cpu_init_detectedx && boot_cpu()) {
|
||||
/* Nothing special needs to be done to find bus 0 */
|
||||
/* Allow the HT devices to be found */
|
||||
@@ -290,11 +294,15 @@ post_code(0x3D);
|
||||
|
||||
post_code(0x40);
|
||||
|
||||
timestamp_add_now(TS_BEFORE_INITRAM);
|
||||
printk(BIOS_DEBUG, "raminit_amdmct()\n");
|
||||
raminit_amdmct(sysinfo);
|
||||
timestamp_add_now(TS_AFTER_INITRAM);
|
||||
cbmem_initialize_empty();
|
||||
post_code(0x41);
|
||||
|
||||
timestamp_add_now(TS_END_ROMSTAGE);
|
||||
|
||||
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
|
||||
post_code(0x42); // Should never see this post code.
|
||||
}
|
||||
|
@@ -33,6 +33,7 @@
|
||||
#include <device/pnp_def.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <console/console.h>
|
||||
#include <timestamp.h>
|
||||
#include <cpu/amd/model_10xxx_rev.h>
|
||||
#include <northbridge/amd/amdfam10/raminit.h>
|
||||
#include <northbridge/amd/amdfam10/amdfam10.h>
|
||||
@@ -79,6 +80,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
u32 val;
|
||||
msr_t msr;
|
||||
|
||||
timestamp_init(timestamp_get());
|
||||
timestamp_add_now(TS_START_ROMSTAGE);
|
||||
|
||||
if (!cpu_init_detectedx && boot_cpu()) {
|
||||
/* Nothing special needs to be done to find bus 0 */
|
||||
/* Allow the HT devices to be found */
|
||||
@@ -210,8 +214,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
post_code(0x40);
|
||||
|
||||
|
||||
timestamp_add_now(TS_BEFORE_INITRAM);
|
||||
printk(BIOS_DEBUG, "raminit_amdmct()\n");
|
||||
raminit_amdmct(sysinfo);
|
||||
timestamp_add_now(TS_AFTER_INITRAM);
|
||||
|
||||
cbmem_initialize_empty();
|
||||
post_code(0x41);
|
||||
|
||||
@@ -230,6 +237,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
sr5650_before_pci_init();
|
||||
sb7xx_51xx_before_pci_init();
|
||||
|
||||
timestamp_add_now(TS_END_ROMSTAGE);
|
||||
|
||||
post_code(0x42);
|
||||
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
|
||||
post_code(0x43); // Should never see this post code.
|
||||
|
@@ -30,6 +30,7 @@
|
||||
#include <device/pnp_def.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <console/console.h>
|
||||
#include <timestamp.h>
|
||||
#include <lib.h>
|
||||
#include <spd.h>
|
||||
#include <cpu/amd/model_10xxx_rev.h>
|
||||
@@ -111,6 +112,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
u32 bsp_apicid = 0, val, wants_reset;
|
||||
msr_t msr;
|
||||
|
||||
timestamp_init(timestamp_get());
|
||||
timestamp_add_now(TS_START_ROMSTAGE);
|
||||
|
||||
if (!cpu_init_detectedx && boot_cpu()) {
|
||||
/* Nothing special needs to be done to find bus 0 */
|
||||
/* Allow the HT devices to be found */
|
||||
@@ -225,11 +229,16 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
|
||||
post_code(0x40);
|
||||
|
||||
timestamp_add_now(TS_BEFORE_INITRAM);
|
||||
printk(BIOS_DEBUG, "raminit_amdmct()\n");
|
||||
raminit_amdmct(sysinfo);
|
||||
timestamp_add_now(TS_AFTER_INITRAM);
|
||||
|
||||
cbmem_initialize_empty();
|
||||
post_code(0x41);
|
||||
|
||||
timestamp_add_now(TS_END_ROMSTAGE);
|
||||
|
||||
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
|
||||
post_code(0x43); // Should never see this post code.
|
||||
}
|
||||
|
Reference in New Issue
Block a user