mb/asus/p8z77-m_pro: Make devicetree prettier
Align comments, and make PCIe port comments consistent. Change-Id: Id39337236deff7721183e749a6b63aadaa036b2f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38070 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
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@@ -30,10 +30,11 @@ chip northbridge/intel/sandybridge
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end
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device domain 0x0 on
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subsystemid 0x1043 0x84ca inherit
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device pci 00.0 on end # Host bridge
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device pci 01.0 on end # PCIe Bridge for discrete graphics
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device pci 02.0 on end # Internal graphics VGA controller
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chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
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device pci 00.0 on end # Host bridge
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device pci 01.0 on end # PCIe Bridge for discrete graphics
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device pci 02.0 on end # Internal graphics VGA controller
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chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
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register "c2_latency" = "0x0065"
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register "gen1_dec" = "0x000c0291"
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register "gen4_dec" = "0x0000ff29"
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@@ -45,65 +46,66 @@ chip northbridge/intel/sandybridge
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register "superspeed_capable_ports" = "0x0000000f"
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register "xhci_overcurrent_mapping" = "0x00000c03"
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register "xhci_switchable_ports" = "0x0000000f" # the 4 ports
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device pci 14.0 on end # USB 3.0 Controller
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT
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device pci 19.0 off end # Intel Gigabit Ethernet
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device pci 1a.0 on end # USB2 EHCI 2
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device pci 1b.0 on end # High Definition Audio controller
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device pci 1c.0 on end # PCIe Root Port 1 PCIEX_16_3
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device pci 1c.1 on end # PCIe Root Port 6 RTL8111F
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device pci 1c.2 off end # PCIe Port 3 unused
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device pci 1c.3 off end # PCIe Port 4 unused
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device pci 1c.4 off end # PCIe Port 5 unused
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device pci 1c.5 on end # PCIe Root Port 7 ASM1042 USB3
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device pci 1c.6 on end # PCIe Root Port 8 ASM1061 eSATA
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device pci 1c.7 off end # PCIe Port 8 unused
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device pci 1d.0 on end # USB2 EHCI 1
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device pci 1e.0 off end # PCI bridge
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device pci 1f.0 on # LPC bridge
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device pci 14.0 on end # USB 3.0 Controller
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT
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device pci 19.0 off end # Intel Gigabit Ethernet
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device pci 1a.0 on end # USB2 EHCI 2
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device pci 1b.0 on end # High Definition Audio controller
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device pci 1c.0 on end # PCIe Port 1 PCIEX_16_3
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device pci 1c.1 on end # PCIe Port 2 RTL8111F
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device pci 1c.2 off end # PCIe Port 3 unused
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device pci 1c.3 off end # PCIe Port 4 unused
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device pci 1c.4 off end # PCIe Port 5 unused
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device pci 1c.5 on end # PCIe Port 6 ASM1042 USB3
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device pci 1c.6 on end # PCIe Port 7 ASM1061 eSATA
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device pci 1c.7 off end # PCIe Port 8 unused
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device pci 1d.0 on end # USB2 EHCI 1
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device pci 1e.0 off end # PCI bridge
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device pci 1f.0 on # LPC bridge
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chip superio/nuvoton/nct6779d
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device pnp 2e.1 off end # Parallel
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device pnp 2e.2 off end # UART A
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device pnp 2e.3 on # UART B, IR
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io 0x60 = 0x2f8 # COM2 address
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device pnp 2e.1 off end # Parallel
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device pnp 2e.2 off end # UART A
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device pnp 2e.3 on # UART B, IR
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io 0x60 = 0x2f8 # COM2 address
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end
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device pnp 2e.5 on # PS2 KBC
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io 0x60 = 0x0060 # KBC1 base
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io 0x62 = 0x0064 # KBC2 base
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irq 0x70 = 1 # Keyboard IRQ
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irq 0x72 = 12 # Mouse IRQ
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device pnp 2e.5 on # PS2 KBC
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io 0x60 = 0x0060 # KBC1 base
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io 0x62 = 0x0064 # KBC2 base
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irq 0x70 = 1 # Keyboard IRQ
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irq 0x72 = 12 # Mouse IRQ
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# KBC 12Mhz/A20 speed/sw KBRST
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drq 0xf0 = 0x82
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end
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device pnp 2e.6 off end # CIR
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device pnp 2e.7 on end # GPIOs 6-8
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device pnp 2e.8 off end # WDT1 GPIO 0-1
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device pnp 2e.9 off end # GPIO 1-8
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device pnp 2e.a on # ACPI
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drq 0xe4 = 0x10 # Enable 3VSBS to power RAM on S3
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drq 0xe7 = 0x10 # 0.5s S3 delay for compatibility
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device pnp 2e.6 off end # CIR
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device pnp 2e.7 on end # GPIOs 6-8
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device pnp 2e.8 off end # WDT1 GPIO 0-1
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device pnp 2e.9 off end # GPIO 1-8
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device pnp 2e.a on # ACPI
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drq 0xe4 = 0x10 # Enable 3VSBS to power RAM on S3
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drq 0xe7 = 0x10 # 0.5s S3 delay for compatibility
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end
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device pnp 2e.b off end # HWM, LED
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device pnp 2e.d off end # WDT1
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device pnp 2e.e off end # CIR wake-up
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device pnp 2e.f on # GPIO PP/OD
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drq 0xe6 = 0x7f # GP7 PP
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device pnp 2e.b off end # HWM, LED
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device pnp 2e.d off end # WDT1
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device pnp 2e.e off end # CIR wake-up
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device pnp 2e.f on # GPIO PP/OD
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drq 0xe6 = 0x7f # GP7 PP
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end
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device pnp 2e.14 on end # Port 80 UART
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device pnp 2e.16 off end # Deep sleep
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device pnp 2e.14 on end # Port 80 UART
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device pnp 2e.16 off end # Deep sleep
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end
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chip drivers/pc80/tpm
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device pnp 4e.0 on end # TPM module
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device pnp 4e.0 on end # TPM
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end
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end
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device pci 1f.2 on end # SATA Controller 1
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device pci 1f.3 on end # SMBus
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device pci 1f.5 off end # SATA Controller 2
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device pci 1f.6 off end # Thermal
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device pci 1f.2 on end # SATA Controller 1
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device pci 1f.3 on end # SMBus
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device pci 1f.5 off end # SATA Controller 2
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device pci 1f.6 off end # Thermal
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end
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end
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end
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