asus/p3b-f,intel/i440bx: Move enable/disable_spd() call
Change-Id: I4a324dcebcd53439206205e64c5bbb7c6eac4fb2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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@@ -49,7 +49,7 @@ int spd_read_byte(unsigned int device, unsigned int address)
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* 24-30 of the PIIX4E (bit 31 is reserved). Thus, GPIOs 27 and 28
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* control which SMBus/I2C offsets can be accessed.
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*/
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static void enable_spd(void)
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void enable_spd(void)
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{
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outb(0x6f, PM_IO_BASE + 0x37);
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}
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@@ -58,7 +58,7 @@ static void enable_spd(void)
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* Disable SPD access after RAM init to allow access to SMBus/I2C offsets
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* 0x48/0x49/0x2d, which is required e.g. by lm-sensors.
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*/
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static void disable_spd(void)
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void disable_spd(void)
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{
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outb(0x67, PM_IO_BASE + 0x37);
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}
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@@ -71,10 +71,8 @@ void mainboard_romstage_entry(void)
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enable_smbus();
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enable_pm();
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enable_spd();
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sdram_initialize();
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disable_spd();
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cbmem_initialize_empty();
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}
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@@ -1035,10 +1035,18 @@ void sdram_enable(void)
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DUMPNORTH();
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}
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/* Implemented under mainboard. */
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void __weak enable_spd(void) { }
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void __weak disable_spd(void) { }
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void sdram_initialize(void)
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{
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enable_spd();
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dump_spd_registers();
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sdram_set_registers();
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sdram_set_spd_registers();
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sdram_enable();
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disable_spd();
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}
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@@ -20,6 +20,9 @@
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/* The 440BX supports up to four (single- or double-sided) DIMMs. */
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#define DIMM_SOCKETS 4
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void enable_spd(void);
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void disable_spd(void);
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/* Function prototypes. */
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int spd_read_byte(unsigned int device, unsigned int address);
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void sdram_set_registers(void);
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