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google/eve: Configure I2C3 pins as GPIO inputs

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On this board i2c3 bus is connected to the display TCON, but it is
acting as the master when it has power so it can read from its own
EEPROM on the bus.  In order to prevent any possible issues in S0
make these pins input on the SOC.

BUG=chrome-os-partner:58666
TEST=tested on eve board, but this bus was not used before so
there is no visible change in behavior.

Change-Id: Ide32f45ee33ca986fd3249a5161e01edf99d6e22
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17800
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie
2016-12-12 10:43:45 -08:00
parent b7a52d3cd6
commit 93eb8c48b6
2 changed files with 4 additions and 5 deletions
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5
src/mainboard/google/eve/devicetree.cb
View File

@@ -163,7 +163,6 @@ chip soc/intel/skylake
register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" # Touchscreen
register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" # TPM
register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8" # Touchpad
register "i2c_voltage[3]" = "I2C_VOLTAGE_1V8" # Display
register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # Audio
# Enable I2C1 bus early for TPM access
@@ -175,7 +174,7 @@ chip soc/intel/skylake
[PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C1] = PchSerialIoPci,
[PchSerialIoIndexI2C2] = PchSerialIoPci,
[PchSerialIoIndexI2C3] = PchSerialIoPci,
[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
[PchSerialIoIndexI2C4] = PchSerialIoPci,
[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
[PchSerialIoIndexSpi0] = PchSerialIoPci,
@@ -237,7 +236,7 @@ chip soc/intel/skylake
device i2c 26 on end
end
end # I2C #2
device pci 15.3 on end # I2C #3
device pci 15.3 off end # I2C #3
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R

4
src/mainboard/google/eve/gpio.h
View File

@@ -177,8 +177,8 @@ static const struct pad_config gpio_table[] = {
/* I2S2_RXD */ PAD_CFG_GPI(GPP_F3, NONE, DEEP),
/* I2C2_SDA */ PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), /* TOUCHPAD */
/* I2C2_SCL */ PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1), /* TOUCHPAD */
/* I2C3_SDA */ PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1), /* DISPLAY */
/* I2C3_SCL */ PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1), /* DISPLAY */
/* I2C3_SDA */ PAD_CFG_GPI(GPP_F6, NONE, DEEP), /* DISPLAY is master */
/* I2C3_SCL */ PAD_CFG_GPI(GPP_F7, NONE, DEEP), /* DISPLAY is master */
/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), /* AUDIO1V8_SDA */
/* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), /* AUDIO1V8_SCL */
/* I2C5_SDA */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), /* MIC_INT_L */