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soc/intel/adl,mtl/romstage/fsp_params: fix clock request warning

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If a root port doesn't use a clock request pin, we shouldn't check if
this pin number, which defaults to 0 when not set, is already used. This
fixes the following spurious warning that was previously printed for
each external PCIe port which has the 'PCIE_RP_CLK_REQ_UNUSED' flag set
and didn't set 'clk_req' to some unused clock request pin number:

  Found overlapped clkreq assignment on clk req 0

Tested on the cw-al-4l-v2.0 mainboard that uses an Alder Lake N100 SoC
which I'm currently porting coreboot to. Also changing this for Meteor
Lake, since they have the same implementation in their romstage
fsp_params.c file

Change-Id: I3ee66ca5ed5a2d06dfb68c45a50e11eb2b93daa0
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
This commit is contained in:
Felix Held
2024-08-11 04:57:32 +02:00
parent c4b7fad847
commit 9419820127
2 changed files with 10 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
src/soc/intel/alderlake/romstage/fsp_params.c
View File

@@ -71,10 +71,12 @@ static void pcie_rp_init(FSP_M_CONFIG *m_cfg, uint32_t en_mask, enum pcie_rp_typ
printk(BIOS_WARNING, "Missing root port clock structure definition\n");
continue;
}
if (clk_req_mapping & (1 << cfg[i].clk_req))
printk(BIOS_WARNING, "Found overlapped clkreq assignment on clk req %d\n"
, cfg[i].clk_req);
if (!(cfg[i].flags & PCIE_RP_CLK_REQ_UNUSED)) {
if (clk_req_mapping & (1 << cfg[i].clk_req))
printk(BIOS_WARNING,
"Found overlapped clkreq assignment on clk req %d\n",
cfg[i].clk_req);
m_cfg->PcieClkSrcClkReq[cfg[i].clk_src] = cfg[i].clk_req;
clk_req_mapping |= 1 << cfg[i].clk_req;
}

8
src/soc/intel/meteorlake/romstage/fsp_params.c
View File

@@ -52,10 +52,12 @@ static void pcie_rp_init(FSP_M_CONFIG *m_cfg, uint32_t en_mask,
printk(BIOS_WARNING, "Missing root port clock structure definition\n");
continue;
}
if (clk_req_mapping & (1 << cfg[i].clk_req))
printk(BIOS_WARNING, "Found overlapped clkreq assignment on clk req %d\n"
, cfg[i].clk_req);
if (!(cfg[i].flags & PCIE_RP_CLK_REQ_UNUSED)) {
if (clk_req_mapping & (1 << cfg[i].clk_req))
printk(BIOS_WARNING,
"Found overlapped clkreq assignment on clk req %d\n",
cfg[i].clk_req);
m_cfg->PcieClkSrcClkReq[cfg[i].clk_src] = cfg[i].clk_req;
clk_req_mapping |= 1 << cfg[i].clk_req;
}