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util/romcc: Drop romcc support

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Finally all boards use a GCC compiled bootblock!

Change-Id: I0c9a1b19dbdc32b43875da7d685718bae9d7f5f4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37337
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans 2019-11-28 16:14:56 +01:00 committed by Patrick Georgi
parent c2092569d5
commit 945b698f82
147 changed files with 0 additions and 50038 deletions
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341
util/romcc/COPYING
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@ -1,341 +0,0 @@
GNU GENERAL PUBLIC LICENSE
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30
util/romcc/Makefile
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CC=gcc
CPPFLAGS=
CFLAGS= -g -Wall -Werror $(CPPFLAGS)
CPROF_FLAGS=-pg -fprofile-arcs
BUILD_DIR=build
default: $(BUILD_DIR)/romcc
$(BUILD_DIR)/romcc: romcc.c $(BUILD_DIR)
$(CC) $(CFLAGS) -o $@ $<
$(BUILD_DIR)/romcc_pg: romcc.c $(BUILD_DIR)
$(CC) $(CFLAGS) $(CPROF_FLAGS) -o $@ $<
$(BUILD_DIR):
mkdir -p $(BUILD_DIR)
test: $(BUILD_DIR)/romcc
./test.sh all
test-simple: $(BUILD_DIR)/romcc
./test.sh simple
test-linux: $(BUILD_DIR)/romcc
./test.sh linux
clean distclean:
rm -rf $(BUILD_DIR)
.PHONY: all test test-simple test-linux clean distclean

2
util/romcc/description.md
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Compile a C source file generating a binary that does not implicitly
use RAM. `C`

BIN
util/romcc/results/linux_test1.out
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Binary file not shown.

1
util/romcc/results/linux_test10.out
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@ -1 +0,0 @@
a: 00000001 b: 00000002 c: ffffffff d: 00000007

1
util/romcc/results/linux_test11.out
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@ -1 +0,0 @@
ffffffff

11
util/romcc/results/linux_test12.out
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hah?
Hi!! There
This should be shown as a string... "enclosed in quotes"
This is a quote" see
135 There
00000003
x ## y
romcc: 00.3b
linux_test12.c:test:0000003c
Compiled at: Apr 12 2004 12:06:09
Compile time: 12:06:09

14
util/romcc/results/linux_test13.out
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A
1
2
3
4
2
3
4
2
4
2
4
5
B

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util/romcc/results/linux_test2.out
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@ -1,59 +0,0 @@
setting up coherent ht domain....
0000c040 <-00010101
0000c044 <-00010101
0000c048 <-00010101
0000c04c <-00010101
0000c050 <-00010101
0000c054 <-00010101
0000c058 <-00010101
0000c05c <-00010101
0000c068 <-0f00840f
0000c06c <-00000070
0000c084 <-11110020
0000c088 <-00000200
0000c094 <-00ff0000
0000c144 <-003f0000
0000c14c <-00000001
0000c154 <-00000002
0000c15c <-00000003
0000c164 <-00000004
0000c16c <-00000005
0000c174 <-00000006
0000c17c <-00000007
0000c140 <-00000003
0000c148 <-00400000
0000c150 <-00400000
0000c158 <-00400000
0000c160 <-00400000
0000c168 <-00400000
0000c170 <-00400000
0000c178 <-00400000
0000c184 <-00e1ff00
0000c18c <-00dfff00
0000c194 <-00e3ff00
0000c19c <-00000000
0000c1a4 <-00000000
0000c1ac <-00000000
0000c1b4 <-00000b00
0000c1bc <-00fe0b00
0000c180 <-00e00003
0000c188 <-00d80003
0000c190 <-00e20003
0000c198 <-00000000
0000c1a0 <-00000000
0000c1a8 <-00000000
0000c1b0 <-00000a03
0000c1b8 <-00400003
0000c1c4 <-0000d000
0000c1cc <-000ff000
0000c1d4 <-00000000
0000c1dc <-00000000
0000c1c0 <-0000d003
0000c1c8 <-00001013
0000c1d0 <-00000000
0000c1d8 <-00000000
0000c1e0 <-ff000003
0000c1e4 <-00000000
0000c1e8 <-00000000
0000c1ec <-00000000
done.

11
util/romcc/results/linux_test3.out
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goto_test
i = 00
i = 01
i = 02
i = 03
i = 04
i = 05
i = 06
i = 07
i = 08
i = 09

11
util/romcc/results/linux_test4.out
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@ -1,11 +0,0 @@
cpu_socketA
.up=0002 .down=ffff .across=0001
.up=0003 .down=ffff .across=0000
.up=ffff .down=0000 .across=0003
.up=ffff .down=0001 .across=0002
cpu_socketB
.up=0002 .down=ffff .across=0001
.up=0003 .down=ffff .across=0000
.up=ffff .down=0000 .across=0003
.up=ffff .down=0001 .across=0002

34
util/romcc/results/linux_test5.out
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@ -1,34 +0,0 @@
min_cycle_time: 75 min_latency: 02
A
B
C
C
D
E
device: 00 new_cycle_time: 75 new_latency: 02
G
C
D
E
G
H
device: 00 new_cycle_time: 75 new_latency: 02
I
device: 00 min_cycle_time: 75 min_latency: 02
A
B
C
C
D
E
device: 01 new_cycle_time: 75 new_latency: 02
G
C
D
E
G
H
device: 01 new_cycle_time: 75 new_latency: 02
I
device: 01 min_cycle_time: 75 min_latency: 02
min_cycle_time: 75 min_latency: 02

2
util/romcc/results/linux_test6.out
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@ -1,2 +0,0 @@
B
Registered

32
util/romcc/results/linux_test7.out
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@ -1,32 +0,0 @@
val[00]: 0000c144 0000f8f8 00000000
val[03]: 0000c14c 0000f8f8 00000001
val[06]: 0000c154 0000f8f8 00000002
val[09]: 0000c15c 0000f8f8 00000003
val[0c]: 0000c164 0000f8f8 00000004
val[0f]: 0000c16c 0000f8f8 00000005
val[12]: 0000c174 0000f8f8 00000006
val[15]: 0000c17c 0000f8f8 00000007
val[00]: 0000c144 0000f8f8 00000000
val[03]: 0000c14c 0000f8f8 00000001
val[06]: 0000c154 0000f8f8 00000002
val[09]: 0000c15c 0000f8f8 00000003
val[0c]: 0000c164 0000f8f8 00000004
val[0f]: 0000c16c 0000f8f8 00000005
val[12]: 0000c174 0000f8f8 00000006
val[15]: 0000c17c 0000f8f8 00000007
val[00]: 0000c144 0000f8f8 00000000
val[03]: 0000c14c 0000f8f8 00000001
val[06]: 0000c154 0000f8f8 00000002
val[09]: 0000c15c 0000f8f8 00000003
val[0c]: 0000c164 0000f8f8 00000004
val[0f]: 0000c16c 0000f8f8 00000005
val[12]: 0000c174 0000f8f8 00000006
val[15]: 0000c17c 0000f8f8 00000007
val[00]: 0000c144 0000f8f8 00000000
val[03]: 0000c14c 0000f8f8 00000001
val[06]: 0000c154 0000f8f8 00000002
val[09]: 0000c15c 0000f8f8 00000003
val[0c]: 0000c164 0000f8f8 00000004
val[0f]: 0000c16c 0000f8f8 00000005
val[12]: 0000c174 0000f8f8 00000006
val[15]: 0000c17c 0000f8f8 00000007

1
util/romcc/results/linux_test8.out
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@ -1 +0,0 @@
clocks: 00000003

134
util/romcc/results/linux_test9.out
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@ -1,134 +0,0 @@
i: 0000007f
i: 00000080
i: 00000081
i: 00000082
i: 00000083
i: 00000084
i: 00000085
i: 00000086
i: 00000087
i: 00000088
i: 00000089
i: 0000008a
i: 0000008b
i: 0000008c
i: 0000008d
i: 0000008e
i: 0000008f
i: 00000090
i: 00000091
i: 00000092
i: 00000093
i: 00000094
i: 00000095
i: 00000096
i: 00000097
i: 00000098
i: 00000099
i: 0000009a
i: 0000009b
i: 0000009c
i: 0000009d
i: 0000009e
i: 0000009f
i: 000000a0
i: 000000a1
i: 000000a2
i: 000000a3
i: 000000a4
i: 000000a5
i: 000000a6
i: 000000a7
i: 000000a8
i: 000000a9
i: 000000aa
i: 000000ab
i: 000000ac
i: 000000ad
i: 000000ae
i: 000000af
i: 000000b0
i: 000000b1
i: 000000b2
i: 000000b3
i: 000000b4
i: 000000b5
i: 000000b6
i: 000000b7
i: 000000b8
i: 000000b9
i: 000000ba
i: 000000bb
i: 000000bc
i: 000000bd
i: 000000be
i: 000000bf
i: 000000c0
i: 000000c1
i: 000000c2
i: 000000c3
i: 000000c4
i: 000000c5
i: 000000c6
i: 000000c7
i: 000000c8
i: 000000c9
i: 000000ca
i: 000000cb
i: 000000cc
i: 000000cd
i: 000000ce
i: 000000cf
i: 000000d0
i: 000000d1
i: 000000d2
i: 000000d3
i: 000000d4
i: 000000d5
i: 000000d6
i: 000000d7
i: 000000d8
i: 000000d9
i: 000000da
i: 000000db
i: 000000dc
i: 000000dd
i: 000000de
i: 000000df
i: 000000e0
i: 000000e1
i: 000000e2
i: 000000e3
i: 000000e4
i: 000000e5
i: 000000e6
i: 000000e7
i: 000000e8
i: 000000e9
i: 000000ea
i: 000000eb
i: 000000ec
i: 000000ed
i: 000000ee
i: 000000ef
i: 000000f0
i: 000000f1
i: 000000f2
i: 000000f3
i: 000000f4
i: 000000f5
i: 000000f6
i: 000000f7
i: 000000f8
i: 000000f9
i: 000000fa
i: 000000fb
i: 000000fc
i: 000000fd
i: 000000fe
i: 000000ff
i: 00000000
i: 00000001
i: 00000002
i: 00000003
i: 00000004

244
util/romcc/romcc.1
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.TH ROMCC 1 "September 19, 2006"
.SH NAME
romcc \- compile C programs into binaries that don't use any RAM
.SH SYNOPSIS
.B romcc
[OPTIONS]
<source>.c
.SH DESCRIPTION
.B romcc
is a C compiler which produces binaries which do not rely on RAM, but
instead only use CPU registers.
.PP
It is prominently used in the coreboot project to compile C code which
needs to run before the firmware has initialized the RAM, but can be
used for other purposes, too.
.SH OPTIONS
.TP
.B "\-o" <filename>
Output file name.
.TP
.B "\-f<option>"
Specify a generic compiler option.
.TP
.B "\-m<option>"
Specify an architecture-dependent compiler option.
.TP
.B "\-\-"
Specify that this is the last option.
.SH "GENERIC COMPILER OPTIONS"
.B "\-O"
.TP
.B "\-O2"
.TP
.B "\-E"
.TP
.B "\-ftrigraphs"
.TP
.B "\-fno-trigraphs"
.TP
.B "\-fpp-only"
.TP
.B "\-fno-pp-only"
.TP
.B "\-feliminate-inefectual-code"
.TP
.B "\-fno-eliminate-inefectual-code"
.TP
.B "\-fsimplify"
.TP
.B "\-fno-simplify"
.TP
.B "\-fscc-transform"
.TP
.B "\-fno-scc-transform"
.TP
.B "\-fsimplify-op"
.TP
.B "\-fno-simplify-op"
.TP
.B "\-fsimplify-phi"
.TP
.B "\-fno-simplify-phi"
.TP
.B "\-fsimplify-label"
.TP
.B "\-fno-simplify-label"
.TP
.B "\-fsimplify-branch"
.TP
.B "\-fno-simplify-branch"
.TP
.B "\-fsimplify-copy"
.TP
.B "\-fno-simplify-copy"
.TP
.B "\-fsimplify-arith"
.TP
.B "\-fno-simplify-arith"
.TP
.B "\-fsimplify-shift"
.TP
.B "\-fno-simplify-shift"
.TP
.B "\-fsimplify-bitwise"
.TP
.B "\-fno-simplify-bitwise"
.TP
.B "\-fsimplify-logical"
.TP
.B "\-fno-simplify-logical"
.TP
.B "\-fsimplify-bitfield"
.TP
.B "\-fno-simplify-bitfield"
.TP
.B "\-finline-policy=always"
.TP
.B "\-finline-policy=never"
.TP
.B "\-finline-policy=defaulton"
.TP
.B "\-finline-policy=defaultoff"
.TP
.B "\-finline-policy=nopenalty"
.TP
.B "\-fdebug-all"
.TP
.B "\-fno-debug-all"
.TP
.B "\-fdebug-abort-on-error"
.TP
.B "\-fno-debug-abort-on-error"
.TP
.B "\-fdebug-basic-blocks"
.TP
.B "\-fno-debug-basic-blocks"
.TP
.B "\-fdebug-fdominators"
.TP
.B "\-fno-debug-fdominators"
.TP
.B "\-fdebug-rdominators"
.TP
.B "\-fno-debug-rdominators"
.TP
.B "\-fdebug-triples"
.TP
.B "\-fno-debug-triples"
.TP
.B "\-fdebug-interference"
.TP
.B "\-fno-debug-interference"
.TP
.B "\-fdebug-scc-transform"
.TP
.B "\-fno-debug-scc-transform"
.TP
.B "\-fdebug-scc-transform2"
.TP
.B "\-fno-debug-scc-transform2"
.TP
.B "\-fdebug-rebuild-ssa-form"
.TP
.B "\-fno-debug-rebuild-ssa-form"
.TP
.B "\-fdebug-inline"
.TP
.B "\-fno-debug-inline"
.TP
.B "\-fdebug-live-range-conflicts"
.TP
.B "\-fno-debug-live-range-conflicts"
.TP
.B "\-fdebug-live-range-conflicts2"
.TP
.B "\-fno-debug-live-range-conflicts2"
.TP
.B "\-fdebug-color-graph"
.TP
.B "\-fno-debug-color-graph"
.TP
.B "\-fdebug-color-graph2"
.TP
.B "\-fno-debug-color-graph2"
.TP
.B "\-fdebug-coalescing"
.TP
.B "\-fno-debug-coalescing"
.TP
.B "\-fdebug-coalescing2"
.TP
.B "\-fno-debug-coalescing2"
.TP
.B "\-fdebug-verification"
.TP
.B "\-fno-debug-verification"
.TP
.B "\-fdebug-calls"
.TP
.B "\-fno-debug-calls"
.TP
.B "\-fdebug-calls2"
.TP
.B "\-fno-debug-calls2"
.TP
.B "\-fdebug-tokens"
.TP
.B "\-fno-debug-tokens"
.TP
.B "\-flabel-prefix=<prefix for assembly language labels>"
.TP
.B "\-\-label-prefix=<prefix for assembly language labels>"
.TP
.B "\-I<include path>"
.TP
.B "\-D<macro>[=defn]"
.TP
.B "\-U<macro>"
.SH "ARCHITECTURE-SPECIFIC COMPILER OPTIONS"
.B "\-mmmx"
.TP
.B "\-mno-mmx"
.TP
.B "\-msse"
.TP
.B "\-mno-sse"
.TP
.B "\-mnoop-copy"
.TP
.B "\-mno-noop-copy"
.TP
.B "\-mcpu=i386"
.TP
.B "\-mcpu=p2"
.TP
.B "\-mcpu=p3"
.TP
.B "\-mcpu=p4"
.TP
.B "\-mcpu=k7"
.TP
.B "\-mcpu=k8"
.TP
.B "\-mcpu=c3"
.TP
.B "\-mcpu=c3-2"
.SH BUGS
Please report any bugs to https://ticket.coreboot.org/projects/coreboot or the
coreboot mailing list at <coreboot@coreboot.org>.
.SH LICENCE
.B romcc
is covered by the GNU General Public License (GPL), version 2.
.SH SEE ALSO
.BR flashrom (1),
.BR abuild (1).
.SH COPYRIGHT
2003-2006 Eric W. Biederman
.SH AUTHORS
Eric W. Biederman <ebiederman@lnxi.com>
.br
Some contributions by others.
.PP
This manual page was written by Uwe Hermann <uwe@hermann-uwe.de>.
It is licensed under the terms of the GNU GPL (v2 or later).

25199
util/romcc/romcc.c
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File diff suppressed because it is too large Load Diff

232
util/romcc/test.sh
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@ -1,232 +0,0 @@
#!/bin/sh
#
# This file is part of the coreboot project.
#
# Copyright 2016 Jonathan Neuschäfer <j.neuschaefer@gmx.net>
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
# These tests are currently known to be broken and should not result in a
# build failure:
XFAIL_TESTS="
simple_test4.c
simple_test6.c
simple_test25.c
simple_test26.c
simple_test46.c
simple_test47.c
simple_test54.c
simple_test72.c
simple_test73.c
linux_test2.c
linux_test5.c
linux_test10.c
linux_test11.c
linux_test12.c
"
# ------------------------------------------------------------------- #
BASEDIR="$(dirname "$0")"
BUILDDIR="$BASEDIR/build"
LOGDIR="$BUILDDIR/logs"
mkdir -p "$BUILDDIR"
mkdir -p "$LOGDIR"
usage () {
echo "Usage: test.sh [--nocolor] CLASS"
echo ""
echo "CLASS selects a group of tests to run. It must be one of the following:"
echo " all - all tests"
echo " simple - simple tests"
echo " linux - linux programs whose output is checked against a reference"
echo ""
echo "--nocolor disables colors."
exit 1
}
COLORS=1
if [ "$1" = "--nocolor" ]; then
shift
COLORS=0
fi
if [ -t 1 -a "$COLORS" -eq 1 ]; then
red() { printf "\033[1;31m%s\033[0m" "$*"; }
green() { printf "\033[1;32m%s\033[0m" "$*"; }
blue() { printf "\033[1;34m%s\033[0m" "$*"; }
else
red() { printf "%s" "$*"; }
green() { printf "%s" "$*"; }
blue() { printf "%s" "$*"; }
fi
init_stats() {
NUM_TOTAL=0 # Number of tests that were run
NUM_FAIL=0 # Number of tests that failed unexpectedly
NUM_BROKEN=0 # Number of tests that failed expectedly
NUM_PASS=0 # Number of tests that passed expectedly
NUM_FIXED=0 # Number of tests that passed unexpectedly
}
get_romcc() {
ROMCC="$BUILDDIR/romcc"
if [ ! -f "$ROMCC" ]; then
echo "romcc not found! Please run \"make\"."
exit 1
fi
}
init_testing() {
init_stats
get_romcc
}
show_stats() {
printf "passed: %s\t(%s newly fixed)\n" $NUM_PASS $NUM_FIXED
printf "failed: %s\t(%s known broken)\n" $NUM_FAIL $NUM_BROKEN
printf "total: %s\n" $NUM_TOTAL
}
is_xfail() {
local t
for t in $XFAIL_TESTS; do
if [ "$t" = "$1" ]; then
return 0
fi
done
return 1
}
pass() {
NUM_TOTAL=$((NUM_TOTAL + 1))
NUM_PASS=$((NUM_PASS + 1))
green "passed"
if is_xfail "$(basename "$1")"; then
blue " (fixed)"
NUM_FIXED=$((NUM_FIXED + 1))
fi
echo
}
fail() {
NUM_TOTAL=$((NUM_TOTAL + 1))
NUM_FAIL=$((NUM_FAIL + 1))
red "failed"
if is_xfail "$(basename "$1")"; then
blue " (known broken)"
NUM_BROKEN=$((NUM_BROKEN + 1))
fi
echo
}
run_simple_test() {
# TODO: "timeout" is not POSIX compliant. Use something that is.
timeout 60 "$ROMCC" $1 "$2" -o "$BUILDDIR/dummy.S"
}
run_simple_tests() {
echo "Running simple tests..."
local t
for t in $(find "$BASEDIR/tests" -name 'simple_test*.c'); do
printf "%s" "$(basename "$t")"
local result=pass
local logfile="$LOGDIR/$(basename "$t").log"
rm "$logfile" >/dev/null 2>&1
for opt in "" "-O" "-O2" "-mmmx" "-msse" "-mmmx -msse" \
"-O -mmmx" "-O -msse" "-O -mmmx -msse" \
"-O2 -mmmx" "-O2 -msse" "-O2 -mmmx -msse"; do
if run_simple_test "$opt" "$t" \
>> "$logfile" 2>&1; then
printf .
else
result=fail
break
fi
done
printf " "
$result "$t"
done
echo
}
run_linux_test() {
local base="$(basename "$1")"
# TODO: "timeout" is not POSIX compliant. Use something that is.
timeout 60 "$ROMCC" "$1" -o "$BUILDDIR/$base.S" || return 1
as --32 "$BUILDDIR/$base.S" -o "$BUILDDIR/$base.o" || return 1
ld -m elf_i386 -T "$BASEDIR/tests/ldscript.ld" \
"$BUILDDIR/$base.o" -o "$BUILDDIR/$base.elf" || return 1
timeout 60 "$BUILDDIR/$base.elf" > "$BUILDDIR/$base.out" || return 1
diff -u "$BASEDIR/results/${base%.c}.out" "$BUILDDIR/$base.out"
}
run_linux_tests() {
echo "Running linux tests..."
local t
for t in $(find "$BASEDIR/tests" -name 'linux_test*.c'); do
printf "%s... " "$(basename "$t")"
local logfile="$LOGDIR/$(basename "$t").log"
if run_linux_test "$t" > "$logfile" 2>&1; then
pass "$t"
else
fail "$t"
fi
done
echo
}
if [ $# -ne 1 ]; then
usage
fi
CLASS="$1"
case "$CLASS" in
all)
init_testing
run_simple_tests
run_linux_tests
show_stats
;;
simple)
init_testing
run_simple_tests
show_stats
;;
linux)
init_testing
run_linux_tests
show_stats
;;
*)
echo "Invalid test class $CLASS"
echo
usage
;;
esac
if [ $NUM_FAIL -ne $NUM_BROKEN ]; then
exit 1
fi

5
util/romcc/tests/fail_test1.c
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@ -1,5 +0,0 @@
static void main(void)
{
int i;
i|=0x80;
}

18
util/romcc/tests/fail_test10.c
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@ -1,18 +0,0 @@
struct result {
int a, b, c, d;
};
struct big_arg {
int a, b;
};
static struct result main(int a, int b, struct big_arg d)
{
struct result result;
result.a = 1;
result.b = 1;
result.c = b + 1;
result.d = a + 1;
}

20
util/romcc/tests/fail_test11.c
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@ -1,20 +0,0 @@
struct big_arg {
int x, y;
};
struct result {
struct big_arg a;
int c, d;
};
static struct result main(int a, int b, int c, int d)
{
struct result result;
result.a.x = d + 1;
result.a.y = c + 1;
result.c = b + 1;
result.d = a + 1;
return result;
}

18
util/romcc/tests/fail_test2.c
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@ -1,18 +0,0 @@
static void main(void)
{
unsigned min;
int value, latency;
latency = -2;
if (latency > (((min) >> 8) & 0xff)) {
value = 0xa;
}
if (value < 0) return;
((min) = (((min) & ~0xff)));
}

10
util/romcc/tests/fail_test3.c
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@ -1,10 +0,0 @@
static void main(void)
{
volatile unsigned long *val = (volatile unsigned long *)0x1234;
int i;
if (val[0] > 25) {
i = 7;
}
val[1] = i;
}

14
util/romcc/tests/fail_test4.c
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@ -1,14 +0,0 @@
static void main(void)
{
static const int foo = 2;
switch(foo) {
case 1:
break;
case 2:
break;
case 1:
break;
default:
break;
}
}

14
util/romcc/tests/fail_test5.c
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@ -1,14 +0,0 @@
static void main(void)
{
static const int foo = 2;
switch(foo) {
case 1:
break;
default:
break;
case 2:
break;
default:
break;
}
}

11
util/romcc/tests/fail_test6.c
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@ -1,11 +0,0 @@
static void hlt(void)
{
}
static void main(void)
{
void *foo;
foo = hlt;
}

10
util/romcc/tests/fail_test7.c
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@ -1,10 +0,0 @@
static void hlt(void)
{
}
static void main(void)
{
&hlt;
}

10
util/romcc/tests/fail_test8.c
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@ -1,10 +0,0 @@
static void hlt(void)
{
}
static void main(void)
{
hlt;
}

8
util/romcc/tests/fail_test9.c
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@ -1,8 +0,0 @@
typedef __builtin_msr_t msr_t;
static msr_t rdmsr(unsigned long index)
{
return __builtin_rdmsr(index);
}
#warning "romcc should die gracefully here"

128
util/romcc/tests/hello_world.c
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@ -1,128 +0,0 @@
void outb(unsigned char value, unsigned short port)
{
__builtin_outb(value, port);
}
unsigned char inb(unsigned short port)
{
return __builtin_inb(port);
}
/* Base Address */
#ifndef CONFIG_TTYS0_BASE
#define CONFIG_TTYS0_BASE 0x3f8
#endif
#ifndef CONFIG_TTYS0_BAUD
#define CONFIG_TTYS0_BAUD 115200
#endif
#if ((115200%CONFIG_TTYS0_BAUD) != 0)
#error Bad ttys0 baud rate
#endif
#if CONFIG_TTYS0_BAUD == 115200
#define CONFIG_TTYS0_DIV (1)
#else
#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD)
#endif
/* Line Control Settings */
#ifndef CONFIG_TTYS0_LCS
/* Set 8bit, 1 stop bit, no parity */
#define CONFIG_TTYS0_LCS 0x3
#endif
#define UART_LCS CONFIG_TTYS0_LCS
/* Data */
#define UART_RBR 0x00
#define UART_TBR 0x00
/* Control */
#define UART_IER 0x01
#define UART_IIR 0x02
#define UART_FCR 0x02
#define UART_LCR 0x03
#define UART_MCR 0x04
#define UART_DLL 0x00
#define UART_DLM 0x01
/* Status */
#define UART_LSR 0x05
#define UART_MSR 0x06
#define UART_SCR 0x07
int uart_can_tx_byte(void)
{
return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20;
}
void uart_wait_to_tx_byte(void)
{
while(!uart_can_tx_byte())
;
}
void uart_wait_until_sent(void)
{
while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40))
;
}
static void uart_tx_byte(unsigned char data)
{
uart_wait_to_tx_byte();
outb(data, CONFIG_TTYS0_BASE + UART_TBR);
/* Make certain the data clears the fifos */
uart_wait_until_sent();
}
void uart_init(void)
{
/* disable interrupts */
outb(0x0, CONFIG_TTYS0_BASE + UART_IER);
/* enable fifo's */
outb(0x01, CONFIG_TTYS0_BASE + UART_FCR);
/* Set Baud Rate Divisor to 12 ==> 115200 Baud */
outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR);
outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL);
outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM);
outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR);
}
void __console_tx_char(unsigned char byte)
{
uart_tx_byte(byte);
}
void __console_tx_string(char *str)
{
unsigned char ch;
while((ch = *str++) != '\0') {
__console_tx_char(ch);
}
}
void print_debug_char(unsigned char byte) { __console_tx_char(byte); }
void print_debug(char *str) { __console_tx_string(str); }
void main(void)
{
static const char msg[] = "hello world\r\n";
uart_init();
#if 0
print_debug(msg);
#endif
#if 1
print_debug("hello world\r\n");
print_debug("how are you today\r\n");
#endif
while(1) {
;
}
}

128
util/romcc/tests/hello_world1.c
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@ -1,128 +0,0 @@
void outb(unsigned char value, unsigned short port)
{
__builtin_outb(value, port);
}
unsigned char inb(unsigned short port)
{
return __builtin_inb(port);
}
/* Base Address */
#ifndef CONFIG_TTYS0_BASE
#define CONFIG_TTYS0_BASE 0x3f8
#endif
#ifndef CONFIG_TTYS0_BAUD
#define CONFIG_TTYS0_BAUD 115200
#endif
#if ((115200%CONFIG_TTYS0_BAUD) != 0)
#error Bad ttys0 baud rate
#endif
#if CONFIG_TTYS0_BAUD == 115200
#define CONFIG_TTYS0_DIV (1)
#else
#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD)
#endif
/* Line Control Settings */
#ifndef CONFIG_TTYS0_LCS
/* Set 8bit, 1 stop bit, no parity */
#define CONFIG_TTYS0_LCS 0x3
#endif
#define UART_LCS CONFIG_TTYS0_LCS
/* Data */
#define UART_RBR 0x00
#define UART_TBR 0x00
/* Control */
#define UART_IER 0x01
#define UART_IIR 0x02
#define UART_FCR 0x02
#define UART_LCR 0x03
#define UART_MCR 0x04
#define UART_DLL 0x00
#define UART_DLM 0x01
/* Status */
#define UART_LSR 0x05
#define UART_MSR 0x06
#define UART_SCR 0x07
int uart_can_tx_byte(void)
{
return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20;
}
void uart_wait_to_tx_byte(void)
{
while(!uart_can_tx_byte())
;
}
void uart_wait_until_sent(void)
{
while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40))
;
}
static void uart_tx_byte(unsigned char data)
{
uart_wait_to_tx_byte();
outb(data, CONFIG_TTYS0_BASE + UART_TBR);
/* Make certain the data clears the fifos */
uart_wait_until_sent();
}
void uart_init(void)
{
/* disable interrupts */
outb(0x0, CONFIG_TTYS0_BASE + UART_IER);
/* enable fifo's */
outb(0x01, CONFIG_TTYS0_BASE + UART_FCR);
/* Set Baud Rate Divisor to 12 ==> 115200 Baud */
outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR);
outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL);
outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM);
outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR);
}
void __console_tx_char(unsigned char byte)
{
uart_tx_byte(byte);
}
void __console_tx_string(char *str)
{
unsigned char ch;
while((ch = *str++) != '\0') {
__console_tx_char(ch);
}
}
void print_debug_char(unsigned char byte) { __console_tx_char(byte); }
void print_debug(char *str) { __console_tx_string(str); }
void main(void)
{
static const char msg[] = "hello world\r\n";
uart_init();
#if 0
print_debug(msg);
#endif
#if 1
print_debug("hello world\r\n");
print_debug("how are you today\r\n");
#endif
while(1) {
;
}
}

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util/romcc/tests/hello_world2.c
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@ -1,127 +0,0 @@
void outb(unsigned char value, unsigned short port)
{
__builtin_outb(value, port);
}
unsigned char inb(unsigned short port)
{
return __builtin_inb(port);
}
/* Base Address */
#ifndef CONFIG_TTYS0_BASE
#define CONFIG_TTYS0_BASE 0x3f8
#endif
#ifndef CONFIG_TTYS0_BAUD
#define CONFIG_TTYS0_BAUD 115200
#endif
#if ((115200%CONFIG_TTYS0_BAUD) != 0)
#error Bad ttys0 baud rate
#endif
#if CONFIG_TTYS0_BAUD == 115200
#define CONFIG_TTYS0_DIV (1)
#else
#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD)
#endif
/* Line Control Settings */
#ifndef CONFIG_TTYS0_LCS
/* Set 8bit, 1 stop bit, no parity */
#define CONFIG_TTYS0_LCS 0x3
#endif
#define UART_LCS CONFIG_TTYS0_LCS
/* Data */
#define UART_RBR 0x00
#define UART_TBR 0x00
/* Control */
#define UART_IER 0x01
#define UART_IIR 0x02
#define UART_FCR 0x02
#define UART_LCR 0x03
#define UART_MCR 0x04
#define UART_DLL 0x00
#define UART_DLM 0x01
/* Status */
#define UART_LSR 0x05
#define UART_MSR 0x06
#define UART_SCR 0x07
int uart_can_tx_byte(void)
{
return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20;
}
void uart_wait_to_tx_byte(void)
{
while(!uart_can_tx_byte())
;
}
void uart_wait_until_sent(void)
{
while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40))
;
}
static void uart_tx_byte(unsigned char data)
{
uart_wait_to_tx_byte();
outb(data, CONFIG_TTYS0_BASE + UART_TBR);
/* Make certain the data clears the fifos */
uart_wait_until_sent();
}
void uart_init(void)
{
/* disable interrupts */
outb(0x0, CONFIG_TTYS0_BASE + UART_IER);
/* enable fifo's */
outb(0x01, CONFIG_TTYS0_BASE + UART_FCR);
/* Set Baud Rate Divisor to 12 ==> 115200 Baud */
outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR);
outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL);
outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM);
outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR);
}
void __console_tx_char(unsigned char byte)
{
uart_tx_byte(byte);
}
void __console_tx_string(char *str)
{
unsigned char ch;
while((ch = *str++) != '\0') {
__console_tx_char(ch);
}
}
void print_debug_char(unsigned char byte) { __console_tx_char(byte); }
void print_debug(char *str) { __console_tx_string(str); }
void main(void)
{
static const char msg[] = "hello world\r\n";
uart_init();
#if 0
print_debug(msg);
#endif
#if 1
print_debug("hello world\r\n");
#endif
while(1) {
;
}
}

136
util/romcc/tests/include/linux_console.h
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@ -1,136 +0,0 @@
#ifndef LINUX_CONSOLE_H
#define LINUX_CONSOLE_H
#include "linux_syscall.h"
static const char *addr_of_char(unsigned char ch)
{
static const char byte[] = {
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f,
0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f,
0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97,
0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f,
0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,
0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf,
0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7,
0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf,
0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf,
0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7,
0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf,
0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7,
0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef,
0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7,
0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff,
};
return byte + ch;
}
static void console_tx_byte(unsigned char ch)
{
write(STDOUT_FILENO, addr_of_char(ch), 1);
}
static inline void console_tx_nibble(unsigned nibble)
{
unsigned char digit;
digit = nibble + '0';
if (digit > '9') {
digit += 39;
}
console_tx_byte(digit);
}
static void console_tx_char(unsigned char byte)
{
console_tx_byte(byte);
}
static void console_tx_hex8(unsigned char value)
{
console_tx_nibble((value >> 4U) & 0x0fU);
console_tx_nibble(value & 0x0fU);
}
static void console_tx_hex16(unsigned short value)
{
console_tx_nibble((value >> 12U) & 0x0FU);
console_tx_nibble((value >> 8U) & 0x0FU);
console_tx_nibble((value >> 4U) & 0x0FU);
console_tx_nibble(value & 0x0FU);
}
static void console_tx_hex32(unsigned int value)
{
console_tx_nibble((value >> 28U) & 0x0FU);
console_tx_nibble((value >> 24U) & 0x0FU);
console_tx_nibble((value >> 20U) & 0x0FU);
console_tx_nibble((value >> 16U) & 0x0FU);
console_tx_nibble((value >> 12U) & 0x0FU);
console_tx_nibble((value >> 8U) & 0x0FU);
console_tx_nibble((value >> 4U) & 0x0FU);
console_tx_nibble(value & 0x0FU);
}
static void console_tx_string(const char *str)
{
unsigned char ch;
while((ch = *str++) != '\0') {
console_tx_byte(ch);
}
}
static void print_emerg_char(unsigned char byte) { console_tx_char(byte); }
static void print_emerg_hex8(unsigned char value) { console_tx_hex8(value); }
static void print_emerg_hex16(unsigned short value){ console_tx_hex16(value); }
static void print_emerg_hex32(unsigned int value) { console_tx_hex32(value); }
static void print_emerg(const char *str) { console_tx_string(str); }
static void print_warn_char(unsigned char byte) { console_tx_char(byte); }
static void print_warn_hex8(unsigned char value) { console_tx_hex8(value); }
static void print_warn_hex16(unsigned short value){ console_tx_hex16(value); }
static void print_warn_hex32(unsigned int value) { console_tx_hex32(value); }
static void print_warn(const char *str) { console_tx_string(str); }
static void print_info_char(unsigned char byte) { console_tx_char(byte); }
static void print_info_hex8(unsigned char value) { console_tx_hex8(value); }
static void print_info_hex16(unsigned short value){ console_tx_hex16(value); }
static void print_info_hex32(unsigned int value) { console_tx_hex32(value); }
static void print_info(const char *str) { console_tx_string(str); }
static void print_debug_char(unsigned char byte) { console_tx_char(byte); }
static void print_debug_hex8(unsigned char value) { console_tx_hex8(value); }
static void print_debug_hex16(unsigned short value){ console_tx_hex16(value); }
static void print_debug_hex32(unsigned int value) { console_tx_hex32(value); }
static void print_debug(const char *str) { console_tx_string(str); }
static void print_spew_char(unsigned char byte) { console_tx_char(byte); }
static void print_spew_hex8(unsigned char value) { console_tx_hex8(value); }
static void print_spew_hex16(unsigned short value){ console_tx_hex16(value); }
static void print_spew_hex32(unsigned int value) { console_tx_hex32(value); }
static void print_spew(const char *str) { console_tx_string(str); }
static void die(const char *str)
{
print_emerg(str);
do {
asm volatile (" ");
} while(1);
}
#endif /* LINUX_CONSOLE_H */

7
util/romcc/tests/include/linux_syscall.h
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@ -1,7 +0,0 @@
#ifndef LINUX_SYSCALL_H
#define LINUX_SYSCALL_H
/* When I support other platforms use #ifdefs here */
#include "linuxi386_syscall.h"
#endif /* LINUX_SYSCALL_H */

299
util/romcc/tests/include/linuxi386_syscall.h
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@ -1,299 +0,0 @@
struct syscall_result {
long val;
int errno;
};
static inline struct syscall_result syscall_return(long result)
{
struct syscall_result res;
if (((unsigned long)result) >= ((unsigned long)-125)) {
res.errno = - result;
res.val = -1;
} else {
res.errno = 0;
res.val = result;
}
return res;
}
static struct syscall_result syscall0(unsigned long nr)
{
long res;
asm volatile(
"int $0x80"
: "=a" (res)
: "a" (nr));
return syscall_return(res);
}
static struct syscall_result syscall1(unsigned long nr, unsigned long arg1)
{
long res;
asm volatile(
"int $0x80"
: "=a" (res)
: "a" (nr), "b" (arg1));
return syscall_return(res);
}
static struct syscall_result syscall2(unsigned long nr, unsigned long arg1, unsigned long arg2)
{
long res;
asm volatile(
"int $0x80"
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2));
return syscall_return(res);
}
static struct syscall_result syscall3(unsigned long nr, unsigned long arg1, unsigned long arg2,
unsigned long arg3)
{
long res;
asm volatile(
"int $0x80"
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3));
return syscall_return(res);
}
static struct syscall_result syscall4(unsigned long nr, unsigned long arg1, unsigned long arg2,
unsigned long arg3, unsigned long arg4)
{
long res;
asm volatile(
"int $0x80"
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), "S" (arg4));
return syscall_return(res);
}
static struct syscall_result syscall5(unsigned long nr, unsigned long arg1, unsigned long arg2,
unsigned long arg3, unsigned long arg4, unsigned long arg5)
{
long res;
asm volatile(
"int $0x80"
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3),
"S" (arg4), "D" (arg5));
return syscall_return(res);
}
#define NR_exit 1
#define NR_fork 2
#define NR_read 3
#define NR_write 4
#define NR_open 5
#define NR_close 6
#define NR_waitpid 7
#define NR_creat 8
#define NR_link 9
#define NR_unlink 10
#define NR_execve 11
#define NR_chdir 12
#define NR_time 13
#define NR_mknod 14
#define NR_chmod 15
#define NR_lchown 16
#define NR_break 17
#define NR_oldstat 18
#define NR_lseek 19
#define NR_getpid 20
#define NR_mount 21
#define NR_umount 22
#define NR_setuid 23
#define NR_getuid 24
#define NR_stime 25
#define NR_ptrace 26
#define NR_alarm 27
#define NR_oldfstat 28
#define NR_pause 29
#define NR_utime 30
#define NR_stty 31
#define NR_gtty 32
#define NR_access 33
#define NR_nice 34
#define NR_ftime 35
#define NR_sync 36
#define NR_kill 37
#define NR_rename 38
#define NR_mkdir 39
#define NR_rmdir 40
#define NR_dup 41
#define NR_pipe 42
#define NR_times 43
#define NR_prof 44
#define NR_brk 45
#define NR_setgid 46
#define NR_getgid 47
#define NR_signal 48
#define NR_geteuid 49
#define NR_getegid 50
#define NR_acct 51
#define NR_umount2 52
#define NR_lock 53
#define NR_ioctl 54
#define NR_fcntl 55
#define NR_mpx 56
#define NR_setpgid 57
#define NR_ulimit 58
#define NR_oldolduname 59
#define NR_umask 60
#define NR_chroot 61
#define NR_ustat 62
#define NR_dup2 63
#define NR_getppid 64
#define NR_getpgrp 65
#define NR_setsid 66
#define NR_sigaction 67
#define NR_sgetmask 68
#define NR_ssetmask 69
#define NR_setreuid 70
#define NR_setregid 71
#define NR_sigsuspend 72
#define NR_sigpending 73
#define NR_sethostname 74
#define NR_setrlimit 75
#define NR_getrlimit 76
#define NR_getrusage 77
#define NR_gettimeofday 78
#define NR_settimeofday 79
#define NR_getgroups 80
#define NR_setgroups 81
#define NR_select 82
#define NR_symlink 83
#define NR_oldlstat 84
#define NR_readlink 85
#define NR_uselib 86
#define NR_swapon 87
#define NR_reboot 88
#define NR_readdir 89
#define NR_mmap 90
#define NR_munmap 91
#define NR_truncate 92
#define NR_ftruncate 93
#define NR_fchmod 94
#define NR_fchown 95
#define NR_getpriority 96
#define NR_setpriority 97
#define NR_profil 98
#define NR_statfs 99
#define NR_fstatfs 100
#define NR_ioperm 101
#define NR_socketcall 102
#define NR_syslog 103
#define NR_setitimer 104
#define NR_getitimer 105
#define NR_stat 106
#define NR_lstat 107
#define NR_fstat 108
#define NR_olduname 109
#define NR_iopl 110
#define NR_vhangup 111
#define NR_idle 112
#define NR_vm86old 113
#define NR_wait4 114
#define NR_swapoff 115
#define NR_sysinfo 116
#define NR_ipc 117
#define NR_fsync 118
#define NR_sigreturn 119
#define NR_clone 120
#define NR_setdomainname 121
#define NR_uname 122
#define NR_modify_ldt 123
#define NR_adjtimex 124
#define NR_mprotect 125
#define NR_sigprocmask 126
#define NR_create_module 127
#define NR_init_module 128
#define NR_delete_module 129
#define NR_get_kernel_syms 130
#define NR_quotactl 131
#define NR_getpgid 132
#define NR_fchdir 133
#define NR_bdflush 134
#define NR_sysfs 135
#define NR_personality 136
#define NR_afs_syscall 137 /* Syscall for Andrew File System */
#define NR_setfsuid 138
#define NR_setfsgid 139
#define NR__llseek 140
#define NR_getdents 141
#define NR__newselect 142
#define NR_flock 143
#define NR_msync 144
#define NR_readv 145
#define NR_writev 146
#define NR_getsid 147
#define NR_fdatasync 148
#define NR__sysctl 149
#define NR_mlock 150
#define NR_munlock 151
#define NR_mlockall 152
#define NR_munlockall 153
#define NR_sched_setparam 154
#define NR_sched_getparam 155
#define NR_sched_setscheduler 156
#define NR_sched_getscheduler 157
#define NR_sched_yield 158
#define NR_sched_get_priority_max 159
#define NR_sched_get_priority_min 160
#define NR_sched_rr_get_interval 161
#define NR_nanosleep 162
#define NR_mremap 163
#define NR_setresuid 164
#define NR_getresuid 165
#define NR_vm86 166
#define NR_query_module 167
#define NR_poll 168
#define NR_nfsservctl 169
#define NR_setresgid 170
#define NR_getresgid 171
#define NR_prctl 172
#define NR_rt_sigreturn 173
#define NR_rt_sigaction 174
#define NR_rt_sigprocmask 175
#define NR_rt_sigpending 176
#define NR_rt_sigtimedwait 177
#define NR_rt_sigqueueinfo 178
#define NR_rt_sigsuspend 179
#define NR_pread 180
#define NR_pwrite 181
#define NR_chown 182
#define NR_getcwd 183
#define NR_capget 184
#define NR_capset 185
#define NR_sigaltstack 186
#define NR_sendfile 187
#define NR_getpmsg 188 /* some people actually want streams */
#define NR_putpmsg 189 /* some people actually want streams */
#define NR_vfork 190
/* Standard file descriptors */
#define STDIN_FILENO 0 /* Standard input */
#define STDOUT_FILENO 1 /* Standard output */
#define STDERR_FILENO 2 /* Standard error output */
typedef long ssize_t;
typedef unsigned long size_t;
static ssize_t write(int fd, const void *buf, size_t count)
{
struct syscall_result res;
res = syscall3(NR_write, fd, (unsigned long)buf, count);
return res.val;
}
static void _exit(int status)
{
struct syscall_result res;
res = syscall1(NR_exit, status);
}

21
util/romcc/tests/ldscript.ld
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@ -1,21 +0,0 @@
ENTRY(_start)
SECTIONS
{
. = 0x20000;
__cpu_reset = 0xdeadbeef;
.text . : {
. = ALIGN(16);
_start = . ;
*(.rom.text);
*(.text)
. = ALIGN(16);
}
.data . : {
. = ALIGN(16);
*(.rom.data);
*(.data)
. = ALIGN(16);
}
}

136
util/romcc/tests/linux_console.h
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@ -1,136 +0,0 @@
#ifndef LINUX_CONSOLE_H
#define LINUX_CONSOLE_H
#include "linux_syscall.h"
static const char *addr_of_char(unsigned char ch)
{
static const char byte[] = {
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f,
0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f,
0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97,
0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f,
0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,
0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf,
0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7,
0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf,
0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf,
0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7,
0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf,
0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7,
0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef,
0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7,
0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff,
};
return byte + ch;
}
static void console_tx_byte(unsigned char ch)
{
write(STDOUT_FILENO, addr_of_char(ch), 1);
}
static void console_tx_nibble(unsigned nibble)
{
unsigned char digit;
digit = nibble + '0';
if (digit > '9') {
digit += 39;
}
console_tx_byte(digit);
}
static void console_tx_char(unsigned char byte)
{
console_tx_byte(byte);
}
static void console_tx_hex8(unsigned char value)
{
console_tx_nibble((value >> 4U) & 0x0fU);
console_tx_nibble(value & 0x0fU);
}
static void console_tx_hex16(unsigned short value)
{
console_tx_nibble((value >> 12U) & 0x0FU);
console_tx_nibble((value >> 8U) & 0x0FU);
console_tx_nibble((value >> 4U) & 0x0FU);
console_tx_nibble(value & 0x0FU);
}
static void console_tx_hex32(unsigned short value)
{
console_tx_nibble((value >> 28U) & 0x0FU);
console_tx_nibble((value >> 24U) & 0x0FU);
console_tx_nibble((value >> 20U) & 0x0FU);
console_tx_nibble((value >> 16U) & 0x0FU);
console_tx_nibble((value >> 12U) & 0x0FU);
console_tx_nibble((value >> 8U) & 0x0FU);
console_tx_nibble((value >> 4U) & 0x0FU);
console_tx_nibble(value & 0x0FU);
}
static void console_tx_string(const char *str)
{
unsigned char ch;
while((ch = *str++) != '\0') {
console_tx_byte(ch);
}
}
static void print_emerg_char(unsigned char byte) { console_tx_char(byte); }
static void print_emerg_hex8(unsigned char value) { console_tx_hex8(value); }
static void print_emerg_hex16(unsigned short value){ console_tx_hex16(value); }
static void print_emerg_hex32(unsigned int value) { console_tx_hex32(value); }
static void print_emerg(const char *str) { console_tx_string(str); }
static void print_warn_char(unsigned char byte) { console_tx_char(byte); }
static void print_warn_hex8(unsigned char value) { console_tx_hex8(value); }
static void print_warn_hex16(unsigned short value){ console_tx_hex16(value); }
static void print_warn_hex32(unsigned int value) { console_tx_hex32(value); }
static void print_warn(const char *str) { console_tx_string(str); }
static void print_info_char(unsigned char byte) { console_tx_char(byte); }
static void print_info_hex8(unsigned char value) { console_tx_hex8(value); }
static void print_info_hex16(unsigned short value){ console_tx_hex16(value); }
static void print_info_hex32(unsigned int value) { console_tx_hex32(value); }
static void print_info(const char *str) { console_tx_string(str); }
static void print_debug_char(unsigned char byte) { console_tx_char(byte); }
static void print_debug_hex8(unsigned char value) { console_tx_hex8(value); }
static void print_debug_hex16(unsigned short value){ console_tx_hex16(value); }
static void print_debug_hex32(unsigned int value) { console_tx_hex32(value); }
static void print_debug(const char *str) { console_tx_string(str); }
static void print_spew_char(unsigned char byte) { console_tx_char(byte); }
static void print_spew_hex8(unsigned char value) { console_tx_hex8(value); }
static void print_spew_hex16(unsigned short value){ console_tx_hex16(value); }
static void print_spew_hex32(unsigned int value) { console_tx_hex32(value); }
static void print_spew(const char *str) { console_tx_string(str); }
static void die(const char *str)
{
print_emerg(str);
do {
asm volatile (" ");
} while(1);
}
#endif /* LINUX_CONSOLE_H */

7
util/romcc/tests/linux_syscall.h
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@ -1,7 +0,0 @@
#ifndef LINUX_SYSCALL_H
#define LINUX_SYSCALL_H
/* When I support other platforms use #ifdefs here */
#include "linuxi386_syscall.h"
#endif /* LINUX_SYSCALL_H */

8
util/romcc/tests/linux_test1.c
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@ -1,8 +0,0 @@
#include "linux_syscall.h"
static void main(void)
{
static const char msg[] = "hello world\n";
write(STDOUT_FILENO, msg, sizeof(msg));
_exit(0);
}

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util/romcc/tests/linux_test10.c
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#include "linux_syscall.h"
#include "linux_console.h"
struct stuff {
signed int a : 5;
signed int b : 6;
signed int c : 2;
unsigned int d : 3;
};
static void test(void)
{
struct stuff var;
#if 0
int a, b, c, d;
a = 1;
b = 2;
c = 3;
d = 7;
var.a = a;
var.b = b;
var.c = c;
var.d = d;
a = var.a;
b = var.b;
c = var.c;
d = var.d;
print_debug(" a: ");
print_debug_hex32(a);
print_debug(" b: ");
print_debug_hex32(b);
print_debug(" c: ");
print_debug_hex32(c);
print_debug(" d: ");
print_debug_hex32(d);
#else
var.a = 1;
var.b = 2;
var.c = 3;
var.d = 7;
print_debug(" a: ");
print_debug_hex32(var.a);
print_debug(" b: ");
print_debug_hex32(var.b);
print_debug(" c: ");
print_debug_hex32(var.c);
print_debug(" d: ");
print_debug_hex32(var.d);
#endif
print_debug("\n");
_exit(0);
}

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util/romcc/tests/linux_test11.c
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#include "linux_syscall.h"
#include "linux_console.h"
static void test(void)
{
signed char x;
x = -1;
print_debug_hex32(x);
print_debug("\n");
_exit(0);
}

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util/romcc/tests/linux_test12.c
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#include "linux_syscall.h"
#include "linux_console.h"
#define MACRO(hello, hello2) 1
#ifndef A
#define A 135
#endif
#define B A
#define C B
#define D C
#define E D
#define F E
#define G F
#define H G
#define I H
#define FOO() "hah?\n"
#define BAR(X) ( X " There\n" )
#define BAZ(X) #X
#define SUM(X, Y) ((X) + (Y))
#define REALLY_SUM(...) SUM(__VA_ARGS__)
#define hash_hash # /* comment */ ## #
#define mkstr(a) # a
#define in_between(a) mkstr(a)
#define join(c, d) in_between(c hash_hash d)
#define ECHO(X) X
#define print_debug(X) ECHO(print_debug(X))
static void test(void)
{
print_debug(FOO());
print_debug(BAR("Hi!!"));
print_debug(BAZ(This should be shown as a string... "enclosed in quotes") "\n");
print_debug("This is a quote\" see\n");
print_debug(BAR(BAZ(I)));
print_debug_hex32(REALLY_SUM(1,2));
print_debug("\n");
print_debug(join(x, y) "\n");
print_debug("romcc: ");
print_debug_hex8(__ROMCC__);
print_debug(".");
print_debug_hex8(__ROMCC_MINOR__);
print_debug("\n");
print_debug(__FILE__);
print_debug(":");
print_debug(__func__);
print_debug(":");
print_debug_hex32(__LINE__);
print_debug("\n");
print_debug("Compiled at: ");
print_debug(__DATE__);
print_debug(" ");
print_debug(__TIME__);
print_debug("\n");
print_debug("Compile time: ");
print_debug(__TIME__);
print_debug("\n");
_exit(0);
}

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util/romcc/tests/linux_test13.c
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#include "linux_syscall.h"
#include "linux_console.h"
struct mem_controller {
unsigned short channel0[4];
};
static unsigned int spd_detect_dimms(const struct mem_controller *ctrl)
{
unsigned dimm_mask;
int i;
print_debug("1\n");
dimm_mask = 0;
for(i = 0; i < 4; i++) {
int byte;
unsigned device;
print_debug("2\n");
device = ctrl->channel0[i];
if (device) {
print_debug("3\n");
byte = ctrl->channel0[i] + 2;
if (byte == 7) {
dimm_mask |= (1 << i);
}
}
print_debug("4\n");
}
print_debug("5\n");
return dimm_mask;
}
static void main(void)
{
static const struct mem_controller cpu[] = {
{
.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
},
};
long dimm_mask;
print_debug("A\n");
dimm_mask = spd_detect_dimms(cpu);
print_debug("B\n");
_exit(0);
}

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util/romcc/tests/linux_test2.c
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#include "linux_syscall.h"
#include "linux_console.h"
static void setup_coherent_ht_domain(void)
{
static const unsigned int register_values[] = {
#if 1
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x40) & 0xFF)), 0xfff0f0f0, 0x00010101,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x44) & 0xFF)), 0xfff0f0f0, 0x00010101,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x48) & 0xFF)), 0xfff0f0f0, 0x00010101,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x4c) & 0xFF)), 0xfff0f0f0, 0x00010101,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x50) & 0xFF)), 0xfff0f0f0, 0x00010101,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x54) & 0xFF)), 0xfff0f0f0, 0x00010101,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x58) & 0xFF)), 0xfff0f0f0, 0x00010101,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x5c) & 0xFF)), 0xfff0f0f0, 0x00010101,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x68) & 0xFF)), 0x00800000, 0x0f00840f,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x6C) & 0xFF)), 0xffffff8c, 0x00000000 | (1 << 6) |(1 << 5)| (1 << 4),
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x84) & 0xFF)), 0x00009c05, 0x11110020,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x88) & 0xFF)), 0xfffff0ff, 0x00000200,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x94) & 0xFF)), 0xff000000, 0x00ff0000,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x44) & 0xFF)), 0x0000f8f8, 0x003f0000,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x4C) & 0xFF)), 0x0000f8f8, 0x00000001,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x54) & 0xFF)), 0x0000f8f8, 0x00000002,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x5C) & 0xFF)), 0x0000f8f8, 0x00000003,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x64) & 0xFF)), 0x0000f8f8, 0x00000004,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x6C) & 0xFF)), 0x0000f8f8, 0x00000005,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x74) & 0xFF)), 0x0000f8f8, 0x00000006,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x7C) & 0xFF)), 0x0000f8f8, 0x00000007,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x40) & 0xFF)), 0x0000f8fc, 0x00000003,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x48) & 0xFF)), 0x0000f8fc, 0x00400000,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x50) & 0xFF)), 0x0000f8fc, 0x00400000,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x58) & 0xFF)), 0x0000f8fc, 0x00400000,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x60) & 0xFF)), 0x0000f8fc, 0x00400000,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x68) & 0xFF)), 0x0000f8fc, 0x00400000,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x70) & 0xFF)), 0x0000f8fc, 0x00400000,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x78) & 0xFF)), 0x0000f8fc, 0x00400000,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x84) & 0xFF)), 0x00000048, 0x00e1ff00,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x8C) & 0xFF)), 0x00000048, 0x00dfff00,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x94) & 0xFF)), 0x00000048, 0x00e3ff00,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x9C) & 0xFF)), 0x00000048, 0x00000000,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xA4) & 0xFF)), 0x00000048, 0x00000000,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xAC) & 0xFF)), 0x00000048, 0x00000000,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xB4) & 0xFF)), 0x00000048, 0x00000b00,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xBC) & 0xFF)), 0x00000048, 0x00fe0b00,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x80) & 0xFF)), 0x000000f0, 0x00e00003,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x88) & 0xFF)), 0x000000f0, 0x00d80003,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x90) & 0xFF)), 0x000000f0, 0x00e20003,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x98) & 0xFF)), 0x000000f0, 0x00000000,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xA0) & 0xFF)), 0x000000f0, 0x00000000,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xA8) & 0xFF)), 0x000000f0, 0x00000000,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xB0) & 0xFF)), 0x000000f0, 0x00000a03,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xB8) & 0xFF)), 0x000000f0, 0x00400003,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xC4) & 0xFF)), 0xFE000FC8, 0x0000d000,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xCC) & 0xFF)), 0xFE000FC8, 0x000ff000,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xD4) & 0xFF)), 0xFE000FC8, 0x00000000,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xDC) & 0xFF)), 0xFE000FC8, 0x00000000,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xC0) & 0xFF)), 0xFE000FCC, 0x0000d003,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xC8) & 0xFF)), 0xFE000FCC, 0x00001013,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xD0) & 0xFF)), 0xFE000FCC, 0x00000000,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xD8) & 0xFF)), 0xFE000FCC, 0x00000000,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xE0) & 0xFF)), 0x0000FC88, 0xff000003,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xE4) & 0xFF)), 0x0000FC88, 0x00000000,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xE8) & 0xFF)), 0x0000FC88, 0x00000000,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xEC) & 0xFF)), 0x0000FC88, 0x00000000,
#else
#define PCI_ADDR(BUS, DEV, FN, WHERE) ( \
(((BUS) & 0xFF) << 16) | \
(((DEV) & 0x1f) << 11) | \
(((FN) & 0x07) << 8) | \
((WHERE) & 0xFF))
/* Routing Table Node i
* F0:0x40 i = 0,
* F0:0x44 i = 1,
* F0:0x48 i = 2,
* F0:0x4c i = 3,
* F0:0x50 i = 4,
* F0:0x54 i = 5,
* F0:0x58 i = 6,
* F0:0x5c i = 7
* [ 0: 3] Request Route
* [0] Route to this node
* [1] Route to Link 0
* [2] Route to Link 1
* [3] Route to Link 2
* [11: 8] Response Route
* [0] Route to this node
* [1] Route to Link 0
* [2] Route to Link 1
* [3] Route to Link 2
* [19:16] Broadcast route
* [0] Route to this node
* [1] Route to Link 0
* [2] Route to Link 1
* [3] Route to Link 2
*/
PCI_ADDR(0, 0x18, 0, 0x40), 0xfff0f0f0, 0x00010101,
PCI_ADDR(0, 0x18, 0, 0x44), 0xfff0f0f0, 0x00010101,
PCI_ADDR(0, 0x18, 0, 0x48), 0xfff0f0f0, 0x00010101,
PCI_ADDR(0, 0x18, 0, 0x4c), 0xfff0f0f0, 0x00010101,
PCI_ADDR(0, 0x18, 0, 0x50), 0xfff0f0f0, 0x00010101,
PCI_ADDR(0, 0x18, 0, 0x54), 0xfff0f0f0, 0x00010101,
PCI_ADDR(0, 0x18, 0, 0x58), 0xfff0f0f0, 0x00010101,
PCI_ADDR(0, 0x18, 0, 0x5c), 0xfff0f0f0, 0x00010101,
/* Hypetransport Transaction Control Register
* F0:0x68
* [ 0: 0] Disable read byte probe
* 0 = Probes issues
* 1 = Probes not issued
* [ 1: 1] Disable Read Doubleword probe
* 0 = Probes issued
* 1 = Probes not issued
* [ 2: 2] Disable write byte probes
* 0 = Probes issued
* 1 = Probes not issued
* [ 3: 3] Disable Write Doubleword Probes
* 0 = Probes issued
* 1 = Probes not issued.
* [ 4: 4] Disable Memroy Controller Target Start
* 0 = TgtStart packets are generated
* 1 = TgtStart packets are not generated.
* [ 5: 5] CPU1 Enable
* 0 = Second CPU disabled or not present
* 1 = Second CPU enabled.
* [ 6: 6] CPU Request PassPW
* 0 = CPU requests do not pass posted writes
* 1 = CPU requests pass posted writes.
* [ 7: 7] CPU read Respons PassPW
* 0 = CPU Responses do not pass posted writes
* 1 = CPU responses pass posted writes.
* [ 8: 8] Disable Probe Memory Cancel
* 0 = Probes may generate MemCancels
* 1 = Probes may not generate MemCancels
* [ 9: 9] Disable Remote Probe Memory Cancel.
* 0 = Probes hitting dirty blocks generate memory cancel packets
* 1 = Only probed caches on the same node as the memory controller
* generate cancel packets.
* [10:10] Disable Fill Probe
* 0 = Probes issued for cache fills
* 1 = Probes not issued for cache fills.
* [11:11] Response PassPw
* 0 = Downstream response PassPW based on original request
* 1 = Downstream response PassPW set to 1
* [12:12] Change ISOC to Ordered
* 0 = Bit 1 of coherent HT RdSz/WrSz command used for iosynchronous prioritization
* 1 = Bit 1 of coherent HT RdSz/WrSz command used for ordering.
* [14:13] Buffer Release Priority select
* 00 = 64
* 01 = 16
* 10 = 8
* 11 = 2
* [15:15] Limit Coherent HT Configuration Space Range
* 0 = No coherent HT configuration space restrictions
* 1 = Limit coherent HT configuration space based on node count
* [16:16] Local Interrupt Conversion Enable.
* 0 = ExtInt/NMI interrupts unaffected.
* 1 = ExtInt/NMI broadcast interrupts converted to LINT0/1
* [17:17] APIC Extended Broadcast Enable.
* 0 = APIC broadcast is 0F
* 1 = APIC broadcast is FF
* [18:18] APIC Extended ID Enable
* 0 = APIC ID is 4 bits.
* 1 = APIC ID is 8 bits.
* [19:19] APIC Extended Spurious Vector Enable
* 0 = Lower 4 bits of spurious vector are read-only 1111
* 1 = Lower 4 bits of spurious vecotr are writeable.
* [20:20] Sequence ID Source Node Enable
* 0 = Normal operation
* 1 = Keep SeqID on routed packets for debugging.
* [22:21] Downstream non-posted request limit
* 00 = No limit
* 01 = Limited to 1
* 10 = Limited to 4
* 11 = Limited to 8
* [23:23] RESERVED
* [25:24] Medium-Priority Bypass Count
* - Maximum # of times a medium priority access can pass a low
* priority access before Medium-Priority mode is disabled for one access.
* [27:26] High-Priority Bypass Count
* - Maximum # of times a high prioirty access can pass a medium or low
* priority access before High-prioirty mode is disabled for one access.
* [28:28] Enable High Priority CPU Reads
* 0 = Cpu reads are medium prioirty
* 1 = Cpu reads are high prioirty
* [29:29] Disable Low Priority Writes
* 0 = Non-isochronous writes are low priority
* 1 = Non-isochronous writes are medium prioirty
* [30:30] Disable High Priority Isochronous writes
* 0 = Isochronous writes are high priority
* 1 = Isochronous writes are medium priority
* [31:31] Disable Medium Priority Isochronous writes
* 0 = Isochronous writes are medium are high
* 1 = With bit 30 set makes Isochrouns writes low priority.
*/
PCI_ADDR(0, 0x18, 0, 0x68), 0x00800000, 0x0f00840f,
/* HT Initialization Control Register
* F0:0x6C
* [ 0: 0] Routing Table Disable
* 0 = Packets are routed according to routing tables
* 1 = Packets are routed according to the default link field
* [ 1: 1] Request Disable (BSP should clear this)
* 0 = Request packets may be generated
* 1 = Request packets may not be generated.
* [ 3: 2] Default Link (Read-only)
* 00 = LDT0
* 01 = LDT1
* 10 = LDT2
* 11 = CPU on same node
* [ 4: 4] Cold Reset
* - Scratch bit cleared by a cold reset
* [ 5: 5] BIOS Reset Detect
* - Scratch bit cleared by a cold reset
* [ 6: 6] INIT Detect
* - Scratch bit cleared by a warm or cold reset not by an INIT
*
*/
PCI_ADDR(0, 0x18, 0, 0x6C), 0xffffff8c, 0x00000000 | (1 << 6) |(1 << 5)| (1 << 4),
/* LDTi Capabilities Registers
* F0:0x80 i = 0,
* F0:0xA0 i = 1,
* F0:0xC0 i = 2,
*/
/* LDTi Link Control Registrs
* F0:0x84 i = 0,
* F0:0xA4 i = 1,
* F0:0xC4 i = 2,
* [ 1: 1] CRC Flood Enable
* 0 = Do not generate sync packets on CRC error
* 1 = Generate sync packets on CRC error
* [ 2: 2] CRC Start Test (Read-Only)
* [ 3: 3] CRC Force Frame Error
* 0 = Do not generate bad CRC
* 1 = Generate bad CRC
* [ 4: 4] Link Failure
* 0 = No link failure detected
* 1 = Link failure detected
* [ 5: 5] Initialization Complete
* 0 = Initialization not complete
* 1 = Initialization complete
* [ 6: 6] Receiver off
* 0 = Recevier on
* 1 = Receiver off
* [ 7: 7] Transmitter Off
* 0 = Transmitter on
* 1 = Transmitter off
* [ 9: 8] CRC_Error
* 00 = No error
* [0] = 1 Error on byte lane 0
* [1] = 1 Error on byte lane 1
* [12:12] Isochrnous Enable (Read-Only)
* [13:13] HT Stop Tristate Enable
* 0 = Driven during an LDTSTOP_L
* 1 = Tristated during and LDTSTOP_L
* [14:14] Extended CTL Time
* 0 = CTL is asserted for 16 bit times during link initialization
* 1 = CTL is asserted for 50us during link initialization
* [18:16] Max Link Width In (Read-Only?)
* 000 = 8 bit link
* 001 = 16bit link
* [19:19] Doubleword Flow Control in (Read-Only)
* 0 = This link does not support doubleword flow control
* 1 = This link supports doubleword flow control
* [22:20] Max Link Width Out (Read-Only?)
* 000 = 8 bit link
* 001 = 16bit link
* [23:23] Doubleworld Flow Control out (Read-Only)
* 0 = This link does not support doubleword flow control
* 1 = This link supports doubleworkd flow control
* [26:24] Link Width In
* 000 = Use 8 bits
* 001 = Use 16 bits
* 010 = reserved
* 011 = Use 32 bits
* 100 = Use 2 bits
* 101 = Use 4 bits
* 110 = reserved
* 111 = Link physically not connected
* [27:27] Doubleword Flow Control In Enable
* 0 = Doubleword flow control disabled
* 1 = Doubleword flow control enabled (Not currently supported)
* [30:28] Link Width Out
* 000 = Use 8 bits
* 001 = Use 16 bits
* 010 = reserved
* 011 = Use 32 bits
* 100 = Use 2 bits
* 101 = Use 4 bits
* 110 = reserved
* 111 = Link physically not connected
* [31:31] Doubleworld Flow Control Out Enable
* 0 = Doubleworld flow control disabled
* 1 = Doubleword flow control enabled (Not currently supported)
*/
PCI_ADDR(0, 0x18, 0, 0x84), 0x00009c05, 0x11110020,
/* LDTi Frequency/Revision Registers
* F0:0x88 i = 0,
* F0:0xA8 i = 1,
* F0:0xC8 i = 2,
* [ 4: 0] Minor Revision
* Contains the HT Minor revision
* [ 7: 5] Major Revision
* Contains the HT Major revision
* [11: 8] Link Frequency (Takes effect the next time the link is reconnected)
* 0000 = 200Mhz
* 0001 = reserved
* 0010 = 400Mhz
* 0011 = reserved
* 0100 = 600Mhz
* 0101 = 800Mhz
* 0110 = 1000Mhz
* 0111 = reserved
* 1000 = reserved
* 1001 = reserved
* 1010 = reserved
* 1011 = reserved
* 1100 = reserved
* 1101 = reserved
* 1110 = reserved
* 1111 = 100 Mhz
* [15:12] Error (Not currently Implemented)
* [31:16] Indicates the frequency capabilities of the link
* [16] = 1 encoding 0000 of freq supported
* [17] = 1 encoding 0001 of freq supported
* [18] = 1 encoding 0010 of freq supported
* [19] = 1 encoding 0011 of freq supported
* [20] = 1 encoding 0100 of freq supported
* [21] = 1 encoding 0101 of freq supported
* [22] = 1 encoding 0110 of freq supported
* [23] = 1 encoding 0111 of freq supported
* [24] = 1 encoding 1000 of freq supported
* [25] = 1 encoding 1001 of freq supported
* [26] = 1 encoding 1010 of freq supported
* [27] = 1 encoding 1011 of freq supported
* [28] = 1 encoding 1100 of freq supported
* [29] = 1 encoding 1101 of freq supported
* [30] = 1 encoding 1110 of freq supported
* [31] = 1 encoding 1111 of freq supported
*/
PCI_ADDR(0, 0x18, 0, 0x88), 0xfffff0ff, 0x00000200,
/* LDTi Feature Capability
* F0:0x8C i = 0,
* F0:0xAC i = 1,
* F0:0xCC i = 2,
*/
/* LDTi Buffer Count Registers
* F0:0x90 i = 0,
* F0:0xB0 i = 1,
* F0:0xD0 i = 2,
*/
/* LDTi Bus Number Registers
* F0:0x94 i = 0,
* F0:0xB4 i = 1,
* F0:0xD4 i = 2,
* For NonCoherent HT specifies the bus number downstream (behind the host bridge)
* [ 0: 7] Primary Bus Number
* [15: 8] Secondary Bus Number
* [23:15] Subordiante Bus Number
* [31:24] reserved
*/
PCI_ADDR(0, 0x18, 0, 0x94), 0xff000000, 0x00ff0000,
/* LDTi Type Registers
* F0:0x98 i = 0,
* F0:0xB8 i = 1,
* F0:0xD8 i = 2,
*/
/* Careful set limit registers before base registers which contain the enables */
/* DRAM Limit i Registers
* F1:0x44 i = 0
* F1:0x4C i = 1
* F1:0x54 i = 2
* F1:0x5C i = 3
* F1:0x64 i = 4
* F1:0x6C i = 5
* F1:0x74 i = 6
* F1:0x7C i = 7
* [ 2: 0] Destination Node ID
* 000 = Node 0
* 001 = Node 1
* 010 = Node 2
* 011 = Node 3
* 100 = Node 4
* 101 = Node 5
* 110 = Node 6
* 111 = Node 7
* [ 7: 3] Reserved
* [10: 8] Interleave select
* specifies the values of A[14:12] to use with interleave enable.
* [15:11] Reserved
* [31:16] DRAM Limit Address i Bits 39-24
* This field defines the upper address bits of a 40 bit address
* that define the end of the DRAM region.
*/
#if MEMORY_1024MB
PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x003f0000,
#endif
#if MEMORY_512MB
PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x001f0000,
#endif
PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
/* DRAM Base i Registers
* F1:0x40 i = 0
* F1:0x48 i = 1
* F1:0x50 i = 2
* F1:0x58 i = 3
* F1:0x60 i = 4
* F1:0x68 i = 5
* F1:0x70 i = 6
* F1:0x78 i = 7
* [ 0: 0] Read Enable
* 0 = Reads Disabled
* 1 = Reads Enabled
* [ 1: 1] Write Enable
* 0 = Writes Disabled
* 1 = Writes Enabled
* [ 7: 2] Reserved
* [10: 8] Interleave Enable
* 000 = No interleave
* 001 = Interleave on A[12] (2 nodes)
* 010 = reserved
* 011 = Interleave on A[12] and A[14] (4 nodes)
* 100 = reserved
* 101 = reserved
* 110 = reserved
* 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
* [15:11] Reserved
* [13:16] DRAM Base Address i Bits 39-24
* This field defines the upper address bits of a 40-bit address
* that define the start of the DRAM region.
*/
PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000003,
#if MEMORY_1024MB
PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00400000,
PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00400000,
PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00400000,
PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00400000,
PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00400000,
PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00400000,
PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00400000,
#endif
#if MEMORY_512MB
PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00200000,
PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00200000,
PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00200000,
PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00200000,
PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00200000,
PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00200000,
PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00200000,
#endif
/* Memory-Mapped I/O Limit i Registers
* F1:0x84 i = 0
* F1:0x8C i = 1
* F1:0x94 i = 2
* F1:0x9C i = 3
* F1:0xA4 i = 4
* F1:0xAC i = 5
* F1:0xB4 i = 6
* F1:0xBC i = 7
* [ 2: 0] Destination Node ID
* 000 = Node 0
* 001 = Node 1
* 010 = Node 2
* 011 = Node 3
* 100 = Node 4
* 101 = Node 5
* 110 = Node 6
* 111 = Node 7
* [ 3: 3] Reserved
* [ 5: 4] Destination Link ID
* 00 = Link 0
* 01 = Link 1
* 10 = Link 2
* 11 = Reserved
* [ 6: 6] Reserved
* [ 7: 7] Non-Posted
* 0 = CPU writes may be posted
* 1 = CPU writes must be non-posted
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
* This field defines the upp address bits of a 40-bit address that
* defines the end of a memory-mapped I/O region n
*/
PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00e1ff00,
PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00dfff00,
PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00e3ff00,
PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000b00,
PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00fe0b00,
/* Memory-Mapped I/O Base i Registers
* F1:0x80 i = 0
* F1:0x88 i = 1
* F1:0x90 i = 2
* F1:0x98 i = 3
* F1:0xA0 i = 4
* F1:0xA8 i = 5
* F1:0xB0 i = 6
* F1:0xB8 i = 7
* [ 0: 0] Read Enable
* 0 = Reads disabled
* 1 = Reads Enabled
* [ 1: 1] Write Enable
* 0 = Writes disabled
* 1 = Writes Enabled
* [ 2: 2] Cpu Disable
* 0 = Cpu can use this I/O range
* 1 = Cpu requests do not use this I/O range
* [ 3: 3] Lock
* 0 = base/limit registers i are read/write
* 1 = base/limit registers i are read-only
* [ 7: 4] Reserved
* [31: 8] Memory-Mapped I/O Base Address i (39-16)
* This field defines the upper address bits of a 40bit address
* that defines the start of memory-mapped I/O region i
*/
PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00e00003,
PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00d80003,
PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00e20003,
PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000a03,
#if MEMORY_1024MB
PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00400003,
#endif
#if MEMORY_512MB
PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00200003,
#endif
/* PCI I/O Limit i Registers
* F1:0xC4 i = 0
* F1:0xCC i = 1
* F1:0xD4 i = 2
* F1:0xDC i = 3
* [ 2: 0] Destination Node ID
* 000 = Node 0
* 001 = Node 1
* 010 = Node 2
* 011 = Node 3
* 100 = Node 4
* 101 = Node 5
* 110 = Node 6
* 111 = Node 7
* [ 3: 3] Reserved
* [ 5: 4] Destination Link ID
* 00 = Link 0
* 01 = Link 1
* 10 = Link 2
* 11 = reserved
* [11: 6] Reserved
* [24:12] PCI I/O Limit Address i
* This field defines the end of PCI I/O region n
* [31:25] Reserved
*/
PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x0000d000,
PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x000ff000,
PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
/* PCI I/O Base i Registers
* F1:0xC0 i = 0
* F1:0xC8 i = 1
* F1:0xD0 i = 2
* F1:0xD8 i = 3
* [ 0: 0] Read Enable
* 0 = Reads Disabled
* 1 = Reads Enabled
* [ 1: 1] Write Enable
* 0 = Writes Disabled
* 1 = Writes Enabled
* [ 3: 2] Reserved
* [ 4: 4] VGA Enable
* 0 = VGA matches Disabled
* 1 = matches all address < 64K and where A[9:0] is in the
* range 3B0-3BB or 3C0-3DF independen of the base & limit registers
* [ 5: 5] ISA Enable
* 0 = ISA matches Disabled
* 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
* from matching agains this base/limit pair
* [11: 6] Reserved
* [24:12] PCI I/O Base i
* This field defines the start of PCI I/O region n
* [31:25] Reserved
*/
PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x0000d003,
PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00001013,
PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
/* Config Base and Limit i Registers
* F1:0xE0 i = 0
* F1:0xE4 i = 1
* F1:0xE8 i = 2
* F1:0xEC i = 3
* [ 0: 0] Read Enable
* 0 = Reads Disabled
* 1 = Reads Enabled
* [ 1: 1] Write Enable
* 0 = Writes Disabled
* 1 = Writes Enabled
* [ 2: 2] Device Number Compare Enable
* 0 = The ranges are based on bus number
* 1 = The ranges are ranges of devices on bus 0
* [ 3: 3] Reserved
* [ 6: 4] Destination Node
* 000 = Node 0
* 001 = Node 1
* 010 = Node 2
* 011 = Node 3
* 100 = Node 4
* 101 = Node 5
* 110 = Node 6
* 111 = Node 7
* [ 7: 7] Reserved
* [ 9: 8] Destination Link
* 00 = Link 0
* 01 = Link 1
* 10 = Link 2
* 11 - Reserved
* [15:10] Reserved
* [23:16] Bus Number Base i
* This field defines the lowest bus number in configuration region i
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration regin i
*/
PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003,
PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
#endif
};
int i;
int max;
print_debug("setting up coherent ht domain....\n");
max = sizeof(register_values)/sizeof(register_values[0]);
for(i = 0; i < max; i += 3) {
unsigned long reg;
#if 1
print_debug_hex32(register_values[i]);
print_debug(" <-");
print_debug_hex32(register_values[i+2]);
print_debug("\n");
#endif
#if 0
reg = pci_read_config32(register_values[i]);
reg &= register_values[i+1];
reg |= register_values[i+2] & ~register_values[i+1];
pci_write_config32(register_values[i], reg);
#endif
}
print_debug("done.\n");
}
static void main(void)
{
static const char msg[] = "hello world\n";
#if 0
write(STDOUT_FILENO, msg, sizeof(msg));
#endif
#if 1
setup_coherent_ht_domain();
#endif
_exit(0);
}

28
util/romcc/tests/linux_test3.c
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@ -1,28 +0,0 @@
#include "linux_syscall.h"
#include "linux_console.h"
static void goto_test(void)
{
int i;
print_debug("goto_test\n");
i = 0;
goto bottom;
{
top:
print_debug("i = ");
print_debug_hex8(i);
print_debug("\n");
i = i + 1;
}
bottom:
if (i < 10) {
goto top;
}
}
static void main(void)
{
goto_test();
_exit(0);
}

46
util/romcc/tests/linux_test4.c
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@ -1,46 +0,0 @@
#include "linux_syscall.h"
#include "linux_console.h"
struct socket_desc {
short up;
short down;
short across;
};
static void main(void)
{
static const struct socket_desc cpu_socketsA[] = {
{ .up = 2, .down = -1, .across = 1 }, /* Node 0 */
{ .up = 3, .down = -1, .across = 0 }, /* Node 1 */
{ .up = -1, .down = 0, .across = 3 }, /* Node 2 */
{ .up = -1, .down = 1, .across = 2 } /* Node 3 */
};
static const struct socket_desc cpu_socketsB[4] = {
{ 2, -1, 1 }, /* Node 0 */
{ 3, -1, 0 }, /* Node 1 */
{ -1, 0, 3 }, /* Node 2 */
{ -1, 1, 2 } /* Node 3 */
};
int i;
print_debug("cpu_socketA\n");
for(i = 0; i < sizeof(cpu_socketsA)/sizeof(cpu_socketsA[0]); i++) {
print_debug(".up=");
print_debug_hex16(cpu_socketsA[i].up);
print_debug(" .down=");
print_debug_hex16(cpu_socketsA[i].down);
print_debug(" .across=");
print_debug_hex16(cpu_socketsA[i].across);
print_debug("\n");
}
print_debug("\ncpu_socketB\n");
for(i = 0; i < sizeof(cpu_socketsB)/sizeof(cpu_socketsB[0]); i++) {
print_debug(".up=");
print_debug_hex16(cpu_socketsB[i].up);
print_debug(" .down=");
print_debug_hex16(cpu_socketsB[i].down);
print_debug(" .across=");
print_debug_hex16(cpu_socketsB[i].across);
print_debug("\n");
}
_exit(0);
}

358
util/romcc/tests/linux_test5.c
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@ -1,358 +0,0 @@
#include "linux_syscall.h"
#include "linux_console.h"
inline int log2(int value)
{
/* __builtin_bsr is a exactly equivalent to the x86 machine
* instruction with the exception that it returns -1
* when the value presented to it is zero.
* Otherwise __builtin_bsr returns the zero based index of
* the highest bit set.
*/
return __builtin_bsr(value);
}
static int smbus_read_byte(unsigned device, unsigned address)
{
static const unsigned char dimm[] = {
0x80, 0x08, 0x07, 0x0d, 0x0a, 0x02, 0x48, 0x00, 0x04, 0x60, 0x70, 0x02, 0x82, 0x08, 0x08, 0x01,
0x0e, 0x04, 0x0c, 0x01, 0x02, 0x20, 0x00, 0x75, 0x70, 0x00, 0x00, 0x48, 0x30, 0x48, 0x2a, 0x40,
0x80, 0x80, 0x45, 0x45, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0x80, 0x08, 0x07, 0x0d, 0x0a, 0x02, 0x48, 0x00, 0x04, 0x60, 0x70, 0x02, 0x82, 0x08, 0x08, 0x01,
0x0e, 0x04, 0x0c, 0x01, 0x02, 0x20, 0x00, 0x75, 0x70, 0x00, 0x00, 0x48, 0x30, 0x48, 0x2a, 0x40,
0x80, 0x80, 0x45, 0x45, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
};
return dimm[(device << 8) + address];
}
#define SMBUS_MEM_DEVICE_START 0x00
#define SMBUS_MEM_DEVICE_END 0x01
#define SMBUS_MEM_DEVICE_INC 1
/* Function 2 */
#define DRAM_CONFIG_HIGH 0x94
#define DCH_MEMCLK_SHIFT 20
#define DCH_MEMCLK_MASK 7
#define DCH_MEMCLK_100MHZ 0
#define DCH_MEMCLK_133MHZ 2
#define DCH_MEMCLK_166MHZ 5
#define DCH_MEMCLK_200MHZ 7
/* Function 3 */
#define NORTHBRIDGE_CAP 0xE8
#define NBCAP_128Bit 0x0001
#define NBCAP_MP 0x0002
#define NBCAP_BIG_MP 0x0004
#define NBCAP_ECC 0x0004
#define NBCAP_CHIPKILL_ECC 0x0010
#define NBCAP_MEMCLK_SHIFT 5
#define NBCAP_MEMCLK_MASK 3
#define NBCAP_MEMCLK_100MHZ 3
#define NBCAP_MEMCLK_133MHZ 2
#define NBCAP_MEMCLK_166MHZ 1
#define NBCAP_MEMCLK_200MHZ 0
#define NBCAP_MEMCTRL 0x0100
typedef unsigned char uint8_t;
typedef unsigned int uint32_t;
static unsigned spd_to_dimm(unsigned device)
{
return (device - SMBUS_MEM_DEVICE_START);
}
static void disable_dimm(unsigned index)
{
print_debug("disabling dimm");
print_debug_hex8(index);
print_debug("\n");
#if 0
pci_write_config32(PCI_DEV(0, 0x18, 2), DRAM_CSBASE + (((index << 1)+0)<<2), 0);
pci_write_config32(PCI_DEV(0, 0x18, 2), DRAM_CSBASE + (((index << 1)+1)<<2), 0);
#endif
}
struct mem_param {
uint8_t cycle_time;
uint32_t dch_memclk;
};
static const struct mem_param *get_mem_param(unsigned min_cycle_time)
{
static const struct mem_param speed[] = {
{
.cycle_time = 0xa0,
.dch_memclk = DCH_MEMCLK_100MHZ << DCH_MEMCLK_SHIFT,
},
{
.cycle_time = 0x75,
.dch_memclk = DCH_MEMCLK_133MHZ << DCH_MEMCLK_SHIFT,
},
{
.cycle_time = 0x60,
.dch_memclk = DCH_MEMCLK_166MHZ << DCH_MEMCLK_SHIFT,
},
{
.cycle_time = 0x50,
.dch_memclk = DCH_MEMCLK_200MHZ << DCH_MEMCLK_SHIFT,
},
{
.cycle_time = 0x00,
},
};
const struct mem_param *param;
for(param = &speed[0]; param->cycle_time ; param++) {
if (min_cycle_time > (param+1)->cycle_time) {
break;
}
}
if (!param->cycle_time) {
die("min_cycle_time to low");
}
return param;
}
#if 1
static void debug(int c)
{
print_debug_char(c);
print_debug_char('\n');
}
#endif
static const struct mem_param *spd_set_memclk(void)
{
/* Compute the minimum cycle time for these dimms */
const struct mem_param *param;
unsigned min_cycle_time, min_latency;
unsigned device;
uint32_t value;
static const int latency_indices[] = { 26, 23, 9 };
static const unsigned char min_cycle_times[] = {
[NBCAP_MEMCLK_200MHZ] = 0x50, /* 5ns */
[NBCAP_MEMCLK_166MHZ] = 0x60, /* 6ns */
[NBCAP_MEMCLK_133MHZ] = 0x75, /* 7.5ns */
[NBCAP_MEMCLK_100MHZ] = 0xa0, /* 10ns */
};
#if 0
value = pci_read_config32(PCI_DEV(0, 0x18, 3), NORTHBRIDGE_CAP);
#else
value = 0x50;
#endif
min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK];
min_latency = 2;
#if 1
print_debug("min_cycle_time: ");
print_debug_hex8(min_cycle_time);
print_debug(" min_latency: ");
print_debug_hex8(min_latency);
print_debug("\n");
#endif
/* Compute the least latency with the fastest clock supported
* by both the memory controller and the dimms.
*/
for(device = SMBUS_MEM_DEVICE_START;
device <= SMBUS_MEM_DEVICE_END;
device += SMBUS_MEM_DEVICE_INC)
{
int new_cycle_time, new_latency;
int index;
int latencies;
int latency;
debug('A');
/* First find the supported CAS latencies
* Byte 18 for DDR SDRAM is interpreted:
* bit 0 == CAS Latency = 1.0
* bit 1 == CAS Latency = 1.5
* bit 2 == CAS Latency = 2.0
* bit 3 == CAS Latency = 2.5
* bit 4 == CAS Latency = 3.0
* bit 5 == CAS Latency = 3.5
* bit 6 == TBD
* bit 7 == TBD
*/
new_cycle_time = 0xa0;
new_latency = 5;
latencies = smbus_read_byte(device, 18);
if (latencies <= 0) continue;
debug('B');
/* Compute the lowest cas latency supported */
latency = log2(latencies) -2;
/* Loop through and find a fast clock with a low latency */
for(index = 0; index < 3; index++, latency++) {
int value;
debug('C');
if ((latency < 2) || (latency > 4) ||
(!(latencies & (1 << latency)))) {
continue;
}
debug('D');
value = smbus_read_byte(device, latency_indices[index]);
if (value < 0) continue;
debug('E');
/* Only increase the latency if we decreas the clock */
if ((value >= min_cycle_time) && (value < new_cycle_time)) {
new_cycle_time = value;
new_latency = latency;
#if 1
print_debug("device: ");
print_debug_hex8(device);
print_debug(" new_cycle_time: ");
print_debug_hex8(new_cycle_time);
print_debug(" new_latency: ");
print_debug_hex8(new_latency);
print_debug("\n");
#endif
}
debug('G');
}
debug('H');
#if 1
print_debug("device: ");
print_debug_hex8(device);
print_debug(" new_cycle_time: ");
print_debug_hex8(new_cycle_time);
print_debug(" new_latency: ");
print_debug_hex8(new_latency);
print_debug("\n");
#endif
if (new_latency > 4){
continue;
}
debug('I');
/* Does min_latency need to be increased? */
if (new_cycle_time > min_cycle_time) {
min_cycle_time = new_cycle_time;
}
/* Does min_cycle_time need to be increased? */
if (new_latency > min_latency) {
min_latency = new_latency;
}
#if 1
print_debug("device: ");
print_debug_hex8(device);
print_debug(" min_cycle_time: ");
print_debug_hex8(min_cycle_time);
print_debug(" min_latency: ");
print_debug_hex8(min_latency);
print_debug("\n");
#endif
}
/* Make a second pass through the dimms and disable
* any that cannot support the selected memclk and cas latency.
*/
for(device = SMBUS_MEM_DEVICE_START;
device <= SMBUS_MEM_DEVICE_END;
device += SMBUS_MEM_DEVICE_INC)
{
int latencies;
int latency;
int index;
int value;
int dimm;
latencies = smbus_read_byte(device, 18);
if (latencies <= 0) {
goto dimm_err;
}
/* Compute the lowest cas latency supported */
latency = log2(latencies) -2;
/* Walk through searching for the selected latency */
for(index = 0; index < 3; index++, latency++) {
if (!(latencies & (1 << latency))) {
continue;
}
if (latency == min_latency)
break;
}
/* If I can't find the latency or my index is bad error */
if ((latency != min_latency) || (index >= 3)) {
goto dimm_err;
}
/* Read the min_cycle_time for this latency */
value = smbus_read_byte(device, latency_indices[index]);
/* All is good if the selected clock speed
* is what I need or slower.
*/
if (value <= min_cycle_time) {
continue;
}
/* Otherwise I have an error, disable the dimm */
dimm_err:
disable_dimm(spd_to_dimm(device));
}
#if 1
print_debug("min_cycle_time: ");
print_debug_hex8(min_cycle_time);
print_debug(" min_latency: ");
print_debug_hex8(min_latency);
print_debug("\n");
#endif
/* Now that I know the minimum cycle time lookup the memory parameters */
param = get_mem_param(min_cycle_time);
#if 0
/* Update DRAM Config High with our selected memory speed */
value = pci_read_config32(PCI_DEV(0, 0x18, 2), DRAM_CONFIG_HIGH);
value &= ~(DCH_MEMCLK_MASK << DCH_MEMCLK_SHIFT);
value |= param->dch_memclk;
pci_write_config32(PCI_DEV(0, 0x18, 2), DRAM_CONFIG_HIGH, value);
static const unsigned latencies[] = { 1, 5, 2 };
/* Update DRAM Timing Low wiht our selected cas latency */
value = pci_read_config32(PCI_DEV(0, 0x18, 2), DRAM_CONFIG_LOW);
value &= ~7;
value |= latencies[min_latency - 2];
pci_write_config32(PCI_DEV(0, 0x18, 2), DRAM_CONFIG_LOW, value);
#endif
return param;
}
static void main(void)
{
const struct mem_param *param;
param = spd_set_memclk();
_exit(0);
}

17
util/romcc/tests/linux_test6.c
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#include "linux_syscall.h"
#include "linux_console.h"
static void main(void)
{
static const int value[] = { 1, 0 };
const char *str;
if (value[1]) {
print_debug("A\n");
str = "Unbuffered\n";
} else {
print_debug("B\n");
str = "Registered\n";
}
print_debug(str);
_exit(0);
}

35
util/romcc/tests/linux_test7.c
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@ -1,35 +0,0 @@
#include "linux_syscall.h"
#include "linux_console.h"
static void main(void)
{
static const int cpu[] = { 0, 1, 2, 3 };
int i;
for(i = 0; i < sizeof(cpu)/sizeof(cpu[0]); i++) {
static const unsigned int register_values[] = {
0x0000c144, 0x0000f8f8, 0x00000000,
0x0000c14C, 0x0000f8f8, 0x00000001,
0x0000c154, 0x0000f8f8, 0x00000002,
0x0000c15C, 0x0000f8f8, 0x00000003,
0x0000c164, 0x0000f8f8, 0x00000004,
0x0000c16C, 0x0000f8f8, 0x00000005,
0x0000c174, 0x0000f8f8, 0x00000006,
0x0000c17C, 0x0000f8f8, 0x00000007,
};
int j;
int max = sizeof(register_values)/sizeof(register_values[0]);
for(j = 0; j < max; j += 3) {
print_debug("val[");
print_debug_hex8(j);
print_debug("]: ");
print_debug_hex32(register_values[j]);
print_debug_char(' ');
print_debug_hex32(register_values[j+1]);
print_debug_char(' ');
print_debug_hex32(register_values[j+2]);
print_debug_char('\n');
}
}
_exit(0);
}

39
util/romcc/tests/linux_test8.c
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@ -1,39 +0,0 @@
#include "linux_syscall.h"
#include "linux_console.h"
struct mem_param {
unsigned char cycle_time;
unsigned char divisor;
unsigned char tRC;
unsigned char tRFC;
unsigned dch_memclk;
unsigned short dch_tref4k, dch_tref8k;
unsigned char dtl_twr;
char name[8];
};
static void test(void)
{
static const struct mem_param param0 = {
.name = "166Mhz\n",
.cycle_time = 0x60,
.divisor = (6<<1),
.tRC = 0x3C,
.tRFC = 0x48,
.dch_memclk = 5 << 20,
.dch_tref4k = 0x02,
.dch_tref8k = 0x0A,
.dtl_twr = 3,
};
int value;
unsigned clocks;
const struct mem_param *param;
param = &param0;
value = 0x48;
/* This used to generate 32bit loads instead of 8 bit loads */
clocks = (value + (param->divisor << 1) - 1)/(param->divisor << 1);
print_debug("clocks: ");
print_debug_hex32(clocks);
print_debug("\n");
_exit(0);
}

13
util/romcc/tests/linux_test9.c
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@ -1,13 +0,0 @@
#include "linux_syscall.h"
#include "linux_console.h"
static void test(void)
{
unsigned char i;
for(i = 127; i != 5; i++) {
print_debug("i: ");
print_debug_hex32((unsigned )i);
print_debug("\n");
}
_exit(0);
}

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util/romcc/tests/linuxi386_syscall.h
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@ -1,299 +0,0 @@
struct syscall_result {
long val;
int errno;
};
static struct syscall_result syscall_return(long result)
{
struct syscall_result res;
if (((unsigned long)result) >= ((unsigned long)-125)) {
res.errno = - result;
res.val = -1;
} else {
res.errno = 0;
res.val = result;
}
return res;
}
static struct syscall_result syscall0(unsigned long nr)
{
long res;
asm volatile(
"int $0x80"
: "=a" (res)
: "a" (nr));
return syscall_return(res);
}
static struct syscall_result syscall1(unsigned long nr, unsigned long arg1)
{
long res;
asm volatile(
"int $0x80"
: "=a" (res)
: "a" (nr), "b" (arg1));
return syscall_return(res);
}
static struct syscall_result syscall2(unsigned long nr, unsigned long arg1, unsigned long arg2)
{
long res;
asm volatile(
"int $0x80"
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2));
return syscall_return(res);
}
static struct syscall_result syscall3(unsigned long nr, unsigned long arg1, unsigned long arg2,
unsigned long arg3)
{
long res;
asm volatile(
"int $0x80"
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3));
return syscall_return(res);
}
static struct syscall_result syscall4(unsigned long nr, unsigned long arg1, unsigned long arg2,
unsigned long arg3, unsigned long arg4)
{
long res;
asm volatile(
"int $0x80"
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), "S" (arg4));
return syscall_return(res);
}
static struct syscall_result syscall5(unsigned long nr, unsigned long arg1, unsigned long arg2,
unsigned long arg3, unsigned long arg4, unsigned long arg5)
{
long res;
asm volatile(
"int $0x80"
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3),
"S" (arg4), "D" (arg5));
return syscall_return(res);
}
#define NR_exit 1
#define NR_fork 2
#define NR_read 3
#define NR_write 4
#define NR_open 5
#define NR_close 6
#define NR_waitpid 7
#define NR_creat 8
#define NR_link 9
#define NR_unlink 10
#define NR_execve 11
#define NR_chdir 12
#define NR_time 13
#define NR_mknod 14
#define NR_chmod 15
#define NR_lchown 16
#define NR_break 17
#define NR_oldstat 18
#define NR_lseek 19
#define NR_getpid 20
#define NR_mount 21
#define NR_umount 22
#define NR_setuid 23
#define NR_getuid 24
#define NR_stime 25
#define NR_ptrace 26
#define NR_alarm 27
#define NR_oldfstat 28
#define NR_pause 29
#define NR_utime 30
#define NR_stty 31
#define NR_gtty 32
#define NR_access 33
#define NR_nice 34
#define NR_ftime 35
#define NR_sync 36
#define NR_kill 37
#define NR_rename 38
#define NR_mkdir 39
#define NR_rmdir 40
#define NR_dup 41
#define NR_pipe 42
#define NR_times 43
#define NR_prof 44
#define NR_brk 45
#define NR_setgid 46
#define NR_getgid 47
#define NR_signal 48
#define NR_geteuid 49
#define NR_getegid 50
#define NR_acct 51
#define NR_umount2 52
#define NR_lock 53
#define NR_ioctl 54
#define NR_fcntl 55
#define NR_mpx 56
#define NR_setpgid 57
#define NR_ulimit 58
#define NR_oldolduname 59
#define NR_umask 60
#define NR_chroot 61
#define NR_ustat 62
#define NR_dup2 63
#define NR_getppid 64
#define NR_getpgrp 65
#define NR_setsid 66
#define NR_sigaction 67
#define NR_sgetmask 68
#define NR_ssetmask 69
#define NR_setreuid 70
#define NR_setregid 71
#define NR_sigsuspend 72
#define NR_sigpending 73
#define NR_sethostname 74
#define NR_setrlimit 75
#define NR_getrlimit 76
#define NR_getrusage 77
#define NR_gettimeofday 78
#define NR_settimeofday 79
#define NR_getgroups 80
#define NR_setgroups 81
#define NR_select 82
#define NR_symlink 83
#define NR_oldlstat 84
#define NR_readlink 85
#define NR_uselib 86
#define NR_swapon 87
#define NR_reboot 88
#define NR_readdir 89
#define NR_mmap 90
#define NR_munmap 91
#define NR_truncate 92
#define NR_ftruncate 93
#define NR_fchmod 94
#define NR_fchown 95
#define NR_getpriority 96
#define NR_setpriority 97
#define NR_profil 98
#define NR_statfs 99
#define NR_fstatfs 100
#define NR_ioperm 101
#define NR_socketcall 102
#define NR_syslog 103
#define NR_setitimer 104
#define NR_getitimer 105
#define NR_stat 106
#define NR_lstat 107
#define NR_fstat 108
#define NR_olduname 109
#define NR_iopl 110
#define NR_vhangup 111
#define NR_idle 112
#define NR_vm86old 113
#define NR_wait4 114
#define NR_swapoff 115
#define NR_sysinfo 116
#define NR_ipc 117
#define NR_fsync 118
#define NR_sigreturn 119
#define NR_clone 120
#define NR_setdomainname 121
#define NR_uname 122
#define NR_modify_ldt 123
#define NR_adjtimex 124
#define NR_mprotect 125
#define NR_sigprocmask 126
#define NR_create_module 127
#define NR_init_module 128
#define NR_delete_module 129
#define NR_get_kernel_syms 130
#define NR_quotactl 131
#define NR_getpgid 132
#define NR_fchdir 133
#define NR_bdflush 134
#define NR_sysfs 135
#define NR_personality 136
#define NR_afs_syscall 137 /* Syscall for Andrew File System */
#define NR_setfsuid 138
#define NR_setfsgid 139
#define NR__llseek 140
#define NR_getdents 141
#define NR__newselect 142
#define NR_flock 143
#define NR_msync 144
#define NR_readv 145
#define NR_writev 146
#define NR_getsid 147
#define NR_fdatasync 148
#define NR__sysctl 149
#define NR_mlock 150
#define NR_munlock 151
#define NR_mlockall 152
#define NR_munlockall 153
#define NR_sched_setparam 154
#define NR_sched_getparam 155
#define NR_sched_setscheduler 156
#define NR_sched_getscheduler 157
#define NR_sched_yield 158
#define NR_sched_get_priority_max 159
#define NR_sched_get_priority_min 160
#define NR_sched_rr_get_interval 161
#define NR_nanosleep 162
#define NR_mremap 163
#define NR_setresuid 164
#define NR_getresuid 165
#define NR_vm86 166
#define NR_query_module 167
#define NR_poll 168
#define NR_nfsservctl 169
#define NR_setresgid 170
#define NR_getresgid 171
#define NR_prctl 172
#define NR_rt_sigreturn 173
#define NR_rt_sigaction 174
#define NR_rt_sigprocmask 175
#define NR_rt_sigpending 176
#define NR_rt_sigtimedwait 177
#define NR_rt_sigqueueinfo 178
#define NR_rt_sigsuspend 179
#define NR_pread 180
#define NR_pwrite 181
#define NR_chown 182
#define NR_getcwd 183
#define NR_capget 184
#define NR_capset 185
#define NR_sigaltstack 186
#define NR_sendfile 187
#define NR_getpmsg 188 /* some people actually want streams */
#define NR_putpmsg 189 /* some people actually want streams */
#define NR_vfork 190
/* Standard file descriptors */
#define STDIN_FILENO 0 /* Standard input */
#define STDOUT_FILENO 1 /* Standard output */
#define STDERR_FILENO 2 /* Standard error output */
typedef long ssize_t;
typedef unsigned long size_t;
static ssize_t write(int fd, const void *buf, size_t count)
{
struct syscall_result res;
res = syscall3(NR_write, fd, (unsigned long)buf, count);
return res.val;
}
static void _exit(int status)
{
struct syscall_result res;
res = syscall1(NR_exit, status);
}

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util/romcc/tests/raminit_test.c
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util/romcc/tests/raminit_test1.c
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util/romcc/tests/raminit_test2.c
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util/romcc/tests/raminit_test3.c
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util/romcc/tests/raminit_test4.c
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util/romcc/tests/raminit_test5.c
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util/romcc/tests/raminit_test6.c
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util/romcc/tests/raminit_test7.c
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util/romcc/tests/simple_test.c
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void land_test(void)
{
int i;
i = 1 && 2;
}
void lor_test(void)
{
int i;
i = 1 || 2;
}
void outb(unsigned char value, unsigned short port)
{
__builtin_outb(value, port);
}
unsigned char inb(unsigned short port)
{
return __builtin_inb(port);
}
static unsigned int config_cmd2(unsigned char bus, unsigned devfn, unsigned where)
{
return 0x80000000 | (bus << 16) | (devfn << 8) | (where & ~3) ;
}
/* Base Address */
#ifndef CONFIG_TTYS0_BASE
#define CONFIG_TTYS0_BASE 0x3f8
#endif
#ifndef CONFIG_TTYS0_BAUD
#define CONFIG_TTYS0_BAUD 115200
#endif
#if ((115200%CONFIG_TTYS0_BAUD) != 0)
#error Bad ttys0 baud rate
#endif
#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD)
/* Line Control Settings */
#ifndef CONFIG_TTYS0_LCS
/* Set 8bit, 1 stop bit, no parity */
#define CONFIG_TTYS0_LCS 0x3
#endif
#define UART_LCS CONFIG_TTYS0_LCS
/* Data */
#define UART_RBR 0x00
#define UART_TBR 0x00
/* Control */
#define UART_IER 0x01
#define UART_IIR 0x02
#define UART_FCR 0x02
#define UART_LCR 0x03
#define UART_MCR 0x04
#define UART_DLL 0x00
#define UART_DLM 0x01
/* Status */
#define UART_LSR 0x05
#define UART_MSR 0x06
#define UART_SCR 0x07
int uart_can_tx_byte(void)
{
return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20;
}
void uart_wait_to_tx_byte(void)
{
while(!uart_can_tx_byte())
;
}
void uart_wait_until_sent(void)
{
while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40))
;
}
void uart_tx_byte(unsigned char data)
{
uart_wait_to_tx_byte();
outb(data, CONFIG_TTYS0_BASE + UART_TBR);
/* Make certain the data clears the fifos */
uart_wait_until_sent();
}
void dummy(void)
{
uart_tx_byte(5);
}
#define PIIX4_DEVFN 0x90
#define SMBUS_MEM_DEVICE_START 0x50
#define SMBUS_MEM_DEVICE_END 0x53
#define SMBUS_MEM_DEVICE_INC 1
#define PM_BUS 0
#define PM_DEVFN (PIIX4_DEVFN+3)
#define SMBUS_IO_BASE 0x1000
#define SMBHSTSTAT 0
#define SMBHSTCTL 2
#define SMBHSTCMD 3
#define SMBHSTADD 4
#define SMBHSTDAT0 5
#define SMBHSTDAT1 6
#define SMBBLKDAT 7
static void smbus_wait_until_done(void)
{
unsigned char byte;
do {
byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
}while((byte &1) == 1);
#if 1
while( (byte & ~1) == 0) {
byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
}
#endif
}
#if 0
void ifthenelse(void)
{
int i;
if (5 > 2) {
i = 1;
}
else {
i = 2;
}
i = i + 3;
}
#endif
#if 0
static int add(int left, int right)
{
{
return left + right;
}
}
#else
#if 0
static int add(int left, int right)
{
return left + right;
}
#endif
#endif
#if 0
static void assign(void)
{
int i, j;
i = j = 1;
}
#endif
#if 0
static void and(void)
{
int i, j, k;
i = 1;
j = 2;
k = i && j;
}
static void and_test(void)
{
and();
}
#endif
#if 0
#define INC_TEST 2
static void inc(void)
{
int i;
i = 5;
#if (INC_TEST == 1)
i += 7;
#endif
#if (INC_TEST == 2)
++i;
#endif
#if (INC_TEST == 3)
i++;
#endif
}
#if 0
static void inc_test(void)
{
inc();
}
#endif
#endif
#if 0
static void loop(void)
{
int i;
for(i = 0; i < 10; i++) {
;
} while(i < 10);
}
static void loop_test(void)
{
loop();
}
#endif
#if 0
static void simple(void)
{
add(1,2);
}
#endif
#if 0
static void fun(void)
{
int bar;
bar = add(1, 2);
}
#endif
#if 0
static void func(void)
{
int bar, baz;
int i;
baz = add(1, 2);
baz = add(1, 2);
bar = 1;
baz = 2;
for(i = 0; i < 10; i = i + 1) {
baz = i;
}
bar = 1 + 2 * 3;
bar = add(3, 4);
bar = add(bar, baz);
}
#endif

252
util/romcc/tests/simple_test1.c
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@ -1,252 +0,0 @@
void land_test(void)
{
int i;
i = 1 && 2;
}
void lor_test(void)
{
int i;
i = 1 || 2;
}
void outb(unsigned char value, unsigned short port)
{
__builtin_outb(value, port);
}
unsigned char inb(unsigned short port)
{
return __builtin_inb(port);
}
static unsigned int config_cmd2(unsigned char bus, unsigned devfn, unsigned where)
{
return 0x80000000 | (bus << 16) | (devfn << 8) | (where & ~3) ;
}
/* Base Address */
#ifndef CONFIG_TTYS0_BASE
#define CONFIG_TTYS0_BASE 0x3f8
#endif
#ifndef CONFIG_TTYS0_BAUD
#define CONFIG_TTYS0_BAUD 115200
#endif
#if ((115200%CONFIG_TTYS0_BAUD) != 0)
#error Bad ttys0 baud rate
#endif
#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD)
/* Line Control Settings */
#ifndef CONFIG_TTYS0_LCS
/* Set 8bit, 1 stop bit, no parity */
#define CONFIG_TTYS0_LCS 0x3
#endif
#define UART_LCS CONFIG_TTYS0_LCS
/* Data */
#define UART_RBR 0x00
#define UART_TBR 0x00
/* Control */
#define UART_IER 0x01
#define UART_IIR 0x02
#define UART_FCR 0x02
#define UART_LCR 0x03
#define UART_MCR 0x04
#define UART_DLL 0x00
#define UART_DLM 0x01
/* Status */
#define UART_LSR 0x05
#define UART_MSR 0x06
#define UART_SCR 0x07
int uart_can_tx_byte(void)
{
return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20;
}
void uart_wait_to_tx_byte(void)
{
while(!uart_can_tx_byte())
;
}
void uart_wait_until_sent(void)
{
while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40))
;
}
void uart_tx_byte(unsigned char data)
{
uart_wait_to_tx_byte();
outb(data, CONFIG_TTYS0_BASE + UART_TBR);
/* Make certain the data clears the fifos */
uart_wait_until_sent();
}
void dummy(void)
{
uart_tx_byte(5);
}
#define PIIX4_DEVFN 0x90
#define SMBUS_MEM_DEVICE_START 0x50
#define SMBUS_MEM_DEVICE_END 0x53
#define SMBUS_MEM_DEVICE_INC 1
#define PM_BUS 0
#define PM_DEVFN (PIIX4_DEVFN+3)
#define SMBUS_IO_BASE 0x1000
#define SMBHSTSTAT 0
#define SMBHSTCTL 2
#define SMBHSTCMD 3
#define SMBHSTADD 4
#define SMBHSTDAT0 5
#define SMBHSTDAT1 6
#define SMBBLKDAT 7
static void smbus_wait_until_done(void)
{
unsigned char byte;
do {
byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
}while((byte &1) == 1);
#if 1
while( (byte & ~1) == 0) {
byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
}
#endif
}
#if 0
void ifthenelse(void)
{
int i;
if (5 > 2) {
i = 1;
}
else {
i = 2;
}
i = i + 3;
}
#endif
#if 0
static int add(int left, int right)
{
{
return left + right;
}
}
#else
#if 0
static int add(int left, int right)
{
return left + right;
}
#endif
#endif
#if 0
static void assign(void)
{
int i, j;
i = j = 1;
}
#endif
#if 0
static void and(void)
{
int i, j, k;
i = 1;
j = 2;
k = i && j;
}
static void and_test(void)
{
and();
}
#endif
#if 0
#define INC_TEST 2
static void inc(void)
{
int i;
i = 5;
#if (INC_TEST == 1)
i += 7;
#endif
#if (INC_TEST == 2)
++i;
#endif
#if (INC_TEST == 3)
i++;
#endif
}
#if 0
static void inc_test(void)
{
inc();
}
#endif
#endif
#if 0
static void loop(void)
{
int i;
for(i = 0; i < 10; i++) {
;
} while(i < 10);
}
static void loop_test(void)
{
loop();
}
#endif
#if 0
static void simple(void)
{
add(1,2);
}
#endif
#if 0
static void fun(void)
{
int bar;
bar = add(1, 2);
}
#endif
#if 0
static void func(void)
{
int bar, baz;
int i;
baz = add(1, 2);
baz = add(1, 2);
bar = 1;
baz = 2;
for(i = 0; i < 10; i = i + 1) {
baz = i;
}
bar = 1 + 2 * 3;
bar = add(3, 4);
bar = add(bar, baz);
}
#endif

30
util/romcc/tests/simple_test10.c
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@ -1,30 +0,0 @@
#define SMBUS_MEM_DEVICE_START 0x50
#define SMBUS_MEM_DEVICE_END 0x53
#define SMBUS_MEM_DEVICE_INC 1
static void spd_set_drb(void)
{
/*
* Effects: Uses serial presence detect to set the
* DRB registers which holds the ending memory address assigned
* to each DIMM.
*/
unsigned end_of_memory;
unsigned char device;
end_of_memory = 0; /* in multiples of 8MiB */
device = SMBUS_MEM_DEVICE_START;
while (device <= SMBUS_MEM_DEVICE_END) {
unsigned side1_bits, side2_bits;
int byte, byte2;
side1_bits = side2_bits = -1;
/* Compute the end address for the DRB register */
/* Only process dimms < 2GB (2^8 * 8MB) */
if (side1_bits < 8) {
end_of_memory += (1 << side1_bits);
}
device += SMBUS_MEM_DEVICE_INC;
}
}

13
util/romcc/tests/simple_test11.c
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@ -1,13 +0,0 @@
static void spd_set_drb(void)
{
unsigned char ch;
char *str;
str = "test_string";
ch = *str;
__builtin_outb(ch, 0xab);
}
void sdram_set_spd_registers(void)
{
spd_set_drb();
}

8
util/romcc/tests/simple_test12.c
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@ -1,8 +0,0 @@
static void spd_set_drb(void)
{
unsigned char ch;
char *str;
str = "test_string";
ch = *str;
__builtin_outb(ch, 0xab);
}

23
util/romcc/tests/simple_test13.c
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@ -1,23 +0,0 @@
static void outb(unsigned char value, unsigned short port)
{
__builtin_outb(value, port);
}
static void uart_init(void)
{
int a;
if (1 == 1) {
a = 1;
outb(a, 0x3f8);
} else {
a = 2;
outb(a, 0x3f8);
}
outb(a, 0x3f8);
}
static void main(void)
{
uart_init();
}

288
util/romcc/tests/simple_test14.c
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@ -1,288 +0,0 @@
static void ram_set_registers(void)
{
static const unsigned int register_values[] = {
0x000c, 0x00000000,
0x0010, 0x90000008,
0x0014, 0x00000000,
0x002c, 0x74541022,
0x0030, 0x00000000,
0x0034, 0x000000a0,
0x0038, 0x00000000,
0x0040, 0x00000001,
0x0044, 0x00000000,
0x0050, 0x0016000b,
0x0058, 0x00000000,
0x0060, 0xd02950e1,
0x0064, 0x00000000,
0x00a0, 0x0030c002,
0x00a4, 0x1f000b77,
0x00a8, 0x00000b21,
0x00ac, 0x00000000,
0x00b0, 0x00000100,
0x00b4, 0x00010900,
0x00b8, 0x00000000,
0x00c0, 0x00600008,
0x00c4, 0x11110020,
0x00c8, 0x00000020,
0x00cc, 0x00350522,
0x00d0, 0x00350002,
0x00d4, 0x00000000,
0x00e0, 0x000d0808,
0x00e4, 0x000c0808,
0x00e8, 0x00130f0f,
0x00ec, 0x00000000,
0x00f0, 0x00040008,
0x00f4, 0x00000000,
0x080c, 0x00012000,
0x0810, 0x00000000,
0x0818, 0x20010100,
0x081c, 0x2220c1c1,
0x0820, 0xe1f0e000,
0x0824, 0xdff0d800,
0x0828, 0x00000000,
0x083c, 0x000c00ff,
0x0840, 0x00000000,
0x300c, 0x00012000,
0x3010, 0x00000000,
0x3018, 0x20020200,
0x301c, 0x220000f0,
0x3020, 0xe3f0e200,
0x3024, 0x0000fff0,
0x3028, 0x00000000,
0x3034, 0x000000c0,
0x3038, 0x00000000,
0x303c, 0x000600ff,
0x3040, 0x00000000,
0x3060, 0x06040000,
0x3064, 0x00000000,
0x30c0, 0x0086f008,
0x30c4, 0x00000020,
0x30c8, 0x000000d0,
0x30cc, 0x00010022,
0x30d0, 0x00000002,
0x30d4, 0x00000000,
0x30e0, 0x000d0008,
0x30e4, 0x000e0008,
0x30e8, 0x0016000f,
0x30ec, 0x00000000,
0x30f0, 0x80000008,
0x30f4, 0x00000000,
0x3a0c, 0x00002000,
0x3a10, 0x0000d401,
0x3a14, 0x00000000,
0x3a2c, 0x746a1022,
0x3a30, 0x00000000,
0x3a3c, 0x0000040c,
0x3a40, 0x0c050002,
0x3a44, 0x746a1022,
0x3a48, 0x00000006,
0x3a4c, 0x00000000,
0x3b0c, 0x00002000,
0x3b10, 0x00000000,
0x3b2c, 0x746b1022,
0x3b30, 0x00000000,
0x3b40, 0x84099100,
0x3b44, 0x00000000,
0x3b48, 0x00500420,
0x3b4c, 0x00000000,
0x3b50, 0x00008101,
0x3b54, 0xc5ba000f,
0x3b58, 0x00005001,
0x3b5c, 0x00000000,
0x3b60, 0x06800000,
0x3b64, 0x00000013,
0x3b68, 0x00000000,
0x3b70, 0xd54b2906,
0x3b74, 0x0000000c,
0x3b78, 0x00000000,
0x3b7c, 0x746b1022,
0x3b80, 0x00000000,
0x3b84, 0x00000001,
0x3b88, 0x00000000,
0x3bf0, 0x0072ff93,
0x3bf4, 0x00000000,
0x900c, 0x00800000,
0x9010, 0x00000000,
0x9014, 0x00000000,
0x9018, 0x00000000,
0x901C, 0x00000000,
0x9020, 0x00000000,
0x9024, 0x00000000,
0x9028, 0x00000000,
0x902C, 0x00000000,
0x9030, 0x00000000,
0x9034, 0x00000080,
0x9038, 0x00000000,
0x903C, 0x00000000,
0x9040, 0x00010101,
0x9044, 0x00000000,
0x9048, 0x00000000,
0x904C, 0x00000000,
0x9050, 0x00000000,
0x9054, 0x00000000,
0x9058, 0x00000000,
0x905C, 0x00000000,
0x9060, 0x00000000,
0x9064, 0x000000e4,
0x9068, 0x0f008c0f,
0x906c, 0x0000002c,
0x9070, 0x00000000,
0x9074, 0x00000000,
0x9078, 0x00000000,
0x907C, 0x00000000,
0x9080, 0x21010008,
0x9084, 0x11110020,
0x9088, 0x80750522,
0x908c, 0x00000002,
0x9090, 0x02510456,
0x9094, 0x00ff0000,
0x9098, 0x00000007,
0x909c, 0x00000000,
0x90a0, 0x00000000,
0x90a4, 0x00000000,
0x90a8, 0x00000000,
0x90aC, 0x00000000,
0x90b0, 0x00000000,
0x90b4, 0x00000000,
0x90b8, 0x00000000,
0x90bC, 0x00000000,
0x90c0, 0x00000000,
0x90c4, 0x00000000,
0x90c8, 0x00000000,
0x90cC, 0x00000000,
0x910c, 0x00800000,
0x9110, 0x00000000,
0x9140, 0x00000003,
0x9144, 0x001f0000,
0x9148, 0x00200000,
0x914c, 0x00000001,
0x9150, 0x00200000,
0x9154, 0x00000002,
0x9158, 0x00200000,
0x915c, 0x00000003,
0x9160, 0x00200000,
0x9164, 0x00000004,
0x9168, 0x00200000,
0x916c, 0x00000005,
0x9170, 0x00200000,
0x9174, 0x00000006,
0x9178, 0x00200000,
0x917c, 0x00000007,
0x9180, 0x00e00003,
0x9184, 0x00e1ff00,
0x9188, 0x00d80003,
0x918c, 0x00dfff00,
0x9190, 0x00e20003,
0x9194, 0x00e3ff00,
0x9198, 0x00000000,
0x91b0, 0x00000a03,
0x91b4, 0x00000b00,
0x91b8, 0x00200003,
0x91bc, 0x00fe0b00,
0x91c0, 0x0000c003,
0x91c4, 0x0000c000,
0x91c8, 0x00001013,
0x91cc, 0x000ff000,
0x91d0, 0x00000000,
0x91e0, 0xff000003,
0x91e4, 0x00000000,
0x9200, 0x11021022,
0x9204, 0x00000000,
0x9208, 0x06000000,
0x920c, 0x00800000,
0x9210, 0x00000000,
0x9240, 0x00000001,
0x9244, 0x00800001,
0x9248, 0x01000001,
0x924c, 0x01800001,
0x9250, 0x00000000,
0x9260, 0x0060fe00,
0x9270, 0x00000000,
0x9280, 0x00000022,
0x9284, 0x00000000,
0x9288, 0x03623125,
0x928c, 0x00000130,
0x9290, 0x080c8000,
0x9294, 0x0e2b0a06,
0x9298, 0x00000000,
0x92b0, 0xd1e8eb05,
0x92b4, 0x000000cc,
0x92b8, 0xdfbfe7ad,
0x92bc, 0xdf4bdfae,
0x92c0, 0x00000003,
0x92c4, 0x00000000,
0x92cc, 0x9f1f0000,
0x92d0, 0xfbf177f5,
0x92d4, 0x3fefda0e,
0x92d8, 0x33bd35dc,
0x92dc, 0x578d89c1,
0x92e0, 0xdae70105,
0x92e4, 0xfa835cfc,
0x92e8, 0x404e87e6,
0x92ec, 0xba35df44,
0x92f0, 0x00000000,
0x930c, 0x00800000,
0x9310, 0x00000000,
0x9340, 0x00003bff,
0x9344, 0x00000040,
0x9348, 0x00000000,
0x935c, 0xfe3fb540,
0x9360, 0x00000090,
0x9364, 0x00000000,
0x9370, 0x51020111,
0x9374, 0x50008011,
0x9378, 0x08003800,
0x937c, 0x0000221b,
0x9380, 0x21272321,
0x9384, 0x00232123,
0x9388, 0x00000000,
0x9390, 0x00000005,
0x9394, 0x00000068,
0x9398, 0x001fe800,
0x939c, 0x00000000,
0x93b8, 0xe000001d,
0x93bc, 0x000000bb,
0x93c0, 0x00000000,
0x93d4, 0x000d0001,
0x93d8, 0x00000000,
0x93e4, 0x00001520,
0x93e8, 0x00000108,
0x93ec, 0x00000000,
};
int max;
max = sizeof(register_values);
}

47
util/romcc/tests/simple_test15.c
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@ -1,47 +0,0 @@
static void outb(unsigned char value, unsigned short port)
{
__builtin_outb(value, port);
}
static unsigned char inb(unsigned short port)
{
return __builtin_inb(port);
}
static int uart_can_tx_byte(void)
{
return inb(0x3f8 + 0x05) & 0x20;
}
static void uart_wait_to_tx_byte(void)
{
while(!uart_can_tx_byte())
;
}
static void uart_wait_until_sent(void)
{
while(!(inb(0x3f8 + 0x05) & 0x40))
;
}
static void uart_tx_byte(unsigned char data)
{
uart_wait_to_tx_byte();
outb(data, 0x3f8 + 0x00);
uart_wait_until_sent();
}
static void print_debug(const char *str)
{
unsigned char ch;
while((ch = *str++) != '\0') {
uart_tx_byte(ch);
}
}
static void main(void)
{
print_debug("one\r\n");
print_debug("two\r\n");
}

18
util/romcc/tests/simple_test16.c
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@ -1,18 +0,0 @@
typedef unsigned char uint8_t;
typedef unsigned short uint16_t;
typedef unsigned int uint32_t;
static void outb(uint8_t value, uint16_t port)
{
__builtin_outb(value, port);
}
static void main(void)
{
uint32_t i;
for(i = 0; i < 32; i++) {
outb(i, 0x80);
}
}

38
util/romcc/tests/simple_test17.c
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@ -1,38 +0,0 @@
typedef unsigned char uint8_t;
typedef unsigned short uint16_t;
typedef unsigned int uint32_t;
struct iter {
uint32_t i;
};
struct point {
uint32_t i, j;
};
static void outb(uint8_t value, uint16_t port)
{
__builtin_outb(value, port);
}
static struct point mkpoint(void)
{
struct point p;
p.i = 1000;
p.j = 2000;
return p;
}
static void main(void)
{
struct iter iter;
for(iter.i = 0; iter.i < 32; iter.i++) {
outb(iter.i, 0x80);
}
struct point p;
p = mkpoint();
outb(p.i, 0x80);
outb(p.j, 0x80);
}

3
util/romcc/tests/simple_test18.c
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@ -1,3 +0,0 @@
static void main(void)
{
}

24
util/romcc/tests/simple_test19.c
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@ -1,24 +0,0 @@
static void hlt(void)
{
__builtin_hlt();
}
typedef __builtin_msr_t msr_t;
static msr_t rdmsr(unsigned long index)
{
return __builtin_rdmsr(index);
}
static void wrmsr(unsigned long index, msr_t msr)
{
__builtin_wrmsr(index, msr.lo, msr.hi);
}
static void main(void)
{
msr_t msr;
msr = rdmsr(0x1234);
msr.lo &= ~(1<<5);
wrmsr(0x1234, msr);
}

36
util/romcc/tests/simple_test2.c
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@ -1,36 +0,0 @@
void outl(unsigned int value, unsigned short port)
{
__builtin_outl(value, port);
}
#define PIIX4_DEVFN 0x90
#define SMBUS_MEM_DEVICE_START 0x50
#define SMBUS_MEM_DEVICE_END 0x53
#define SMBUS_MEM_DEVICE_INC 1
static void spd_set_drb(void)
{
/*
* Effects: Uses serial presence detect to set the
* DRB registers which holds the ending memory address assigned
* to each DIMM.
*/
unsigned end_of_memory;
unsigned device;
end_of_memory = 0; /* in multiples of 8MiB */
device = SMBUS_MEM_DEVICE_START;
while (device <= SMBUS_MEM_DEVICE_END) {
unsigned side1_bits;
side1_bits = -1;
/* Compute the end address for the DRB register */
/* Only process dimms < 2GB (2^8 * 8MB) */
if (side1_bits < 8) {
end_of_memory += (1 << side1_bits);
}
outl(end_of_memory, 0x1234);
}
}

148
util/romcc/tests/simple_test20.c
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@ -1,148 +0,0 @@
static void outb(unsigned char value, unsigned short port)
{
__builtin_outb(value, port);
}
static void outl(unsigned int value, unsigned short port)
{
__builtin_outl(value, port);
}
static unsigned char inb(unsigned short port)
{
return __builtin_inb(port);
}
static unsigned char inl(unsigned short port)
{
return __builtin_inl(port);
}
static unsigned int config_cmd(unsigned char bus, unsigned devfn, unsigned where)
{
return 0x80000000 | (bus << 16) | (devfn << 8) | (where & ~3);
}
static unsigned int pcibios_read_config_dword(
unsigned char bus, unsigned devfn, unsigned where)
{
outl(config_cmd(bus, devfn, where), 0xCF8);
return inl(0xCFC);
}
/* Base Address */
#ifndef CONFIG_TTYS0_BASE
#define CONFIG_TTYS0_BASE 0x3f8
#endif
#ifndef CONFIG_TTYS0_BAUD
#define CONFIG_TTYS0_BAUD 115200
#endif
#if ((115200%CONFIG_TTYS0_BAUD) != 0)
#error Bad ttys0 baud rate
#endif
#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD)
/* Line Control Settings */
#ifndef CONFIG_TTYS0_LCS
/* Set 8bit, 1 stop bit, no parity */
#define CONFIG_TTYS0_LCS 0x3
#endif
#define UART_LCS CONFIG_TTYS0_LCS
/* Data */
#define UART_RBR 0x00
#define UART_TBR 0x00
/* Control */
#define UART_IER 0x01
#define UART_IIR 0x02
#define UART_FCR 0x02
#define UART_LCR 0x03
#define UART_MCR 0x04
#define UART_DLL 0x00
#define UART_DLM 0x01
/* Status */
#define UART_LSR 0x05
#define UART_MSR 0x06
#define UART_SCR 0x07
int uart_can_tx_byte(void)
{
return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20;
}
void uart_wait_to_tx_byte(void)
{
while(!uart_can_tx_byte())
;
}
void uart_wait_until_sent(void)
{
while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40))
;
}
void uart_tx_byte(unsigned char data)
{
uart_wait_to_tx_byte();
outb(data, CONFIG_TTYS0_BASE + UART_TBR);
/* Make certain the data clears the fifos */
uart_wait_until_sent();
}
void uart_init(void)
{
/* disable interrupts */
outb(0x0, CONFIG_TTYS0_BASE + UART_IER);
/* enable fifo's */
outb(0x01, CONFIG_TTYS0_BASE + UART_FCR);
/* Set Baud Rate Divisor to 12 ==> 115200 Baud */
outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR);
outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL);
outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM);
outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR);
}
void __console_tx_char(unsigned char byte)
{
uart_tx_byte(byte);
}
void __console_tx_nibble(unsigned nibble)
{
unsigned char digit;
digit = nibble + '0';
if (digit > '9') {
digit += 39;
}
__console_tx_char(digit);
}
void __console_tx_hex32(unsigned int value)
{
__console_tx_nibble((value >> 28) & 0x0f);
__console_tx_nibble((value >> 24) & 0x0f);
__console_tx_nibble((value >> 20) & 0x0f);
__console_tx_nibble((value >> 16) & 0x0f);
__console_tx_nibble((value >> 12) & 0x0f);
__console_tx_nibble((value >> 8) & 0x0f);
__console_tx_nibble((value >> 4) & 0x0f);
__console_tx_nibble(value & 0x0f);
}
void print_debug_hex32(unsigned int value) { __console_tx_hex32(value); }
void main(void)
{
unsigned long htic;
htic = pcibios_read_config_dword(0, 0xc0, 0x6c);
print_debug_hex32(htic);
}

6
util/romcc/tests/simple_test21.c
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@ -1,6 +0,0 @@
static void main(void)
{
asm("hlt");
}

306
util/romcc/tests/simple_test22.c
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@ -1,306 +0,0 @@
struct syscall_result {
long val;
int errno;
};
static struct syscall_result syscall_return(long result)
{
struct syscall_result res;
if (((unsigned long)result) >= ((unsigned long)-125)) {
res.errno = - result;
res.val = -1;
} else {
res.errno = 0;
res.val = result;
}
return res;
}
static struct syscall_result syscall0(unsigned long nr)
{
long res;
asm volatile(
"int $0x80"
: "=a" (res)
: "a" (nr));
return syscall_return(res);
}
static struct syscall_result syscall1(unsigned long nr, unsigned long arg1)
{
long res;
asm volatile(
"int $0x80"
: "=a" (res)
: "a" (nr), "b" (arg1));
return syscall_return(res);
}
static struct syscall_result syscall2(unsigned long nr, unsigned long arg1, unsigned long arg2)
{
long res;
asm volatile(
"int $0x80"
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2));
return syscall_return(res);
}
static struct syscall_result syscall3(unsigned long nr, unsigned long arg1, unsigned long arg2,
unsigned long arg3)
{
long res;
asm volatile(
"int $0x80"
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3));
return syscall_return(res);
}
static struct syscall_result syscall4(unsigned long nr, unsigned long arg1, unsigned long arg2,
unsigned long arg3, unsigned long arg4)
{
long res;
asm volatile(
"int $0x80"
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), "S" (arg4));
return syscall_return(res);
}
static struct syscall_result syscall5(unsigned long nr, unsigned long arg1, unsigned long arg2,
unsigned long arg3, unsigned long arg4, unsigned long arg5)
{
long res;
asm volatile(
"int $0x80"
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3),
"S" (arg4), "D" (arg5));
return syscall_return(res);
}
#define NR_exit 1
#define NR_fork 2
#define NR_read 3
#define NR_write 4
#define NR_open 5
#define NR_close 6
#define NR_waitpid 7
#define NR_creat 8
#define NR_link 9
#define NR_unlink 10
#define NR_execve 11
#define NR_chdir 12
#define NR_time 13
#define NR_mknod 14
#define NR_chmod 15
#define NR_lchown 16
#define NR_break 17
#define NR_oldstat 18
#define NR_lseek 19
#define NR_getpid 20
#define NR_mount 21
#define NR_umount 22
#define NR_setuid 23
#define NR_getuid 24
#define NR_stime 25
#define NR_ptrace 26
#define NR_alarm 27
#define NR_oldfstat 28
#define NR_pause 29
#define NR_utime 30
#define NR_stty 31
#define NR_gtty 32
#define NR_access 33
#define NR_nice 34
#define NR_ftime 35
#define NR_sync 36
#define NR_kill 37
#define NR_rename 38
#define NR_mkdir 39
#define NR_rmdir 40
#define NR_dup 41
#define NR_pipe 42
#define NR_times 43
#define NR_prof 44
#define NR_brk 45
#define NR_setgid 46
#define NR_getgid 47
#define NR_signal 48
#define NR_geteuid 49
#define NR_getegid 50
#define NR_acct 51
#define NR_umount2 52
#define NR_lock 53
#define NR_ioctl 54
#define NR_fcntl 55
#define NR_mpx 56
#define NR_setpgid 57
#define NR_ulimit 58
#define NR_oldolduname 59
#define NR_umask 60
#define NR_chroot 61
#define NR_ustat 62
#define NR_dup2 63
#define NR_getppid 64
#define NR_getpgrp 65
#define NR_setsid 66
#define NR_sigaction 67
#define NR_sgetmask 68
#define NR_ssetmask 69
#define NR_setreuid 70
#define NR_setregid 71
#define NR_sigsuspend 72
#define NR_sigpending 73
#define NR_sethostname 74
#define NR_setrlimit 75
#define NR_getrlimit 76
#define NR_getrusage 77
#define NR_gettimeofday 78
#define NR_settimeofday 79
#define NR_getgroups 80
#define NR_setgroups 81
#define NR_select 82
#define NR_symlink 83
#define NR_oldlstat 84
#define NR_readlink 85
#define NR_uselib 86
#define NR_swapon 87
#define NR_reboot 88
#define NR_readdir 89
#define NR_mmap 90
#define NR_munmap 91
#define NR_truncate 92
#define NR_ftruncate 93
#define NR_fchmod 94
#define NR_fchown 95
#define NR_getpriority 96
#define NR_setpriority 97
#define NR_profil 98
#define NR_statfs 99
#define NR_fstatfs 100
#define NR_ioperm 101
#define NR_socketcall 102
#define NR_syslog 103
#define NR_setitimer 104
#define NR_getitimer 105
#define NR_stat 106
#define NR_lstat 107
#define NR_fstat 108
#define NR_olduname 109
#define NR_iopl 110
#define NR_vhangup 111
#define NR_idle 112
#define NR_vm86old 113
#define NR_wait4 114
#define NR_swapoff 115
#define NR_sysinfo 116
#define NR_ipc 117
#define NR_fsync 118
#define NR_sigreturn 119
#define NR_clone 120
#define NR_setdomainname 121
#define NR_uname 122
#define NR_modify_ldt 123
#define NR_adjtimex 124
#define NR_mprotect 125
#define NR_sigprocmask 126
#define NR_create_module 127
#define NR_init_module 128
#define NR_delete_module 129
#define NR_get_kernel_syms 130
#define NR_quotactl 131
#define NR_getpgid 132
#define NR_fchdir 133
#define NR_bdflush 134
#define NR_sysfs 135
#define NR_personality 136
#define NR_afs_syscall 137 /* Syscall for Andrew File System */
#define NR_setfsuid 138
#define NR_setfsgid 139
#define NR__llseek 140
#define NR_getdents 141
#define NR__newselect 142
#define NR_flock 143
#define NR_msync 144
#define NR_readv 145
#define NR_writev 146
#define NR_getsid 147
#define NR_fdatasync 148
#define NR__sysctl 149
#define NR_mlock 150
#define NR_munlock 151
#define NR_mlockall 152
#define NR_munlockall 153
#define NR_sched_setparam 154
#define NR_sched_getparam 155
#define NR_sched_setscheduler 156
#define NR_sched_getscheduler 157
#define NR_sched_yield 158
#define NR_sched_get_priority_max 159
#define NR_sched_get_priority_min 160
#define NR_sched_rr_get_interval 161
#define NR_nanosleep 162
#define NR_mremap 163
#define NR_setresuid 164
#define NR_getresuid 165
#define NR_vm86 166
#define NR_query_module 167
#define NR_poll 168
#define NR_nfsservctl 169
#define NR_setresgid 170
#define NR_getresgid 171
#define NR_prctl 172
#define NR_rt_sigreturn 173
#define NR_rt_sigaction 174
#define NR_rt_sigprocmask 175
#define NR_rt_sigpending 176
#define NR_rt_sigtimedwait 177
#define NR_rt_sigqueueinfo 178
#define NR_rt_sigsuspend 179
#define NR_pread 180
#define NR_pwrite 181
#define NR_chown 182
#define NR_getcwd 183
#define NR_capget 184
#define NR_capset 185
#define NR_sigaltstack 186
#define NR_sendfile 187
#define NR_getpmsg 188 /* some people actually want streams */
#define NR_putpmsg 189 /* some people actually want streams */
#define NR_vfork 190
typedef long ssize_t;
typedef unsigned long size_t;
/* Standard file descriptors */
#define STDIN_FILENO 0 /* Standard input */
#define STDOUT_FILENO 1 /* Standard output */
#define STDERR_FILENO 2 /* Standard error output */
static ssize_t write(int fd, const void *buf, size_t count)
{
struct syscall_result res;
res = syscall3(NR_write, fd, (unsigned long)buf, count);
return res.val;
}
static void _exit(int status)
{
struct syscall_result res;
res = syscall1(NR_exit, status);
}
static void main(void)
{
static const char msg[] = "hello world\r\n";
write(STDOUT_FILENO, msg, sizeof(msg));
_exit(0);
}

18
util/romcc/tests/simple_test23.c
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@ -1,18 +0,0 @@
static void print(char *str)
{
while(1) {
unsigned char ch;
ch = *str;
if (ch == '\0') {
break;
}
__builtin_outb(ch, 0x1234);
str += 1;
}
}
static void main(void)
{
print("hello world\r\n");
print("how are you today\r\n");
}

16
util/romcc/tests/simple_test24.c
View File

@ -1,16 +0,0 @@
void smbus_read_byte(void)
{
unsigned char host_status_register;
unsigned char byte;
int result;
host_status_register = __builtin_inb(0x1234);
/* read results of transaction */
byte = __builtin_inb(0x4567);
result = byte;
if (host_status_register != 0x02) {
result = -1;
}
}

109
util/romcc/tests/simple_test25.c
View File

@ -1,109 +0,0 @@
#define COUNT 26
static void main(void)
{
unsigned char a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p, q, r, s, t, u, v, w, x, y, z;
a = 1;
b = 2;
c = 3;
d = 4;
e = 5;
f = 6;
g = 7;
h = 8;
i = 9;
j = 10;
k = 11;
l = 12;
m = 13;
n = 14;
o = 15;
p = 16;
q = 17;
r = 18;
s = 19;
t = 20;
u = 21;
v = 22;
w = 23;
x = 24;
y = 25;
z = 26;
#if COUNT >= 26
__builtin_outb(z, 0xab);
#endif
#if COUNT >= 25
__builtin_outb(y, 0xab);
#endif
#if COUNT >= 24
__builtin_outb(x, 0xab);
#endif
#if COUNT >= 23
__builtin_outb(w, 0xab);
#endif
#if COUNT >= 22
__builtin_outb(v, 0xab);
#endif
#if COUNT >= 21
__builtin_outb(u, 0xab);
#endif
#if COUNT >= 20
__builtin_outb(t, 0xab);
#endif
#if COUNT >= 19
__builtin_outb(s, 0xab);
#endif
#if COUNT >= 18
__builtin_outb(r, 0xab);
#endif
#if COUNT >= 17
__builtin_outb(q, 0xab);
#endif
#if COUNT >= 16
__builtin_outb(p, 0xab);
#endif
#if COUNT >= 15
__builtin_outb(o, 0xab);
#endif
#if COUNT >= 14
__builtin_outb(n, 0xab);
#endif
#if COUNT >= 13
__builtin_outb(m, 0xab);
#endif
#if COUNT >= 12
__builtin_outb(l, 0xab);
#endif
#if COUNT >= 11
__builtin_outb(k, 0xab);
#endif
#if COUNT >= 10
__builtin_outb(j, 0xab);
#endif
#if COUNT >= 9
__builtin_outb(i, 0xab);
#endif
#if COUNT >= 8
__builtin_outb(h, 0xab);
#endif
#if COUNT >= 7
__builtin_outb(g, 0xab);
#endif
#if COUNT >= 6
__builtin_outb(f, 0xab);
#endif
#if COUNT >= 5
__builtin_outb(e, 0xab);
#endif
#if COUNT >= 4
__builtin_outb(d, 0xab);
#endif
#if COUNT >= 3
__builtin_outb(c, 0xab);
#endif
#if COUNT >= 2
__builtin_outb(b, 0xab);
#endif
#if COUNT >= 1
__builtin_outb(a, 0xab);
#endif
}

109
util/romcc/tests/simple_test26.c
View File

@ -1,109 +0,0 @@
#define COUNT 23
static void main(void)
{
unsigned int a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p, q, r, s, t, u, v, w, x, y, z;
a = __builtin_inb(0xab);
b = __builtin_inb(0xab);
c = __builtin_inb(0xab);
d = __builtin_inb(0xab);
e = __builtin_inb(0xab);
f = __builtin_inb(0xab);
g = __builtin_inb(0xab);
h = __builtin_inb(0xab);
i = __builtin_inb(0xab);
j = __builtin_inb(0xab);
k = __builtin_inb(0xab);
l = __builtin_inb(0xab);
m = __builtin_inb(0xab);
n = __builtin_inb(0xab);
o = __builtin_inb(0xab);
p = __builtin_inb(0xab);
q = __builtin_inb(0xab);
r = __builtin_inb(0xab);
s = __builtin_inb(0xab);
t = __builtin_inb(0xab);
u = __builtin_inb(0xab);
v = __builtin_inb(0xab);
w = __builtin_inb(0xab);
x = __builtin_inb(0xab);
y = __builtin_inb(0xab);
z = __builtin_inb(0xab);
#if COUNT >= 26
__builtin_outb(z, 0xab);
#endif
#if COUNT >= 25
__builtin_outb(y, 0xab);
#endif
#if COUNT >= 24
__builtin_outb(x, 0xab);
#endif
#if COUNT >= 23
__builtin_outb(w, 0xab);
#endif
#if COUNT >= 22
__builtin_outb(v, 0xab);
#endif
#if COUNT >= 21
__builtin_outb(u, 0xab);
#endif
#if COUNT >= 20
__builtin_outb(t, 0xab);
#endif
#if COUNT >= 19
__builtin_outb(s, 0xab);
#endif
#if COUNT >= 18
__builtin_outb(r, 0xab);
#endif
#if COUNT >= 17
__builtin_outb(q, 0xab);
#endif
#if COUNT >= 16
__builtin_outb(p, 0xab);
#endif
#if COUNT >= 15
__builtin_outb(o, 0xab);
#endif
#if COUNT >= 14
__builtin_outb(n, 0xab);
#endif
#if COUNT >= 13
__builtin_outb(m, 0xab);
#endif
#if COUNT >= 12
__builtin_outb(l, 0xab);
#endif
#if COUNT >= 11
__builtin_outb(k, 0xab);
#endif
#if COUNT >= 10
__builtin_outb(j, 0xab);
#endif
#if COUNT >= 9
__builtin_outb(i, 0xab);
#endif
#if COUNT >= 8
__builtin_outb(h, 0xab);
#endif
#if COUNT >= 7
__builtin_outb(g, 0xab);
#endif
#if COUNT >= 6
__builtin_outb(f, 0xab);
#endif
#if COUNT >= 5
__builtin_outb(e, 0xab);
#endif
#if COUNT >= 4
__builtin_outb(d, 0xab);
#endif
#if COUNT >= 3
__builtin_outb(c, 0xab);
#endif
#if COUNT >= 2
__builtin_outb(b, 0xab);
#endif
#if COUNT >= 1
__builtin_outb(a, 0xab);
#endif
}

133
util/romcc/tests/simple_test27.c
View File

@ -1,133 +0,0 @@
void outb(unsigned char value, unsigned short port)
{
__builtin_outb(value, port);
}
unsigned char inb(unsigned short port)
{
return __builtin_inb(port);
}
/* Base Address */
#ifndef CONFIG_TTYS0_BASE
#define CONFIG_TTYS0_BASE 0x3f8
#endif
#ifndef CONFIG_TTYS0_BAUD
#define CONFIG_TTYS0_BAUD 115200
#endif
#if ((115200%CONFIG_TTYS0_BAUD) != 0)
#error Bad ttys0 baud rate
#endif
#if CONFIG_TTYS0_BAUD == 115200
#define CONFIG_TTYS0_DIV (1)
#else
#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD)
#endif
/* Line Control Settings */
#ifndef CONFIG_TTYS0_LCS
/* Set 8bit, 1 stop bit, no parity */
#define CONFIG_TTYS0_LCS 0x3
#endif
#define UART_LCS CONFIG_TTYS0_LCS
/* Data */
#define UART_RBR 0x00
#define UART_TBR 0x00
/* Control */
#define UART_IER 0x01
#define UART_IIR 0x02
#define UART_FCR 0x02
#define UART_LCR 0x03
#define UART_MCR 0x04
#define UART_DLL 0x00
#define UART_DLM 0x01
/* Status */
#define UART_LSR 0x05
#define UART_MSR 0x06
#define UART_SCR 0x07
int uart_can_tx_byte(void)
{
return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20;
}
void uart_wait_to_tx_byte(void)
{
while(!uart_can_tx_byte())
;
}
void uart_wait_until_sent(void)
{
while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40))
;
}
static void uart_tx_byte(unsigned char data)
{
uart_wait_to_tx_byte();
outb(data, CONFIG_TTYS0_BASE + UART_TBR);
/* Make certain the data clears the fifos */
uart_wait_until_sent();
}
void uart_init(void)
{
/* disable interrupts */
outb(0x0, CONFIG_TTYS0_BASE + UART_IER);
/* enable fifo's */
outb(0x01, CONFIG_TTYS0_BASE + UART_FCR);
/* Set Baud Rate Divisor to 12 ==> 115200 Baud */
outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR);
outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL);
outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM);
outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR);
}
void __console_tx_char(unsigned char byte)
{
uart_tx_byte(byte);
}
void __console_tx_string(char *str)
{
unsigned char ch;
while((ch = *str++) != '\0') {
__console_tx_char(ch);
}
}
void print_debug_char(unsigned char byte) { __console_tx_char(byte); }
void print_debug(char *str) { __console_tx_string(str); }
void main(void)
{
static const char msg[] = "hello world\r\n";
uart_init();
#if 0
print_debug(msg);
#endif
#if 1
print_debug("hello world\r\n");
print_debug("how are you today\r\n");
#endif
while(1) {
;
}
}
void main2(void)
{
main();
}

24
util/romcc/tests/simple_test28.c
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@ -1,24 +0,0 @@
static void outl(unsigned int value, unsigned short port)
{
__builtin_outl(value, port);
}
static unsigned char inl(unsigned short port)
{
return __builtin_inl(port);
}
static void setup_coherent_ht_domain(void)
{
static const unsigned int register_values[] = {
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x40) & 0xFF)), 0xfff0f0f0, 0x00010101,
};
unsigned long reg;
reg = inl(0xFC);
reg &= register_values[1];
reg |= register_values[2] & ~register_values[1];
outl(register_values[0], 0xF8);
outl(reg, 0xFC);
}

37
util/romcc/tests/simple_test29.c
View File

@ -1,37 +0,0 @@
static void outb(unsigned char value, unsigned short port)
{
__builtin_outb(value, port);
}
static unsigned char inb(unsigned short port)
{
return __builtin_inb(port);
}
static void __console_tx_byte(unsigned char byte)
{
while(inb(0x3f8 + 0x05))
;
outb(byte, 0x3f8 + 0x00);
}
static void __console_tx_string(int loglevel, const char *str)
{
if (8 > loglevel) {
unsigned char ch;
while((ch = *str++) != '\0') {
__console_tx_byte(ch);
}
}
}
static void console_init(void)
{
static const char console_test[] =
"\r\n\r\nLinuxBIOS-"
"1.1.0"
".0Fallback"
" "
"Mon Jun 9 18:15:20 MDT 2003"
" starting...\r\n";
__console_tx_string(6, console_test);
}

38
util/romcc/tests/simple_test3.c
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@ -1,38 +0,0 @@
static void spd_set_drb(void)
{
/*
* Effects: Uses serial presence detect to set the
* DRB registers which holds the ending memory address assigned
* to each DIMM.
*/
unsigned end_of_memory;
unsigned device;
end_of_memory = 0; /* in multiples of 8MiB */
device = 0x50;
while (device <= 0x53) {
unsigned side1_bits, side2_bits;
int byte, byte2;
side1_bits = side2_bits = -1;
/* rows */
byte = -1;
if (1) {
/* now I have the ram size in bits as a power of two (less 1) */
/* Make it mulitples of 8MB */
side1_bits -= 25;
}
/* Compute the end address for the DRB register */
/* Only process dimms < 2GB (2^8 * 8MB) */
if (1) {
end_of_memory += side1_bits;
}
__builtin_outl(end_of_memory, 0x1234);
if (1) {
end_of_memory += side2_bits;
}
}
}

1087
util/romcc/tests/simple_test30.c
View File

File diff suppressed because it is too large Load Diff

16
util/romcc/tests/simple_test31.c
View File

@ -1,16 +0,0 @@
static unsigned pci_locate_device(unsigned addr)
{
addr &= ~0xff;
for(; addr <= 0x00ffff00; addr += 0x00000100) {
__builtin_outl(addr, 0x12);
}
return addr;
}
static void main(void)
{
unsigned long addr;
addr = pci_locate_device(0);
__builtin_outl(addr, 0x12);
}

35
util/romcc/tests/simple_test32.c
View File

@ -1,35 +0,0 @@
void main(void)
{
unsigned long addr, start, stop;
start = 0x00100000;
stop = 0x00180000;
for(addr = start; addr < stop ;) {
unsigned char ch;
const char *str = "\r";
while((ch = *str++) != '\0') {
while(__builtin_inb(0x3f))
;
__builtin_outb(ch, 0x3f8);
while(__builtin_inb(0x3f))
;
}
asm (
"jmp 2f\n\t"
"1:\n\t"
"testl $0xffff, %0\n\t"
"jz 3f\n\t"
"movnti %0, (%0)\n\t"
"add $4, %0\n\t"
"2:\n\t"
"cmp %2, %0\n\t"
"jl 1b\n\t"
"3:\n\t"
: "=b" (addr) /* outputs */
: "0" (addr), "r" (stop) /* intputs */
: /* clobbers */
);
};
}

39
util/romcc/tests/simple_test33.c
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@ -1,39 +0,0 @@
static void main(void)
{
unsigned long loops0, loops1, loops2;
unsigned long accum;
accum = 0;
loops0 = 10;
do {
unsigned short val;
val = __builtin_inw(0x10e0);
if (((val & 0x08) == 0) || (val == 1)) {
break;
}
} while(--loops0);
if (loops0 < 0) return;
accum += loops0;
loops1 = 20;
do {
unsigned short val;
val = __builtin_inw(0x10e0);
if (((val & 0x08) == 0) || (val == 1)) {
break;
}
} while(--loops1);
loops2 = 30;
do {
unsigned short val;
val = __builtin_inw(0x10e0);
if (((val & 0x08) == 0) || (val == 1)) {
break;
}
} while(--loops2);
accum += loops1 + loops0;
}

71
util/romcc/tests/simple_test34.c
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@ -1,71 +0,0 @@
typedef __builtin_msr_t msr_t;
static msr_t rdmsr(unsigned long index)
{
return __builtin_rdmsr(index);
}
static void uart_tx_byte(unsigned char data)
{
while(!(__builtin_inb(0x3f8 + 0x05) & 0x20))
;
__builtin_outb(data, 0x3f8 + 0x00);
while(!(__builtin_inb(0x3f8 + 0x05) & 0x40))
;
}
static void print_nibble(unsigned nibble)
{
unsigned char digit;
digit = nibble + '0';
if (digit > '9') {
digit += 39;
}
uart_tx_byte(digit);
}
static void print_debug_hex32(unsigned int value)
{
print_nibble((value >> 28U) & 0x0fU);
print_nibble((value >> 24U) & 0x0fU);
print_nibble((value >> 20U) & 0x0fU);
print_nibble((value >> 16U) & 0x0fU);
print_nibble((value >> 12U) & 0x0fU);
print_nibble((value >> 8U) & 0x0fU);
print_nibble((value >> 4U) & 0x0fU);
print_nibble(value & 0x0fU);
}
static void print_debug(const char *str)
{
unsigned char ch;
while((ch = *str++) != '\0') {
uart_tx_byte(ch);
}
}
static void main(void)
{
unsigned long start, stop;
msr_t msr;
msr = rdmsr(0xC001001A);
print_debug("TOP_MEM: ");
print_debug_hex32(msr.hi);
print_debug_hex32(msr.lo);
print_debug("\r\n");
start = 0;
stop = msr.lo;
print_debug("Testing DRAM : ");
print_debug_hex32(start);
print_debug("-");
print_debug_hex32(stop);
print_debug("\r\n");
print_debug("DRAM verify: ");
print_debug_hex32(start);
print_debug_hex32(stop);
}

9
util/romcc/tests/simple_test35.c
View File

@ -1,9 +0,0 @@
static void main(void)
{
__builtin_msr_t msr;
msr = __builtin_rdmsr(0xC001001A);
while(__builtin_inb(0x3fd))
;
__builtin_outb(msr.hi, 0x3f8);
}

41
util/romcc/tests/simple_test36.c
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@ -1,41 +0,0 @@
static void order_dimms(void)
{
unsigned long tom;
tom = 0;
for(;;) {
unsigned csbase, csmask;
unsigned size;
unsigned index;
csbase = 0;
for(index = 0; index < 1; index++) {
csbase = __builtin_inl(0x40);
}
if (csbase == 0) {
break;
}
size = csbase;
csbase = (tom << 21);
tom += size;
csmask = size;
csmask |= 0xfe00;
__builtin_outl(csbase, 0xCFC);
__builtin_outl(0xc260, 0xCF8);
__builtin_outl(csmask, 0xCFC);
}
tom &= ~0xff000000;
__builtin_outl(tom, 0x1234);
}

10
util/romcc/tests/simple_test37.c
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@ -1,10 +0,0 @@
static void main(void)
{
unsigned csbase, csmask;
csbase = 0x40;
csmask = 0xfe00;
__builtin_outl(csbase, 0x40);
__builtin_outl(csmask, 0x60);
}

425
util/romcc/tests/simple_test38.c
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@ -1,425 +0,0 @@
struct syscall_result {
long val;
int errno;
};
static struct syscall_result syscall_return(long result)
{
struct syscall_result res;
if (((unsigned long)result) >= ((unsigned long)-125)) {
res.errno = - result;
res.val = -1;
} else {
res.errno = 0;
res.val = result;
}
return res;
}
static struct syscall_result syscall0(unsigned long nr)
{
long res;
asm volatile(
"int $0x80"
: "=a" (res)
: "a" (nr));
return syscall_return(res);
}
static struct syscall_result syscall1(unsigned long nr, unsigned long arg1)
{
long res;
asm volatile(
"int $0x80"
: "=a" (res)
: "a" (nr), "b" (arg1));
return syscall_return(res);
}
static struct syscall_result syscall2(unsigned long nr, unsigned long arg1, unsigned long arg2)
{
long res;
asm volatile(
"int $0x80"
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2));
return syscall_return(res);
}
static struct syscall_result syscall3(unsigned long nr, unsigned long arg1, unsigned long arg2,
unsigned long arg3)
{
long res;
asm volatile(
"int $0x80"
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3));
return syscall_return(res);
}
static struct syscall_result syscall4(unsigned long nr, unsigned long arg1, unsigned long arg2,
unsigned long arg3, unsigned long arg4)
{
long res;
asm volatile(
"int $0x80"
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), "S" (arg4));
return syscall_return(res);
}
static struct syscall_result syscall5(unsigned long nr, unsigned long arg1, unsigned long arg2,
unsigned long arg3, unsigned long arg4, unsigned long arg5)
{
long res;
asm volatile(
"int $0x80"
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3),
"S" (arg4), "D" (arg5));
return syscall_return(res);
}
#define NR_exit 1
#define NR_fork 2
#define NR_read 3
#define NR_write 4
#define NR_open 5
#define NR_close 6
#define NR_waitpid 7
#define NR_creat 8
#define NR_link 9
#define NR_unlink 10
#define NR_execve 11
#define NR_chdir 12
#define NR_time 13
#define NR_mknod 14
#define NR_chmod 15
#define NR_lchown 16
#define NR_break 17
#define NR_oldstat 18
#define NR_lseek 19
#define NR_getpid 20
#define NR_mount 21
#define NR_umount 22
#define NR_setuid 23
#define NR_getuid 24
#define NR_stime 25
#define NR_ptrace 26
#define NR_alarm 27
#define NR_oldfstat 28
#define NR_pause 29
#define NR_utime 30
#define NR_stty 31
#define NR_gtty 32
#define NR_access 33
#define NR_nice 34
#define NR_ftime 35
#define NR_sync 36
#define NR_kill 37
#define NR_rename 38
#define NR_mkdir 39
#define NR_rmdir 40
#define NR_dup 41
#define NR_pipe 42
#define NR_times 43
#define NR_prof 44
#define NR_brk 45
#define NR_setgid 46
#define NR_getgid 47
#define NR_signal 48
#define NR_geteuid 49
#define NR_getegid 50
#define NR_acct 51
#define NR_umount2 52
#define NR_lock 53
#define NR_ioctl 54
#define NR_fcntl 55
#define NR_mpx 56
#define NR_setpgid 57
#define NR_ulimit 58
#define NR_oldolduname 59
#define NR_umask 60
#define NR_chroot 61
#define NR_ustat 62
#define NR_dup2 63
#define NR_getppid 64
#define NR_getpgrp 65
#define NR_setsid 66
#define NR_sigaction 67
#define NR_sgetmask 68
#define NR_ssetmask 69
#define NR_setreuid 70
#define NR_setregid 71
#define NR_sigsuspend 72
#define NR_sigpending 73
#define NR_sethostname 74
#define NR_setrlimit 75
#define NR_getrlimit 76
#define NR_getrusage 77
#define NR_gettimeofday 78
#define NR_settimeofday 79
#define NR_getgroups 80
#define NR_setgroups 81
#define NR_select 82
#define NR_symlink 83
#define NR_oldlstat 84
#define NR_readlink 85
#define NR_uselib 86
#define NR_swapon 87
#define NR_reboot 88
#define NR_readdir 89
#define NR_mmap 90
#define NR_munmap 91
#define NR_truncate 92
#define NR_ftruncate 93
#define NR_fchmod 94
#define NR_fchown 95
#define NR_getpriority 96
#define NR_setpriority 97
#define NR_profil 98
#define NR_statfs 99
#define NR_fstatfs 100
#define NR_ioperm 101
#define NR_socketcall 102
#define NR_syslog 103
#define NR_setitimer 104
#define NR_getitimer 105
#define NR_stat 106
#define NR_lstat 107
#define NR_fstat 108
#define NR_olduname 109
#define NR_iopl 110
#define NR_vhangup 111
#define NR_idle 112
#define NR_vm86old 113
#define NR_wait4 114
#define NR_swapoff 115
#define NR_sysinfo 116
#define NR_ipc 117
#define NR_fsync 118
#define NR_sigreturn 119
#define NR_clone 120
#define NR_setdomainname 121
#define NR_uname 122
#define NR_modify_ldt 123
#define NR_adjtimex 124
#define NR_mprotect 125
#define NR_sigprocmask 126
#define NR_create_module 127
#define NR_init_module 128
#define NR_delete_module 129
#define NR_get_kernel_syms 130
#define NR_quotactl 131
#define NR_getpgid 132
#define NR_fchdir 133
#define NR_bdflush 134
#define NR_sysfs 135
#define NR_personality 136
#define NR_afs_syscall 137 /* Syscall for Andrew File System */
#define NR_setfsuid 138
#define NR_setfsgid 139
#define NR__llseek 140
#define NR_getdents 141
#define NR__newselect 142
#define NR_flock 143
#define NR_msync 144
#define NR_readv 145
#define NR_writev 146
#define NR_getsid 147
#define NR_fdatasync 148
#define NR__sysctl 149
#define NR_mlock 150
#define NR_munlock 151
#define NR_mlockall 152
#define NR_munlockall 153
#define NR_sched_setparam 154
#define NR_sched_getparam 155
#define NR_sched_setscheduler 156
#define NR_sched_getscheduler 157
#define NR_sched_yield 158
#define NR_sched_get_priority_max 159
#define NR_sched_get_priority_min 160
#define NR_sched_rr_get_interval 161
#define NR_nanosleep 162
#define NR_mremap 163
#define NR_setresuid 164
#define NR_getresuid 165
#define NR_vm86 166
#define NR_query_module 167
#define NR_poll 168
#define NR_nfsservctl 169
#define NR_setresgid 170
#define NR_getresgid 171
#define NR_prctl 172
#define NR_rt_sigreturn 173
#define NR_rt_sigaction 174
#define NR_rt_sigprocmask 175
#define NR_rt_sigpending 176
#define NR_rt_sigtimedwait 177
#define NR_rt_sigqueueinfo 178
#define NR_rt_sigsuspend 179
#define NR_pread 180
#define NR_pwrite 181
#define NR_chown 182
#define NR_getcwd 183
#define NR_capget 184
#define NR_capset 185
#define NR_sigaltstack 186
#define NR_sendfile 187
#define NR_getpmsg 188 /* some people actually want streams */
#define NR_putpmsg 189 /* some people actually want streams */
#define NR_vfork 190
typedef long ssize_t;
typedef unsigned long size_t;
/* Standard file descriptors */
#define STDIN_FILENO 0 /* Standard input */
#define STDOUT_FILENO 1 /* Standard output */
#define STDERR_FILENO 2 /* Standard error output */
static ssize_t write(int fd, const void *buf, size_t count)
{
struct syscall_result res;
res = syscall3(NR_write, fd, (unsigned long)buf, count);
return res.val;
}
static void _exit(int status)
{
struct syscall_result res;
res = syscall1(NR_exit, status);
}
static const char *addr_of_char(unsigned char ch)
{
static const char byte[] = {
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f,
0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f,
0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97,
0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f,
0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,
0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf,
0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7,
0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf,
0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf,
0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7,
0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf,
0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7,
0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef,
0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7,
0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff,
};
return byte + ch;
}
static void console_tx_byte(unsigned char ch)
{
write(STDOUT_FILENO, addr_of_char(ch), 1);
}
static void console_tx_nibble(unsigned nibble)
{
unsigned char digit;
digit = nibble + '0';
if (digit > '9') {
digit += 39;
}
console_tx_byte(digit);
}
static void console_tx_char(unsigned char byte)
{
console_tx_byte(byte);
}
static void console_tx_hex8(unsigned char value)
{
console_tx_nibble((value >> 4U) & 0x0fU);
console_tx_nibble(value & 0x0fU);
}
static void console_tx_hex16(unsigned short value)
{
console_tx_nibble((value >> 12U) & 0x0FU);
console_tx_nibble((value >> 8U) & 0x0FU);
console_tx_nibble((value >> 4U) & 0x0FU);
console_tx_nibble(value & 0x0FU);
}
static void console_tx_hex32(unsigned short value)
{
console_tx_nibble((value >> 28U) & 0x0FU);
console_tx_nibble((value >> 24U) & 0x0FU);
console_tx_nibble((value >> 20U) & 0x0FU);
console_tx_nibble((value >> 16U) & 0x0FU);
console_tx_nibble((value >> 12U) & 0x0FU);
console_tx_nibble((value >> 8U) & 0x0FU);
console_tx_nibble((value >> 4U) & 0x0FU);
console_tx_nibble(value & 0x0FU);
}
static void console_tx_string(const char *str)
{
unsigned char ch;
while((ch = *str++) != '\0') {
console_tx_byte(ch);
}
}
static void print_debug_char(unsigned char byte) { console_tx_char(byte); }
static void print_debug_hex8(unsigned char value) { console_tx_hex8(value); }
static void print_debug_hex16(unsigned short value){ console_tx_hex16(value); }
static void print_debug_hex32(unsigned int value) { console_tx_hex32(value); }
static void print_debug(const char *str) { console_tx_string(str); }
static void goto_test(void)
{
int i;
print_debug("goto_test\n");
i = 0;
goto bottom;
{
top:
print_debug("i = ");
print_debug_hex8(i);
print_debug("\n");
i = i + 1;
}
bottom:
if (i < 10) {
goto top;
}
}
static void main(void)
{
goto_test();
_exit(0);
}

463
util/romcc/tests/simple_test39.c
View File

@ -1,463 +0,0 @@
struct syscall_result {
long val;
int errno;
};
static struct syscall_result syscall_return(long result)
{
struct syscall_result res;
if (((unsigned long)result) >= ((unsigned long)-125)) {
res.errno = - result;
res.val = -1;
} else {
res.errno = 0;
res.val = result;
}
return res;
}
static struct syscall_result syscall0(unsigned long nr)
{
long res;
asm volatile(
"int $0x80"
: "=a" (res)
: "a" (nr));
return syscall_return(res);
}
static struct syscall_result syscall1(unsigned long nr, unsigned long arg1)
{
long res;
asm volatile(
"int $0x80"
: "=a" (res)
: "a" (nr), "b" (arg1));
return syscall_return(res);
}
static struct syscall_result syscall2(unsigned long nr, unsigned long arg1, unsigned long arg2)
{
long res;
asm volatile(
"int $0x80"
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2));
return syscall_return(res);
}
static struct syscall_result syscall3(unsigned long nr, unsigned long arg1, unsigned long arg2,
unsigned long arg3)
{
long res;
asm volatile(
"int $0x80"
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3));
return syscall_return(res);
}
static struct syscall_result syscall4(unsigned long nr, unsigned long arg1, unsigned long arg2,
unsigned long arg3, unsigned long arg4)
{
long res;
asm volatile(
"int $0x80"
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), "S" (arg4));
return syscall_return(res);
}
static struct syscall_result syscall5(unsigned long nr, unsigned long arg1, unsigned long arg2,
unsigned long arg3, unsigned long arg4, unsigned long arg5)
{
long res;
asm volatile(
"int $0x80"
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3),
"S" (arg4), "D" (arg5));
return syscall_return(res);
}
#define NR_exit 1
#define NR_fork 2
#define NR_read 3
#define NR_write 4
#define NR_open 5
#define NR_close 6
#define NR_waitpid 7
#define NR_creat 8
#define NR_link 9
#define NR_unlink 10
#define NR_execve 11
#define NR_chdir 12
#define NR_time 13
#define NR_mknod 14
#define NR_chmod 15
#define NR_lchown 16
#define NR_break 17
#define NR_oldstat 18
#define NR_lseek 19
#define NR_getpid 20
#define NR_mount 21
#define NR_umount 22
#define NR_setuid 23
#define NR_getuid 24
#define NR_stime 25
#define NR_ptrace 26
#define NR_alarm 27
#define NR_oldfstat 28
#define NR_pause 29
#define NR_utime 30
#define NR_stty 31
#define NR_gtty 32
#define NR_access 33
#define NR_nice 34
#define NR_ftime 35
#define NR_sync 36
#define NR_kill 37
#define NR_rename 38
#define NR_mkdir 39
#define NR_rmdir 40
#define NR_dup 41
#define NR_pipe 42
#define NR_times 43
#define NR_prof 44
#define NR_brk 45
#define NR_setgid 46
#define NR_getgid 47
#define NR_signal 48
#define NR_geteuid 49
#define NR_getegid 50
#define NR_acct 51
#define NR_umount2 52
#define NR_lock 53
#define NR_ioctl 54
#define NR_fcntl 55
#define NR_mpx 56
#define NR_setpgid 57
#define NR_ulimit 58
#define NR_oldolduname 59
#define NR_umask 60
#define NR_chroot 61
#define NR_ustat 62
#define NR_dup2 63
#define NR_getppid 64
#define NR_getpgrp 65
#define NR_setsid 66
#define NR_sigaction 67
#define NR_sgetmask 68
#define NR_ssetmask 69
#define NR_setreuid 70
#define NR_setregid 71
#define NR_sigsuspend 72
#define NR_sigpending 73
#define NR_sethostname 74
#define NR_setrlimit 75
#define NR_getrlimit 76
#define NR_getrusage 77
#define NR_gettimeofday 78
#define NR_settimeofday 79
#define NR_getgroups 80
#define NR_setgroups 81
#define NR_select 82
#define NR_symlink 83
#define NR_oldlstat 84
#define NR_readlink 85
#define NR_uselib 86
#define NR_swapon 87
#define NR_reboot 88
#define NR_readdir 89
#define NR_mmap 90
#define NR_munmap 91
#define NR_truncate 92
#define NR_ftruncate 93
#define NR_fchmod 94
#define NR_fchown 95
#define NR_getpriority 96
#define NR_setpriority 97
#define NR_profil 98
#define NR_statfs 99
#define NR_fstatfs 100
#define NR_ioperm 101
#define NR_socketcall 102
#define NR_syslog 103
#define NR_setitimer 104
#define NR_getitimer 105
#define NR_stat 106
#define NR_lstat 107
#define NR_fstat 108
#define NR_olduname 109
#define NR_iopl 110
#define NR_vhangup 111
#define NR_idle 112
#define NR_vm86old 113
#define NR_wait4 114
#define NR_swapoff 115
#define NR_sysinfo 116
#define NR_ipc 117
#define NR_fsync 118
#define NR_sigreturn 119
#define NR_clone 120
#define NR_setdomainname 121
#define NR_uname 122
#define NR_modify_ldt 123
#define NR_adjtimex 124
#define NR_mprotect 125
#define NR_sigprocmask 126
#define NR_create_module 127
#define NR_init_module 128
#define NR_delete_module 129
#define NR_get_kernel_syms 130
#define NR_quotactl 131
#define NR_getpgid 132
#define NR_fchdir 133
#define NR_bdflush 134
#define NR_sysfs 135
#define NR_personality 136
#define NR_afs_syscall 137 /* Syscall for Andrew File System */
#define NR_setfsuid 138
#define NR_setfsgid 139
#define NR__llseek 140
#define NR_getdents 141
#define NR__newselect 142
#define NR_flock 143
#define NR_msync 144
#define NR_readv 145
#define NR_writev 146
#define NR_getsid 147
#define NR_fdatasync 148
#define NR__sysctl 149
#define NR_mlock 150
#define NR_munlock 151
#define NR_mlockall 152
#define NR_munlockall 153
#define NR_sched_setparam 154
#define NR_sched_getparam 155
#define NR_sched_setscheduler 156
#define NR_sched_getscheduler 157
#define NR_sched_yield 158
#define NR_sched_get_priority_max 159
#define NR_sched_get_priority_min 160
#define NR_sched_rr_get_interval 161
#define NR_nanosleep 162
#define NR_mremap 163
#define NR_setresuid 164
#define NR_getresuid 165
#define NR_vm86 166
#define NR_query_module 167
#define NR_poll 168
#define NR_nfsservctl 169
#define NR_setresgid 170
#define NR_getresgid 171
#define NR_prctl 172
#define NR_rt_sigreturn 173
#define NR_rt_sigaction 174
#define NR_rt_sigprocmask 175
#define NR_rt_sigpending 176
#define NR_rt_sigtimedwait 177
#define NR_rt_sigqueueinfo 178
#define NR_rt_sigsuspend 179
#define NR_pread 180
#define NR_pwrite 181
#define NR_chown 182
#define NR_getcwd 183
#define NR_capget 184
#define NR_capset 185
#define NR_sigaltstack 186
#define NR_sendfile 187
#define NR_getpmsg 188 /* some people actually want streams */
#define NR_putpmsg 189 /* some people actually want streams */
#define NR_vfork 190
typedef long ssize_t;
typedef unsigned long size_t;
/* Standard file descriptors */
#define STDIN_FILENO 0 /* Standard input */
#define STDOUT_FILENO 1 /* Standard output */
#define STDERR_FILENO 2 /* Standard error output */
static ssize_t write(int fd, const void *buf, size_t count)
{
struct syscall_result res;
res = syscall3(NR_write, fd, (unsigned long)buf, count);
return res.val;
}
static void _exit(int status)
{
struct syscall_result res;
res = syscall1(NR_exit, status);
}
static const char *addr_of_char(unsigned char ch)
{
static const char byte[] = {
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f,
0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f,
0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97,
0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f,
0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,
0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf,
0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7,
0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf,
0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf,
0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7,
0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf,
0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7,
0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef,
0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7,
0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff,
};
return byte + ch;
}
static void console_tx_byte(unsigned char ch)
{
write(STDOUT_FILENO, addr_of_char(ch), 1);
}
static void console_tx_nibble(unsigned nibble)
{
unsigned char digit;
digit = nibble + '0';
if (digit > '9') {
digit += 39;
}
console_tx_byte(digit);
}
static void console_tx_char(unsigned char byte)
{
console_tx_byte(byte);
}
static void console_tx_hex8(unsigned char value)
{
console_tx_nibble((value >> 4U) & 0x0fU);
console_tx_nibble(value & 0x0fU);
}
static void console_tx_hex16(unsigned short value)
{
console_tx_nibble((value >> 12U) & 0x0FU);
console_tx_nibble((value >> 8U) & 0x0FU);
console_tx_nibble((value >> 4U) & 0x0FU);
console_tx_nibble(value & 0x0FU);
}
static void console_tx_hex32(unsigned short value)
{
console_tx_nibble((value >> 28U) & 0x0FU);
console_tx_nibble((value >> 24U) & 0x0FU);
console_tx_nibble((value >> 20U) & 0x0FU);
console_tx_nibble((value >> 16U) & 0x0FU);
console_tx_nibble((value >> 12U) & 0x0FU);
console_tx_nibble((value >> 8U) & 0x0FU);
console_tx_nibble((value >> 4U) & 0x0FU);
console_tx_nibble(value & 0x0FU);
}
static void console_tx_string(const char *str)
{
unsigned char ch;
while((ch = *str++) != '\0') {
console_tx_byte(ch);
}
}
static void print_debug_char(unsigned char byte) { console_tx_char(byte); }
static void print_debug_hex8(unsigned char value) { console_tx_hex8(value); }
static void print_debug_hex16(unsigned short value){ console_tx_hex16(value); }
static void print_debug_hex32(unsigned int value) { console_tx_hex32(value); }
static void print_debug(const char *str) { console_tx_string(str); }
static void goto_test(void)
{
int i;
print_debug("goto_test\n");
i = 0;
goto bottom;
{
top:
print_debug("i = ");
print_debug_hex8(i);
print_debug("\n");
i = i + 1;
}
bottom:
if (i < 10) {
goto top;
}
}
struct socket_desc {
short up;
short down;
short across;
};
static void main(void)
{
static const struct socket_desc cpu_socketsA[] = {
{ .up = 2, .down = -1, .across = 1 }, /* Node 0 */
{ .up = 3, .down = -1, .across = 0 }, /* Node 1 */
{ .up = -1, .down = 0, .across = 3 }, /* Node 2 */
{ .up = -1, .down = 1, .across = 2 } /* Node 3 */
};
static const struct socket_desc cpu_socketsB[4] = {
{ 2, -1, 1 }, /* Node 0 */
{ 3, -1, 0 }, /* Node 1 */
{ -1, 0, 3 }, /* Node 2 */
{ -1, 1, 2 } /* Node 3 */
};
int i;
print_debug("cpu_socketA\n");
for(i = 0; i < sizeof(cpu_socketsA)/sizeof(cpu_socketsA[0]); i++) {
print_debug(".up=");
print_debug_hex16(cpu_socketsA[i].up);
print_debug(" .down=");
print_debug_hex16(cpu_socketsA[i].down);
print_debug(" .across=");
print_debug_hex16(cpu_socketsA[i].across);
print_debug("\n");
}
print_debug("\ncpu_socketB\n");
for(i = 0; i < sizeof(cpu_socketsB)/sizeof(cpu_socketsB[0]); i++) {
print_debug(".up=");
print_debug_hex16(cpu_socketsB[i].up);
print_debug(" .down=");
print_debug_hex16(cpu_socketsB[i].down);
print_debug(" .across=");
print_debug_hex16(cpu_socketsB[i].across);
print_debug("\n");
}
_exit(0);
}

509
util/romcc/tests/simple_test4.c
View File

@ -1,509 +0,0 @@
#define HAVE_STRING_SUPPORT 1
#define HAVE_CAST_SUPPORT 1
#define HAVE_STATIC_ARRAY_SUPPORT 1
#define HAVE_POINTER_SUPPORT 1
#define HAVE_CONSTANT_PROPOGATION 0
#define CALCULATE_DRB_REG 1
void outb(unsigned char value, unsigned short port)
{
__builtin_outb(value, port);
}
void outw(unsigned short value, unsigned short port)
{
__builtin_outw(value, port);
}
void outl(unsigned int value, unsigned short port)
{
__builtin_outl(value, port);
}
unsigned char inb(unsigned short port)
{
return __builtin_inb(port);
}
unsigned char inw(unsigned short port)
{
return __builtin_inw(port);
}
unsigned char inl(unsigned short port)
{
return __builtin_inl(port);
}
static unsigned int config_cmd(unsigned char bus, unsigned devfn, unsigned where)
{
return 0x80000000 | (bus << 16) | (devfn << 8) | (where & ~3);
}
static unsigned char pcibios_read_config_byte(
unsigned char bus, unsigned devfn, unsigned where)
{
outl(config_cmd(bus, devfn, where), 0xCF8);
return inb(0xCFC + (where & 3));
}
static unsigned short pcibios_read_config_word(
unsigned char bus, unsigned devfn, unsigned where)
{
outl(config_cmd(bus, devfn, where), 0xCF8);
return inw(0xCFC + (where & 2));
}
static unsigned int pcibios_read_config_dword(
unsigned char bus, unsigned devfn, unsigned where)
{
outl(config_cmd(bus, devfn, where), 0xCF8);
return inl(0xCFC);
}
static void pcibios_write_config_byte(
unsigned char bus, unsigned devfn, unsigned where, unsigned char value)
{
outl(config_cmd(bus, devfn, where), 0xCF8);
outb(value, 0xCFC + (where & 3));
}
static void pcibios_write_config_word(
unsigned char bus, unsigned devfn, unsigned where, unsigned short value)
{
outl(config_cmd(bus, devfn, where), 0xCF8);
outw(value, 0xCFC + (where & 2));
}
static void pcibios_write_config_dword(
unsigned char bus, unsigned devfn, unsigned where, unsigned int value)
{
outl(config_cmd(bus, devfn, where), 0xCF8);
outl(value, 0xCFC);
}
int log2(int value)
{
/* __builtin_bsr is a exactly equivalent to the x86 machine
* instruction with the exception that it returns -1
* when the value presented to it is zero.
* Otherwise __builtin_bsr returns the zero based index of
* the highest bit set.
*/
return __builtin_bsr(value);
}
/* Base Address */
#ifndef CONFIG_TTYS0_BASE
#define CONFIG_TTYS0_BASE 0x3f8
#endif
#ifndef CONFIG_TTYS0_BAUD
#define CONFIG_TTYS0_BAUD 115200
#endif
#if ((115200%CONFIG_TTYS0_BAUD) != 0)
#error Bad ttys0 baud rate
#endif
#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD)
/* Line Control Settings */
#ifndef CONFIG_TTYS0_LCS
/* Set 8bit, 1 stop bit, no parity */
#define CONFIG_TTYS0_LCS 0x3
#endif
#define UART_LCS CONFIG_TTYS0_LCS
/* Data */
#define UART_RBR 0x00
#define UART_TBR 0x00
/* Control */
#define UART_IER 0x01
#define UART_IIR 0x02
#define UART_FCR 0x02
#define UART_LCR 0x03
#define UART_MCR 0x04
#define UART_DLL 0x00
#define UART_DLM 0x01
/* Status */
#define UART_LSR 0x05
#define UART_MSR 0x06
#define UART_SCR 0x07
int uart_can_tx_byte(void)
{
return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20;
}
void uart_wait_to_tx_byte(void)
{
while(!uart_can_tx_byte())
;
}
void uart_wait_until_sent(void)
{
while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40))
;
}
void uart_tx_byte(unsigned char data)
{
uart_wait_to_tx_byte();
outb(data, CONFIG_TTYS0_BASE + UART_TBR);
/* Make certain the data clears the fifos */
uart_wait_until_sent();
}
void uart_init(void)
{
/* disable interrupts */
outb(0x0, CONFIG_TTYS0_BASE + UART_IER);
/* enable fifo's */
outb(0x01, CONFIG_TTYS0_BASE + UART_FCR);
/* Set Baud Rate Divisor to 12 ==> 115200 Baud */
outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR);
outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL);
outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM);
outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR);
}
void __console_tx_char(unsigned char byte)
{
uart_tx_byte(byte);
}
void __console_tx_nibble(unsigned nibble)
{
unsigned char digit;
digit = nibble + '0';
if (digit > '9') {
digit += 39;
}
__console_tx_char(digit);
}
void __console_tx_hex8(unsigned char byte)
{
__console_tx_nibble(byte >> 4);
__console_tx_nibble(byte & 0x0f);
}
void __console_tx_hex32(unsigned char value)
{
__console_tx_nibble((value >> 28) & 0x0f);
__console_tx_nibble((value >> 24) & 0x0f);
__console_tx_nibble((value >> 20) & 0x0f);
__console_tx_nibble((value >> 16) & 0x0f);
__console_tx_nibble((value >> 12) & 0x0f);
__console_tx_nibble((value >> 8) & 0x0f);
__console_tx_nibble((value >> 4) & 0x0f);
__console_tx_nibble(value & 0x0f);
}
#if HAVE_STRING_SUPPORT
void __console_tx_string(char *str)
{
unsigned char ch;
while((ch = *str++) != '\0') {
__console_tx_char(ch);
}
}
#else
void __console_tx_string(char *str)
{
}
#endif
void print_emerg_char(unsigned char byte) { __console_tx_char(byte); }
void print_emerg_hex8(unsigned char value) { __console_tx_hex8(value); }
void print_emerg_hex32(unsigned int value) { __console_tx_hex32(value); }
void print_emerg(char *str) { __console_tx_string(str); }
void print_alert_char(unsigned char byte) { __console_tx_char(byte); }
void print_alert_hex8(unsigned char value) { __console_tx_hex8(value); }
void print_alert_hex32(unsigned int value) { __console_tx_hex32(value); }
void print_alert(char *str) { __console_tx_string(str); }
void print_crit_char(unsigned char byte) { __console_tx_char(byte); }
void print_crit_hex8(unsigned char value) { __console_tx_hex8(value); }
void print_crit_hex32(unsigned int value) { __console_tx_hex32(value); }
void print_crit(char *str) { __console_tx_string(str); }
void print_err_char(unsigned char byte) { __console_tx_char(byte); }
void print_err_hex8(unsigned char value) { __console_tx_hex8(value); }
void print_err_hex32(unsigned int value) { __console_tx_hex32(value); }
void print_err(char *str) { __console_tx_string(str); }
void print_warning_char(unsigned char byte) { __console_tx_char(byte); }
void print_warning_hex8(unsigned char value) { __console_tx_hex8(value); }
void print_warning_hex32(unsigned int value) { __console_tx_hex32(value); }
void print_warning(char *str) { __console_tx_string(str); }
void print_notice_char(unsigned char byte) { __console_tx_char(byte); }
void print_notice_hex8(unsigned char value) { __console_tx_hex8(value); }
void print_notice_hex32(unsigned int value) { __console_tx_hex32(value); }
void print_notice(char *str) { __console_tx_string(str); }
void print_info_char(unsigned char byte) { __console_tx_char(byte); }
void print_info_hex8(unsigned char value) { __console_tx_hex8(value); }
void print_info_hex32(unsigned int value) { __console_tx_hex32(value); }
void print_info(char *str) { __console_tx_string(str); }
void print_debug_char(unsigned char byte) { __console_tx_char(byte); }
void print_debug_hex8(unsigned char value) { __console_tx_hex8(value); }
void print_debug_hex32(unsigned int value) { __console_tx_hex32(value); }
void print_debug(char *str) { __console_tx_string(str); }
void print_spew_char(unsigned char byte) { __console_tx_char(byte); }
void print_spew_hex8(unsigned char value) { __console_tx_hex8(value); }
void print_spew_hex32(unsigned int value) { __console_tx_hex32(value); }
void print_spew(char *str) { __console_tx_string(str); }
#define PIIX4_DEVFN 0x90
#define SMBUS_MEM_DEVICE_START 0x50
#define SMBUS_MEM_DEVICE_END 0x53
#define SMBUS_MEM_DEVICE_INC 1
#define PM_BUS 0
#define PM_DEVFN (PIIX4_DEVFN+3)
#if HAVE_CONSTANT_PROPOGATION
#define SMBUS_IO_BASE 0x1000
#define SMBHSTSTAT 0
#define SMBHSTCTL 2
#define SMBHSTCMD 3
#define SMBHSTADD 4
#define SMBHSTDAT0 5
#define SMBHSTDAT1 6
#define SMBBLKDAT 7
static void smbus_wait_until_ready(void)
{
while((inb(SMBUS_IO_BASE + SMBHSTSTAT) & 1) == 1) {
/* nop */
}
}
static void smbus_wait_until_done(void)
{
unsigned char byte;
do {
byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
}while((byte &1) == 1);
while( (byte & ~1) == 0) {
byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
}
}
int smbus_read_byte(unsigned device, unsigned address)
{
unsigned char host_status_register;
unsigned char byte;
int result;
smbus_wait_until_ready();
/* setup transaction */
/* disable interrupts */
outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL);
/* set the device I'm talking to */
outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBHSTADD);
/* set the command/address... */
outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
/* set up for a byte data read */
outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2), SMBUS_IO_BASE + SMBHSTCTL);
/* clear any lingering errors, so the transaction will run */
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
/* clear the data byte...*/
outb(0, SMBUS_IO_BASE + SMBHSTDAT0);
/* start the command */
outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL);
/* poll for transaction completion */
smbus_wait_until_done();
host_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT);
/* read results of transaction */
byte = inb(SMBUS_IO_BASE + SMBHSTDAT0);
result = byte;
if (host_status_register != 0x02) {
result = -1;
}
return result;
}
#else /* !HAVE_CONSTANT_PROPOGATION */
#define SMBUS_IO_HSTSTAT 0x1000
#define SMBUS_IO_HSTCTL 0x1002
#define SMBUS_IO_HSTCMD 0x1003
#define SMBUS_IO_HSTADD 0x1004
#define SMBUS_IO_HSTDAT0 0x1005
#define SMBUS_IO_HSTDAT1 0x1006
#define SMBUS_IO_HSTBLKDAT 0x1007
static void smbus_wait_until_ready(void)
{
while((inb(SMBUS_IO_HSTSTAT) & 1) == 1) {
/* nop */
}
}
static void smbus_wait_until_done(void)
{
unsigned char byte;
do {
byte = inb(SMBUS_IO_HSTSTAT);
}while((byte &1) == 1);
while( (byte & ~1) == 0) {
byte = inb(SMBUS_IO_HSTSTAT);
}
}
short smbus_read_byte(unsigned char device, unsigned char address)
{
unsigned char host_status_register;
short result;
smbus_wait_until_ready();
/* setup transaction */
/* disable interrupts */
outb(inb(SMBUS_IO_HSTCTL) & (~1), SMBUS_IO_HSTCTL);
/* set the device I'm talking to */
outb(((device & 0x7f) << 1) | 1, SMBUS_IO_HSTADD);
/* set the command/address... */
outb(address & 0xFF, SMBUS_IO_HSTCMD);
/* set up for a byte data read */
outb((inb(SMBUS_IO_HSTCTL) & 0xE3) | 8, SMBUS_IO_HSTCTL);
/* clear any lingering errors, so the transaction will run */
outb(inb(SMBUS_IO_HSTSTAT), SMBUS_IO_HSTSTAT);
/* clear the data byte...*/
outb(0, SMBUS_IO_HSTDAT0);
/* start the command */
outb((inb(SMBUS_IO_HSTCTL) | 0x40), SMBUS_IO_HSTCTL);
/* poll for transaction completion */
smbus_wait_until_done();
host_status_register = inb(SMBUS_IO_HSTSTAT);
/* read results of transaction */
result = inb(SMBUS_IO_HSTDAT0);
if (host_status_register != 0x02) {
result = -1;
}
return result;
}
#endif /* HAVE_CONSTANT_PROPOGATION */
#define I440GX_BUS 0
#define I440GX_DEVFN ((0x00 << 3) + 0)
static void spd_set_drb(void)
{
/*
* Effects: Uses serial presence detect to set the
* DRB registers which holds the ending memory address assigned
* to each DIMM.
*/
unsigned end_of_memory;
unsigned char device;
unsigned char drb_reg;
end_of_memory = 0; /* in multiples of 8MiB */
device = SMBUS_MEM_DEVICE_START;
#if !CALCULATE_DRB_REG
drb_reg = 0x60;
#endif
while (device <= SMBUS_MEM_DEVICE_END) {
unsigned side1_bits, side2_bits;
int byte, byte2;
side1_bits = side2_bits = -1;
/* rows */
byte = smbus_read_byte(device, 3);
if (byte >= 0) {
side1_bits += byte & 0xf;
/* columns */
byte = smbus_read_byte(device, 4);
side1_bits += byte & 0xf;
/* banks */
byte = smbus_read_byte(device, 17);
side1_bits += log2(byte);
/* Get the module data width and convert it to a power of two */
/* low byte */
byte = smbus_read_byte(device, 6);
/* high byte */
byte2 = smbus_read_byte(device, 7);
#if HAVE_CAST_SUPPORT
side1_bits += log2((((unsigned long)byte2 << 8)| byte));
#else
side1_bits += log2((((byte2 << 8) | byte));
#endif
/* now I have the ram size in bits as a power of two (less 1) */
/* Make it mulitples of 8MB */
side1_bits -= 25;
/* side two */
/* number of physical banks */
byte = smbus_read_byte(device, 5);
if (byte > 1) {
/* for now only handle the symmetrical case */
side2_bits = side1_bits;
}
}
/* Compute the end address for the DRB register */
/* Only process dimms < 2GB (2^8 * 8MB) */
if (side1_bits < 8) {
end_of_memory += (1 << side1_bits);
}
#if CALCULATE_DRB_REG
drb_reg = ((device - SMBUS_MEM_DEVICE_START) << 1) + 0x60;
#endif
#if HAVE_STRING_SUPPORT
print_debug("end_of_memory: "); print_debug_hex32(end_of_memory); print_debug("\n");
#endif
pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, drb_reg, end_of_memory);
if (side2_bits < 8 ) {
end_of_memory += (1 << side2_bits);
}
#if HAVE_STRING_SUPPORT
print_debug("end_of_memory: "); print_debug_hex32(end_of_memory); print_debug("\n");
#endif
pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, drb_reg +1, end_of_memory);
#if !CALCULATE_DRB_REG
drb_reg += 2;
#endif
device += SMBUS_MEM_DEVICE_INC;
}
}

6
util/romcc/tests/simple_test40.c
View File

@ -1,6 +0,0 @@
static void main(void)
{
int i = 1;
return;
i++;
}

14
util/romcc/tests/simple_test41.c
View File

@ -1,14 +0,0 @@
static void main(void)
{
unsigned long a,b,c, d;
volatile unsigned long *val = (volatile unsigned long *)0x1234;
a = val[0];
b = val[1];
c = a*b;
val[2] = c;
d = val[3];
a = c / d;
b = c % d;
val[4] = a;
val[5] = b;
}

47
util/romcc/tests/simple_test43.c
View File

@ -1,47 +0,0 @@
static void spd_set_memclk(void)
{
unsigned min;
unsigned device;
min = 0x250;
for(device = 0x80; device <= 0x81; device += 1)
{
unsigned cur;
int latency;
unsigned long loops;
cur = 5 | 0xa0;
latency = __builtin_inw(0xab);
if (latency > 0x250) {
loops = 1000000;
while(--loops)
;
if (!loops) {
goto end;
}
loops = 1000000;
while(--loops)
;
end:
;
}
loops = 1000000;
while(--loops)
;
if (latency > 0x250) {
;
}
if (cur > 0x250) {
}
}
}

41
util/romcc/tests/simple_test45.c
View File

@ -1,41 +0,0 @@
static void spd_set_memclk(void)
{
unsigned min_cycle_time;
unsigned device;
int new_cycle_time, new_latency;
int index;
int latency;
min_cycle_time = 0x50;
device = 0x50;
new_cycle_time = 0xa0;
new_latency = 5;
latency = 0;
for(index = 0; index < 3; index++, latency++) {
unsigned long loops;
loops = 1000000;
do {
unsigned short val;
val = __builtin_inw(0x10e0);
} while(--loops);
if (!loops) {
continue;
}
__builtin_outb(device, 0xe4);
__builtin_outb(index, 0xe8);
loops = 1000000;
while(--loops)
;
}
if (new_latency > 4){
return;
}
if (new_cycle_time > min_cycle_time) {
min_cycle_time = new_cycle_time;
}
}

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