soc/intel/cannonlake: Add debugging of a number of FSPM parameters
This implements soc_display_fspm_upd_params for soc/intel/cannonlake Some parameters are available only on Coffee Lake FSP or Comet Lake FSP Tested on System76 galp3-c (Coffee Lake FSP) and System76 galp4 (Comet Lake FSP)
This commit is contained in:
Jeremy Soller
parent
d4e111ff97
commit
954d813a61
@ -141,3 +141,316 @@ void mainboard_romstage_entry(void)
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if (!s3wake)
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save_dimm_info();
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}
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void soc_display_fspm_upd_params(const FSPM_UPD *fspm_old_upd,
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const FSPM_UPD *fspm_new_upd)
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{
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const FSP_M_CONFIG *new;
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const FSP_M_CONFIG *old;
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old = &fspm_old_upd->FspmConfig;
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new = &fspm_new_upd->FspmConfig;
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/* Display the parameters for MemoryInit */
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printk(BIOS_SPEW, "UPD values for MemoryInit:\n");
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//TODO: Add more Comet Lake values
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fsp_display_upd_value("PlatformMemorySize", 8,
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old->PlatformMemorySize, new->PlatformMemorySize);
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fsp_display_upd_value("MemorySpdPtr00", 4, old->MemorySpdPtr00,
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new->MemorySpdPtr00);
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fsp_display_upd_value("MemorySpdPtr01", 4, old->MemorySpdPtr01,
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new->MemorySpdPtr01);
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fsp_display_upd_value("MemorySpdPtr10", 4, old->MemorySpdPtr10,
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new->MemorySpdPtr10);
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fsp_display_upd_value("MemorySpdPtr11", 4, old->MemorySpdPtr11,
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new->MemorySpdPtr11);
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fsp_display_upd_value("MemorySpdDataLen", 2, old->MemorySpdDataLen,
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new->MemorySpdDataLen);
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fsp_display_upd_value("DqByteMapCh0[0]", 1, old->DqByteMapCh0[0],
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new->DqByteMapCh0[0]);
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fsp_display_upd_value("DqByteMapCh0[1]", 1, old->DqByteMapCh0[1],
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new->DqByteMapCh0[1]);
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fsp_display_upd_value("DqByteMapCh0[2]", 1, old->DqByteMapCh0[2],
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new->DqByteMapCh0[2]);
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fsp_display_upd_value("DqByteMapCh0[3]", 1, old->DqByteMapCh0[3],
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new->DqByteMapCh0[3]);
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fsp_display_upd_value("DqByteMapCh0[4]", 1, old->DqByteMapCh0[4],
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new->DqByteMapCh0[4]);
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fsp_display_upd_value("DqByteMapCh0[5]", 1, old->DqByteMapCh0[5],
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new->DqByteMapCh0[5]);
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fsp_display_upd_value("DqByteMapCh0[6]", 1, old->DqByteMapCh0[6],
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new->DqByteMapCh0[6]);
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fsp_display_upd_value("DqByteMapCh0[7]", 1, old->DqByteMapCh0[7],
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new->DqByteMapCh0[7]);
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fsp_display_upd_value("DqByteMapCh0[8]", 1, old->DqByteMapCh0[8],
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new->DqByteMapCh0[8]);
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fsp_display_upd_value("DqByteMapCh0[9]", 1, old->DqByteMapCh0[9],
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new->DqByteMapCh0[9]);
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fsp_display_upd_value("DqByteMapCh0[10]", 1, old->DqByteMapCh0[10],
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new->DqByteMapCh0[10]);
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fsp_display_upd_value("DqByteMapCh0[11]", 1, old->DqByteMapCh0[11],
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new->DqByteMapCh0[11]);
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fsp_display_upd_value("DqByteMapCh1[0]", 1, old->DqByteMapCh1[0],
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new->DqByteMapCh1[0]);
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fsp_display_upd_value("DqByteMapCh1[1]", 1, old->DqByteMapCh1[1],
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new->DqByteMapCh1[1]);
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fsp_display_upd_value("DqByteMapCh1[2]", 1, old->DqByteMapCh1[2],
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new->DqByteMapCh1[2]);
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fsp_display_upd_value("DqByteMapCh1[3]", 1, old->DqByteMapCh1[3],
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new->DqByteMapCh1[3]);
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fsp_display_upd_value("DqByteMapCh1[4]", 1, old->DqByteMapCh1[4],
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new->DqByteMapCh1[4]);
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fsp_display_upd_value("DqByteMapCh1[5]", 1, old->DqByteMapCh1[5],
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new->DqByteMapCh1[5]);
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fsp_display_upd_value("DqByteMapCh1[6]", 1, old->DqByteMapCh1[6],
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new->DqByteMapCh1[6]);
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fsp_display_upd_value("DqByteMapCh1[7]", 1, old->DqByteMapCh1[7],
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new->DqByteMapCh1[7]);
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fsp_display_upd_value("DqByteMapCh1[8]", 1, old->DqByteMapCh1[8],
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new->DqByteMapCh1[8]);
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fsp_display_upd_value("DqByteMapCh1[9]", 1, old->DqByteMapCh1[9],
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new->DqByteMapCh1[9]);
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fsp_display_upd_value("DqByteMapCh1[10]", 1, old->DqByteMapCh1[10],
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new->DqByteMapCh1[10]);
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fsp_display_upd_value("DqByteMapCh1[11]", 1, old->DqByteMapCh1[11],
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new->DqByteMapCh1[11]);
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fsp_display_upd_value("DqsMapCpu2DramCh0[0]", 1,
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old->DqsMapCpu2DramCh0[0], new->DqsMapCpu2DramCh0[0]);
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fsp_display_upd_value("DqsMapCpu2DramCh0[1]", 1,
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old->DqsMapCpu2DramCh0[1], new->DqsMapCpu2DramCh0[1]);
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fsp_display_upd_value("DqsMapCpu2DramCh0[2]", 1,
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old->DqsMapCpu2DramCh0[2], new->DqsMapCpu2DramCh0[2]);
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fsp_display_upd_value("DqsMapCpu2DramCh0[3]", 1,
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old->DqsMapCpu2DramCh0[3], new->DqsMapCpu2DramCh0[3]);
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fsp_display_upd_value("DqsMapCpu2DramCh0[4]", 1,
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old->DqsMapCpu2DramCh0[4], new->DqsMapCpu2DramCh0[4]);
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fsp_display_upd_value("DqsMapCpu2DramCh0[5]", 1,
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old->DqsMapCpu2DramCh0[5], new->DqsMapCpu2DramCh0[5]);
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fsp_display_upd_value("DqsMapCpu2DramCh0[6]", 1,
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old->DqsMapCpu2DramCh0[6], new->DqsMapCpu2DramCh0[6]);
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fsp_display_upd_value("DqsMapCpu2DramCh0[7]", 1,
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old->DqsMapCpu2DramCh0[7], new->DqsMapCpu2DramCh0[7]);
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fsp_display_upd_value("DqsMapCpu2DramCh1[0]", 1,
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old->DqsMapCpu2DramCh1[0], new->DqsMapCpu2DramCh1[0]);
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fsp_display_upd_value("DqsMapCpu2DramCh1[1]", 1,
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old->DqsMapCpu2DramCh1[1], new->DqsMapCpu2DramCh1[1]);
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fsp_display_upd_value("DqsMapCpu2DramCh1[2]", 1,
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old->DqsMapCpu2DramCh1[2], new->DqsMapCpu2DramCh1[2]);
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fsp_display_upd_value("DqsMapCpu2DramCh1[3]", 1,
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old->DqsMapCpu2DramCh1[3], new->DqsMapCpu2DramCh1[3]);
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fsp_display_upd_value("DqsMapCpu2DramCh1[4]", 1,
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old->DqsMapCpu2DramCh1[4], new->DqsMapCpu2DramCh1[4]);
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fsp_display_upd_value("DqsMapCpu2DramCh1[5]", 1,
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old->DqsMapCpu2DramCh1[5], new->DqsMapCpu2DramCh1[5]);
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fsp_display_upd_value("DqsMapCpu2DramCh1[6]", 1,
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old->DqsMapCpu2DramCh1[6], new->DqsMapCpu2DramCh1[6]);
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fsp_display_upd_value("DqsMapCpu2DramCh1[7]", 1,
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old->DqsMapCpu2DramCh1[7], new->DqsMapCpu2DramCh1[7]);
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fsp_display_upd_value("RcompResistor[0]", 2, old->RcompResistor[0],
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new->RcompResistor[0]);
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fsp_display_upd_value("RcompResistor[1]", 2, old->RcompResistor[1],
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new->RcompResistor[1]);
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fsp_display_upd_value("RcompResistor[2]", 2, old->RcompResistor[2],
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new->RcompResistor[2]);
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fsp_display_upd_value("RcompTarget[0]", 2, old->RcompTarget[0],
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new->RcompTarget[0]);
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fsp_display_upd_value("RcompTarget[1]", 2, old->RcompTarget[1],
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new->RcompTarget[1]);
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fsp_display_upd_value("RcompTarget[2]", 2, old->RcompTarget[2],
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new->RcompTarget[2]);
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fsp_display_upd_value("RcompTarget[3]", 2, old->RcompTarget[3],
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new->RcompTarget[3]);
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fsp_display_upd_value("RcompTarget[4]", 2, old->RcompTarget[4],
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new->RcompTarget[4]);
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fsp_display_upd_value("DqPinsInterleaved", 1, old->DqPinsInterleaved,
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new->DqPinsInterleaved);
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fsp_display_upd_value("CaVrefConfig", 1, old->CaVrefConfig,
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new->CaVrefConfig);
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fsp_display_upd_value("SmramMask", 1, old->SmramMask, new->SmramMask);
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#if CONFIG(SOC_INTEL_COMETLAKE)
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// Value only exists on Comet Lake
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fsp_display_upd_value("MrcTimeMeasure", 1, old->MrcTimeMeasure,
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new->MrcTimeMeasure);
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#endif
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fsp_display_upd_value("MrcFastBoot", 1, old->MrcFastBoot,
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new->MrcFastBoot);
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fsp_display_upd_value("RmtPerTask", 1, old->RmtPerTask,
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new->RmtPerTask);
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fsp_display_upd_value("TrainTrace", 1, old->TrainTrace,
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new->TrainTrace);
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fsp_display_upd_value("IedSize", 4, old->IedSize, new->IedSize);
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fsp_display_upd_value("TsegSize", 4, old->TsegSize, new->TsegSize);
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fsp_display_upd_value("MmioSize", 2, old->MmioSize, new->MmioSize);
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fsp_display_upd_value("ProbelessTrace", 1, old->ProbelessTrace,
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new->ProbelessTrace);
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fsp_display_upd_value("GdxcIotSize", 1, old->GdxcIotSize,
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new->GdxcIotSize);
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fsp_display_upd_value("GdxcMotSize", 1, old->GdxcMotSize,
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new->GdxcMotSize);
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fsp_display_upd_value("SmbusEnable", 1, old->SmbusEnable,
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new->SmbusEnable);
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fsp_display_upd_value("SpdAddressTable[0]", 1, old->SpdAddressTable[0],
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new->SpdAddressTable[0]);
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fsp_display_upd_value("SpdAddressTable[1]", 1, old->SpdAddressTable[1],
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new->SpdAddressTable[1]);
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fsp_display_upd_value("SpdAddressTable[2]", 1, old->SpdAddressTable[2],
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new->SpdAddressTable[2]);
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fsp_display_upd_value("SpdAddressTable[3]", 1, old->SpdAddressTable[3],
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new->SpdAddressTable[3]);
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fsp_display_upd_value("PlatformDebugConsent", 1,
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old->PlatformDebugConsent, new->PlatformDebugConsent);
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fsp_display_upd_value("DciUsb3TypecUfpDbg", 1, old->DciUsb3TypecUfpDbg,
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new->DciUsb3TypecUfpDbg);
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fsp_display_upd_value("PchTraceHubMode", 1, old->PchTraceHubMode,
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new->PchTraceHubMode);
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fsp_display_upd_value("PchTraceHubMemReg0Size", 1,
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old->PchTraceHubMemReg0Size, new->PchTraceHubMemReg0Size);
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fsp_display_upd_value("PchTraceHubMemReg1Size", 1,
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old->PchTraceHubMemReg1Size, new->PchTraceHubMemReg1Size);
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// Skip PchPreMemRsvd[9]
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fsp_display_upd_value("IgdDvmt50PreAlloc", 1, old->IgdDvmt50PreAlloc,
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new->IgdDvmt50PreAlloc);
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fsp_display_upd_value("InternalGfx", 1, old->InternalGfx,
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new->InternalGfx);
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fsp_display_upd_value("ApertureSize", 1, old->ApertureSize,
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new->ApertureSize);
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fsp_display_upd_value("UserBd", 1, old->UserBd,
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new->UserBd);
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fsp_display_upd_value("SaGv", 1, old->SaGv,
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new->SaGv);
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// Skip UnusedUpdSpace0
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fsp_display_upd_value("DdrFreqLimit", 2, old->DdrFreqLimit,
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new->DdrFreqLimit);
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fsp_display_upd_value("FreqSaGvLow", 2, old->FreqSaGvLow,
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new->FreqSaGvLow);
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#if ! CONFIG(SOC_INTEL_COMETLAKE)
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// Value does not exist on Comet Lake
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fsp_display_upd_value("FreqSaGvMid", 2, old->FreqSaGvMid,
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new->FreqSaGvMid);
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#endif
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fsp_display_upd_value("RMT", 1, old->RMT,
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new->RMT);
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fsp_display_upd_value("DisableDimmChannel0", 1,
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old->DisableDimmChannel0, new->DisableDimmChannel0);
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fsp_display_upd_value("DisableDimmChannel1", 1,
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old->DisableDimmChannel1, new->DisableDimmChannel1);
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fsp_display_upd_value("ScramblerSupport", 1, old->ScramblerSupport,
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new->ScramblerSupport);
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fsp_display_upd_value("SkipMpInit", 1, old->SkipMpInit,
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new->SkipMpInit);
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// Skip UnusedUpdSpace1[15]
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fsp_display_upd_value("SpdProfileSelected", 1,
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old->SpdProfileSelected, new->SpdProfileSelected);
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fsp_display_upd_value("RefClk", 1, old->RefClk,
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new->RefClk);
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fsp_display_upd_value("VddVoltage", 2, old->VddVoltage,
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new->VddVoltage);
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fsp_display_upd_value("Ratio", 1, old->Ratio,
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new->Ratio);
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fsp_display_upd_value("OddRatioMode", 1, old->OddRatioMode,
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new->OddRatioMode);
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fsp_display_upd_value("tCL", 1, old->tCL,
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new->tCL);
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fsp_display_upd_value("tCWL", 1, old->tCWL,
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new->tCWL);
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fsp_display_upd_value("tRCDtRP", 1, old->tRCDtRP,
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new->tRCDtRP);
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fsp_display_upd_value("tRRD", 1, old->tRRD,
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new->tRRD);
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fsp_display_upd_value("tFAW", 2, old->tFAW,
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new->tFAW);
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fsp_display_upd_value("tRAS", 2, old->tRAS,
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new->tRAS);
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fsp_display_upd_value("tREFI", 2, old->tREFI,
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new->tREFI);
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fsp_display_upd_value("tRFC", 2, old->tRFC,
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new->tRFC);
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fsp_display_upd_value("tRTP", 1, old->tRTP,
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new->tRTP);
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fsp_display_upd_value("tWR", 1, old->tWR,
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new->tWR);
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fsp_display_upd_value("NModeSupport", 1, old->NModeSupport,
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new->NModeSupport);
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fsp_display_upd_value("DllBwEn0", 1, old->DllBwEn0,
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new->DllBwEn0);
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fsp_display_upd_value("DllBwEn1", 1, old->DllBwEn1,
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new->DllBwEn1);
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fsp_display_upd_value("DllBwEn2", 1, old->DllBwEn2,
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new->DllBwEn2);
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fsp_display_upd_value("DllBwEn3", 1, old->DllBwEn3,
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new->DllBwEn3);
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fsp_display_upd_value("IsvtIoPort", 1, old->IsvtIoPort,
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new->IsvtIoPort);
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fsp_display_upd_value("CpuTraceHubMode", 1, old->CpuTraceHubMode,
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new->CpuTraceHubMode);
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fsp_display_upd_value("CpuTraceHubMemReg0Size", 1,
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old->CpuTraceHubMemReg0Size, new->CpuTraceHubMemReg0Size);
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fsp_display_upd_value("CpuTraceHubMemReg1Size", 1,
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old->CpuTraceHubMemReg1Size, new->CpuTraceHubMemReg1Size);
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fsp_display_upd_value("PeciC10Reset", 1, old->PeciC10Reset,
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new->PeciC10Reset);
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fsp_display_upd_value("PeciSxReset", 1, old->PeciSxReset,
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new->PeciSxReset);
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// Skip UnusedUpdSpace2[4]
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fsp_display_upd_value("PchHdaEnable", 1, old->PchHdaEnable,
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new->PchHdaEnable);
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fsp_display_upd_value("PchIshEnable", 1, old->PchIshEnable,
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new->PchIshEnable);
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fsp_display_upd_value("HeciTimeouts", 1, old->HeciTimeouts,
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new->HeciTimeouts);
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// Skip UnusedUpdSpace3
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fsp_display_upd_value("Heci1BarAddress", 4, old->Heci1BarAddress,
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new->Heci1BarAddress);
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fsp_display_upd_value("Heci2BarAddress", 4, old->Heci2BarAddress,
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new->Heci2BarAddress);
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fsp_display_upd_value("Heci3BarAddress", 4, old->Heci3BarAddress,
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new->Heci3BarAddress);
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fsp_display_upd_value("SgDelayAfterPwrEn", 2, old->SgDelayAfterPwrEn,
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new->SgDelayAfterPwrEn);
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fsp_display_upd_value("SgDelayAfterHoldReset", 2, old->SgDelayAfterHoldReset,
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new->SgDelayAfterHoldReset);
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fsp_display_upd_value("MmioSizeAdjustment", 2, old->MmioSizeAdjustment,
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new->MmioSizeAdjustment);
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fsp_display_upd_value("DmiGen3ProgramStaticEq", 1,
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old->DmiGen3ProgramStaticEq, new->DmiGen3ProgramStaticEq);
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fsp_display_upd_value("Peg0Enable", 1, old->Peg0Enable,
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new->Peg0Enable);
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fsp_display_upd_value("Peg1Enable", 1, old->Peg1Enable,
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new->Peg1Enable);
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fsp_display_upd_value("Peg2Enable", 1, old->Peg2Enable,
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new->Peg2Enable);
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fsp_display_upd_value("Peg3Enable", 1, old->Peg3Enable,
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new->Peg3Enable);
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fsp_display_upd_value("Peg0MaxLinkSpeed", 1, old->Peg0MaxLinkSpeed,
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new->Peg0MaxLinkSpeed);
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fsp_display_upd_value("Peg1MaxLinkSpeed", 1, old->Peg1MaxLinkSpeed,
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new->Peg1MaxLinkSpeed);
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fsp_display_upd_value("Peg2MaxLinkSpeed", 1, old->Peg2MaxLinkSpeed,
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new->Peg2MaxLinkSpeed);
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fsp_display_upd_value("Peg3MaxLinkSpeed", 1, old->Peg3MaxLinkSpeed,
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new->Peg3MaxLinkSpeed);
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fsp_display_upd_value("Peg0MaxLinkWidth", 1, old->Peg0MaxLinkWidth,
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new->Peg0MaxLinkWidth);
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fsp_display_upd_value("Peg1MaxLinkWidth", 1, old->Peg1MaxLinkWidth,
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new->Peg1MaxLinkWidth);
|
||||
fsp_display_upd_value("Peg2MaxLinkWidth", 1, old->Peg2MaxLinkWidth,
|
||||
new->Peg2MaxLinkWidth);
|
||||
fsp_display_upd_value("Peg3MaxLinkWidth", 1, old->Peg3MaxLinkWidth,
|
||||
new->Peg3MaxLinkWidth);
|
||||
fsp_display_upd_value("Peg0PowerDownUnusedLanes", 1,
|
||||
old->Peg0PowerDownUnusedLanes, new->Peg0PowerDownUnusedLanes);
|
||||
fsp_display_upd_value("Peg1PowerDownUnusedLanes", 1,
|
||||
old->Peg1PowerDownUnusedLanes, new->Peg1PowerDownUnusedLanes);
|
||||
fsp_display_upd_value("Peg2PowerDownUnusedLanes", 1,
|
||||
old->Peg2PowerDownUnusedLanes, new->Peg2PowerDownUnusedLanes);
|
||||
fsp_display_upd_value("Peg3PowerDownUnusedLanes", 1,
|
||||
old->Peg3PowerDownUnusedLanes, new->Peg3PowerDownUnusedLanes);
|
||||
fsp_display_upd_value("InitPcieAspmAfterOprom", 1,
|
||||
old->InitPcieAspmAfterOprom, new->InitPcieAspmAfterOprom);
|
||||
fsp_display_upd_value("PegDisableSpreadSpectrumClocking", 1,
|
||||
old->PegDisableSpreadSpectrumClocking,
|
||||
new->PegDisableSpreadSpectrumClocking);
|
||||
// Skip UnusedUpdSpace4[3]
|
||||
//TODO: Offset 0x128 and up
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user