Remove some unused code.
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6010 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@@ -24,69 +24,6 @@
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#define CALIBRATE_INTERVAL ((20*CLOCK_TICK_RATE)/1000) /* 20ms */
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#define CALIBRATE_DIVISOR (20*1000) /* 20ms / 20000 == 1usec */
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#if 0
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static unsigned int calibrate_tsc(void)
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{
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/* Set the Gate high, disable speaker */
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outb((inb(0x61) & ~0x02) | 0x01, 0x61);
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/*
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* Now let's take care of CTC channel 2
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*
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* Set the Gate high, program CTC channel 2 for mode 0,
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* (interrupt on terminal count mode), binary count,
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* load 5 * LATCH count, (LSB and MSB) to begin countdown.
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*/
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outb(0xb0, 0x43); /* binary, mode 0, LSB/MSB, Ch 2 */
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outb(CALIBRATE_INTERVAL & 0xff, 0x42); /* LSB of count */
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outb(CALIBRATE_INTERVAL >> 8, 0x42); /* MSB of count */
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{
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tsc_t start;
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tsc_t end;
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unsigned long count;
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start = rdtsc();
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count = 0;
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do {
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count++;
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} while ((inb(0x61) & 0x20) == 0);
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end = rdtsc();
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/* Error: ECTCNEVERSET */
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if (count <= 1)
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goto bad_ctc;
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/* 64-bit subtract - gcc just messes up with long longs */
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__asm__("subl %2,%0\n\t"
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"sbbl %3,%1"
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:"=a" (end.lo), "=d" (end.hi)
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:"g" (start.lo), "g" (start.hi),
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"0" (end.lo), "1" (end.hi));
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/* Error: ECPUTOOFAST */
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if (end.hi)
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goto bad_ctc;
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/* Error: ECPUTOOSLOW */
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if (end.lo <= CALIBRATE_DIVISOR)
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goto bad_ctc;
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return (end.lo + CALIBRATE_DIVISOR -1)/CALIBRATE_DIVISOR;
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}
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/*
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* The CTC wasn't reliable: we got a hit on the very first read,
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* or the CPU was so fast/slow that the quotient wouldn't fit in
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* 32 bits..
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*/
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bad_ctc:
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print_err("bad_ctc\n");
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return 0;
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}
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#endif
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/* spll_raw_clk = SYSREF * FbDIV,
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* GLIU Clock = spll_raw_clk / MDIV
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* CPU Clock = spll_raw_clk / VDIV
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@@ -108,17 +45,6 @@ static const unsigned char fbdiv2plldiv[] = {
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49, 40, 19, 59, 32, 54, 35, 0, 41, 60, 55, 0, 61, 0, 0, 0
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};
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static const unsigned char pci33_ddr_crt [] = {
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/* FbDIV, VDIV, MDIV CPU/GeodeLink */
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12, 2, 3, // 200/133
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16, 2, 3, // 266/177
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18, 2, 3, // 300/200
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20, 2, 3, // 333/222
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22, 2, 3, // 366/244
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24, 2, 3, // 400/266
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26, 2, 3 // 433/289
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};
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/* FbDIV VDIV MDIV CPU/GeodeLink */
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/* 12 2 3 200/133 */
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/* 16 2 3 266/177 */
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@@ -128,31 +54,12 @@ static const unsigned char pci33_ddr_crt [] = {
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/* 24 2 3 400/266 */
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/* 26 2 3 433/289 */
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#if 0
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static unsigned int get_memory_speed(void)
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{
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unsigned char val, hi, lo;
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val = spd_read_byte(0xA0, 9);
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hi = (val >> 4) & 0x0f;
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lo = val & 0x0f;
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return 20000/(hi*10 + lo);
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}
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#endif
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#define USE_GOODRICH_VERSION 1
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#if USE_GOODRICH_VERSION
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///////////////////////////////////////////////////////////////////////////////
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// Goodrich Version of pll_reset
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/* PLLCHECK_COMPLETED is the "we've already done this" flag */
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#define PLLCHECK_COMPLETED (1 << RSTPLL_LOWER_SWFLAGS_SHIFT)
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#ifndef RSTPPL_LOWER_BYPASS_SET
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#define RSTPPL_LOWER_BYPASS_SET (1 << GLCP_SYS_RSTPLL_BYPASS)
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#endif /* RSTPPL_LOWER_BYPASS_SET */
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#endif // RSTPPL_LOWER_BYPASS_SET
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#define DEFAULT_MDIV 3
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#define DEFAULT_VDIV 2
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@@ -218,7 +125,7 @@ static void pll_reset(void)
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/* CheckSemiSync proc */
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/* Check for Semi-Sync in GeodeLink and CPU. */
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/* We need to do this here since the strap settings don't account for these bits. */
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SyncBits = 0; // store the sync bits in up ebx
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SyncBits = 0; /* store the sync bits in up ebx */
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/* Check for Bypass mode. */
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if (msrGlcpSysRstpll.lo & RSTPPL_LOWER_BYPASS_SET)
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@@ -247,7 +154,6 @@ static void pll_reset(void)
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}
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}
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/* SetSync: */
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msrGlcpSysRstpll.lo &= ~(RSTPPL_LOWER_PCI_SEMI_SYNC_SET | RSTPPL_LOWER_CPU_SEMI_SYNC_SET);
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msrGlcpSysRstpll.lo |= SyncBits;
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@@ -273,78 +179,3 @@ static void pll_reset(void)
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} /* we haven't configured the PLL; do it now */
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}
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// End of Goodrich version of pll_reset
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///////////////////////////////////////////////////////////////////////////////
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#else // #if USE_GOODRICH_VERSION
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static void pll_reset(void)
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{
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msr_t msr;
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unsigned int sysref, spll_raw, cpu_core, gliu;
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unsigned mdiv, vdiv, fbdiv;
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/* get CPU core clock in MHZ */
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cpu_core = calibrate_tsc();
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print_debug("Cpu core is ");
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print_debug_hex32(cpu_core);
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print_debug("\n");
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msr = rdmsr(GLCP_SYS_RSTPLL);
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if (msr.lo & (1 << GLCP_SYS_RSTPLL_BYPASS)) {
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#if 0
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print_debug("MSR ");
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print_debug_hex32(GLCP_SYS_RSTPLL);
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print_debug("is ");
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print_debug_hex32(msr.hi);
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print_debug(":");
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print_debug_hex32(msr.lo);
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msr.hi = PLLMSRhi;
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msr.lo = PLLMSRlo;
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wrmsr(GLCP_SYS_RSTPLL, msr);
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msr.lo |= PLLMSRlo1;
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wrmsr(GLCP_SYS_RSTPLL, msr);
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print_debug("Reset PLL\n");
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msr.lo |= PLLMSRlo2;
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wrmsr(GLCP_SYS_RSTPLL,msr);
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print_debug("should not be here\n");
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#endif
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print_err("shit");
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while (1)
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;
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}
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if (msr.lo & GLCP_SYS_RSTPLL_SWFLAGS_MASK) {
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/* PLL is already set and we are reboot from PLL reset */
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print_debug("reboot from BIOS reset\n");
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return;
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}
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/* get the sysref clock rate */
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vdiv = (msr.hi >> GLCP_SYS_RSTPLL_VDIV_SHIFT) & 0x07;
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vdiv += 2;
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fbdiv = (msr.hi >> GLCP_SYS_RSTPLL_FBDIV_SHIFT) & 0x3f;
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fbdiv = fbdiv2plldiv[fbdiv];
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spll_raw = cpu_core * vdiv;
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sysref = spll_raw / fbdiv;
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/* get target memory rate by SPD */
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//gliu = get_memory_speed();
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msr.hi = 0x00000019;
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msr.lo = 0x06de0378;
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wrmsr(0x4c000014, msr);
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msr.lo |= ((0xde << 16) | (1 << 26) | (1 << 24));
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wrmsr(0x4c000014, msr);
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print_debug("Reset PLL\n");
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msr.lo |= ((1<<14) |(1<<13) | (1<<0));
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wrmsr(0x4c000014,msr);
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print_debug("should not be here\n");
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}
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#endif // #if USE_GOODRICH_VERSION
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