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Remove some unused code.

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Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6010 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Nils Jacobs
2010-11-01 14:39:49 +00:00
committed by Uwe Hermann
parent 809e29ec8f
commit 9644623934
1 changed files with 2 additions and 171 deletions
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173
src/northbridge/amd/gx2/pll_reset.c
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@@ -24,69 +24,6 @@
#define CALIBRATE_INTERVAL ((20*CLOCK_TICK_RATE)/1000) /* 20ms */
#define CALIBRATE_DIVISOR (20*1000) /* 20ms / 20000 == 1usec */
#if 0
static unsigned int calibrate_tsc(void)
{
/* Set the Gate high, disable speaker */
outb((inb(0x61) & ~0x02) | 0x01, 0x61);
/*
* Now let's take care of CTC channel 2
*
* Set the Gate high, program CTC channel 2 for mode 0,
* (interrupt on terminal count mode), binary count,
* load 5 * LATCH count, (LSB and MSB) to begin countdown.
*/
outb(0xb0, 0x43); /* binary, mode 0, LSB/MSB, Ch 2 */
outb(CALIBRATE_INTERVAL & 0xff, 0x42); /* LSB of count */
outb(CALIBRATE_INTERVAL >> 8, 0x42); /* MSB of count */
{
tsc_t start;
tsc_t end;
unsigned long count;
start = rdtsc();
count = 0;
do {
count++;
} while ((inb(0x61) & 0x20) == 0);
end = rdtsc();
/* Error: ECTCNEVERSET */
if (count <= 1)
goto bad_ctc;
/* 64-bit subtract - gcc just messes up with long longs */
__asm__("subl %2,%0\n\t"
"sbbl %3,%1"
:"=a" (end.lo), "=d" (end.hi)
:"g" (start.lo), "g" (start.hi),
"0" (end.lo), "1" (end.hi));
/* Error: ECPUTOOFAST */
if (end.hi)
goto bad_ctc;
/* Error: ECPUTOOSLOW */
if (end.lo <= CALIBRATE_DIVISOR)
goto bad_ctc;
return (end.lo + CALIBRATE_DIVISOR -1)/CALIBRATE_DIVISOR;
}
/*
* The CTC wasn't reliable: we got a hit on the very first read,
* or the CPU was so fast/slow that the quotient wouldn't fit in
* 32 bits..
*/
bad_ctc:
print_err("bad_ctc\n");
return 0;
}
#endif
/* spll_raw_clk = SYSREF * FbDIV,
* GLIU Clock = spll_raw_clk / MDIV
* CPU Clock = spll_raw_clk / VDIV
@@ -108,17 +45,6 @@ static const unsigned char fbdiv2plldiv[] = {
49, 40, 19, 59, 32, 54, 35, 0, 41, 60, 55, 0, 61, 0, 0, 0
};
static const unsigned char pci33_ddr_crt [] = {
/* FbDIV, VDIV, MDIV CPU/GeodeLink */
12, 2, 3, // 200/133
16, 2, 3, // 266/177
18, 2, 3, // 300/200
20, 2, 3, // 333/222
22, 2, 3, // 366/244
24, 2, 3, // 400/266
26, 2, 3 // 433/289
};
/* FbDIV VDIV MDIV CPU/GeodeLink */
/* 12 2 3 200/133 */
/* 16 2 3 266/177 */
@@ -128,31 +54,12 @@ static const unsigned char pci33_ddr_crt [] = {
/* 24 2 3 400/266 */
/* 26 2 3 433/289 */
#if 0
static unsigned int get_memory_speed(void)
{
unsigned char val, hi, lo;
val = spd_read_byte(0xA0, 9);
hi = (val >> 4) & 0x0f;
lo = val & 0x0f;
return 20000/(hi*10 + lo);
}
#endif
#define USE_GOODRICH_VERSION 1
#if USE_GOODRICH_VERSION
///////////////////////////////////////////////////////////////////////////////
// Goodrich Version of pll_reset
/* PLLCHECK_COMPLETED is the "we've already done this" flag */
#define PLLCHECK_COMPLETED (1 << RSTPLL_LOWER_SWFLAGS_SHIFT)
#ifndef RSTPPL_LOWER_BYPASS_SET
#define RSTPPL_LOWER_BYPASS_SET (1 << GLCP_SYS_RSTPLL_BYPASS)
#endif /* RSTPPL_LOWER_BYPASS_SET */
#endif // RSTPPL_LOWER_BYPASS_SET
#define DEFAULT_MDIV 3
#define DEFAULT_VDIV 2
@@ -218,7 +125,7 @@ static void pll_reset(void)
/* CheckSemiSync proc */
/* Check for Semi-Sync in GeodeLink and CPU. */
/* We need to do this here since the strap settings don't account for these bits. */
SyncBits = 0; // store the sync bits in up ebx
SyncBits = 0; /* store the sync bits in up ebx */
/* Check for Bypass mode. */
if (msrGlcpSysRstpll.lo & RSTPPL_LOWER_BYPASS_SET)
@@ -247,7 +154,6 @@ static void pll_reset(void)
}
}
/* SetSync: */
msrGlcpSysRstpll.lo &= ~(RSTPPL_LOWER_PCI_SEMI_SYNC_SET | RSTPPL_LOWER_CPU_SEMI_SYNC_SET);
msrGlcpSysRstpll.lo |= SyncBits;
@@ -273,78 +179,3 @@ static void pll_reset(void)
} /* we haven't configured the PLL; do it now */
}
// End of Goodrich version of pll_reset
///////////////////////////////////////////////////////////////////////////////
#else // #if USE_GOODRICH_VERSION
static void pll_reset(void)
{
msr_t msr;
unsigned int sysref, spll_raw, cpu_core, gliu;
unsigned mdiv, vdiv, fbdiv;
/* get CPU core clock in MHZ */
cpu_core = calibrate_tsc();
print_debug("Cpu core is ");
print_debug_hex32(cpu_core);
print_debug("\n");
msr = rdmsr(GLCP_SYS_RSTPLL);
if (msr.lo & (1 << GLCP_SYS_RSTPLL_BYPASS)) {
#if 0
print_debug("MSR ");
print_debug_hex32(GLCP_SYS_RSTPLL);
print_debug("is ");
print_debug_hex32(msr.hi);
print_debug(":");
print_debug_hex32(msr.lo);
msr.hi = PLLMSRhi;
msr.lo = PLLMSRlo;
wrmsr(GLCP_SYS_RSTPLL, msr);
msr.lo |= PLLMSRlo1;
wrmsr(GLCP_SYS_RSTPLL, msr);
print_debug("Reset PLL\n");
msr.lo |= PLLMSRlo2;
wrmsr(GLCP_SYS_RSTPLL,msr);
print_debug("should not be here\n");
#endif
print_err("shit");
while (1)
;
}
if (msr.lo & GLCP_SYS_RSTPLL_SWFLAGS_MASK) {
/* PLL is already set and we are reboot from PLL reset */
print_debug("reboot from BIOS reset\n");
return;
}
/* get the sysref clock rate */
vdiv = (msr.hi >> GLCP_SYS_RSTPLL_VDIV_SHIFT) & 0x07;
vdiv += 2;
fbdiv = (msr.hi >> GLCP_SYS_RSTPLL_FBDIV_SHIFT) & 0x3f;
fbdiv = fbdiv2plldiv[fbdiv];
spll_raw = cpu_core * vdiv;
sysref = spll_raw / fbdiv;
/* get target memory rate by SPD */
//gliu = get_memory_speed();
msr.hi = 0x00000019;
msr.lo = 0x06de0378;
wrmsr(0x4c000014, msr);
msr.lo |= ((0xde << 16) | (1 << 26) | (1 << 24));
wrmsr(0x4c000014, msr);
print_debug("Reset PLL\n");
msr.lo |= ((1<<14) |(1<<13) | (1<<0));
wrmsr(0x4c000014,msr);
print_debug("should not be here\n");
}
#endif // #if USE_GOODRICH_VERSION