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soc/intel/tigerlake: Remove write to IOP TCSS_IN_D3

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Change-Id: Ibbf6b5e0bf627536d10c8dee2f632e66da427151
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
This commit is contained in:
Jeremy Soller
2021-09-08 15:04:48 -06:00
committed by Tim Crawford
parent a377b8b744
commit 97014a5ab9
1 changed files with 0 additions and 16 deletions
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16
src/soc/intel/tigerlake/acpi/tcss.asl
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@@ -354,12 +354,6 @@ Scope (\_SB.PCI0)
Offset(0x10), Offset(0x10),
RBAR, 64 /* RegBar, offset 0x7110 in MCHBAR */ RBAR, 64 /* RegBar, offset 0x7110 in MCHBAR */
} }
Field (MBAR, DWordAcc, NoLock, Preserve)
{
Offset(0x304), /* PRIMDN_MASK1_0_0_0_MCHBAR_IMPH, offset 0x7404 */
, 31,
TCD3, 1 /* [31:31] TCSS IN D3 bit */
}
/* /*
* Operation region defined to access the pCode mailbox interface. Get the MCHBAR * Operation region defined to access the pCode mailbox interface. Get the MCHBAR
@@ -689,11 +683,6 @@ Scope (\_SB.PCI0)
} }
Else Else
{ {
/*
* Program IOP MCTP Drop (TCSS_IN_D3) after D3 cold exit and
* acknowledgement by IOM.
*/
TCD3 = 0
/* /*
* If the TCSS Deven is cleared by BIOS Mailbox request, then * If the TCSS Deven is cleared by BIOS Mailbox request, then
* restore to previously saved value of TCSS DEVNE. * restore to previously saved value of TCSS DEVNE.
@@ -741,11 +730,6 @@ Scope (\_SB.PCI0)
} }
} }
/*
* Program IOM MCTP Drop (TCSS_IN_D3) in D3Cold entry before entering D3 cold.
*/
TCD3 = 1
/* Request IOM for D3 cold entry sequence. */ /* Request IOM for D3 cold entry sequence. */
TD3C = 1 TD3C = 1
} }