soc/intel/tigerlake: Fix IPU and Vtd config
- FSP enables IPU (Imaging Processing Unit) by default even if its disabled in devicetree. We need to fill FSP upd based on the device enablement in devicetree. - Enable Vtd IPU and IGD settings only if respective IPs are enabled. BUG=165340186 BRANCH=None TEST=IPU is disabled and doesn't show in lspci. Change-Id: Ieff57fb0ebc8522546d6b34da6ca2f2f845bf61d Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44627 Reviewed-by: Daniel H Kang <daniel.h.kang@intel.corp-partner.google.com> Reviewed-by: John Zhao <john.zhao@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
committed by
Patrick Georgi
parent
028e527cbd
commit
97b4224943
@@ -158,6 +158,10 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
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memcpy(m_cfg->PchHdaAudioLinkSndwEnable, config->PchHdaAudioLinkSndwEnable,
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sizeof(m_cfg->PchHdaAudioLinkSndwEnable));
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/* IPU configuration */
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dev = pcidev_path_on_root(SA_DEVFN_IPU);
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m_cfg->SaIpuEnable = is_dev_enabled(dev);
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/* Vt-D config */
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cpu_id = cpu_get_cpuid();
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if (cpu_id == CPUID_TIGERLAKE_A0) {
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@@ -166,11 +170,18 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
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} else {
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/* Enable VT-d support for QS platform */
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m_cfg->VtdDisable = 0;
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m_cfg->VtdIgdEnable = 0x1;
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m_cfg->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS;
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m_cfg->VtdIpuEnable = 0x1;
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m_cfg->VtdBaseAddress[1] = IPUVT_BASE_ADDRESS;
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m_cfg->VtdIopEnable = 0x1;
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if (m_cfg->InternalGfx) {
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m_cfg->VtdIgdEnable = 0x1;
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m_cfg->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS;
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}
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if (m_cfg->SaIpuEnable) {
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m_cfg->VtdIpuEnable = 0x1;
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m_cfg->VtdBaseAddress[1] = IPUVT_BASE_ADDRESS;
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}
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m_cfg->VtdBaseAddress[2] = VTVC0_BASE_ADDRESS;
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if (m_cfg->TcssDma0En || m_cfg->TcssDma1En)
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