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soc/intel/tigerlake: Fix IPU and Vtd config

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- FSP enables IPU (Imaging Processing Unit) by default even if its
disabled in devicetree. We need to fill FSP upd based on the device
enablement in devicetree.

- Enable Vtd IPU and IGD settings only if respective IPs are enabled.

BUG=165340186
BRANCH=None
TEST=IPU is disabled and doesn't show in lspci.

Change-Id: Ieff57fb0ebc8522546d6b34da6ca2f2f845bf61d
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44627
Reviewed-by: Daniel H Kang <daniel.h.kang@intel.corp-partner.google.com>
Reviewed-by: John Zhao <john.zhao@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Ravi Sarawadi
2020-08-19 14:23:19 -07:00
committed by Patrick Georgi
parent 028e527cbd
commit 97b4224943
1 changed files with 15 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
src/soc/intel/tigerlake/romstage/fsp_params.c
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@@ -158,6 +158,10 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
memcpy(m_cfg->PchHdaAudioLinkSndwEnable, config->PchHdaAudioLinkSndwEnable,
sizeof(m_cfg->PchHdaAudioLinkSndwEnable));
/* IPU configuration */
dev = pcidev_path_on_root(SA_DEVFN_IPU);
m_cfg->SaIpuEnable = is_dev_enabled(dev);
/* Vt-D config */
cpu_id = cpu_get_cpuid();
if (cpu_id == CPUID_TIGERLAKE_A0) {
@@ -166,11 +170,18 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
} else {
/* Enable VT-d support for QS platform */
m_cfg->VtdDisable = 0;
m_cfg->VtdIgdEnable = 0x1;
m_cfg->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS;
m_cfg->VtdIpuEnable = 0x1;
m_cfg->VtdBaseAddress[1] = IPUVT_BASE_ADDRESS;
m_cfg->VtdIopEnable = 0x1;
if (m_cfg->InternalGfx) {
m_cfg->VtdIgdEnable = 0x1;
m_cfg->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS;
}
if (m_cfg->SaIpuEnable) {
m_cfg->VtdIpuEnable = 0x1;
m_cfg->VtdBaseAddress[1] = IPUVT_BASE_ADDRESS;
}
m_cfg->VtdBaseAddress[2] = VTVC0_BASE_ADDRESS;
if (m_cfg->TcssDma0En || m_cfg->TcssDma1En)