mb/google/brya/var/orisa: Remove redundant defaults from overridetree
Streamline variant-level overrides by removing redundant entries that already exist in either the SoC-level or the platform-level configurations. BUG=None TEST=emerge-nissa coreboot Change-Id: I0b28354dfb865900a78a9d0738e00aa952eade0e Signed-off-by: Rishika Raj <rishikaraj@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
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Subrata Banik
parent
8977282e12
commit
97bc693abc
@@ -86,10 +86,7 @@ chip soc/intel/alderlake
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register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A0
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register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A1
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register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera
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register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable USB2 Port 4
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register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0
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register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2 Port 7
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register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Disable USB2 Port 8
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A0
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A1
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@@ -511,7 +508,6 @@ chip soc/intel/alderlake
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end
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end #I2C5
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device ref heci1 on end
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device ref pcie_rp7 off end
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device ref emmc on
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probe STORAGE STORAGE_UNKNOWN
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probe STORAGE STORAGE_EMMC
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