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mb/google/brya/var/orisa: Remove redundant defaults from overridetree

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Streamline variant-level overrides by removing redundant entries that
already exist in either the SoC-level or the platform-level configurations.

BUG=None
TEST=emerge-nissa coreboot

Change-Id: I0b28354dfb865900a78a9d0738e00aa952eade0e
Signed-off-by: Rishika Raj <rishikaraj@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
This commit is contained in:
Rishika Raj
2024-07-29 08:03:01 +00:00
committed by Subrata Banik
parent 8977282e12
commit 97bc693abc
1 changed files with 0 additions and 4 deletions
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4
src/mainboard/google/brya/variants/orisa/overridetree.cb
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@@ -86,10 +86,7 @@ chip soc/intel/alderlake
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A0
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A1
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera
register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable USB2 Port 4
register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0
register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2 Port 7
register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Disable USB2 Port 8
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A0
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A1
@@ -511,7 +508,6 @@ chip soc/intel/alderlake
end
end #I2C5
device ref heci1 on end
device ref pcie_rp7 off end
device ref emmc on
probe STORAGE STORAGE_UNKNOWN
probe STORAGE STORAGE_EMMC