mb/google/nissa/var/uldren: Update eMMC DLL settings
Update eMMC DLL settings based on Uldren board. BUG=b:280120229 TEST=executed 10 cycles of cold boot successfully Change-Id: I46e2f9df0e82e66fa3ae32aa87b4bcf30d5737ab Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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@@ -1,6 +1,51 @@
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chip soc/intel/alderlake
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register "sagv" = "SaGv_Enabled"
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# EMMC Tx CMD Delay
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# Refer to EDS-Vol2-42.3.7.
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# [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39.
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# [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39.
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register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x00000505"
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# EMMC TX DATA Delay 1
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# Refer to EDS-Vol2-42.3.8.
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# [14:8] steps of delay for HS400, each 125ps, range: 0 - 78.
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# [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79.
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register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x00000a12"
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# EMMC TX DATA Delay 2
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# Refer to EDS-Vol2-42.3.9.
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# [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79.
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# [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
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# [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79.
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# [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79.
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register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1c292828"
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# EMMC RX CMD/DATA Delay 1
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# Refer to EDS-Vol2-42.3.10.
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# [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119.
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# [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
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# [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
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# [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
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register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1c175a3b"
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# EMMC RX CMD/DATA Delay 2
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# Refer to EDS-Vol2-42.3.12.
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# [17:16] stands for Rx Clock before Output Buffer,
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# 00: Rx clock after output buffer,
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# 01: Rx clock before output buffer,
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# 10: Automatic selection based on working mode.
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# 11: Reserved
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# [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39.
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# [6:0] steps of delay for HS200, each 125ps, range: 0 - 79.
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register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x00010023"
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# EMMC Rx Strobe Delay
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# Refer to EDS-Vol2-42.3.11.
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# [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39.
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# [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
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register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x00011111"
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# SOC Aux orientation override:
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# This is a bitfield that corresponds to up to 4 TCSS ports.
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# Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2.
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